TDA7478 SINGLE CHIP RDS DEMODULATOR 1 ■ ■ ■ ■ ■ ■ ■ ■ 2 FEATURES Figure 1. Packages VERY HIGH RDS DEMODULATION QUALITY WITH IMPROVED DIGITAL SIGNAL PROCESSING HIGH PERFORMANCE, 57KHz BANDPASS FILTER (8th ORDER) FILTER ADJUSTMENT FREE AND WITHOUT EXTERNAL COMPONENTS PURELY DIGITAL RDS DEMODULATION WITHOUT EXTERNAL COMPONENTS RDS SIGNAL QUALITY OUTPUT 4.332MHz CRYSTAL OSCILLATOR(8.664MHz OPTIONAL) LOW NOISE CMOS TECHNOLOGY LOW RADIATION SO16 TSSOP16 Table 1. Order Codes Part Number Package TDA7478D SO16 E-TDA7478AD TSSOP16 EBU (European Broadcasting Union) specifications. The device is made up of two sections: a cascaded antialiasing + switched capacitors 8th bandpass filter for precise RDS band selection and a demodulating section that performs the extraction od RDS data stream (RDDA) and clock (RDCL), to be further processed by a suitable RDS decoder. DESCRIPTION The TDA7478 recovers the additional inaudible RDS information which is transmitted by FM radio broadcasting stations and operates in accordance with the Output for RDS signal quality is also present. Figure 2. Block Diagram C1 27pF T57 4.332MHz OSCIN OSCOUT 13 15 C2 47pF 14 4 MPX 2nd ORDER ANTIALIASING FILTER 270pF 5 OSCILLATOR & DIVIDER 9 16 FILOUT 8th ORDER SC-BANDPASS FILTER 8 1187.5Hz PLL 57KHz PLL 7 1 12 VS QUAL DET. OSEL FSEL RDCL N.U. QUAL 100nF VREF - 3 + POLARITY BIPHASE DEC. 0 1 10µF MUX DIFF. DECODER 10 INTEGRAL BIPHASE DEC. 6 GND November 2004 2 TEST LOGIC RDDA TM 11 EXTRES D03AU1490 Rev. 2 1/8 TDA7478 Table 2. Pin Description No pin Name 1 QUAL Description 2 RDDA RDS data output 3 VREF Reference voltage Output for signal quality indication (High = good) 4 MPX RDS input signal 5 OSEL Oscillator selector pin: - open, closed to VS = quartz oscillator - closed to GND=external driven 6 GND Ground 7 N.U. Not Used (to be left open) 8 FILOUT 9 FSEL 10 TM 11 EXTRES 12 VS 13 OSCIN 14 OSCOUT 15 T57 16 RDCL Filter output Frequency selector pin: - open = 4.332MHz - closed to VS = 8.664MHz Test mode pin: - open = normal operation - closed to VS = testmode Reset pin: - open=run mode - closed to VS = reset condition Supply voltage Oscillator input Oscillator output Testing output pin: 57kHz clock output RDS clock output 1187.5Hz Figure 3. Pin Connection (Top view) QUAL 1 16 RDCL RDDA 2 15 T57 VREF 3 14 OSCOUT MPX 4 13 OSCIN OSEL 5 12 VS GND 6 11 EXTRES N.U. 7 10 TM FILOUT 8 9 FSEL D97AU752A Table 3. Thermal Data Symbol Rth j-case 2/8 Description Thermal Resistance Junction-case Max. Value Unit 200 °C/W TDA7478 Table 4. Absolute Maximum Ratings Symbol Parameter Value Unit VS Supply Voltage -0.3 to 7 V Top Operating Temperature Range -40 to 85 °C Tstg Storage Temperature -55 to 150 °C Table 5. Electrical Characteristcs (Tamb = 25°C, VS = 5V, unless otherwise specified) Symbol Parameter VS Supply voltage IS Supply current Test Condition Min. 4.5 Typ. Max. Unit 5 5.5 V 7.5 12.0 mA FILTER fC BW Center frequency 56.6 57 57.4 kHz 3dB Bandwidth 2.5 3 3.5 kHz 20 23 G Gain f = 57kHz A Attenuation ∆f ± 4kHz 17 22 dB f = 38kHz 60 dB f = 67kHz RI Input impedance of MPX RL Load impedance on FILOUT S/N Signal to noise ratio VIN MPX input signal 45 dB 120 KΩ 1 VIN = 3mVRMS 30 dB MΩ 40 dB 1000 50 (1) f = 19kHz; T3 ≤ 40dB f = 57kHz (RDS) mVRMS mVRMS SRDS RDS Detection Sensitivity 1 mVrms SARI ARI Detection Sensitivity 3 mVrms VREF Reference VS/2 V DEMODULATOR Input pins (EXTRES, FSEL, TM) Input pin (OSEL) all with internal pull down resistor with internal pull up resistor IPD Input Current VIN = 5V (pull-down input) VIN = 0V (pull-up input) IPU Input Current VIH Input voltage high VIL Input voltage low 15 30 µA -25 -10 µA 0.7 · VS 0.8 · VS V 0.2 · VS 0.3 · VS V Output pins (RDCL, RDDA, QUAL, T57) VOH Ouput voltage high IL = 0.5mA VOL Output voltage low IL = 0.5mA 4 4.6 0.4 V 1 V 1 V OSCILLATOR VCLL Input level OSCIN pin OSEL = open circuit VCLH Input level OSCIN pin OSEL = open circuit Amplitude OSCOUT OSEL = open circuit 4.5 V Amplitude OSCIN (for external drive) OSEL = GND, f = 4.332MHz OSEL = GND, f = 8.664MHz 100 120 mVpp mVpp VPP 4 V (1) The 3rd harmonic (57kHz) must be less than -40dB with respect to the input signal plus gain. 3/8 TDA7478 Figure 4. RDS timing diagram CLOCK LINE DATA LINE 3 OUTPUT TIMING The RDS (1187.5Hz) output clock on RDCL line is synchronized to the incoming data. According to the internal PLL lock condition data change can result on the falling or on the rising clock edge. (see Fig. 1)Whichever clock edge is used by the decoder (rising or falling edge) the data will remain valid for 416.7 µs after the clock transition. 4 OSCILLATOR CONTROLS (FSEL, OSEL) Two different crystal frequencies can be used. The adaption of the internal clock divider to the external crystal is achieved via the input pin FSEL. See the following table for reference: Table 6. Crystal 4.332MHz 8.664MHz FSEL (pin configuration) connected to GND or open connected to Vs A special mode is introduced to reduce EMI. With pin OSEL connected to GND the internal oscillator is switched off and an external sinusoidal frequency could be applied on OSCIN. The peak to peak voltage of this signal can be reduced down to 60mV. In this mode the frequency selection via FSEL is still active. Suggested values of C1 and C2 are shown in the following table: Table 7. 4/8 Crystal C1 C2 4.332MHz 8.664MHz 27pF 27pF 47pF - TDA7478 Figure 5. SO16 Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.200 C 0.23 0.32 0.009 0.013 D (1) 10.10 10.50 0.398 0.413 E 7.40 7.60 0.291 0.299 e 1.27 0.050 H 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.40 1.27 0.016 0.050 k ddd OUTLINE AND MECHANICAL DATA 0˚ (min.), 8˚ (max.) 0.10 0.004 (1) “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO16 (Wide) 0016021 C 5/8 TDA7478 Figure 6. TSSOP16 Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. A MAX. MIN. TYP. 1.200 A1 0.050 A2 0.800 b MAX. 0.047 0.150 0.002 1.050 0.031 0.190 0.300 0.007 0.012 c 0.090 0.200 0.005 0.009 D (1) 4.900 5.000 5.100 0.114 0.118 0.122 E 6.200 6.400 6.600 0.244 0.252 0.260 E1 (1) 4.300 4.400 4.500 0.170 0.173 0.177 e L L1 k aaa 1.000 0.650 0.450 0.600 OUTLINE AND MECHANICAL DATA 0.006 0.039 0.041 0.026 0.750 0.018 1.000 0.024 0.030 0.039 0˚ (min.) 8˚ (max.) 0.100 0.004 Note: 1. D and E1 does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch) per side. TSSOP16 (Body 4.4mm) 0080338 (Jedec MO-153-AB) 6/8 TDA7478 Table 8. Revision History Date Revision Description of Changes July 2004 1 First Issue November 2004 2 Add in the table 5 “RDS and ARI Detection Sensitivity” parameters. 7/8 TDA7478 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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