STMICROELECTRONICS HCF4015BEY

HCF4015B
DUAL 4-STAGE STATIC SHIFT REGISTER WITH
SERIAL INPUT/PARALLEL OUTPUT
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■
■
■
■
■
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■
MEDIUM SPEED OPERATION 12 MHz (Typ.)
CLOCK RATE AT VDD - VSS = 10V
FULLY STATIC OPERATION
8 MASTER-SLAVE FLIP-FLOPS PLUS
INPUT AND OUTPUT BUFFERING
HIGH NOISE IMMUNITY
QUIESCENT CURRENT SPECIFIED UP TO
20V
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
HCF4015B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4015B consists of two identical, independent,
4 stage serial-input/parallel-output registers.
Each register has independent CLOCK and
RESET inputs as well as a single serial DATA
input. "Q" outputs are available from each of the
DIP
SOP
ORDER CODES
PACKAGE
TUBE
T&R
DIP
SOP
HCF4015BEY
HCF4015BM1
HCF4015M013TR
four stages on both registers. All register stages
are D-TYPE, MASTER-SLAVE flip-flops. The
logic level present at the DATA input is transferred
into the first register stage and shifted over one
stage at each positive going clock transition. The
resetting of all stages is accomplished by a high
level on the reset line. It is possible to expand the
register to 8 stages using one HCF4015B
package and to expand to more than 8 stages by
using addition HCF4015Bs.
PIN CONNECTION
September 2002
1/10
HCF4015B
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
8
CLOCK A
CLOCK B
RESET A
RESET B
DATA A
DATA B
QnA
QnB
VSS
16
VDD
1, 9
6, 14
7, 15
5, 4, 3, 10
13, 12, 11, 2
NAME AND FUNCTION
Clock Input
Reset Input
Data Inputs
Outputs A-Stage
Outpus B-Stage
Negative Supply Voltage
Positive Supply Voltage
FUNCTIONAL DIAGRAM
TRUTH TABLE
CLOCK
X
X : Don’t Care
2/10
D
R
Q1
Qn
L
L
L
Qn - 1
H
L
H
Qn - 1
X
L
Q1
Qn - (NO CHANGE)
X
H
L
0
HCF4015B
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Parameter
Supply Voltage
VI
DC Input Voltage
II
DC Input Current
Value
Unit
-0.5 to +22
V
-0.5 to VDD + 0.5
± 10
V
mA
200
100
mW
mW
Top
Power Dissipation per Package
Power Dissipation per Output Transistor
Operating Temperature
-55 to +125
°C
Tstg
Storage Temperature
-65 to +150
°C
PD
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
Parameter
Supply Voltage
VI
Input Voltage
Top
Operating Temperature
Value
Unit
3 to 20
V
0 to VDD
V
-55 to 125
°C
3/10
HCF4015B
DC SPECIFICATIONS
Test Condition
Symbol
IL
VOH
VOL
VIH
VIL
IOH
IOL
II
CI
Parameter
Quiescent Current
High Level Output
Voltage
Low Level Output
Voltage
VI
(V)
0/5
0/10
0/15
0/20
0/5
0/10
0/15
5/0
10/0
15/0
High Level Input
Voltage
Low Level Input
Voltage
Output Drive
Current
Output Sink
Current
Input Leakage
Current
Input Capacitance
VO
(V)
0/5
0/5
0/10
0/15
0/5
0/10
0/15
0/18
0.5/4.5
1/9
1.5/13.5
4.5/0.5
9/1
13.5/1.5
2.5
4.6
9.5
13.5
0.4
0.5
1.5
Value
|IO| VDD
(µA) (V)
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
Any Input
Any Input
5
10
15
20
5
10
15
5
10
15
5
10
15
5
10
15
5
5
10
15
5
10
15
18
TA = 25°C
Min.
Typ.
Max.
0.04
0.04
0.04
0.08
5
10
20
100
4.95
9.95
14.95
-40 to 85°C
-55 to 125°C
Min.
Min.
150
300
600
3000
4.95
9.95
14.95
0.05
0.05
0.05
4.95
9.95
14.95
3.5
7
11
1.5
3
4
-3.2
-1
-2.6
-6.8
1
2.6
6.8
±0.1
5
7.5
0.05
0.05
0.05
1.5
3
4
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
4/10
V
V
1.5
3
4
±1
µA
V
3.5
7
11
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
±10-5
Max.
150
300
600
3000
0.05
0.05
0.05
3.5
7
11
-1.36
-0.44
-1.1
-3.0
0.44
1.1
3.0
Max.
Unit
V
mA
mA
±1
µA
pF
HCF4015B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
Test Condition
Symbol
Parameter
CLOCKED OPERATION
tPLH tPHL Propagation Delay Time
(carry out or decoded out
lines)
tTHL tTLH Transition Time (carry out
or decoded out lines)
fCL
tW
tr , tf (1)
tsetup
Maximum Clock Input
Frequency
Clock Pulse Width
Clock Input Rise or Fall
Time
Data Setup Time
RESET OPERATION
tPLH, tPHL Propagation Delay Time
tW
Reset Pulse Width
VDD (V)
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
Value (*)
Unit
Min.
Typ.
Max.
320
160
120
200
100
80
3
6
8.5
180
80
50
160
80
60
100
50
40
6
12
17
90
40
25
35
20
15
200
80
60
200
100
80
100
40
30
ns
MHz
ns
15
15
15
70
40
30
ns
µs
ns
400
200
160
ns
ns
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
(1) If more than one unit is cascaded in the parallel clocked application, trCL should be made less than or equal to the sum of the fixed propagation delay at 15 pF and the transmission time of the carry output driving stage of the estimated capacitive load.
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HCF4015B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : MINIMUM PULSE WIDTH, PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
6/10
HCF4015B
WAVEFORM 2 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle)
7/10
HCF4015B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.
inch
DIM.
MIN.
a1
0.51
B
0.77
TYP
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
Z
3.3
0.130
1.27
0.050
P001C
8/10
HCF4015B
SO-16 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.068
0.2
a2
MAX.
0.003
0.007
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45˚ (typ.)
D
9.8
E
5.8
10
0.385
6.2
0.228
0.393
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
S
0.62
0.024
8 ˚ (max.)
PO13H
9/10
HCF4015B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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