HCF4038B TRIPLE SERIAL ADDER ■ ■ ■ ■ ■ ■ ■ ■ ■ INVERT INPUTS ON ALL ADDERS FOR SUM COMPLEMENTING APPLICATIONS FULLY STATIC OPERATION...DC TO 10MHz (Typ.) at VDD = 10V BUFFERED INPUTS AND OUTPUTS SINGLE PHASE CLOCKING QUIESCENT CURRENT SPECIFIED UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION The HCF4038B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. The HCF4038B consists of three serial adder circuits with common CLOCK and CARRY-RESET inputs. Each adder has two provisions for two serial DATA INPUT signals and an INVERT command signal. When the command signal is a logical "1", the sum is complemented. DIP SOP ORDER CODES PACKAGE TUBE T&R DIP SOP HCF4038BEY HCF4038BM1 HCF4038M013TR Data words enter the adder with the least significant bit first; the sign bit trails. The output is the MOD 2 sum of the input bits plus the carry from the previous bit position. The carry is only added at the negative going clock transition, thus, for spike-free operation the input data transitions should occur as soon as possible after the triggering edge. The CARRY is reset to a logical "0" at the end of each word by applying a logical "1" signal to a CARRY-RESET input one bit position before the application of the first bit of the next word. PIN CONNECTION September 2001 1/9 HCF4038B IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 10, 13, 15 11, 12, 14 8 A1 to A3 B1 to B3 INVERT1 to INVERT3 SUM1 to SUM3 CLOCK CARRY-RES ET VSS Negative Supply Voltage 16 VDD Positive Supply Voltage 7, 5, 2 9, 4, 1 3 6 FUNCTIONAL DIAGRAM 2/9 NAME AND FUNCTION Data Inputs Data Inputs Invert Command Inputs Data Outputs Clock Input Carry Reset Input HCF4038B LOGIC DIAGRAM TIMING CHART 3/9 HCF4038B ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Supply Voltage VI DC Input Voltage II DC Input Current PD Value Unit -0.5 to +22 V -0.5 to VDD + 0.5 ± 10 V mA 200 100 mW mW Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature -55 to +125 °C Tstg Storage Temperature -65 to +150 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD 4/9 Parameter Supply Voltage VI Input Voltage Top Operating Temperature Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C HCF4038B DC SPECIFICATIONS Test Conditions Symbol IL VOH VOL VIH VIL IOH IOL II CI Parameter Quiescent Current High Level Output Voltage Low Level Output Voltage VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 High Level Input Voltage Low Level Input Voltage Output Drive Current Output Sink Current Input Leakage Current Input Capacitance VO (V) 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 0.5/4.5 1/9 1.5/18.5 0.5/4.5 9/1 1.5/18.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 Value IO VDD (µA) (V) <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 any input any input 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25°C Min. Typ. Max. 0.04 0.04 0.04 0.08 5 10 20 100 4.95 9.95 14.95 -40 to 85°C -55 to 125°C Min. Min. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 4.95 9.95 14.95 3.5 7 11 1.5 3 4 -3.2 -1 -2.6 -6.8 1 2.6 6.8 ±0.1 5 7.5 0.05 0.05 0.05 1.5 3 4 V V 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 ±1 µA V 3.5 7 11 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 ±10-5 Max. 150 300 600 3000 0.05 0.05 0.05 3.5 7 11 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 Max. Unit V mA mA ±1 µA pF The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V 5/9 HCF4038B DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns) Test Condition Symbol Parameter tPHL tPLH Propagation Delay Time (A, B or Inverter Inputs to Sum Outputs) tPHL tPLH Propagation Delay Time (Clock Inputs to Sum Outputs) tTHL tTLH Transition Time thold fMAX tr, tf (1) Data Input Hold Time (clock edge to A, B, or reset inputs) Maximum Clock Input Frequency Clock Input Rise or Fall Time VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Value (*) Unit Min. Typ. Max. 520 240 180 650 350 300 200 100 80 200 80 60 2.5 5 7.5 260 120 90 325 175 150 100 50 40 120 50 40 4.5 10 15 ns ns ns ns MHz 500 500 500 µs (*) Typical temperature coefficient for all VDD value is 0.3 %/°C. (1) If more than one unit is cascaded tr should be made less than or equal to the sum of the transition time and the fixed propagation delay of the output of the driving state for the estimated capacitive load. TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200KΩ RT = ZOUT of pulse generator (typically 50Ω) 6/9 HCF4038B Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 7/9 HCF4038B SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.024 8° (max.) PO13H 8/9 HCF4038B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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