STMICROELECTRONICS IMSC011-E20S

IMS C011
)
Link adaptor
FEATURES
Standard INMOS link protocol
10 or 20 Mbits/sec operating speed
Communicates with transputers
Converts between serial link and parallel bus
Converts between serial link and parallel device
Two modes of parallel operation:
Mode 1: Peripheral interface
Eight bit parallel input interface
Eight bit parallel output interface
Full handshake on input and output
Mode 2: Bus interface
Tristate bidirectional bus interface
Memory mapped registers
Interrupt capability
Input
Interface
System
Services
Output
Interface
Link
8
8
Mode 1
Single +5V 5% power supply
TTL and CMOS compatibility
120mW power dissipation
28 pin 0.6” plastic package
Interrupt
Control
28 pin SOJ package
28 pin LCCC package
System
Services
Register
Select
Extended temperature version available
APPLICATIONS
Programmable I/O for transputer
Connecting microprocessors to transputers
Data and
Status
Registers
Link
8
High speed links between microprocessors
Inter-family microprocessor interfacing
Interconnecting different speed links
Mode 2
July 1995
42 1412 08
1/30
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
2 Pin designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
3 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
3.1
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
3.2
CapMinus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
3.3
ClockIn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
3.4
SeparateIQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
3.5
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
4 Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
5 Mode 1 parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
5.1
Input port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
5.2
Output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
6 Mode 2 parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
6.1
D0–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
6.2
notCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
6.3
RnotW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
6.4
RS0–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
6.5
InputInt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
6.6
OutputInt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
6.7
Data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
6.8
Data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
7 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
7.1
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
7.2
Equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
7.3
AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
7.4
Power rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
8 Package details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
8.1
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
8.2
28-pin plastic DIL package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
8.3
28-pin SOJ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
8.4
28-pin LCCC package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
8.5
Thermal specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
9 Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 / 30
29
1
Introduction
The INMOS communication link is a high speed system interconnect which provides full duplex communication between members of the transputer family, according to the INMOS serial link protocol. The
IMS C011, a member of this family, provides for full duplex transputer link communication with standard
microprocessor and sub-system architectures, by converting bi-directional serial link data into parallel
data streams.
All transputer products which use communication links, regardless of device type, support a standard communications frequency of 10 Mbits/sec; most products also support 20 Mbits/sec. Products of different
type or performance can, therefore, be interconnected directly and future systems will be able to communicate directly with those of today. The IMS C011 link will run at either the standard speed of 10 Mbits/sec
or at the higher speed of 20 Mbits/sec. Data reception is asynchronous, allowing communication to be independent of clock phase.
The link adaptor can be operated in one of two modes. In Mode 1 the IMS C011 converts between a link
and two independent fully handshaken byte-wide interfaces, one input and one output. It can be used by
a peripheral device to communicate with a transputer, a peripheral processor or another link adaptor, or
it can provide programmable input and output pins for a transputer. Two IMS C011 devices in this mode
can be connected back to back via the parallel ports and used as a frequency changer between different
speed links.
In Mode 2 the IMS C011 provides an interface between an INMOS serial link and a microprocessor system
bus. Status and data registers for both input and output ports can be accessed across the byte-wide
bi-directional interface. Two interrupt outputs are provided, one to indicate input data available and one
for output buffer empty.
VDD
GND
CapMinus
ClockIn
Reset
SeparateIQ
LinkOut
LinkIn
System
Services
Link
8
Input
Interface
Output
Interface
I0–7
IAck
IValid
Q0–7
8
Qack
QValid
Figure 1.1 IMS C011 Mode 1 block diagram
VDD
GND
CapMinus
ClockIn
Reset
SeparateIQ
LinkSpeed
LinkOut
LinkIn
Interrupt
Control
InputInt
OutputInt
Register
Select
RS0
RS1
RnotW
notCS
System
Services
Link
Data and
Status
Registers
8
D0–7
Figure 1.2 IMS C011 Mode 2 block diagram
3 / 30
IMS C011
2
Pin designations
Signal names are prefixed by not if they are active low, otherwise they are active high.
Pinout details for various packages are given on page 24.
Pin
VDD, GND
CapMinus
ClockIn
Reset
SeparateIQ
LinkIn
LinkOut
In/Out
in
in
in
in
out
Function
Power supply and return
External capacitor for internal clock power supply
Input clock
System reset
Select mode and Mode 1 link speed
Serial data input channel
Serial data output channel
Table 2.1
Pin
I0-7
IValid
IAck
Q0-7
QValid
QAck
In/Out
in
in
out
out
out
in
Function
Parallel input bus
Data on I0-7 is valid
Acknowledge I0-7 data received by other link
Parallel output bus
Data on Q0-7 is valid
Acknowledge from device: data Q0-7 was read
Table 2.2
Pin
D0-7
notCS
RS0-1
RnotW
InputInt
OutputInt
LinkSpeed
HoldToGND
DoNotWire
In/Out
in/out
in
in
in
out
out
in
Mode 1 parallel interface
Function
Bi-directional data bus
Chip select
Register select
Read/write control signal
Interrupt on link receive buffer full
Interrupt on link transmit buffer empty
Select link speed as 10 or 20 Mbits/sec
Must be connected to GND
Must not be wired
Table 2.3
4 / 30
Services and link
Mode 2 parallel interface
3 System services
3
System services
System services include all the necessary logic to start up and maintain the IMS C011.
3.1
Power
Power is supplied to the device via the VDD and GND pins. The supply must be decoupled close to the
chip by at least one 100 nF low inductance (e.g. ceramic) capacitor between VDD and GND. Four layer
boards are recommended; if two layer boards are used, extra care should be taken in decoupling.
AC noise between VDD and GND must be kept below 200 mV peak to peak at all frequencies above
100 KHz. AC noise between VDD and the ground reference of load capacitances must be kept below
200 mV peak to peak at all frequencies above 30 MHz. Input voltages must not exceed specification with
respect to VDD and GND, even during power-up and power-down ramping, otherwise latchup can occur.
CMOS devices can be permanently damaged by excessive periods of latchup.
3.2
CapMinus
The internally derived power supply for internal clocks requires an external low leakage, low inductance
1F capacitor to be connected between VDD and CapMinus. A ceramic capacitor is preferred, with an
impedance less than 3 Ohms between 100 KHz and 10 MHz. If a polarised capacitor is used the negative
terminal should be connected to CapMinus. Total PCB track length should be less than 50 mm. The positive connection of the capacitor must be connected directly to VDD. Connections must not otherwise touch
power supplies or other noise sources.
VDD
VDD pin
P.C.B track
Decoupling
capacitor 1 F
Phase–locked
loops
CapMinus
P.C.B track
GND
Figure 3.1 Recommended PLL decoupling
3.3
ClockIn
Transputer family components use a standard clock frequency, supplied by the user on the ClockIn input.
The nominal frequency of this clock for all transputer family components is 5 MHz, regardless of device
type, transputer word length or processor cycle time. High frequency internal clocks are derived from
ClockIn, simplifying system design and avoiding problems of distributing high speed clocks externally.
A number of transputer family devices may be connected to a common clock, or may have individual clocks
providing each one meets the specified stability criteria. In a multi-clock system the relative phasing of
ClockIn clocks is not important, due to the asynchronous nature of the links. Mark/space ratio is unimportant provided the specified limits of ClockIn pulse widths are met.
Oscillator stability is important. ClockIn must be derived from a crystal oscillator; RC oscillators are not
sufficiently stable. ClockIn must not be distributed through a long chain of buffers. Clock edges must be
monotonic and remain within the specified voltage and time limits.
5 / 30
IMS C011
Symbol
Parameter
Min
TDCLDCH
ClockIn pulse width low
TDCHDCL
ClockIn pulse width high
TDCLDCL
ClockIn period
TDCerror
ClockIn timing error
TDC1DC2
Nom
Max
Units
Notes
40
ns
1
40
ns
1
ns
1,2,4
0.5
ns
1,3
Difference in ClockIn for 2 linked devices
400
ppm
1,4
TDCr
ClockIn rise time
10
ns
1,5
TDCf
ClockIn fall time
8
ns
1,5
200
Notes
1 Guaranteed, but not tested.
2 Measured between corresponding points on consecutive falling edges.
3 Variation of individual falling edges from their nominal times.
4 This value allows the use of 200ppm crystal oscillators for two devices connected together by
a link.
5 Clock transitions must be monotonic within the range VIH to VIL (table 7.3).
Table 3.1
Input clock
TDCerror
TDCerror
TDCerror
TDCerror
2.0V
1.5V
0.8V
TDCLDCH
TDCHDCL
TDCLDCL
90%
90%
10%
10%
TDCf
Figure 3.2
3.4
TDCr
ClockIn timing
SeparateIQ
The IMS C011 link adaptor has two different modes of operation. Mode 1 is basically a link to peripheral
adaptor, whilst Mode 2 interfaces between a link and a microprocessor bus system.
Mode 1 can be selected for one of two link speeds by connecting SeparateIQ to VDD (10 Mbits/sec) or
to ClockIn (20 Mbits/sec).
Mode 2 is selected by connecting SeparateIQ to GND; in this mode 10 Mbits/sec or 20 Mbits/sec is selected by LinkSpeed. Link speeds are specified for a ClockIn frequency of 5 MHz.
In order to select the link speed, SeparateIQ may be changed dynamically providing the link is in a quiescent state and no input or output is required. Reset must be applied subsequent to the selection to initialise
6 / 30
3 System services
the device. If ClockIn is gated to achieve this, its skew must be limited to the value TDCHSIQH shown
in table 3.3. The mode of operation (Mode 1, Mode 2) must not be changed dynamically.
SeparateIQ
Mode
Link Speed Mbits/sec
VDD
1
10
ClockIn
1
20
GND
2
10 or 20
Table 3.2
SeparateIQ mode selection
Symbol
Parameter
Min
TDCHSIQH
Skew from ClockIn to ClockIn
Nom
Max
Units
Notes
20
ns
1
Notes
1 Skew between ClockIn arriving on the ClockIn pin and on the SeparateIQ pin.
Table 3.3
3.5
SeparateIQ
Reset
The Reset pin can go high with VDD, but must at no time exceed the maximum specified voltage for VIH.
After VDD is valid ClockIn should be running for a minimum period TDCVRL before the end of Reset. All
inputs, with the exception of ClockIn and SeparateIQ (plus LinkSpeed in mode 2), must be held in their
inactive state during reset.
Reset initialises the IMS C011 to the following state: LinkOut is held low; the control outputs (IAck and
QValid in Mode 1, InputInt and OutputInt in Mode 2) are held low; interrupts (Mode 2) are disabled; the
states of Q0-7 in Mode 1 are unspecified; D0-7 in Mode 2 are high impedance.
Symbol
Parameter
Min
Nom
Max
Units
Notes
TPVRH
Power valid before Reset
10
ms
TRHRL
Reset pulse width high
8
ClockIn
1
TDCVRL
ClockIn running before Reset end
10
ms
2
TRLIvH
Reset low before IValid high (mode 1)
0
ns
TRLCSL
Reset low before chip select low (mode 2)
0
ns
Notes
1 Full periods of ClockIn TDCLDCL required.
2 At power-on reset.
Table 3.4
Reset
7 / 30
IMS C011
ClockIn
TDCVRL
VDD
TPVRH
TRHRL
Reset
TRLIvH
IValid
TRLCSL
notCS
Figure 3.3 Reset timing
8 / 30
4 Links
4
Links
INMOS bi-directional serial links provide synchronized communication between transputer products and
with the outside world. Each link comprises an input channel and output channel. A link between two devices is implemented by connecting a link interface on one device to a link interface on the other device.
Every byte of data sent on a link is acknowledged on the input of the same link, thus each signal line carries
both data and control information.
The quiescent state of a link output is low. Each data byte is transmitted as a high start bit followed by a
one bit followed by eight data bits followed by a low stop bit. The least significant bit of data is transmitted
first. After transmitting a data byte the sender waits for the acknowledge, which consists of a high start bit
followed by a zero bit. The acknowledge signifies both that a process was able to receive the acknowledged data byte and that the receiving link is able to receive another byte.
Links are not synchronised with ClockIn and are insensitive to its phase. Thus links from independently
clocked systems may communicate, providing only that the clocks are nominally identical and within specification.
Links are TTL compatible and intended to be used in electrically quiet environments, between devices on
a single printed circuit board or between two boards via a backplane. Direct connection may be made between devices separated by a distance of less than 300 millimetres. For longer distances a matched
100 ohm transmission line should be used with series matching resistors RM. When this is done the line
delay should be less than 0.4 bit time to ensure that the reflection returns before the next data bit is sent.
Buffers may be used for very long transmissions. If so, their overall propagation delay should be stable
within the skew tolerance of the link, although the absolute value of the delay is immaterial.
The IMS C011 link supports the standard INMOS communication speed of 10 Mbits/sec. In addition it can
be used at 20 Mbits/sec. Link speed can be selected in one of two ways. In Mode 1 it is altered by SeparateIQ (page 6). In Mode 2 it is selected by LinkSpeed; when the LinkSpeed pin is low, the link operates
at the standard 10 Mbits/sec; when high it operates at 20 Mbits/sec.
H
H
0
1
2
3
4
5
6
7
L
Data
H
L
Ack
Figure 4.1 IMS C011 link data and acknowledge packets
9 / 30
IMS C011
Symbol
Parameter
TJQr
Min
Nom
Max
Units
Notes
LinkOut rise time
20
ns
1
TJQf
LinkOut fall time
10
ns
1
TJDr
LinkIn rise time
20
ns
1
TJDf
LinkIn fall time
20
ns
1
TJQJD
Buffered edge delay
TJBskew
Variation in TJQJD
0
ns
20 Mbits/s
3
ns
2
10 Mbits/s
10
ns
2
@ f=1MHz
7
pF
1
50
pF
CLIZ
LinkIn capacitance
CLL
LinkOut load capacitance
RM
Series resistor for 100W transmission line
56
ohms
Notes
1 Guaranteed, but not tested.
2 This is the variation in the total delay through buffers, transmission lines, differential receivers
etc., caused by such things as short term variation in supply voltages and differences in delays
for rising and falling edges.
Table 4.1 Link
90%
LinkOut
10%
TJQr
TJQf
90%
LinkIn
10%
TJDr
Figure 4.2 IMS C011 link timing
LinkOut
1.5 V
Latest TJQJD
Earliest TJQJD
LinkIn
1.5 V
TJBskew
Figure 4.3 IMS C011 buffered link timing
10 / 30
TJDf
4 Links
Transputer family device A
LinkOut
LinkIn
LinkIn
LinkOut
Transputer family device B
Figure 4.4 Links directly connected
Transputer family device A
LinkOut
LinkIn
RM
Zo=100 ohms
LinkIn
LinkOut
Zo=100 ohms
RM
Transputer family device B
Figure 4.5 Links connected by transmission line
Transputer family device A
LinkOut
LinkIn
buffers
LinkIn
LinkOut
Transputer family device B
Figure 4.6 Links connected by buffers
11 / 30
IMS C011
5
Mode 1 parallel interface
In Mode 1 the IMS C011 link adaptor is configured as a parallel peripheral interface with handshake lines.
Communication with a transputer family device is via the serial link. The parallel interface comprises an
input port and an output port, both with handshake.
5.1
Input port
The eight bit parallel input port I0-7 can be read by a transputer family device via the serial link. IValid and
IAck provide a simple two-wire handshake for this port. When data is valid on I0-7, IValid is taken high
by the peripheral device to commence the handshake. The link adaptor transmits data presented on I0-7
out through the serial link. After the data byte transmission has been completed and an acknowledge packet is received on the input link, the IMS C011 sets IAck high. To complete the handshake, the peripheral
device must return IValid low. The link adaptor will then set IAck low. New data should not be put onto
I0-7 until IAck is returned low.
Symbol
Parameter
Min
Nom
Max
Units
TIdVIvH
Data setup
5
TIvHLdV
IValid high to link data output
TLaVIaH
Link acknowledge start to IAck high
TIaHIdX
Data hold after IAck high
0
ns
TIaHIvL
IValid hold after IAck high
0
ns
TIvLIaL
IAck hold after IValid low
0.8
TIaLIvH
Delay before next IValid high
Notes
ns
0.8
2.5
bits
1,2
3.5
bits
1,3
3
bits
0
1
ns
Notes
1 Unit of measurement is one link data bit time; at 10 Mbits/s data link speed, one bit time is nominally 100 ns.
2 Maximum time assumes there is no acknowledge packet already on the link. Maximum time with
acknowledge on the link is extended by 2 bits.
3 Both data transmission and the returned acknowledge must be completed before IAck can go
high.
Table 5.1
Mode 1 parallel data input
I0–7
TIdVIvH
TIaHIdX
IValid
TIaHIvL
TIvLIaL
TIaLIvH
IAck
TIvHLdV
LinkOut
Data
TLaVIaH
LinkIn
Ack
Figure 5.1 IMS C011 Mode 1 parallel data input to link adaptor
12 / 30
5 Mode 1 parallel interface
5.2
Output port
The eight bit parallel output port Q0-7 can be controlled by a transputer family device via the serial link.
QValid and QAck provide a simple two-wire handshake for this port.
A data packet received on the input link is presented on Q0-7; the link adaptor then takes QValid high to
initiate the handshake. After reading data from Q0-7, the peripheral device sets QAck high. The IMS C011
will then send an acknowledge packet out of the serial link to indicate a completed transaction and set
QValid low to complete the handshake.
Symbol
Parameter
Min
TLdVQvH
Start of link data to QValid
TQdVQvH
Nom
Max
Units
Notes
11.5
bits
1
Data setup
12
ns
2
TQvHQaH
QAck setup time from QValid high
0
ns
TQaHQvL
QAck high to QValid low
1.8
bits
1
TQaHLaV
QAck high to Ack on link
0.8
bits
1,3
TQvLQaL
QAck hold after QValid low
0
ns
TQvLQdX
Data hold
11
bits
2.5
1,4
Notes
1 Unit of measurement is one link data bit time; at 10 Mbits/s data link speed, one bit time is nominally 100 ns.
2 Where an existing data output bit is re-written with the same level there will be no glitch in the
output level.
3 Maximum time assumes there is no data packet already on the link. Maximum time with data on
the link is extended by 11 bits.
4 Data output remains valid until overwritten by new data.
Table 5.2
LinkIn
Mode 1 parallel data output
Data
Data
Q0–7
TLdVQvH
TQdVQvH
TQvLQdX
QValid
TQaHQvL
TQvHQaH
TQvLQaL
QAck
TQaHLaV
LinkOut
Ack
Figure 5.2 IMS C011 Mode 1 parallel data output from link adaptor
13 / 30
IMS C011
6
Mode 2 parallel interface
The IMS C011 provides an interface between a link and a microprocessor style bus. Operation of the link
adaptor is controlled through the parallel interface bus lines D0-7 by reading and writing various registers
in the link adaptor. Registers are selected by RS0-1 and RnotW, and the chip enabled with notCS.
For convenience of description, the device connected to the parallel side of the link adaptor is presumed
to be a microprocessor, although this will not always be the case.
6.1
D0–7
Data is communicated between a microprocessor bus and the link adaptor via the bidirectional bus lines
D0-7. The bus is high impedance unless the link adaptor chip is selected and the RnotW line is high. The
bus is used by the microprocessor to access status and data registers.
6.2
notCS
The link adaptor chip is selected when notCS is low. Register selectors RS0-1 and RnotW must be valid
before notCS goes low; D0-7 must also be valid if writing to the chip (RnotW low). Data is read by the link
adaptor on the rising edge of notCS.
6.3
RnotW
RnotW, in conjunction with notCS, selects the link adaptor registers for read or write mode. When RnotW
is high, the contents of an addressed register appear on the data bus D0-7; when RnotW is low the data
on D0-7 is written into the addressed register.The state of RnotW is latched into the link adaptor by notCS
going low; it may be changed before notCS returns high, within the timing restrictions given.
6.4
RS0–1
One of four registers is selected by RS0-1. A register is addressed by setting up RS0-1 and then taking
notCS low; the state of RnotW when notCS goes low determines whether the register will be read or written. The state of RS0-1 is latched into the link adaptor by notCS going low; it may be changed before
notCS returns high, within the timing restrictions given. The register set comprises a read-only data input
register, a write-only data output register and a read/write status register for each.
RS1
0
0
0
0
1
1
1
1
RS0
0
0
1
1
0
0
1
1
Table 6.1
6.4.1
RnotW
1
0
1
0
1
0
1
0
Register
Read data
Invalid
Invalid
Write data
Read input status
Write input status
Read output status
Write output status
IMS C011 Mode 2 register selection
Input Data Register
This register holds the last data packet received from the serial link. It never contains acknowledge packets. It contains valid data only whilst the data present flag is set in the input status register. It cannot be
assumed to contain valid data after it has been read; a double read may or may not return valid data on
the second read. If data present is valid on a subsequent read it indicates new data is in the buffer. Writing
to this register will have no effect.
14 / 30
6 Mode 2 parallel interface
Symbol
Parameter
Min
TRSVCSL
TCSLRSX
TRWVCSL
TCSLRWX
TCSLCSH
TCSHCSL
Register select setup
Register select hold
Read/write strobe setup
Read/write strobe hold
Chip select active
Delay before re-assertion of chip select
Table 6.2
Nom
Max
5
8
5
8
60
50
Units
Notes
ns
ns
ns
ns
ns
ns
IMS C011 Mode 2 parallel interface control
Symbol
Parameter
Min
TLdVIIH
TCSLIIL
TCSLDrX
TCSLDrV
TCSHDrZ
TCSHDrX
TCSHLaV
Start of link data to InputInt high
Chip select to InputInt low
Chip select to bus active
Chip select to data valid
Chip select high to bus tristate
Data hold after chip select high
Chip de-select to start of Ack
Nom
Max
Units
Notes
14
35
bits
ns
ns
ns
ns
ns
bits
1
5
50
38
5
0.8
2.5
1,2
Notes
1 Unit of measurement is one link data bit time; at 10 Mbits/s data link speed, one bit time is nominally 100 ns.
2 Maximum time assumes there is no data packet already on the link. Maximum time with data on
the link is extended by 11 bits.
Table 6.3
LinkIn
IMS C011 Mode 2 parallel interface read
Data
Data
TLdVIIH
InputInt
TCSLIIL
RS0–1
TRSVCSL
TCSLRSX
RnotW
TRWVCSL
TCSLRSX
TCSLCSH
TCSHCSL
notCS
TCSLDrV
TCSLDrX
TCSHDrZ
TCSHDrX
D0–7
TCSHLaV
LinkOut
Ack
Figure 6.1 IMS C011 Mode 2 read parallel data from link adaptor
15 / 30
IMS C011
Symbol
Parameter
Min
Nom
Max
Units
TCSHDwV
Data setup
10
ns
TCSHDwX
Data hold
10
ns
TCSLOIL
Chip select to OutputInt low
TCSHLdV
Chip select high to start of link data
TLaVOIH
TLdVOIH
Notes
35
ns
2.5
bits
1,2
Start of link Ack to OutputInt high
3.3
bits
1,3
Start of link data to OutputInt high
13
bits
1,3
0.8
Notes
1 Unit of measurement is one link data bit time; at 10 Mbits/s data link speed, one bit time is nominally 100 ns.
2 Maximum time assumes there is no acknowledge packet already on the link. Maximum time with
acknowledge on the link is extended by 2 bits.
3 Both data transmission and the returned acknowledge must be completed before OutputInt can
go high.
Table 6.4
IMS C011 Mode 2 parallel interface write
RS0–1
TRSVCSL
TCSLRSX
RnotW
TRWVCSL
TCSLRWX
TCSLCSH
TCSHCSL
notCS
TCSHDwV
TCSHDwX
D0–7
TCSLOIL
OutputInt
TCSHLdV
LinkOut
TLdVOIH
Data
TLaVOIH
LinkIn
Ack
Figure 6.2 IMS C011 Mode 2 write parallel data to link adaptor
16 / 30
6 Mode 2 parallel interface
6.4.2
Input Status Register
This register contains the data present flag and the interrupt enable control bit for InputInt. The data present flag is set to indicate that data in the data input buffer is valid. It is reset low only when the data input
buffer is read, or by Reset. When writing to this register, the data present bit must be written as zero.
The interrupt enable bit can be set and reset by writing to the status register with this bit high or low respectively. When the interrupt enable and data present flags are both high, the InputInt output will be high (section 6.5). Resetting interrupt enable will take InputInt low; setting it again before reading the data input
register will set InputInt high again. The interrupt enable bit can be read to determine its status.
When writing to this register, bits 2-7 must be written as zero; this ensures that they will be zero when the
register is read. Failure to write zeroes to these bits may result in undefined data being returned by these
bits during a status register read.
7
6
5
4
3
2
1
0
Interrupt
Data
Enable Present
InputInt
&
Figure 6.3 IMS C011 Mode 2 input status register
6.4.3
Output Data Register
Data written to this link adaptor register is transmitted out of the serial link as a data packet. Data should
only be written to this register when the output ready bit in the output status register is high, otherwise data
already being transmitted may be corrupted. Reading this register will result in undefined data being read.
6.4.4
Output Status Register
This register contains the output ready flag and the interrupt enable control bit for OutputInt. The output
ready flag is set to indicate that the data output buffer is empty and a link acknowledge has been received.
It is reset low only when data is written to the data output buffer; it is set high by Reset. When writing to
this register, the output ready bit must be written as zero.
The interrupt enable bit can be set and reset by writing to the status register with this bit high or low respectively. When the interrupt enable and output ready flags are both high, the OutputInt output will be high
(section 6.6). Resetting interrupt enable will take OutputInt low; setting it again whilst the data output register is empty will set OutputInt high again. The interrupt enable bit can be read to determine its status.
When writing to this register, bits 2-7 must be written as zero; this ensures that they will be zero when the
register is read. Failure to write zeroes to these bits may result in undefined data being returned by these
bits during a status register read.
6.5
InputInt
The InputInt output is set high to indicate that a data packet has been received from the serial link. It is
inhibited from going high when the interrupt enable bit in the input status register is low (section 6.4.2).
InputInt is reset low when data is read from the input data register (section 6.4.1) and by Reset (page 7).
17 / 30
IMS C011
7
6
5
4
3
2
1
0
Interrupt
Enable
Output
Ready
OutputInt
&
Figure 6.4 IMS C011 Mode 2 output status register
6.6
OutputInt
The OutputInt output is set high to indicate that the link is free to receive data from the microprocessor
for transmission as a data packet out of the serial link. It is inhibited from going high when the interrupt
enable bit in the output status register is low (section 6.4.4). OutputInt is reset low when data is written
to the data output register; it is set low by Reset (page 7).
6.7
Data read
A data packet received on the input link sets the data present flag in the input status register.If the interrupt
enable bit in the status register is set, the InputInt output pin will be set high. The microprocessor will either
respond to the interrupt (if the interrupt enable bit is set) or will periodically read the input status register
until the data present bit is high.
When data is available from the link, the microprocessor reads the data packet from the data input register.
This will reset the data present flag and cause the link adaptor to transmit an acknowledge packet out of
the serial link output. InputInt is automatically reset by reading the data input register; it is not necessary
to read or write the input status register.
6.8
Data write
When the data output buffer is empty and a link acknowledge has been received the output ready flag in
the output status register is set high. If the interrupt enable bit in the status register is set, the OutputInt
output pin will also be set high. The microprocessor will either respond to the interrupt (if the interrupt enable bit is set) or will periodically read the output status register until the output ready bit is high.
When the output ready flag is high, the microprocessor can write data to the data output buffer. This will
result in the link adaptor resetting the output ready flag and commencing transmission of the data packet
out of the serial link. The output ready status bit will remain low until the data byte transmission has been
completed and an acknowledge packet is received by the input link. This will set the output ready flag high;
if the interrupt enable bit is set, OutputInt will also be set high.
18 / 30
7 Electrical specifications
7
Electrical specifications
7.1
DC electrical characteristics
SYMBOL
PARAMETER
VDD
DC supply voltage
VI, VO
Voltage on input and output pins
II
Input current
tOSC
Output short circuit time (one pin)
MIN
MAX
UNITS
NOTES
0
7.0
V
1,2,3
–0.5
VDD+0.5
V
1,2,3
25
mA
4
1
s
2
2
2
TS
Storage temperature
–65
150
oC
TA
Ambient temperature under bias
–55
125
oC
PDmax
Maximum allowable dissipation
600
mW
Notes
1 All voltages are with respect to GND.
2 This is a stress rating only and functional operation of the device at these or any other conditions
beyond those indicated in the operating sections of this specification is not implied. Stresses
greater than those listed may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
3 This device contains circuitry to protect the inputs against damage caused by high static voltages
or electrical fields. However, it is advised that normal precautions be taken to avoid application
of any voltage higher than the absolute maximum rated voltages to this high impedance circuit.
Unused inputs should be tied to an appropriate logic level such as VDD or GND.
4 The input current applies to any input or output pin and applies when the voltage on the pin is
between GND and VDD.
Table 7.1
SYMBOL
PARAMETER
VDD
DC supply voltage
VI, VO
Input or output voltage
CL
Load capacitance on any pin
TA
Absolute maximum ratings
Operating temperature range
MIN
MAX
UNITS
NOTES
4.75
5.25
V
1
0
VDD
V
1,2
0
60
pF
70
oC
3
Notes
1 All voltages are with respect to GND.
2 Excursions beyond the supplies are permitted but not recommended; see DC characteristics.
3 Air flow rate 400 linear ft/min transverse air flow.
Table 7.2
Operating conditions
19 / 30
IMS C011
SYMBOL
PARAMETER
MIN
MAX
UNITS
NOTES
VIH
High level input voltage
2.0§
VDD+0.5
V
1, 2
VIL
Low level input voltage
–0.5
0.8
V
1, 2
II
Input current
10
mA
1, 2, 3
200
mA
1, 2, 4
V
1, 2
0.4
V
1, 2
10
mA
1, 2
120
mW
2, 5
7
pF
6
10
pF
6
@ GND<VI<VDD
VOH
Output high voltage
@ IOH=2mA
VOL
Output low voltage
@ IOL=4mA
IOZ
Tristate output current
PD
Power dissipation
CIN
Input capacitance
@ f=1MHz
COZ
Output capacitance
@ f=1MHz
VDD–1
@ GND<V0<VDD
§For RnotW, RS0-1, SeparateIQ over temperature range
tute 2.2V.
–40<TA<25oC
(where applicable), substi-
Notes
1 All voltages are with respect to GND.
2 Parameters for IMS C011 measured at 4.75V<VDD<5.25V and 0oC<TA<70oC.
3 For inputs other than those in Note 4.
4 For pins 2, 3, 5, 6, 7, 9, 11, 13, 15, 16, 25.
5 Power dissipation varies with output loading.
6 Guaranteed, but not tested.
Table 7.3
7.2
DC characteristics
Equivalent circuits
IOL
1.5V
D.U.T.
1MW
50pF
IOH
GND
Note: This circuit represents the device sinking IOL and sourcing IOH with a 50pF capacitive load.
Figure 7.1 Load circuit for AC measurements
20 / 30
7 Electrical specifications
VDD–1
Inputs
VIH
0V
VDD–1
Inputs
0V
VIL
tpHL
VDD
1.5V
Outputs
0V
tpLH
VDD
Outputs
1.5V
0V
Figure 7.2 AC measurements timing waveforms
7.3
AC timing characteristics
SYMBOL
PARAMETER
MIN
MAX
UNITS
NOTES
TDr
Input rising edges
2
20
ns
1, 2, 3
TDf
Input falling edges
2
20
ns
1, 2, 3
TQr
Output rising edges
25
ns
1, 3
TQf
Output falling edges
15
ns
1, 3
Notes
1 Non-link pins; see section on links.
2 All inputs except ClockIn; see section on ClockIn.
3 Guaranteed, but not tested.
Table 7.4
Input and output edges
21 / 30
IMS C011
90%
90%
10%
10%
TDf
TDr
90%
90%
10%
10%
TQf
TQr
Figure 7.3 IMS C011 input and output edge timing
1.5 V
1.5 V
TCSHDrHZ
TCSHDrLZ
90%
10%
Figure 7.4 IMS C011 tristate timing relative to notCS
30
30
Rise time
20
Time
ns
10
Fall time
Rise time
Time
ns
20
10
Fall time
40
60
80 100
Load capacitance pF
Link
Figure 7.5 Typical rise/fall times
22 / 30
40
60
80 100
Load capacitance pF
Non Links
7 Electrical specifications
7.4
Power rating
Internal power dissipation (PINT) of transputer and peripheral chips depends on VDD, as shown in
figure 7.6. PINT is substantially independent of temperature.
200
150
Power
PINT
(mW)
100
50
4.4
4.6
4.8
5.0
5.2
5.4
5.6
VDD (Volts)
Figure 7.6 IMS C011 internal power dissipation vs VDD
Total power dissipation (PD) of the chip is
PD = PINT + PIO
where PIO is the power dissipation in the input and output pins; this is application dependent.
Internal working temperature TJ of the chip is
TJ = TA + qJA * PD
where TA is the external ambient temperature in oC and q JA is the junction-to-ambient thermal resistance
in oC/W.
Information about device thermal management can be found in the following SGS-THOMSON catalogues, available from SGS-THOMSON sales offices and authorized distributors worldwide.
1 Thermal Management in Surface Mount Technology, order code: BRTHERMAN/0788
2 Reliability in Surface Mount Technology, order code: BRRELSMT/1088
23 / 30
IMS C011
8
Package details
8.1
Package pinouts
Figure 8.1 IMS C011 package pinouts
24 / 30
8 Package details
8.2
28-pin plastic DIL package dimensions
Figure 8.2 IMSC011 28-pin plastic dual-in-line package dimensions
25 / 30
IMS C011
8.3
28-pin SOJ package dimensions
Figure 8.3 IMSC011 28-pin SOJ package dimensions
26 / 30
8 Package details
8.4
28-pin LCCC package dimensions
Figure 8.4 IMSC011 28-lead chip carrier (LCC) package dimensions
27 / 30
IMS C011
8.5
Thermal specification
The IMS C011 is tested to a maximum silicon temperature of 100_C. For operation within the given specifications, the case temperature should not exceed 85_C.
For temperatures above 85_C the operation of the device cannot be guaranteed and reliability may be
impaired.
For further information on reliability refer to the SGS–THOMSON Microelectronics Quality and Reliability
Program.
28 / 30
9 Ordering
9
Ordering
This section indicates the designation of package selections for the IMS C011. Speed of ClockIn is 5 MHz
for all parts.
For availability contact your local SGS–THOMSON sales office or authorized distributor.
SGS–THOMSON designation
Package
IMS C011-P20S
28 pin plastic dual-in-line
IMS C011-E20S
28 pin SOJ
IMS C011-W20S
28 pin LCCC non-solder dip
Table 9.1
IMS C011 ordering details
An extended temperature version is available, see the IMS C011E Datasheet for details.
29 / 30
IMS C011
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no
responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This
publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics.
E
,
1995 SGS-THOMSON Microelectronics - All Rights Reserved
, IMS, occam and DS-Link are trademarks of SGS-THOMSON Microelectronics Limited.
is a registered trademark of the SGS-THOMSON Microelectronics Group.
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
30 / 30