INTEGRATED CIRCUITS SC68C562 CMOS dual universal serial communications controller (CDUSCC) Product specification Supersedes data of 1994 Apr 27 IC19 Data Handbook 1998 Sep 04 Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) SC68C562 • 0 to 10MHz data rate • Programmable bit rate for each receiver and transmitter selectable DESCRIPTION The Philips Semiconductors SC68C562 Dual Universal Serial Communications Controller (CDUSCC) is a single-chip CMOS-LSI communications device that provides two independent, multi-protocol, full-duplex receiver/transmitter channels in a single package. It supports bit-oriented and character-oriented (byte count and byte control) synchronous data link controls as well as asynchronous protocols. The SC68C562 interfaces to the 68000 MPUs via asynchronous bus control signals and is capable of program-polled, interrupt driven, block-move or DMA data transfers. from: – 19 fixed rates: 50 to 64k baud – One user-defined rate derived from programmable counter/timer – External 1X or 16X clock – Digital phase-locked loop • Parity and FCS (frame check sequence LRC or CRC) generation The SC68C562 is hardware (pin) and software (Register) compatible with SCN68562 (NMOS version). It will automatically configure to NMOS DUSCC register map on power-up or reset. and checking • Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1, Manchester The operating mode and data format of each channel can be programmed independently. Each channel consists of a receiver, a transmitter, a 16-bit multifunction counter/timer, a digital phase-locked loop (DPLL), a parity/CRC generator and checker, and associated control circuits. The two channels share a common bit rate generator (BRG), operating directly from a crystal or an external clock, which provides 16 common bit rates simultaneously. The operating rate for the receiver and transmitter of each channel can be independently selected from the BRG, the DPLL, the counter/timer, or from an external 1X or 16X clock. • Programmable channel mode: full- and half-duplex, auto-echo, or local loopback • Programmable data transfer mode: polled, interrupt, DMA, wait • DMA interface – Compatible with the Philips Semiconductors SCB68430 Direct Memory Access Interface (DMAI) and other DMA controllers – Single- or dual-address dual transfers – Half- or full-duplex operation This makes the CDUSCC well suited for dual speed channel applications. Data rates up to 10Mb/s are supported. – Automatic frame termination on counter/timer terminal count or DMA DONE • Transmit path clear status • Interrupt capabilities Each transmitter and each receiver is serviced by a 16 byte FIFO. The receiver FIFO also stores 9 status bits for each character received; the transmit FIFO is able to store transmitter commands with each byte. This permits reading and writing of up to 16 bytes at a time, thus minimizing the – Daisy chain option – Vector output (fixed or modified by status) potential for transmitter underrun, receiver overrun and reducing interrupt or DMA overhead. – Programmable internal priorities In addition, a flow control capability is provided to disable a remote transmitter when the FIFO of the local receiving device is full. Two modem control inputs (DCD and CTS) and three modem control outputs (RTS and two general purpose) are provided. Because the modem control inputs are general purpose in nature, they can be optionally programmed for other functions. This document contains the electrical specifications for the SC68C562. Refer to the CMOS Dual Universal Serial Communications Controller (CDUSCC) User Manual for a complete operational description of this product. – Maskable interrupt conditions – Interrupt at any FIFO fill level • FIFO’d status bits • Watchdog timer • Multi-function programmable 16-bit counter/timer – Bit rate generator – Event counter – Count received or transmitted characters – Delay generator – Automatic bit length measurement FEATURES • Modem controls • Full hardware and software upward compatibility with previous NMOS device – RTS, CTS, DCD, and up to four general I/O pins per channel – CTS and DCD programmable auto-enables for Tx and Rx General Features – Programmable interrupt on change of CTS or DCD • Dual full-duplex synchronous/ asynchronous receiver and • On-chip oscillator for crystal • TTL compatible • Single +5V power supply transmitter • Low power CMOS process • Multiprotocol operation – BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level, etc. Asynchronous Mode Features • Character length: 5 to 8 bits • Odd or even parity, no parity, or force parity • Up to two stop bits programmable in 1/16-bit increments – COP: BISYNC, DDCMP – ASYNC: 5–8 bits plus optional parity • Sixteen character receiver and transmitter FIFOs 1998 Sep 04 2 853-1682 19973 Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) • 1X or 16X Rx and Tx clock factors • Parity, overrun, and framing error detection • False start bit detection • Start bit search 1/2-bit time after framing error detection • Break generation with handshake for counting break characters • Detection of start and end of received break • Character compare with optional interrupt on match • Transmits up to 10Mb/s at 1X and receive up to 1Mb/s at 16X SC68C562 • Auto transparent mode switching • Auto hunt after receipt of EOM sequence (with closing PAD check after EOT or NAK) • Control character sequence detection for both transparent and normal text Bit-Oriented Protocol Features • Character length: 5 to 8 bits • Detection and transmission of residual character: 0–7 bits • Automatic switch to programmed character length for I field • Zero insertion and deletion • Optional opening PAD transmission • Detection and generation of FLAG, ABORT, and IDLE bit patterns • Detection and generation of shared (single) FLAG between data rates Character-Oriented Protocol Features • Character length: 5 to 8 bits • Odd or even parity, no parity, or force parity • LRC or CRC generation and checking • Optional opening PAD transmission • One or two SYN characters • External sync capability • SYN detection and optional stripping • SYN or MARK line fill on underrun • Idle in MARK or SYNs • Parity, FCS, overrun, and underrun error detection frames • Detection of overlapping (shared zero) FLAGs • ABORT, ABORT-FLAGs, or FCS FLAGs line fill on underrun • Idle in MARK or FLAGs • Secondary address recognition including group and global address • Single- or dual-octet secondary address • Extended address and control fields • Short frame rejection for receiver • Detection and notification of received end of message • CRC generation and checking • SDLC loop mode capability BISYNC Features • EBCDIC or ASCII header, text and control messages • SYN, DLE stripping • EOM (end of message) detection and transmission ORDERING INFORMATION VCC = +5V ±10%, TA = 0 to +70°C VCC = +5V ±10%, TA = –40 to +85°C Serial Data Rate = 10Mbps Maximum Serial Data Rate = 8Mbps Maximum 48-Pin Plastic Dual In-Line Package (DIP) SC68C562C1N Not available SOT240-1 52-Pin Plastic Leaded Chip Carrier (PLCC) Package SC68C562C1A SC68C562A8A SOT238-3 DESCRIPTION DWG # ABSOLUTE MAXIMUM RATINGS1 SYMBOL PARAMETER RATING COMMERCIAL INDUSTRIAL UNIT TA Operating ambient temperature2 0 to +70 -40 to +85 °C TSTG Storage temperature -65 to +150 -65 to +150 °C VCC Voltage from VCC to GND3 –0.5 to +7.0 –0.5 to +7.0 V VS Voltage from any pin to ground3 –0.5 to VCC +0.5 –0.5 to VCC +0.5 V 1998 Sep 04 3 Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) SC68C562 PIN CONFIGURATIONS IACKN 1 48 VDD A3 2 47 A4 A2 3 46 A5 A1 4 45 A6 RTxDAKBN/ GPI1BN 5 44 RTxDAKAN/ GPI1AN IRQN 6 43 X1/CLK RESETN 7 42 X2/IDCN RTSBN/ SYNOUTBN 8 41 RTSAN/ SYNOUTAN TRxCB 9 40 TRxCA RTxCB 10 39 RTxCA 38 DCDAN/ SYNIAN 37 Rxda DCDBN/ 11 SYNIBN RxDB 12 TxDB 13 7 47 1 8 46 PLCC 34 20 21 Pin Function 1 2 3 4 5 6 7 8 9 36 TxDA 14 35 15 34 16 33 TxDAKAN/ GPI2AN RTxDRQAN/ GPO1AN TxDRQAN/ GPO2AN/RTSAN 17 32 CTSAN/LCAN D7 18 31 D0 13 14 15 16 D6 19 30 D1 17 D5 20 29 D2 18 D4 21 28 D3 DTACKN 22 27 DONEN DTCN 23 26 R/WN GND 24 25 CSN 19 20 21 22 23 24 25 26 TxDAKBN/ GPI2BN RTxDRQBN/ GPO1BN TxDRQBN/ GPO2BN/RTSBN CTSBN/LCBN 1998 Sep 04 DIP A PACKAGE INDEX CORNER N PACKAGE 10 11 12 4 33 TOP VIEW Pin Function IACKN A3 A2 A1 RTxDAKBN/ GPI1BN IRQN NC RESETN RTSBN/ SYNOUTBN TRxCB RTxCB DCDBN/ SYNIBN NC RxDB TxDB TxDAKBN/ GPI2BN RTxDRQBN/ GPO1BN TxDRQBN/ GPO2BN/RTSBN CTSBN/LCBN D7 D6 D5 D4 DTACKN DTCN GND 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 CSN R/WN DONEN D3 D2 D1 D0 NC CTSAN/LCAN TxDRQAN/ GPO2AN/RTSAN RTxDRQAN/ GPO1AN TxDAKAN/ GPI2AN TxDA RxDA NC DCDAN/ SYNIAN RTxCA TRxCA RTSAN/ SYNOUTAN X2/IDCN X1/CLK RTxDAKAN/ GPI1AN A6 A5 A4 VDD SD00222 Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) SC68C562 BLOCK DIAGRAM D0-D7 CHANNEL MODE AND TIMING A/B BUS BUFFER DPLL CLK MUX A/B DPLL A/B INTERFACE/ OPERATION CONTROL A7 CONTROL LOGIC DTACKN RWN A1-A6 CSN RESETN BRG ADDRESS DECODE MPU INTERFACE COUNTER/ TIMER A/B R/W DECODE C/T CLK MUX A/B DMA CONTROL CTPRHA/B CTCRA/B CTPRLA/B CCRA/B CTLA/B RSRA/B INTERNAL BUS TxDRQAN/GPO2AN TxDRQBN/GPO2BN RTxDAKAN/GPI1AN RTxDAKBN/GPI1BN CTHA/B PCRA/B RTxDRQAN/GPO1AN RTxDRQBN/GPO1BN TRSRA/B ICTSRA/B GSR DMA INTERFACE CMR1A/B TxDAKAN/GPI2AN TxDAKBN/GPI2BN DTCN DONEN CMR2A/B OMRA/B TRANS CLK MUX TPRA/B TRCR A/B TTRA/B FTLR A/B TX SHIFT REG TRMR A/B CID SPECIAL FUNCTION PINS TxD A/B TRANSMIT 16 DEEP FIFO TRxCA/B RTxCA/B RTSBN/SYNOUTBN RTSAN/SYNOUTAN CTSA/BN DCDBN/SYNIBN TRANSMIT A/B TELRA/B CONTROL DCDAN/SYNIAN CRC GEN SPEC CHAR GEN LOGIC RECEIVER A/B INTERRRUPT CONTROL RCVR CLK MUX ICRA/B RPRA/B IERA/B RTRA/B IRQN IACKN S1RA/B IVR S2RA/B RxD A/B IVRM IER1 RCVR SHIFT REG IER2 RECEIVER 16 DEEP FIFO IER3 RFLRA/B DUSCC LOGIC CRC ACCUM X1/CLK X2/IDCN BISYNC COMPARE LOGIC OSCILLATOR SD00253 1998 Sep 04 5 Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) SC68C562 PIN DESCRIPTION MNEMONIC PIN NO. TYPE NAME AND FUNCTION 4-2, 51-49 I Address Lines: Active-high. Address inputs which specify which of the internal registers is accessed for read/write operation. 31-28, 21-18 33-30, 23-20 I/O Bidirectional Data Bus: Active-high, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All data, command and status transfers between the CPU and the CDUSCC take place over this bus. The data bus is enabled when CSN and R/WN or during interrupt acknowledge cycles and single address DMA acknowledge cycles. R/WN 26 28 I Read/Write: A high input indicates a read cycle and a low indicates a write cycle when CEN is active. CSN 25 27 I Chip Select: Active-low input. When active, data transfers between the CPU and the CDUSCC are enabled on D0–D7 as controlled by R/WN and A1–A6 inputs. When CSN is high, the data lines are placed in the 3-State condition (except during interrupt acknowledge cycles and single address DMA transfers). IRQN 6 6 O Interrupt Request: Active-low, open-drain. This output is asserted upon occurrence of any enabled interrupting condition. The CPU can read the general status register to determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle to cause the CDUSCC to output an interrupt vector on the data bus. IACKN 1 1 I Interrupt Acknowledge: Active-low. When IACKN is asserted, the CDUSCC responds by either forcing the bus into high-impedance, placing a vector number, call instruction or zero on the data bus. The vector number can be modified or unmodified by the status. If no interrupt is pending, IACKN is ignored and the data bus placed in high-impedance. X1/CLK 43 47 I Crystal or External Clock: When using the crystal oscillator, the crystal is connected between pins X1 and X2. If a crystal is not used, an external clock is supplied at this input. This clock is used to drive the internal bit rate generator, as an optional input to the counter/timer or DPLL, and to provide other required clocking signals. When a crystal is used, a capacitor must be connected from this pin to ground. X2/IDCN 42 46 O Crystal or Interrupt Daisy Chain: When a crystal is used as the timing source, the crystal is connected between pins X1 and X2. This pin can be programmed to provide an interrupt daisy chain active-low output which propagates the IACKN signal to lower priority devices, if no active interrupt is pending. This pin should be left floating when an external clock is used on X1 and X2 is not used as an interrupt daisy chain output. When a crystal is used, a capacitor must be connected from this pin to ground. RESETN 7 8 I Master Reset: Active-low. A low on this pin resets the transmitters and receivers and resets the registers shown in Table 1 of the CDUSCC Users’ Guide. Reset is asynchronous, i.e., no clock is required. RxDA, RxDB 37, 12 40, 14 I Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If external receiver clock is specified for the channel, the input is sampled on the rising edge of the clock. TxDA, TxDB 36, 13 39, 15 O Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted first. This output is in the marking (high) condition when the transmitter is disabled or when the channel is operating in local loopback mode. If external transmitter clock is specified for the channel, the data is shifted on the falling edge of the clock. RTxCA, RTxCB 39, 10 43, 11 I/O Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer output, the transmitter shift clock (1X), or the receiver sampling clock (1X). TRxCA, TRxCB 40, 9 44, 10 I/O Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer output, the DPLL output, the transmitter shift clock (1X), the receiver sampling clock (1X), the transmitter BRG clock (16X), The receiver BRG clock (16X), or the internal system clock (X1 ÷ 2). CTSA/BN, LCA/BN 32, 17 35, 19 I/O Channel A (B) Clear-to-Send Input or Loop Control Output: Active-low. The signal can be programmed to act as an enable for the transmitter when not in loop mode. The CDUSCC detects logic level transitions on this input and can be programmed to generate an interrupt when a transition occurs. When operating in the BOP loop mode, this pin becomes a loop control output which is asserted and negated by CDUSCC commands. This output provides the means of controlling external loop interface hardware to go on-line and off-line without disturbing operation of the loop. DIP PLCC A1–A6 4-2, 47-45 D0–D7 1998 Sep 04 6 Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) SC68C562 PIN DESCRIPTION (Continued) MNEMONIC PIN NO. TYPE NAME AND FUNCTION 42, 12 I Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is programmable. As a DCD active-low input, it acts as an enable for the receiver or can be used as a general purpose input. For the DCD function, the CDUSCC detects logic level transitions on this pin and can be programmed to generate an interrupt when a transition occurs. As an active-low external sync input, it is used in COP mode to obtain character synchronization for the receiver without receipt of a SYN character. This mode can be used in disc or tape controller applications or for the optional byte timing lead in X.21. 34, 15 37, 17 O Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose Output: Active-low. For half-duplex DMA operation, this output indicates to the DMA controller that one or more characters are available in the receiver FIFO (when the receiver is enabled) or that the transmit FIFO is not full (when the transmitter is enabled). For full-duplex DMA operation, this output indicates to the DMA controller that data is available in the receiver FIFO. In non-DMA mode, this pin is a general purpose output that can be asserted and negated under program control. TxDRQA/BN, GPO2A/BN, RTSA/BN 33, 16 36, 18 O Channel A (B) Transmitter DMA Service Request, General Purpose Output, or Request-to-Send: Active-low. For full-duplex DMA operation, this output indicates to the DMA controller that the transmit FIFO is not full and can accept more data. When not in full-duplex DMA mode, this pin can be programmed as a general purpose or a Request-to-Send output, which can be asserted and negated under program control. RTxDAKA/BN, GPI1A/BN 44, 5 48, 5 I Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input: Active-low. For half-duplex single address operation, this input indicates to the CDUSCC that the DMA controller has acquired the bus and that the requested bus cycle (read receiver FIFO when the receiver is enabled or load transmitter FIFO when the transmitter is enabled) is beginning. For full-duplex single address DMA operation, this input indicates to the CDUSCC that the DMA controller has acquired the bus and that the requested read receiver FIFO bus cycle is beginning. Because the state of this input can be read under program control, it can be used as a general purpose input when not in single address DMA mode. TxDAKA/BN, GPI2A/BN 35, 14 38, 16 I Channel A (B) Transmitter DMA Acknowledge or General Purpose Input: Active-low. When the channel is programmed for full-duplex single address DMA operation, this input is asserted to indicate to the CDUSCC that the DMA controller has acquired the bus and that the requested load transmitter FIFO bus cycle is beginning. Because the state of this input can be read under program control, it can be used as a general purpose input when not in full-duplex single address DMA mode. 27 29 I/O Done: Active-low, open-drain. DONEN can be used and is active in both DMA and non-DMA modes. As an input, DONEN indicates the last DMA transfer cycle to the TxFIFO. As an output, DONEN indicates either the last DMA transfer from the RxFIFO or that the transmitted character count has reached terminal count. 41, 8 45, 9 O Channel A (B) Sync Detect or Request-to-Send: Active-low. If programmed as a sync output, it is asserted one bit time after the specified sync character (COP or BISYNC modes) or a FLAG (BOP modes) is detected by the receiver. As a Request-to-Send modem control signal, it functions as described previously for the TxDRQN/RTSN pin. DTACKN 22 24 O Data Transfer Acknowledge: Active-low, 3-state. DTACKN is asserted on a write cycle to indicate that the data on the bus has been latched, and on a read cycle or interrupt acknowledge cycle to indicate valid data is on the bus. In a write bus cycle, input data is latched by the assertion (falling edge) of DTACKN or by the negation (rising edge) of CSN, whichever occurs first. The signal is negated when completion of the cycle is indicated by negation of CSN or IACKN input, and returns to the inactive state (3-state) a short period after it is negated. In single address DMA mode, input data is latched by the assertion (falling edge) of DTCN or by the negation (rising edge) of the DMA acknowledge input, whichever occurs first. DTACK is negated when completion of the cycle is indicated by the assertion of DTCN or negation of DMA acknowledge inputs (whichever occurs first), and returns to the inactive state (3-state) a short period after it is negated. When inactive, DTACKN requires an external pull-up resistor. DTC 23 25 I Device Transfer Complete: Active-low. DTCN is asserted by the DMA controller to indicate that the requested data transfer is complete. VCC 48 34, 52 I +5V Power Input GND 24 26, 13, 41, 7 I Signal and Power Ground Input DIP PLCC DCDA/BN, SYNIA/BN 38, 11 RTxDRQA/BN, GPO1A/BN DONEN RTSA/BN, SYNOUTA/BN 1998 Sep 04 7 Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) SC68C562 DC ELECTRICAL CHARACTERISTICS4, 5 TA = 0 to +70°C, –40 to +85C, VCC = 5.0V 10% SYMBOL VIL VIH VOL VOH PARAMETER Input low voltage: All except X1/CLK X1/CLK Input high voltage: All except X1/CLK X1/CLK Output low voltage:14 All except IRQN IRQN7 Output high voltage:14 (Except open drain outputs) IILX1 IIHX1 ISCX2 X1/CLK input low current10 X1/CLK input high current10 X2 short circuit current (X2 mode) IIL Input low current RESETN, DTCN, TxDAKA/BN, RTxDAKA/BN TEST CONDITIONS 0 to 70C –40 to 85C IOL = 5.3mA (Comm), 4.8mA (Indus) IOL = 8.8mA (Comm), 7.8mA (Indus) IOH = -400µA VIN = 0, X2 = GND VIN = VCC, X2 = GND X1 open VIN = 0 VIN = VCC VCC V V V V V 0.5 0.5 V V V VCC–0.5 µA µA mA mA VIN = 0 -15 –0.5 µA VIN = 0 to VCC, 0 to 70C –40 to 85C -1 –10 +1 +10 µA +1 +10 µA µA Output off current high, 3-State data bus VIN = VCC, 0 to 70C –40 to 85C IOZL Output off current low, 3-State data bus VIN = 0 , 0 to 70C –40 to 85C IODL Open drain output low current in off state: DONEN, DTACKN (3-state) IRQN Open drain output high current in off state: DONEN, IRQN, DTACKN (3-state) Power supply current16 (See Figure 17 for graphs) Input capacitance9 Output capacitance9 Input/output capacitance9 2.0 2.3 0.8xVCC UNIT 0.0 150 –15 +15 IOZH CIN COUT CI/O Max –150 Input leakage current ICC LIMITS Typ 0.8 0.8 IL IODH6 Min µA µA -1 –10 VIN = 0 -15 -1 -0.5 µA µA +1 80 95 µA mA 10 15 20 pF pF pF VIN = VCC –1 0 to 70C –40 to 85C VCC = GND = 0 VCC = GND = 0 VCC = GND = 0 25 NOTES: 1. Stresses above those listed under Abs. Max Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. 2. Clock may be stopped (DC) for testing purposes or when the CDUSCC is in non-operational modes. Operation down to 0 rate clocks is implied by a full static CMOS design, but is not verified in testing or characterization. 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 4. Parameters are valid over specified temperature and voltage range. 5. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.2V and 3.0V with a transition time of 20ns maximum. For X1/CLK, this swing is between 0.2V and 4.4V. All time measurements are referenced at input voltages of 0.2V and 3.0V and output voltages of 0.8V and 2.0V, as appropriate. 6. See Figure 18 for test conditions for outputs. 7. Tests for open drain outputs are intended to guarantee switching of the output transistor. To include noise margin this response is measured from the switching signal midpoint to 0.2 V above the required output level. 8. Execution of the valid command (after it is latched) requires a minimum of three rising edges of X1 (see Figure 19). 9. These values were no explicitly tested; they are guaranteed by design and characterization data. 10. X1/CLK and X2 are not tested with a crystal installed. 11. X1/CLK frequency must be at least as fast as the faster of the receiver or transmitter data rate. 12. The X1 clock drives DTACKN, Baud Rate Generator, command register and the update of the FIFO fill level encoders. The Command Register requires three X1 clocks between two commands; FIFO fill level encoding requires 2.5 to 3.5 X1 cycles. 13. The 68562 bus interface may be operated in two modes; a 68000 compatible mode with automatic DTACK generation and a short chip select mode. DTACKN should not be used externally in the short chip select mode. The DTACKN signal is generated by the assertion of the chip select, and data is latched by assertion of DTACKN or by de-assertion of the chip select, whichever comes first. In single address DMA, the DTACK signal will be de-asserted by the assertion of the DTCN or from the de-assertion of the TxDAKN, whichever occurs first. 14. Also includes X2/IDCN pin in IDC mode. 15. In case of 3-state output, output levels VOL + 0.2 are considered float or high impedance. 16. VO = 0 to VCC, Rx/Tx at 10MHz and X1 at 10MHz 1998 Sep 04 8 Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) SC68C562 RESETN tRELREH SD00205 Figure 1. Reset Timing LIMITS SYMBOL PARAMETER INDUSTRIAL SC68C562 Min tRELREH RESETN low to RESETN high COMMERCIAL SC68C562 Max Min 200 UNIT Max 200 ns tADVCSL A1–A6 tRWHCSL tCSHRWL R/WN tCSLADI tCSHCSL tCSLCSH CSN tCSLDDV D0–D7 tCSHDDF INVALID DATA VALID INVALID tCSHDDI tDDVDAL tCSLDDA DTACKN12 tCSLDAL tCSHDAH tDALCSH tCSHDAZ SD00254 Figure 2. Read Cycle Bus Timing Times represent an X1 clock frequency of 14.745MHz LIMITS SYMBOL PARAMETER INDUSTRIAL SC68C562 Min Max COMMERCIAL SC68C562 Min UNIT Max tADVCSL A0-A6 valid to CSN low 10 5 ns tRWHCSL RWN high to CSN low 10 5 ns tCSHRWL CSN high to RWN low 20 10 ns tCSHCSL CSN high to CSN low8 50 tCSLDDV CSN low to read data valid 150 130 ns tCSHDDF CSN high to data bus float 50 40 ns tDDVDAL Read data valid to DTACKN low9 20 20 tDALCSH DTACKN low to CSN high9 0 0 tCSLDAL13 CSN low to DTACKN low9 30 ) 1 f CL tCSHDAH CSN high to DTACKN high 60 60 ns tCSHDAZ CSN high to DTACKN high impedance 90 90 ns tCSLADI CSN low to address invalid 60 50 ns tCSLCSH CSN low to CSN high 150 130 ns tCSLDDA CSN low to data bus driver active9 5 10 ns tCSHDDI CSN high to data invalid 5 5 ns 1998 Sep 04 9 30 140 ) 1.5 f CL 40 ) 1 f CL ns ns ns 130 ) 1.5 f CL ns Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) SC68C562 tADVCSL A1–A6 tCSHRWH tCSLADI R/WN tCSLCSH tRWLCSL tCSHCSL tDALCSH CSN tCSHWDI D0–D7 tCSLWDV tDALWDI DTACKN12 tCSHDAH tCSLDAL tCSHDAZ SD00255 Figure 3. Write Cycle Bus Timing LIMITS SYMBOL PARAMETER INDUSTRIAL SC68C562 Min Max COMMERCIAL SC68C562 Min UNIT Max tADVCSL A0-A6 valid to CSN low 10 5 ns tCSLADI CSN low to A0-A6 invalid 60 50 ns tRWLCSL RWN low to CSN low 0 0 ns tCSHRWH CSN high to RWN high 0 0 ns tCSHCSL CSN high to CSN low8 50 30 ns tDALCSH DTACKN low to CSN high9 0 0 ns tDALWDI DTACKN low to write data invalid9 0 0 ns tCSLDAL13 CSN low to DTACKN low9 tCSHDAH CSN high to DTACKN high 60 60 ns tCSHDAZ CSN high to DTACKN high impedance 90 90 ns tCSLCSH CSN low to CSN high 150 130 ns tCSLWDV CSN low to write data valid 30 35 ns tCSHWDI CSN high to write data invalid 10 5 ns 1998 Sep 04 30 ) 1 f CL 10 140 ) 1.5 f CL 40 ) 1 f CL 130 ) 1.5 f CL ns Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) SC68C562 IRQN tIALIAH tIAHDDF IACKN tIALDDV tIAHDDI INVALID D0-D7 DATA VALID tIALDDA INVALID tIAHDAH tDDVDAL DTACHN12 tIALDAL tIAHDAZ tDALIAH SD00256 Figure 4. Interrupt Cycle Timing LIMITS PARAMETER12 SYMBOL INDUSTRIAL SC68C562 Min COMMERCIAL SC68C562 Max Min tIALIAH IACKN low to IACKN high tIALDDA IACKN low to data bus drivers active9 tIALDDV IACKN low to read data valid 140 130 ns tIAHDDF IACKN high to data bus floating 60 60 ns low9 140 130 5 10 UNIT Max ns tDDVDAL Read data valid to DTACKN tIAHDAH IACKN high to DTACKN high 80 70 ns tIAHDAZ IACKN high to DTACKN high impedance 110 100 ns IACKN low to DTACKN tIAHDDI IACKN high to data bus invalid DTACKN low to IACKN 30 ) 1 f CL low9 tIALDAL tDALIAH 20 ns high9 20 140 ) 1.5 f CL ns 40 ) 1 f CL 130 ) 1.5 f CL ns 5 5 ns 0 0 ns IACKN tIALDCL IDCN SD00257 Figure 5. Interrupt Daisy Chain Timing LIMITS SYMBOL PARAMETER INDUSTRIAL SC68C562 Min tIALDCL IACKN low to IDCN (daisy chain) low Max COMMERCIAL SC68C562 Min 70 60 RWN CSN GPI1_N AND/OR GPI2_N tGIVCSL tCSLGII SD00258 Figure 6. Input Port Timing 1998 Sep 04 11 UNIT Max ns Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) SC68C562 LIMITS SYMBOL PARAMETER INDUSTRIAL SC68C562 Min COMMERCIAL SC68C562 Max Min UNIT Max tGIVCSL GPI input valid to CSN low 20 20 ns tCSLGII CSN low to GPI input invalid 40 40 ns RWN tCSHGOV CSN tDALGOV GPO1_N AND/OR GPO2_N OLD DATA NEW DATA DTACKN12 tCSLDAL SD00259 Figure 7. Output Port Timing LIMITS SYMBOL PARAMETER INDUSTRIAL SC68C562 Min tDALGOV tCSLDAL 13 tCSHGOV 1998 Sep 04 DTACKN low to GPO output data valid9 CSN low to DTACKN low9 Max COMMERCIAL SC68C562 Min 40 30 ) 1 f CL CSN high to GPO output data valid 140 ) 1.5 f CL 100 12 40 40 ) 1 f CL UNIT Max 130 ) 1.5 f CL 100 ns ns ns Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) SC68C562 CSN tCSHIRH DTACKN tDALIRH IRQN SD00260 Figure 8. Interrupt Timing, Write Cycle LIMITS SYMBOL PARAMETER INDUSTRIAL SC68C562 Min tDALIRH tCSHIRH COMMERCIAL SC68C562 Max Min UNIT Max DTACKN low to IRQN high, write cycle9 Write TxFIFO (TxRDY interrupt)9 40 40 ns Write RSR (Rx condition interrupt)9 40 40 ns Write TRSR (Rx/Tx interrupt)9 40 40 ns Write ICTSR (port change and CT interrupt)9 40 40 ns Write TRMSR (Tx Path, Patt recognition)9 40 40 ns Write TxFIFO (TxRDY interrupt) 100 90 ns Write RSR (Rx condition interrupt) 100 90 ns Write TRSR (Rx/Tx interrupt) 100 90 ns Write ICTSR (port change and CT interrupt) 100 90 ns Write TRMSR (Tx Path, Patt recognition)9 100 90 ns CSN high to IRQN high, write cycle CSN tCSHIRH IRQN VOL +.5V SD00261 Figure 9. Interrupt Timing, Read Cycle LIMITS SYMBOL PARAMETER INDUSTRIAL SC68C562 Min tCSHIRH COMMERCIAL SC68C562 Min UNIT Max CSN high to IRQN high, read cycle Read RxFIFO (RxRDY interrupt) 1998 Sep 04 Max 100 13 90 ns Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) tCLHCLL tCCHCCL tRCHRCL tTCHTCL SC68C562 *PULL-UP RESISTOR IS NOT REQUIRED WHEN USING CMOS LEVELS +5V TTL X1/CLK CTCLK RxC TxC 470Ω X1 * CLK tCLLCLH tCCLCCH tRCLRCH tTCLTCH OPEN X2 a. Driving X1 from an External Source CRYSTAL SERIES RESISTANCE SHOULD BE LESS THAN 180Ω X1 CP1 C1 TO DTACKN BLOCK 360k TO 1.5M Y1 ÷2 C2 ALL OTHER BLOCKS CDUSCC X2 CP2 SD00262 Figure 10. Receive, Dual Address DMA LIMITS SYMBOL PARAMETER INDUSTRIAL SC68C562 Min Typ Max COMMERCIAL SC68C562 Min Typ UNIT Max tCLHCLL X1/CLK high to low time 25 25 ns tCLLCLH X1/CLK low to high time 25 25 ns tCCHCCL CT and DPLL CLK high to low time 50 45 ns tCCLCCH CT and DPLL CLK low to high time 50 45 ns tRCHRCL RxC high to low time 55 50 ns tRCLRCH RxC low to high time 55 50 ns tTCHTCL TxC high to low time 55 50 ns tTCLTCH TxC low to high time 55 50 fCL X1/CLK frequency11, 2 0 fCC CT CLK frequency fRC RxC frequency (16X or 1X) fTC TxC frequency (16X or 1X) fRTC Tx/Rx frequency for FM/Manchester encoding 1998 Sep 04 14.7456 16.0 0 0 8 0 8 0 8 4 14 ns 14.7456 16.0 MHz 0 10 MHz 0 10 MHz 0 10 MHz 5 MHz Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) 1 BIT TIME (1 OR 16 CLOCKS) SC68C562 TxC (INPUT) TxC (INPUT) tCILTXV tCILTXV tCILTXV TxD TxD tCOLTXV tCOLTXV TxC (1X OUTPUT) TxC (1X OUTPUT) a. Transmit Timing NRZ tCOLTXV b. Transmit Timing FM0/1, Manchester Encoding SD00263 Figure 11. LIMITS SYMBOL PARAMETER INDUSTRIAL SC68C562 Min tCILTXV tCOLTXV* COMMERCIAL SC68C562 Max Min UNIT Max TxC input low (1X) to TxD output 120 120 ns TxC input low (16X) to TxD output 125 120 ns TxC output low to TxD output (NRZ, NRZI)9 25 20 ns 35 30 ns (FM, Manchester)9 NOTE: Characterized with no loads on TxD and TxC outputs.* Tester load approximately 50pF. tRCHSOL RXC (INPUT) SYNOUTN tSILRCH tRCHRXI tRXVRCH tRXVRCH tRCHSIH SYNIN RxD RXC (1X) INPUT tRXVRCH tRCHRXI tRCHRXI RxD a. Receive Timing NRZ b. Receive Timing FM0/1, Manchester Encoding SD00264 Figure 12. LIMITS SYMBOL PARAMETER INDUSTRIAL SC68C562 Min tRXVRCH tRCHRXI Max COMMERCIAL SC68C562 Min UNIT Max RxD data valid to RxC high: For NRZ data 25 20 ns For NRZI, Manchester, FM0, FM1 data 30 30 ns For NRZ data 25 20 ns RxC high to RxD data invalid: For NRZI, Manchester, FM0, FM1 data 30 30 ns tSILRCH SYNIN low to RxC high 50 50 ns tRCHSIH RxC high to SYNIN high 20 20 tRCHSOL RxC high to SYNOUT low 1998 Sep 04 110 15 ns 100 ns Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) SC68C562 tCSLDAL CSN tROLDAL DTACKN12 tCSLROL tCSHROH DONEN (OUTPUT) (EOM) tRRHDAL tCSLRRH RTxDRQ_N SD00265 Figure 13. Receive, Dual Address DMA LIMITS SYMBOL PARAMETER INDUSTRIAL SC68C562 Min Max COMMERCIAL SC68C562 Min UNIT Max tCSLROL CSN low to Rx DONEN output low 110 100 ns tCSLRRH CSN low to Rx DMA REQN high 110 100 ns tCSHROH CSN high to Rx DONEN output high 70 60 ns tROLDAL Rx DONEN output low to DTACKN low9 40 40 tRRHDAL Rx DMA REQN high to DTACKN low9 40 40 tCSLDAL13 1998 Sep 04 CSN low to DTACKN low9 30 ) 1 f CL 16 140 ) 1.5 f CL 40 ) 1 f CL ns ns 130 ) 1.5 f CL ns Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) tTOLDAL SC68C562 tDALTOH DONEN (OUTPUT) tCSHTOH tCSLTOL CSN tCSLDAL DTACKN12 tCSHDIH tCSLDIL tDALDIH DONEN (INPUT) tCSLTRH TxDRQ_N OR RTxDRQ_N tTRHDAL SD00266 Figure 14. Transmit, Dual Address DMA SYMBOL PARAMETER LIMITS LIMITS INDUSTRIAL SC68C562 COMMERCIAL SC68C562 Min Max Min UNIT Max tCSLTOL CSN low to Tx DONEN output low 110 100 ns tCSLTRH CSN low to Tx DMA REQN high 110 100 ns tDALDIH DTACKN low to Tx DONEN input high9 0 high9 0 tDALTOH DTACKN low to Tx DONEN output tTOLDAL Tx DONEN output low to DTACKN low9 40 40 tTRHDAL Tx DMA REQN high to DTACKN low9 40 40 tCSLDAL13 CSN low to DTACKN low9 tCSLDIL CSN low to Tx DONEN input low tCSHTOH CSN high to Tx DONEN output high tCSHDIH CSN high to Tx DONEN input high 1998 Sep 04 20 30 ) 1 f CL 140 ) 1.5 f CL 35 20 40 ) 1 f CL 17 ns 130 ) 1.5 f CL ns ns 60 25 ns ns 40 70 30 ns ns ns 1998 Sep 04 18 Figure 15. DMA Rx Read Timing—Single Address DMA RTxDRQ_N DONEN (OUTPUT) DTCN DTACKN12 D0-D7 RxDAK_N t DALDTL t DTLDAZ t RAHDAH t RAHDAZ t DTLDTH t DTLDAH t DTLDDI INVALID t DTLDDF t RAHDDF t RAHDDI DATA VALID t DDVDAL t RALDTL t RALDAL t RALDDA INVALID t RALDDV t RALRAH t RALRRH t ROLDAL t RRHDAL t RALROL t RAHRAL t DTLROH t RAHROH Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) SC68C562 SD00267 Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) SC68C562 DMA Rx Read Timing — Single Address DMA LIMITS SYMBOL PARAMETER INDUSTRIAL SC68C562 Min Max COMMERCIAL SC68C562 Min tRALDDV Receive DMA ACKN low to read data valid tDTLDTH DTCN low to DTCN high 50 40 tDALDTL DTACKN low to DTCN low9 0 0 tDTLDDF DTCN low to data bus float tRALDAL Rx DMA ACK low to DTACKN low9 tDDVDAL Read data valid to DTACKN low9 tDTLDAH DTCN low to DTACKN high 80 80 ns tDTLDAZ DTCN low to DTACKN high impedance 110 110 ns tRRHDAL Rx DMA REQN high to DTACKN low9 40 40 tROLDAL Rx DONEN output low to DTACKN low9 40 40 tRALRRH Rx DMA ACKN low to receive DMA REQN high tRAHRAL Receive DMA ACKN high to low time tRALROL Rx DMA ACK low to Rx DONEN output low 100 100 ns tDTLROH DTCN low to Rx DONEN output high 80 70 ns tRALRAH Rx DMA ACKN low to Rx DMA ACKN high tRAHDDF Rx DMA ACKN high to data bus float tRALDDA Rx DMA ACKN low to data bus drivers active9 5 10 ns tRAHDDI Rx DMA ACKN high to data bus invalid 5 5 ns tDTLDDI DTCN low to data bus invalid 5 5 ns tRALDTL Rx DMA ACKN low to DTCN low 140 130 tRAHDAH Rx DMA ACKN high to DTACKN high 80 70 ns tRAHDAZ Rx DMA ACKN high to DTACKN high impedance 110 100 ns tRAHROH Rx DMA ACKN high to DONEN output high 70 60 ns 1998 Sep 04 140 UNIT Max 130 70 30 ) 1 f CL 140 ) 1.5 f CL 20 ns 130 ) 1.5 f CL 20 100 50 ns ns ns 100 ns ns 130 60 ns ns 30 140 19 ns 60 40 ) 1 f CL ns ns 60 ns ns Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) SC68C562 DMA Tx Write Timing — Single Address DMA LIMITS SYMBOL PARAMETER INDUSTRIAL SC68C562 Min tDTLDTH tDALDTL DTCN low to DTCN high DTACKN low to DTCN Max 50 low9 30 ) 1 f CL Min ns 0 140 ) 1.5 f CL 40 ) 1 f CL UNIT Max 40 0 low9 COMMERCIAL SC68C562 ns 130 ) 1.5 f CL tTALDAL Tx DMA ACK low to DTACKN tDTLDAH DTCN low to DTACKN high 80 80 ns tDTLDAZ DTCN low to DTACKN high impedance 110 110 ns tTRHDAL Tx DMA REQN high to DTACKN low9 40 low9 40 ns tTOLDAL Tx DONEN output low to DTACKN tDTLTOH DTCN low to Tx DONEN output high tWDVDTL Write data valid to DTCN low 40 40 tDTLWDI DTCN low to write data invalid 30 20 tTALTRH Tx DMA ACKN low to transmit DMA REQN high tTAHTAL Transmit DMA ACKN high to low time tTALTOL Tx DMA ACKN low to Tx DONEN output low tDILDTL Transmit DONEN input low to DTCN low tDTLDIH DTCN low to transmit DONEN input high tTALTAH Tx ACKN low to Tx ACKN high tTAHWDI Tx ACKN high to write data invalid tWDVTAH Write data valid to Tx DAKN high tTAHDAH Tx DAKN high to DTACKN high 80 70 ns tTAHDAZ Tx DAKN high to DTACKN high impedance 110 100 ns tTAHTOH Tx DAKN high to DONEN output high 70 60 ns tDILTAH DONEN input low to Tx DAKN high tTAHDIH Tx DAKN high to DONEN input high tTALDTL Tx DAKN low to DTCN low 1998 Sep 04 40 ns 40 80 110 40 ns 30 40 ns ns 100 100 ns ns 90 ns 30 ns 40 30 ns 110 100 ns 15 10 ns 60 40 40 20 ns 70 ns 30 ns 30 25 ns 110 100 ns 1998 Sep 04 21 DONEN (output) TxDRQN DONEN (input) DTCN DTACKN12 D0-D7 TxDAKN t TALDTL t TALDAL t TALTAH t WDVTAH t DALDTL t WDVDTL t TAHWDI t DTLDTH t DTLDAH t DTLDAZ t DTLWDI t TAHDAH t TAHDAZ t TAHTAL t TALTOL t TALTRH t TOLDAL t DILDTL t TRHDAL t DILTAH t TAHTOH t DTLTOH t DTLDIH t TAHDIH Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) SC68C562 Figure 16. DMA Tx Write Timing—SIngle Address DMA SD00269 Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) 50 SC68C562 50 0°C 40 40 25°C 30 30 ICC ICC 70°C 20 20 10 10 0 0 4 4.5 5 5.5 6 4 6 8 10 Tx/Rx Clk and X1 Frequency VCC Test Condition: Tx/Rx and X1 Frequency @ 10MHz Test Condition: VCC = 5V @ 25°C SD00250 Figure 17. 2.7k TRxC VCC IRQN 50pF RTxC 50pF 820Ω DTACKN +5.0V 150pF 1k DONEN VCC 50pF 710 ALL OTHER OUTPUTS +5.0V 150pF 6.0k NOTE: All CL includes 50pF stray capacitance, i.e., CL = 150pF = (100pF discrete + 50pF stray). SD00270 Figure 18. Test Conditions for Outputs X1/CLK WRN COMMAND VALID SD00219 Figure 19. Command Timing 1998 Sep 04 22 Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) RxC 1 SC68C562 2 3 4 5 6 7 8 2 3 4 5 6 7 8 RxD LCN a. Loop Control Output Assertion RxC 1 9 RxD LCN b. Loop Control Output Negation SD00220 Figure 20. Relationship Between Received Data and the Loop Control Output 1998 Sep 04 23 Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) DIP48: plastic dual in-line package; 48 leads (600 mil) 1998 Sep 04 24 SC68C562 SOT240-1 Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) PLCC52: plastic leaded chip carrier; 52 leads; pedestal 1998 Sep 04 25 SC68C562 SOT238-3 Philips Semiconductors Product specification CMOS Dual universal serial communications controller (CDUSCC) SC68C562 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 08-98 Document order number: 1998 Sep 04 26 9397 750 04356