INTEL 278875

Intel® 41210 Serial to Parallel PCI Bridge
Datasheet
Product Features
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PCI Express Specification, Revision 1.0a
Support for single x8, single x4 or single x1
PCI Express operation.
64-bit addressing support
32-bit CRC (cyclic redundancy checking)
covering all transmitted data packets.
16-bit CRC on all link message
information.
Raw bit-rate on the data pins of 2.5 Gbit/s,
resulting in a raw bandwidth per pin of
250 MB/s.
Maximum realized bandwidth on PCI
Express interface is 2 GB/s (in x8 mode) in
each direction simultaneously, for an
aggregate of 4 GB/s.
PCI Local Bus Specification, Revision 2.3.
PCI-to-PCI Bridge Specification,
Revision 1.1.
PCI-X Addendum to the PCI Local Bus
Specification, Revision 1.0b
64-bit 66 MHz, 3.3 V, NOT 5 V tolerant.
On Die Termination (ODT) with 8.3KOhm
pull-up to 3.3V for PCI signals.
Six external REQ/GNT Pairs for internal
arbiter on segment A and B respectively.
Programmable bus parking on either the
last agent or always on the 41210 Bridge
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2-level programmable round-robin internal
arbiter with Multi-Transaction Timer
(MTT)
External PCI clock-feed support for
asynchronous primary and secondary
domain operation.
64-bit addressing for upstream and
downstream transactions
Downstream LOCK# support.
No upstream LOCK# support.
PCI fast Back-to-Back capable as target.
Up to four active and four pending
upstream memory read transactions
Up to two downstream delayed (memory
read, I/O read/write and configuration read/
write) transaction.
Tunable inbound read prefetch algorithm
for PCI MRM/MRL commands
Device hiding support for secondary PCI
devices.
Secondary bus Private Memory support via
Opaque memory region
Local initialization via SMBus
Secondary side initialization via Type 0
configuration cycles.
Full peer-to-peer read/write capability
between the two secondary PCI segments.
Order Number: 278875-005US
May 2005
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2
Contents
Contents
1
Introduction.................................................................................................................................... 7
1.1
1.2
2
About This Document ........................................................................................................... 7
Product Overview ................................................................................................................. 7
Signal Description ......................................................................................................................... 8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
On Die Termination (ODT).................................................................................................... 8
PCI Express Interface.........................................................................................................10
PCI Bus Interface (Two Instances) .....................................................................................10
PCI Bus Interface 64-Bit Extension (Two Interfaces) .........................................................12
PCI Bus Interface Clocks and, Reset and Power Management (Two Interfaces) ..............13
Interrupt Interface (Two Interfaces) ....................................................................................13
Reset Straps .......................................................................................................................13
SMBus Interface .................................................................................................................15
Miscellaneous Pins .............................................................................................................15
Electrical and Thermal Characteristics .....................................................................................17
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4
DC Voltage and Current Specifications ..............................................................................17
AC Specifications................................................................................................................25
Voltage Filter Specifications ...............................................................................................27
VCC15 and VCC33 Voltage Requirements ........................................................................27
Timing Specifications ..........................................................................................................28
41210 Bridge Power Consumption .....................................................................................36
Power Delivery Guidelines..................................................................................................37
Reference and Compensation Pins ....................................................................................37
Thermal Specifications .......................................................................................................38
Package Specification and Ballout ............................................................................................40
4.1
4.2
4.3
4.4
Package Specification ........................................................................................................40
Ball Map ..............................................................................................................................42
Signal List, sorted by Ball Location.....................................................................................44
Signal List, sorted by Signal Name.....................................................................................48
Figures
1
2
3
4
5
6
7
8
9
10
Minimum Transmitter Timing and Voltage Output Compliance Specification.............................22
Compliance Test/Measurement Load.........................................................................................23
Minimum Receiver Eye Timing and Voltage Compliance Specification .....................................23
Voltage Requirements VCC33 versus VCC15 ...........................................................................27
PCI Output Timing ......................................................................................................................31
PCI Input Timing .........................................................................................................................31
PCI-X 3.3V Clock Waveform ......................................................................................................33
41210 Bridge Reference and Compensation Circuit Implementations .......................................38
41210 Bridge Package Dimensions (Top View) .........................................................................40
41210 Bridge Package Dimensions (Side View) ........................................................................41
3
Contents
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
4
ODT Signals ................................................................................................................................. 9
PCI Express Interface Pins......................................................................................................... 10
PCI Interface Pins....................................................................................................................... 11
PCI Interface Pins: 64-Bit Extensions......................................................................................... 12
PCI Clock and Reset Pins .......................................................................................................... 13
Interrupt Interface Pins ............................................................................................................... 13
Reset Strap Pins......................................................................................................................... 14
SMBus Interface Pins ................................................................................................................. 15
Miscellaneous Pins ..................................................................................................................... 15
Intel® 41210 Bridge DC Voltage Specifications ......................................................................... 17
DC Characteristics Input Signal Association .............................................................................. 18
DC Input Characteristics............................................................................................................. 18
DC Characteristic Output Signal Association ............................................................................. 18
DC Output Characteristic............................................................................................................ 19
Differential Transmitter (TX) DC Output Specifications .............................................................. 19
Differential Receiver (RX) DC Input Specifications .................................................................... 21
DC Specifications for PCI and PCI-X 3.3 V Signaling ................................................................ 24
DC Specification for Input Clock Signals .................................................................................... 25
DC Specification for Output Clock Signals ................................................................................. 25
Conventional PCI 3.3V AC Characteristics ................................................................................ 25
PCI-X 3.3V AC Characteristics ................................................................................................... 26
Differential Transmitter (TX) AC Output Specifications .............................................................. 28
Differential Receiver (RX) AC Input Specifications..................................................................... 29
PCI Interface Timing................................................................................................................... 30
PCI-X 3.3V Signal Timing Parameters ....................................................................................... 31
PCI and PCI-X Clock Timings .................................................................................................... 33
41210 Bridge Clock Timings....................................................................................................... 35
41210 Bridge Maximum Voltage Plane Currents ....................................................................... 37
41210 Bridge Thermal Voltage Plane Currents .......................................................................... 37
41210 Bridge Thermal Specifications ......................................................................................... 39
Signal List, sorted by Ball Name................................................................................................. 44
Signal List, sorted by Signal Name............................................................................................. 48
Contents
Revision History
Date
Revision
Description
May 2005
005
Revised Table 1, Table 9, and Section 3.8
April 2005
004
Revised Table 26 “PCI and PCI-X Clock Timings” on page 33 CLK Cycle Time parameters
September 2004
003
Revised first page PCI Express operation description; updated information in Table 2.
June 2004
002
Added Chapter 2. Removed original Sections 3.6 and 3.7. Updated VCC information to
VCC15.
September 2003
001
Initial release
5
Order Number: 278875-005US
May 2005
Datasheet — 41210 Bridge
Introduction
1.1
1
About This Document
This document provides information on the Intel® 41210 Serial to Parallel PCI Bridge, including a
functional overview, signal descriptions, mechanical data, package signal location and bus
functional waveforms.
1.2
Product Overview
The Intel® 41210 Serial to Parallel PCI Bridge (also called the 41210 Bridge) integrates two PCI
Express-to-PCI/PCI-X bridges. Each bridge follows the PCI-to-PCI Bridge programming model.
The PCI Express port is compatible with the PCI Express Specification, Revision 1.0a. The two
PCI bus interfaces are compatible with the PCI Local Bus Specification, Revision 2.3 and PCI-X
Addendum to the PCI Local Bus Specification, Revision 1.0b.
7
41210 Bridge — Datasheet
Signal Description
2
The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when
the signal is at a low voltage level. When “#” is not present after the signal name the signal is
asserted when at the high voltage level. The following notations are used to describe the signal
type:
2.1
I:
Input pin
O:
Output pin
OD:
Open-drain Output pin
I/O:
Bidirectional Input/Output pin
I/OD:
Bidirectional Input/Open-drain Output pin
On Die Termination (ODT)
The 41210 Bridge incorporates on-die termination for most of the PCI interface signals. This
eliminates the need for the system designer to incorporate external pull-up resistors in the design.
The following signals have an on die termination of 8.33KOhm @40%:
8
Datasheet — 41210 Bridge
Table 1.
ODT Signals
A_ACK64#
B_ACK64#
A_AD[63:32]
B_AD[63:32]
A_CBE#[7:4]
B_CBE#[7:4]
A_DEVSEL#
B_DEVSEL#
A_FRAME#
B_FRAME#
A_GNT#[5:0]
B_GNT#[5:0]
A_IRDY#
B_IRDY#
A_PAR
B_PAR
A_PAR64
B_PAR64
A_PERR#
B_PERR#
A_LOCK#
B_LOCK#
A_REQ#[5:0]
B_REQ#[5:0]
A_REQ64#
B_REQ64#
A_SERR#
B_SERR#
A_STOP#
B_STOP#
A_TRDY#
B_TRDY#
A_INTA#
B_INTA#
A_INTB#
B_INTB#
A_INTC#
B_INTC#
A_INTD#
B_INTD#
TCK
TDI
TDO
TMS
9
41210 Bridge — Datasheet
2.2
PCI Express Interface
Table 2.
PCI Express Interface Pins
Signal
REFCLKp/
REFCLKn
I/O
I
Description
PCI Express Reference Clocks: 100 MHz differential clock pair.
PCI Express Serial Data Transmit: PCI Express differential data transmit
signals.
PETp[7:0]/
PETn[7:0]
O
X8 Mode: All PETp[7:0]/ PETn[7:0] are used
X4 Mode: Only PETp[3:0]/ PETn[3:0] are used
x1 Mode: Either PETp[0]/ PETn[0] is used or PETp[7]/ PETn[7] is used
PCI Express Serial Data Receive: PCI Express differential data receive
signals.
PERp[7:0]/
PERn[7:0]
I
X8 Mode: All PERp[7:0]/ PERn[7:0] are used
X4 Mode: Only PERp[3:0]/ PERn[3:0] are used
x1 Mode: Either PERp[0]/ PERn[0] is used or PERp[7]/ PERn[7] is used
2.3
PE_RCOMP[1:0]
I
Total
36
PCI Express Compensation Inputs: Analog signals. Connect to a
24.9Ω±1% pull-up resitor to 1.5V. A single resistor can be used for both
signals.
PCI Bus Interface (Two Instances)
Each interface is marked by either the letter “A” or “B” to signify the interface. Therefore, A_AD
refers to the AD bus on PCI bus A, and B_AD refers to the AD bus on PCI bus B. For pin names
described in the following sections, an ‘X’ in the name indicates either A or B, for the PCI bus A
and PCI bus B sides. For example, X_PAR signal would be called A_PAR on the PCI bus A and
B_PAR on the PCI bus B.
10
Datasheet — 41210 Bridge
Table 3.
PCI Interface Pins (Sheet 1 of 2)
Signal
I/O
A_AD[31:0]
B_AD[31:0]
I/O
Description
PCI Address/Data: These signals are a multiplexed address and data bus. During the address
phase or phases of a transaction, the initiator drives a physical address on X_AD[31:0]. During the
data phases of a transaction, the initiator drives write data, or the target drives read data.
No External pull-up resistors are required on the system board for these signals.
A_C/BE#[3:0]
B_C/BE#[3:0]
I/O
Bus Command and Byte Enables: These signals are a multiplexed command field and byte enable
field. During the address phase or phases of a transaction, the initiator drives the transaction type on
C/BE#[3:0]. When there are two address phases, the first address phase carries the dual address
command and the second address phase carries the transaction type. For both read and write
transactions, the initiator drives byte enables on C/BE#[3:0] during the data phases.
No External pull-up resistors are required on the system board for these signals.
A_PAR
B_PAR
I/O
Parity: Even parity calculated on 36 bits - AD[31:0] plus C/BE[3:0]#. It is calculated on all 36 bits
regardless of the valid byte enables. It is generated for address and data phases. It is driven
identically to the AD[31:0] lines, except it is delayed by exactly one PCI clock. It is an output during
the address phase for all 41210 Bridge initiated transactions and all data phases when the 41210
Bridge is the initiator of a PCI write transaction, and when it is the target of a read transaction.
41210 Bridge checks parity when it is the initiator of PCI read transactions and when it is the target of
PCI write transactions.
No External pull-up resistors are required on the system board for these signals.
A_DEVSEL#
B_DEVSEL#
I/O
Device Select: The bridge asserts DEVSEL# to claim a PCI transaction. As a target, the 41210 Bridge
asserts DEVSEL# when a PCI master peripheral attempts an access an address destined for PCI
Express. As an initiator, DEVSEL# indicates the response to a 41210 Bridge initiated transaction on the
PCI bus. DEVSEL# is tri-stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated by
the 41210 Bridge until driven as a target.
No External pull-up resistors are required on the system board for these signals.
A_FRAME#
B_FRAME#
I/O
Frame: FRAME# is driven by the Initiator to indicate the beginning and duration of an access. While
FRAME# is asserted data transfers continue. When FRAME# is negated the transaction is in the final
data phase.
No External pull-up resistors are required on the system board for these signals.
A_IRDY#
B_IRDY#
I/O
A_TRDY#
B_TRDY#
I/O
Initiator Ready: IRDY# indicates the ability of the initiator to complete the current data phase of the
transaction. A data phase is completed when both IRDY# and TRDY# are sampled asserted.
No External pull-up resistors are required on the system board for these signals.
Target Ready: Indicates the ability of the target to complete the current data phase of the transaction.
A data phase is completed when both TRDY# and IRDY# are sampled asserted. TRDY# is tri-stated
from the leading edge of RST#. TRDY# remains tri-stated by the 41210 Bridge until driven as a target.
No External pull-up resistors are required on the system board for these signals.
A_STOP#
B_STOP#
I/O
A_PERR#
B_PERR#
I/O
Stop: Indicates that the target is requesting an initiator to stop the current transaction.
No External pull-up resistors are required on the system board for these signals.
Parity Error: Driven by an external PCI device when it receives data that has a parity error. Driven by
41210 Bridge when, as a initiator it detects a parity error during a read transaction and as a target
during write transactions.
No External pull-up resistors are required on the system board for these signals.
A_SERR#
B_SERR#
A_M66EN
B_M66EN
I
System Error: The 41210
PCI Express.
Bridge samples SERR# as an input and conditionally forwards it to the
No External pull-up resistors are required on the system board for these signals.
I/OD
66 MHz Enable: This input signal from the PCI Bus indicates the speed of the PCI Bus. If it is high
then the Bus speed is 66 MHz and if it is low then the bus speed is 33 MHz. This signal will be used
to generate appropriate clock (33 or 66 MHz) on the PCI Bus.
Use an approximately 8.2KΩ resistor to pull to VCC33 or pull-down to ground.
11
41210 Bridge — Datasheet
Table 3.
PCI Interface Pins (Sheet 2 of 2)
Signal
I/O
A_PCIXCAP
B_PCIXCAP
I
A_LOCK#
B_LOCK#
O
Description
PCI-X Capable: Indicates whether all devices on the PCI bus are PCI-X devices, so that the 41210
Bridge can switch into PCI-X mode. Use an approximately 8.2KΩ resistor to pull to VCC33.
PCI Lock: Indicates an exclusive bus operation and may require multiple transactions to complete.
This signal is an output from the bridge when it is initiating exclusive transactions on PCI. LOCK# is
ignored when PCI masters are granted the bus. Locked transaction do not propagate upstream.
No External pull-up resistors are required on the system board for these signals.
Total
118
2.4
PCI Bus Interface 64-Bit Extension (Two Interfaces)
Table 4.
PCI Interface Pins: 64-Bit Extensions
Signal
I/O
A_AD[63:32]
B_AD[63:32]
I/O
A_C/BE#[7:4]
B_C/BE#[7:4]
I/O
Description
PCI Address/Data: These signals are a multiplexed address and data bus. This bus provides an
additional 32 bits to the PCI bus. During the data phases of a transaction, the initiator drives the
upper 32 bits of 64-bit write data, or the target drives the upper 32 bits of 64-bit read data, when
REQ64# and ACK64# are both asserted.
Bus Command and Byte enables upper 4 bits: These signals are a multiplexed command field and
byte enable field. For both reads and write transactions, the initiator will drive byte enables for the
AD[63:32] data bits on C/BE7:4] during the data phases when REQ64# and ACK64# are both
asserted.
12
A_PAR64
B_PAR64
I/O
PCI interface upper 32 bits parity: This carries the even parity of the 36 bits of AD[63:32] and C/
BE#[7:4] for both address and data phases.
A_REQ64#
B_REQ64#
I/O
PCI interface request 64-bit transfer: This is asserted by the initiator to indicate that the initiator is
requesting a 64-bit data transfer. It has the same timing as FRAME#. When the 41210 Bridge is
the initiator, this signal is an output. When the 41210 Bridge is the target this signal is an input.
A_ACK64#
B_ACK64#
I/O
PCI interface acknowledge 64-bit transfer: This is asserted by the target only when REQ64# is
asserted by the initiator, to indicate the target ability to transfer data using 64 bits. It has the same
timing as DEVSEL#.
Total
78
Datasheet — 41210 Bridge
2.5
PCI Bus Interface Clocks and, Reset and Power
Management (Two Interfaces)
Table 5.
PCI Clock and Reset Pins
Signal
I/O
A_CLKO[6:0]
B_CLKO[6:0]
Description
PCI Clock Output: 33/66/100/133 MHz clock for a PCI device. X_CLK[6] must be connected to the
respective X_CLKIN input. for feeding the PCI interface logic. Unused clock outputs may be
disabled via the “Offset 43: PCLKC – PCI Clock Control” register and should be treated as no
connects on the board.
O
Note:
Registers are listed in the Intel® 41210 Serial to Parallel PCI Bridge
Developer’s Manual.
A_CLKIN
B_CLKIN
I
PCI Clock In: This signal is PCI clock feedback input. This pin should be connected to the
corresponding X_CLKO[6] through a 22Ω±1% series resistor.
A_RST#
B_RST#
O
PCI Reset: The bridge asserts RST# to reset devices that reside on the secondary PCI bus.
I
PCI Power Management Event: PCI bus power management event signal. This is a shared open
drain input from all the PCI cards on the corresponding PCI bus segment. This is a level sensitive
signal that will be converted to a PME event on PCI Express.
A_PME#
B_PME#
This pin does not have on-die 8.3K pull-up. This pull-up must be provided externally.
Total
2.6
20
Interrupt Interface (Two Interfaces)
This section lists the interrupt interface signals. There are two sets of interrupt signals for the
standard INTA:INTD pci signals.
Table 6.
Interrupt Interface Pins
Signal
I/O
A_INTA#
A_INTB#
A_INTC#
A_INTD#
Total
2.7
Interrupt Request Bus: The interrupt lines from PCI interrupts INTA#:INTD# can be routed to these
interrupt lines.
I
B_INTA#
B_INTB#
B_INTC#
B_INTD#
Description
Refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide for more information on device
numbering.
8
Reset Straps
The following signals are used for static configuration. These signals are all sampled on the rising
edge of PERST#.
13
41210 Bridge — Datasheet
Table 7.
Reset Strap Pins
Signal
A_133EN
B_133EN
I/O
Description
I
PCI-X 133 MHz Enable: This pin, when high, allows the PCI-X segment to
run at 133 MHz when X_PCIXCAP is sampled high. When low, the PCI-X
segment will only run at 100 MHz when X_PCIXCAP is sampled high.
Use an approximately 8.2KΩ resistor to pull to VCC33 or pull-down to
ground.
Internal Test Modes: Straps 6, 2:0 should be pulled low and straps 5:3
must be pulled high for normal operation.
X_STRAP
A_STRAP[6:0
]
B_STRAP[6:0
]
0
1
2
3
4
5
6
I
Logic Level
‘0’
‘0’
‘0’
‘1’
‘1’
‘1’
‘0’
Use approximately an 8.2KΩ resistor to pull-up to VCC33 or pull-down to
VSS
A_TEST[2:1]
B_TEST{2:1]
CFGRETRY
Internal Test Modes: These straps should be pulled high to VCC33.
I
Use approximately an 8.2KΩ resistor to pull-up to VCC33.
Configuration Retry: This pin, when sampled high sets the Configuration
Cycle Retry Bit (bit 3) in the Bridge Initialization Register at Offset FC.
If no local initialization is needed, this pin should be pulled low to VSS.
I
Refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide for
more information.
Total
14
19
Datasheet — 41210 Bridge
2.8
SMBus Interface
Table 8.
SMBus Interface Pins
Signal
I/O
Description
SMBCLK
I/OD
SMBus Clock: This signal should be pulled to 3.3V via an 8.2KOhm
resistor.
SMBDAT
I/OD
SMBus Data: This signal should be pulled to 3.3V via an 8.2KOhm
resistor.
SMBus Addressing Straps: These straps set the SMBus Address for
41210 Bridge. The address is determined as indicated below:
Bit 7‘1’
Bit 6‘1’
SMBUS[5]
SMBUS[3:1]
Bit 5SMBUS[5]
I
Bit 4‘0’
Bit 3SMBUS[3]
Bit 2SMBUS[2]
Bit 1SMBUS[1]
These signals (bits 5, 3:1) should be pulled up to 3.3V or down to
ground. Sampled at the rising edge of PERST#.
Total
6
2.9
Miscellaneous Pins
Table 9.
Miscellaneous Pins
Signal
CFGRST#
I/O
Description
O
Configuration Reset: This signal is asserted low when ever the bridge goes
through a fundemental reset (PERST#, RSTIN#, or PCI Express Reset). This
signal should be used to indicate when the local initialization methods should be
executed.
Refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide for more
information.
PERST#
I
PCI Express Fundamental Reset: When low, asynchronously resets the
internal logic (including sticky bits).
RSTIN#
I
Reset In: When Asserted, this signal asynchronously resets the internal logic
and asserts X_RST# output for both PCI interfaces. This signal should be pulled
high for adapter card usage.
TCK
I
TAP Clock In: This is the input clock to the JTAG TAP controller. Acceptable
frequency is 0-16MHz
If not utilizing JTAG, this signal can be left as a no connect.
TDI
I
Test Data In: This is the serial data input to the JTAG BSCAN shift register
chain and to the JTAG BSCAN control logic. This is latched in on the rising edge
of TCK.
If not utilizing JTAG, this signal can be left as a no connect.
TDO
O
Test Data Output: This is the serial data output from the JTAG BSCAN logic
If not utilizing JTAG, this signal can be left as a no connect.
15
41210 Bridge — Datasheet
Signal
I/O
TMS
I
Test Mode Select: This signal controls the TAP controller state machine to
move to different states and is sampled on the rising edge of TCK.
If not utilizing JTAG, this signal can be left as a no connect.
TRST#
I
Test Reset In: This signal is used to asynchronously reset the JTAG BSCAN
logic.
If not utilizing JTAG, connect this signal to ground through a 1KΩ pull-down
resistor.
RESERVED[8:1]
I
Reserved: (8 pins) These input pins should be pulled low
Use an approximately 8.2KΩ resistor to pull-down to ground.
NC[19:18], NC[16:1]
A_NC[10:1]
B_NC[10:1]
O
No Connect: (39 pins) These output pins should be left floating
NC[17]
O
This signal requires an external pull-up, 8.2K ohm to 3.3V
Total
16
Description
57
Datasheet — 41210 Bridge
Electrical and Thermal Characteristics 3
3.1
DC Voltage and Current Specifications
3.1.1
41210 Bridge DC Specifications
Table 10.
Intel® 41210 Bridge DC Voltage Specifications
Symbol
Parameter
Min
Typ
Max
Unit
VCC15
Intel® 41210 Bridge Core
1.425
1.5
1.575
V
VCC15
PCI-X I/O Voltage
1.425
1.5
1.575
V
VCCAPE
Analog PCI Express Voltage
1.455
1.5
1.545
V
VCCAPCI[2:0]
Analog PCI Voltages
1.455
1.5
1.545
VCCBGPE
Analog Bandgap Voltage
2.425
2.5
2.575
VCCPE
PCI Express Interface Voltage
1.46
1.5
1.55
V
VCC33
PCI Bus Interface Voltage
3.0
3.3
3.6
V
PTDP
Thermal Design Power
10.2
W
Notes
1
2
1. Transient tolerance ±5 mV above 1 MHz at package pin under DC load conditions.
2. Transient tolerance ±10 mV above 1 MHz at package pin under DC load conditions.
17
41210 Bridge — Datasheet
3.1.2
Input Characteristic Signal Association
Table 11.
DC Characteristics Input Signal Association
Symbol
Signals
Interrupt Signals: A_IRQ[15:0]#, B_IRQ[15:0]#
VIH1/VIL1
PCI Signals: A_AD[63:0], B_AD[63:0], A_CBE[7:0]#, B_CBE[7:0]#, A_PAR, B_PAR,
A_DEVSEL#, B_DEVSEL#, A_FRAME#, B_FRAME#, A_IRDY#, B_IRDY#, A_TRDY#,
B_TRDY#, A_STOP#, B_STOP#, A_PERR#, B_PERR#, A_SERR#, B_SERR#, A_REQ[5:0]#,
B_REQ[5:0]#, A_M66EN, B_M66EN, A_133EN, B_133EN, A_PCIXCAP, B_PCIXCAP,
A_PAR64, B_PAR64, A_REQ64#, B_REQ64#, A_ACK64#, B_ACK64#
Clock Signals (3.3 V Only): A_CLKI, B_CLKI
Miscellaneous Signals: PERST#
VIH2/VIL2
PCI Express Signals: REFCLK, REFCLK#, PETP[7:0], PETN[7:0], PE_RCOMP[1:0]
VIH3/VIL3
SMB Signals: SMBDAT, SMBCLK
3.1.3
DC Input Characteristics
Table 12.
DC Input Characteristics
3.3 V Signal
Symbol
Parameter
Unit
Min
Max
VIL1
Input Low Voltage
-0.5
0.35 VCC33
V
VIH1
Input High Voltage
0.5 VCC33
VCC33 +0.5
V
Symbol
Parameter
Max
VIL2
Input Low Voltage
N/A
V
VIH2
Input High Voltage
N/A
V
VIL3
Input Low Voltage
0.6
V
VIH3
Input High Voltage
VCC33 + 0.5
V
3.1.4
DC Characteristic Output Signal Association
Table 13.
DC Characteristic Output Signal Association
Symbol
VOH1/VOL1
Signals
PCI Signals: A_AD[63:0], B_AD[63:0], A_CBE[7:0]#, B_CBE[7:0]#, A_PAR, B_PAR,
A_DEVSEL#, B_DEVSEL#, A_FRAME#, B_FRAME#, A_IRDY#, B_IRDY#, A_TRDY#,
B_TRDY#, A_STOP#, B_STOP#, A_PERR#, B_PERR#, A_M66EN, B_M66EN,
A_GNT[6:0]#, B_GNT[5:0]#, A_LOCK#, B_LOCK#, A_PAR64, B_PAR64, A_REQ64#,
B_REQ64#, A_ACK64#, B_ACK64#
PCI Clock Signals (3.3 V Only): A_CLKO[6:0], B_CLKO[6:0], A_RST#, B_RST#
Miscellaneous Signals: RASERR#
18
VOH2/VOL2
PCI Express Signals: PERP[7:0], PERN[7:0]
VOH3/VOL3
SMBus Signals: SMBDAT, SMBCLK
Datasheet — 41210 Bridge
3.1.5
DC Output Characteristics
Table 14.
DC Output Characteristic
3.3 V Signal
Symbol
Parameter
Unit
Min
VOL1
Output Low Voltage
VOH1
Output High Voltage
Symbol
0.1VCC33
0.9VCC33
Parameter
Notes
Max
(5 V) Iout = 6 mA
V
(3.3 V) Iout = 1500 uA
(5 V) Iout = -2 mA
V
Max
(3.3 V) Iout = -500 uA
Unit
Notes
VOL2
Output Low Voltage
N/A
V
VOH2
Output High Voltage
N/A
V
VOL3
Output Low Voltage
0.4
V
IOL4=14 mA
VOH3
Output High Voltage
N/A
V
Open Drain
3.1.6
PCI Express Interface DC Specifications
3.1.6.1
Differential Transmitter (TX) DC Output Specifications
Table 15 defines the DC specifications of parameters for the differential output at all transmitters
(TXs). The parameters are specified at the component pins.
Table 15.
Differential Transmitter (TX) DC Output Specifications (Sheet 1 of 2)
Symbol
Parameter
Min
VTX-DIFFp-p
Differential Peak to
Peak Output
Voltage
0.80
VTX-DE-RATIO
De-Emphasized
Differential Output
Voltage (Ratio)
-3.0
Nom
-3.5
Max
Units
1.2
V
-4.0
dB
Comments
VTX-DIFFp-p = 2*|VTX-D+-VTX-D-|
See Note 1.
This is the ratio of the VTX-DIFFp-p of the
second and following bits after a
transition divided by the VTX-DIFFp-p of
the first bit after a transition
See Note 1.
VTX-CM-ACp
VTX-CM-ACp =
CM-DC
AC Peak
Common Mode
Output Voltage
20
mV
|VTX-D+ + vTX-D-| / 2 – vTX-
vTX-CM-DC = DC(avg) of
/ 2 during L0
|VTX-D+ + VTX-D-|
See Note 1.
VTX-CM-DCACTIVE-IDLEDELTA
Absolute Delta of
DC Common Mode
Voltage During L0
and Electrical Idle
|VTX-CM-DC [during L0] – VTX-CM-IdleDC[during electrical idle]| <= 100mv
0
100
mV
VTX-CM-DC = DC(avg) of |VTX-D+ + VTX-D-|
/ 2 [electrical idle]
See Note 1.
19
41210 Bridge — Datasheet
Table 15.
Differential Transmitter (TX) DC Output Specifications (Sheet 2 of 2)
|VTX-CM-DC-D+ [during L0] – VTX-CM-DC-D[During L0.]|<=25mV
VTX-CM-DCLINE-DELTA
Absolute Delta of
DC Common Mode
Voltage between D+
and D-.
VTX-CM-DC-D+ = DC(avg) of |VTX-D+|
0
25
mV
[during L0]
VTX-CM-DC-D- = DC(avg) of |VTX-D-|
[during L0]
See Note 1.
VTX-IDLEDIFFp
VTX-RCVDETECT
Electrical Idle
Differential Peak
Output Voltage
0
20
mV
VTX-IDLE-DIFFp =|VTX-Idle-D+ -VTx-Idle-D|<=20mV
See Note 1.
The amount of
voltage change
allowed during
Receiver Detection.
600
mV
The total amount of voltage change that
a transmitter can apply to sense
whether a low impedance receiver is
present.
RLTX-DIFF
Differential Return
Loss
12
dB
Measured over 50 MHz to 1.25 GHz
See Note 2.
RLTX-CM
Common Mode
Return Loss
6
dB
Measured over 50 MHz to 1.25 GHz
See Note 2.
ZTX-DIFF-DC
DC Differential TX
Impedance
80
120
W
TX DC Differential Mode Low
impedance
5k
20k
W
TX DC High Impedance.
IMP-DC
Transmitter
Common Mode
High Impedance
State (DC)
CTX
AC Coupling
Capacitor
75
200
nF
All transmitters shall be AC coupled.
The AC coupling is required either
within the media or within the
transmitting component itself.
ZTX-COMHigh-
100
1. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 2,
“Compliance Test/Measurement Load” on page 23 and measured over any 250 consecutive TX UIs. (Also
refer to the Transmitter Compliance Eye Diagram as shown in Minimum Transmitter Timing and Voltage
Output Compliance Specification.)
2. The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a
common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This
input impedance requirement applies to all valid input levels. The reference impedance for return loss
measurements is 50W to ground for both the D+ and D- line (i.e., as measured by a Vector Network Analyzer
with 50W probes – see Figure 2). Note that the series capacitors CTX is optional for the return loss
measurement.
20
Datasheet — 41210 Bridge
3.1.6.2
Differential Receiver (RX) DC Input Specifications
Table 16 defines the DC specifications of parameters for all differential Receivers (RXs). The
parameters are specified at the component pins.
Table 16.
Differential Receiver (RX) DC Input Specifications
Symbol
VRX-DIFFp-p
VRX-CM-ACp
Parameter
Differential Input
Peak to Peak
Voltage
Min
Nom
0.17
5
Max
Units
1.20
0
V
Comments
VRX-DIFFp-p = 2*|VRX-D+ - VRX-D-|
See Note 1.
VRX-CM-AC=
|VRX-D+ + VRX-D-|/2– VRX-CM-DC
AC Peak Common
Mode Input Voltage
150
mV
VRX-CM-DC =
DC(avg) of |VRX-D++VRX-D-|/2 during L0
See Note 1.
RLRX-DIFF
Differential Return
Loss
15
dB
RLRX-CM
Common Mode
Return Loss
6
dB
ZRX-DIFF-DC
DC Differential Input
Impedance
80
100
120
W
ZRX-COM-
DC Input Common
Mode Input
Impedance
40
50
60
W
DC
ZRX-COMINITIAL-DC
ZRX-COMHIGH-IMP-
DC
VRX-IDLEDET-DIFFp-
p
Initial DC Input
Common Mode
Input Impedance
Measured over 50 MHz to 1.25 GHz
See Note 2.
Measured over 50 MHz to 1.25 GHz
See Note 2
RX DC Differential Mode impedance.
See Note 3.
RX DC Common Mode impedance 50
?+/-20% tolerance.
See Notes 1 and 3.
5
50
60
W
RX DC Common Mode impedance
allowed when the receiver terminations
are first powered on.
See Note 4.
Powered Down DC
Input Common
Mode Input
Impedance
200 k
Electrical Idle
Detect Threshold
65
W
RX DC Common Mode impedance when
the receiver terminations are not
powered (i.e., no power).
See Note 5.
175
mV
VRX-IDLE-DET-DIFFp-p =2*|VRX-D+ - VRX-D-|
Measured at the package pins of the
Receiver.
1. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 2,
“Compliance Test/Measurement Load” on page 23 should be used as the RX device when taking
measurements (also refer to the Receiver Compliance Eye Diagram as shown in Figure 3, “Minimum
Receiver Eye Timing and Voltage Compliance Specification” on page 23). If the clocks to the RX and TX are
not derived from the same clock chip the TX UI must be used as a reference for the eye diagram.
2. The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB and a
common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This
input impedance requirement applies to all valid input levels. The reference impedance for return loss
measurements for is 50 Ω to ground for both the D+ and D- line (i.e., as measured by a Vector Network
Analyzer with 50Ω probes - see Figure 2). Note: that the series capacitors CTX is optional for the return loss
measurement.
3. Impedance during all operating conditions.
4. The Rx DC Common Mode Impedance that must be present when the receiver terminations are first enabled
to ensure that the Receiver Detect occurs properly. Compensation of this impedance can start immediately
and the (ZRX-COM-DC)RxDC Common Mode Impedance must be with in the specified range by the time
Detect is entered.
5. The Rx DC Common Mode Impedance that exists when the receiver terminations are disabled or when no
power is present. This helps ensure that the Receiver Detect circuit will not falsely assume a receiver is
powered on when it is not.
21
41210 Bridge — Datasheet
Figure 1.
Minimum Transmitter Timing and Voltage Output Compliance Specification
There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be
aligned in time using the jitter median to locate the center of the eye diagram. The different eye
diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit.
The eye diagram must be valid for any 250 consecutive UIs. An appropriate average TX UI must
be used as the interval for measuring the eye diagram.
3.1.6.3
Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified by
the device vendor within 0.2 inches of the package pins, into a test/measurement load shown in
Figure 2.
Note:
The allowance of the measurement point to be within 0.2 inches of the package pins is meant to
acknowledge that package/board routing may benefit from D+ and D- not being exactly matched in length at
the package pin boundary. If the vendor does not explicitly state where the measurement point is located, the
measurement point is assumed to be the D+ and D-package pins.
22
Datasheet — 41210 Bridge
Figure 2.
Compliance Test/Measurement Load
The test load is shown at the transmitter package reference plane, but the same Test/Measurement
load is applicable to the receiver package reference plane. CTX is an optional portion of the
measurement test load. The measurement should be taken on the opposite side of the capacitor
from the package, and the value of the CTX must be in the range of 75 nF to 200 nF.
.
Figure 3.
Minimum Receiver Eye Timing and Voltage Compliance Specification
The RX eye diagram must be aligned in time using the jitter median to locate the center of the eye
diagram. The eye diagram must be valid for any 250 consecutive UIs. An appropriate average TX
UI must be used as the interval for measuring the eye diagram.
23
41210 Bridge — Datasheet
3.1.6.4
PCI and PCI-X Interface DC Specifications
Table 17 summarizes the DC specifications for 3.3V signaling.
Table 17.
DC Specifications for PCI and PCI-X 3.3 V Signaling
Symbol
Parameter
Min
Max
Units
Condition
VCC33
Supply Voltage
3.0
3.6
V
Vih
Input High Voltage
0.5 VCC33
VCC33 +0.5
V
Vil
Input Low Voltage
-0.5
0.3VCC33
V
Vipu
Input Pull-up Voltage
0.7VCC33
Iil
Input Leakage Current
±10
µA
0 < Vin < VCC33
Voh
Output High Voltage
V
Iout = -500 µA
Vol
Output Low Voltage
V
Iout = 1500 µA
Cin
Input Pin Capacitance
Cclk
X_CLKIN Pin Capacitance
CIDSEL
V
0.9VCC33
0.1VCC33
Notes
1
2
10
pF
8
pF
IDSEL Pin Capacitance
8
pF
4
Lpin
Pin Inductance
20
nH
5
IOff
X_PME# input leakage
1
µA
5
-
3
Vo ≤ 3.6 VCC33 off or
floating
6
1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are
calculated to pull a floated network. Applications sensitive to static power utilization must assure that the
input buffer is conducting minimum current at this input voltage.
2. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
3. Absolute maximum pin capacitance for a PCI/PCIX input except X_CLKIN and X_IDSEL.
4. For conventional PCI only, lower capacitance on this input-only pin allows for non-resistive coupling to
X_AD[xx]. PCI-X configuration transactions drive the AD bus four clocks before X_FRAME# asserts (see
Section 2.7.2.1, “Configuration Transaction Timing,” in the PCI-X Protocol Addendum to the PCI Local Bus
Specification Revision 2.0a).
5. For conventional PCI, this is a recommendation, not an absolute requirement. For PCI-X, this is a
requirement.
6. This input leakage is the maximum allowable leakage into the X_PME# open drain driver when power is
removed from VCC33 of the component. This assumes that no event has occurred to cause the device to
attempt to assert X_PME#.
24
Datasheet — 41210 Bridge
3.1.6.5
Input Clock DC Specifications
Table 18.
DC Specification for Input Clock Signals
Symbol
Parameter
Min
Max
Units
CLK100
Input Low Voltage
-0.5
0.8
V
CLK100
Input High Voltage
2.0
VCC3.3 + 0.5
V
CLK133
Input Low Voltage
-0.5
0.8
V
CLK133
Input High Voltage
2.0
VCC3.3 + 0.5
V
Units
Condition
3.1.6.6
Output Clock DC Specifications
Table 19.
DC Specification for Output Clock Signals
Symbol
Parameter
CLK33
Output Low Voltage
CLK33
Output High Voltage
CLK66
Output Low Voltage
CLK66
Output High Voltage
CLK100
Output Low Voltage
CLK100
Output High Voltage
CLK133
Output Low Voltage
CLK133
Output High Voltage
Min
Max
0.4
2.4
0.4
2.4
0.4
2.4
0.4
2.4
3.2
AC Specifications
3.2.1
PCI and PCI-X AC Characteristics
Table 20.
Conventional PCI 3.3V AC Characteristics (Sheet 1 of 2)
Sym
Parameter
Ioh(AC)
Switching Current
High
Iol(AC)
Switching Current
Low
Ich
High Clamp Current
Condition
Min
Vout = 0.7VCC33
Vout = 0.3VCC33
V
Iol = 1 mA
V
Ioh= -1 mA
V
Iol = 1 mA
V
Ioh= -1 mA
V
Iol = 1 mA
V
Ioh= -1 mA
V
Iol = 1 mA
V
Ioh= -1 mA
Max
-32VCC33
-12VCC33
Vout = 0.18VCC33
Unit
mA
mA
38VCC33
Note
1
mA
Vout = 0.6VCC33
16VCC33
mA
VCC33 + 4 > Vin
VCC33 + 1
25 + (Vin –
VCC33 – 1) /
0.015
mA
1
25
41210 Bridge — Datasheet
Table 20.
Conventional PCI 3.3V AC Characteristics (Sheet 2 of 2)
Icl
Low Clamp Current
-3 < Vin -1
-25 + (Vin + 1) /
mA
0.015
slewr
Output Rise Slew
Rate
0.3VCC33 to
0.6VCC33
1
4
V/ns
2
slewf
Output Fall Slew
Rate
0.6VCC33 to
0.3VCC33
1
4
V/ns
2
1. In conventional PCI switching, current characteristics for X_REQ# and X_GNT# are permitted to be one half
of that specified here; i.e., half size drivers may be used on these signals. This specification does not apply to
CLK and RSTIN# which are system outputs. “Switching Current High” specifications are not relevant to
X_SERR# which is an open drain output.
2. This parameter is to be interpreted as the cumulative edge rate across the specified range rather than the
instantaneous rate at any point within the transition range. For more details on slew rate measurement
conditions please refer to the PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification,
Revision 2.0a
Table 21.
PCI-X 3.3V AC Characteristics
Sym
Parameter
Condition
Min
0 < VCC33 –
Vout 3.6V
Ioh(AC)
Switching Current High
-74(VCC33 Vout)
Icl
Ich
Switching Current Low
Low Clamp Current
Unit
Note
mA
0 < VCC33 –
Vout 1.2V
-32 (VCC33 –
Vout)
mA
1
1.2V < VCC33 –
Vout 1.9V
-11 (VCC33 Vout) – 25.2
mA
1
1.9V < VCC33 –
Vout 3.6V
-1.8 (VCC33 Vout) – 42.7
mA
1
0 Vout 3.6V
Iol(AC)
Max
100Vout
mA
0 < Vout 1.3V
48Vout
1
1.3V < Vout
3.6V
5.7Vout + 55
1
-3V < Vin ≤ 0.8875V
-40 + (Vin + 1) /
0.005
mA
-0.8875V < Vin ≤
-0.625V
-25 + (Vin + 1) /
0.015
mA
0.8875V < Vin –
VCC33 ≤ -4V
40 + (Vin –
VCC33 - 1) /
0.005
mA
0.625V < Vin –
VCC33 ≤
0.8875V
25 + (Vin –
VCC33 - 1) /
0.015
mA
High Clamp Current
slewr
Output Rise Slew Rate
0.3VCC33 to
0.6VCC33
1
4
V/ns
2
slewf
Output Fall Slew Rate
0.6VCC33 to
0.3VCC33
1
4
V/ns
2
1. In conventional PCI switching, current characteristics for X_REQ# and X_GNT# are permitted to be one half
of that specified here; i.e., half size drivers may be used on these signals. This specification does not apply to
CLK and RST# which are system outputs. “Switching Current High” specifications are not relevant to
X_SERR#, which is an open drain output.
26
Datasheet — 41210 Bridge
2. This parameter is to be interpreted as the cumulative edge rate across the specified range rather than the
instantaneous rate at any point within the transition range. For more details on slew rate measurement
conditions please refer to the PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification,
Revision 2.0a.
3.3
Voltage Filter Specifications
The 41210 Bridge requires voltage filtering to reduce noise on critical voltage planes. There are
two filter types necessary on the platform:
• Analog Voltage Filter (PCI-Express and PCI)
• Bandgap Filter
Note:
3.4
For filter specifications, refer to the 41210 Serial to Parallel PCI Bridge Design Guide.
VCC15 and VCC33 Voltage Requirements
The 41210 Bridge requires that the VCC33 voltage rail be equal to or no less than 0.5V below
VCC15 (absolute voltage value) at all times during 41210 Bridge operation, including during
system power up and power down. In other words, the following must always be true:
VCC33 ≥ (VCC15 –0.5V)
Figure 4 graphically illustrates this requirement. This can be accomplished by placing a diode (with
a voltage drop < 0.5V) between VCC15 and VCC33. Anode will be connected to VCC15 and
cathode will be connected to VCC33.
Figure 4.
Voltage Requirements VCC33 versus VCC15
27
41210 Bridge — Datasheet
3.5
Timing Specifications
3.5.1
PCI Express Interface Timing
3.5.1.1
Differential Transmitter (TX) AC Output Specifications
Table 22 defines the AC specifications of parameters for the differential output at all transmitters
(TXs). The parameters are specified at the component pins.
Table 22.
Differential Transmitter (TX) AC Output Specifications
Symbol
UI
Parameter
Unit Interval
Min
399.88
Nom
400
Max
400.12
Units
ps
Comments
Each UI is 400 ps +/-300 ppm. UI
does not account for SSC dictated
variations.
See Note 1.
TTX-EYE
Minimum TX Eye
Width
0.70
UI
The maximum transmitter jitter
can be derived as TTX-MAX-JITTER
= 1 - TTX-EYE = .3 UI
See Notes 2 and 3.
TTX-EYEMEDIAN-toMAX-JITTER
Maximum time
between the jitter
median and
maximum deviation
for the median
0.15
UI
Jitter is defined as the
measurement variation of the
crossing points (VTX-DIFFp-p = 0V)
in relation to an appropriate
average TX UI.
See Notes 2 and 3.
TTX-RISE,
TTX-FALL
D+/D- TX Output
Rise/Fall Time
0.125
UI
See Notes 2 and 4.
TTX-IDLE-
Minimum time spent
in Electrical Idle
50
UI
Minimum time a transmitter must
be in electrical idle.
MIN
Maximum time to
transition to a valid
Electrical Idle after
sending an Electrical
Idle ordered-set
20
UI
After sending an electrical idle
ordered-set, the transmitter must
meet all electrical idle
specifications within this time.
DETECTMAX
Maximum time spent
in Electrical Idle
before initiating a
receiver detect
sequence.
100
ms
Maximum time spent in Electrical
Idle before initiating a receiver
detect sequence.
LTX-SKEW
Lane-to-Lane Output
Skew
500
ps
Between any two Lanes within a
single Transmitter.
TTX-IDLESET-
TO-IDLE
TTX-IDLERCV-
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 2,
“Compliance Test/Measurement Load” on page 23 and measured over any 250 consecutive TX UIs. (Also
refer to the Transmitter Compliance Eye Diagram as shown in Minimum Transmitter Timing and Voltage
Output Compliance Specification.)
3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX =
0.30 UI for the transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER
specification ensures a jitter distribution in which the median and the maximum deviation from the median is
less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that
the median is not the same as the mean. The jitter median describes the point in time where the number of
jitter points on either side is approximately equal as opposed to the averaged time value.
28
Datasheet — 41210 Bridge
4. Measured between 20-80% at Transmitter package pins into a test load as shown in Figure 2 for both VTX-D+
and VTX-D-.
3.5.1.2
Differential Receiver (RX) AC Input Specifications
Table 23 defines the AC specifications of parameters for all differential Receivers (RXs). The
parameters are specified at the component pins.
Table 23.
Differential Receiver (RX) AC Input Specifications
Symbol
Parameter
UI
Unit Interval
TRX-EYE
Minimum
Receiver Eye
Width
Min
399.88
Nom
400
Max
400.12
0.4
Units
ps
UI
Comments
The UI is 400 ps +/-300 ppm. UI
does not account for SSC dictated
variations. See Note 1.
The maximum interconnect media
and transmitter jitter that can be
tolerated by the receiver can be
derived asTRX-MAX-JITTER =1 -TRXEYE =0.6 UI
See Notes 2 and 3.
TRX-EYEMEDIAN-to-
MAX-JITTER
TRX-IDLE-DETDIFF-
ENTERTIME
LRX-SKEW
Maximum time
between the jitter
median and
maximum
deviation from
the median.
Unexpected
Electrical Idle
Enter Detect
Threshold
Integration Time
Total Skew
0.3
UI
Jitter is defined as the
measurement variation of the
crossing points (VRX- DIFFp-p = 0 V)
in relation to an appropriate
average TX UI.
See Notes 2 and 3.
10
20
ms
An unexpected electrical idle (VRXmust
be recognized no longer than TRXIDLE-DET- DIFF-ENTERTIME to signal
an unexpected idle condition.
ns
Across all Lanes on a port. This
includes variation in the length of a
skip ordered-set (e.g., COM and 1
to 5 SKP symbols) at the RX as well
as any delay differences arising
from the interconnect itself.
DIFFp-p <VRX-IDLE-DET- DIFFp-p)
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 2,
“Compliance Test/Measurement Load” on page 23 should be used as the RX device when taking
measurements (also refer to the Receiver Compliance Eye Diagram as shown in Figure 3, “Minimum
Receiver Eye Timing and Voltage Compliance Specification” on page 23). If the clocks to the RX and TX are
not derived from the same clock chip the TX UI must be used as a reference for the eye diagram.
3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the
transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER
specification ensures a jitter distribution in which the median and the maximum deviation from the median is
less than half of the total .6 UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that
the median is not the same as the mean. The jitter median describes the point in time where the number of
jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the
RX and TX are not derived from the same clock chip, the appropriate average TX UI must be used as the
reference for the eye diagram.
29
41210 Bridge — Datasheet
3.5.2
PCI and PCI-X Interface Timing
Table 24.
PCI Interface Timing
Functional Operating Range (VCC33 = 3.3 V + 5%, Tcase=0°C to 105°C)
66 MHz
Symbol
Parameter
Min
33 MHz
Max
Min
Max
Units
Notes
Tval
CLK to Signal Valid Delay;
bused signals
2
6
2
11
ns
1, 2, 3
Tval(ptp)
CLK to Signal Valid Delay;
point-to-point signals
2
6
2
12
ns
1, 2, 3
Ton
Float to Active Delay
2
ns
1, 7
Toff
Active to Float Delay
ns
1, 7
Tsu
Input Setup Time to CLK;
Bused signals
3
7
ns
3, 4, 8
Tsu(ptp)
Input Setup Time to CLK;
point-to-point
5
10,12
ns
3, 4
Th
Input Hold Time from CLK
0
0
ns
4
Trst
Reset Active Time after power
stable
1
1
ms
5
Trst-clk
Reset Active Time after CLK
stable
100
100
µs
5
ns
5, 6
2
14
28
Trst-off
Reset Active to output float delay
Trrsu
PxREQ64# to RSTIN# setup time
10
Trrh
RSTIN# to PxREQ64# hold Time
0
Trhfa
RSTIN# high to first configuration
access
225
225
clocks
Trhff
RSTIN# high to first PxFRAME#
Assertion
5
5
clocks
Tpvrh
Power Valid to RSTIN# High
100
100
ms
40
40
10
50
0
clocks
50
ns
9
1. It is important that all driven signal transitions drive to their Voh or Vol level within one Tcyc.
2. Minimum times are measured at the package pin (not the test point) with the load circuit shown in the PCI-X
Electrical and Mechanical Addendum, Revision 2.0a. Maximum times are measured with the test point and
load circuit shown in the PCI-X Electrical and Mechanical Addendum, Revision 2.0a.
3. X_REQ_[5:0]# and X_GNT_[5:0]# are point-to-point signals and have different input setup times than do
bused signals. X_GNT_[5:0]# and X_REQ_[5:0]# have a setup of 5 ns at 66 MHz. All other signals are
bused.
4. See Section 3.5, “Timing Specifications” on page 28 and the measurement conditions in the PCI-X Electrical
and Mechanical Addendum, Revision 2.0a.
5. If X_M66EN is asserted, CLK is stable when it meets the requirements in the PCI Local Bus Specification
Revision 2.3. RSTIN# is asserted and deasserted asynchronously with respect to CLK.
6. When X_M66EN is asserted, the minimum specification for Tval(min), Tval(ptp)(min), and Ton may be reduced
to 1 ns if a mechanism is provided to guarantee a minimum value of 2 ns when X_M66EN is deasserted.
7. For purposes of active/float timing measurements, the Hi-Z or “off” state is defined to be when the total
current delivered through the component pin is less than or equal to the leakage current specification.
8. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at
the same time. Refer to the PCI Local Bus Specification Revision 2.3 for more details.
9. Maximum value is also limited by delay to the first transaction (Trhff).
30
Datasheet — 41210 Bridge
Figure 5.
PCI Output Timing
Figure 6.
PCI Input Timing
Table 25.
PCI-X 3.3V Signal Timing Parameters (Sheet 1 of 2)
Sym
Parameter
PCI-X 133
Min
Tval
CLK to Signal Valid Delay
0.7
Max
3.8
PCI-X 66
Min
0.7
Units
Notes
Max
3.8
ns
1, 2, 8
31
41210 Bridge — Datasheet
Table 25.
PCI-X 3.3V Signal Timing Parameters (Sheet 2 of 2)
Ton
Float to Active Delay
Toff
Active to Float Delay
0
0
ns
1, 6, 8
ns
1, 6, 8
Tsu
Input Setup Time to CLK
1.2
1.7
ns
3, 7
Th
Input Hold Time from CLK
Trst
Reset Active Time after power
stable
0.5
0.5
ns
3
1
1
ms
4
Trst-clk
Reset Active Time after CLK stable
100
100
µs
4
Trst-off
Reset Active to output float delay
ns
4
Trrsu
PxREQ64# to RSTIN# setup time
10
Trrh
RSTIN# to PxREQ64# hold Time
0
Trhfa
RSTIN# high to first configuration
access
226
226
clocks
Trhff
RSTIN# high to first PxFRAME#
Assertion
5
5
clocks
Tpvrh
Power valid to RSTIN# high
100
100
ms
Tprsu
PCI-X initialization pattern to
RSTIN# setup time
10
10
clocks
Tprh
RSTIN# to PCI-X initialization
pattern hold time
0
Trlcx
Delay from RSTIN# low to CLK
frequency change
0
7
7
40
40
10
50
50
0
0
0
ns
50
50
ns
ns
7
7
ns
1. See the timing measurement conditions in Section 3.5, “Timing Specifications” on page 28.
2. Minimum times are measured at the package pin (not the test point) with the load circuit shown in the PCI-X
Electrical and Mechanical Addendum, Revision 2.0a. Maximum times are measured with the test point and
load circuit shown in PCI-X Electrical and Mechanical Addendum, Revision 2.0a.
3. See the timing measurement conditions in Section 3.5, “Timing Specifications” on page 28 and the PCI-X
Electrical and Mechanical Addendum, Revision 2.0a.
4. RST# is asserted and deasserted asynchronously with respect to CLK.
5. For purposes of Active/Float timing measurements, the Hi-Z or "off" state is defined to be when the total
current delivered through the component pin is less than or equal to the leakage current specification
6. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at
the same time.
7. Maximum value is also limited by delay to the first transaction (Trhfa). The PCI-X initialization pattern control
signals after the rising edge of RSTIN# must be deasserted no later than two clocks before the first
PxFRAME# and must be floated no later than one clock before PxFRAME# is asserted.
8. Device must meet this specification independent of how many outputs switch simultaneously.
32
Datasheet — 41210 Bridge
3.5.3
PCI and PCI-X Clock Specification
Clock measurement conditions are the same for PCI-X devices as for conventional PCI devices in a
3.3V signaling environment except for voltage levels specified in Table 26, “PCI and PCI-X Clock
Timings” on page 33. The same spread-spectrum clocking techniques are allowed in PCI-X as for
66 MHz conventional PCI. If a device includes a PLL, that PLL must track the input variations of
spread-spectrum clocking specified in Table 26.
Figure 7. PCI-X 3.3V Clock Waveform
Table 26.
PCI and PCI-X Clock Timings
PCI-X 133
Symbol
T
cyc
PCI-X 66
PCI 66
PCI 33
Parameter
CLK Cycle
Time
Min
Max
Min
Max
Min
Max
Min
Max
Units
Notes
Average
7.5
20
15
20
15
30
30
∞
ns
1,3,4
Absolute
Minimum
7.375
14.8
14.8
29.7
ns
1,3
Thigh
CLK high
time
3
6
6
11
ns
Tlow
CLK low
time
3
6
6
11
ns
Tjit
CLK Period
Jitter
125
-125
200
-200
200
-200
300
-300
ps
5
1.5
4
1
4
V/ns
2
Slew Rate
—
CLK slew
rate
1.5
4
1.5
4
Spread Spectrum Requirements
fmod
Modulation
frequency
30
33
30
33
30
33
kHz
fsprea
d
Frequency
spread
-1
0
-1
0
-1
0
%
1. For clock frequencies above 33 MHz, the clock frequency may not change beyond the spread-spectrum and
jitter limits except while RSTIN# is asserted.
2. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in the
PCI-X Electrical and Mechanical Addendum, Revision 2.0a.
3. The minimum clock period must not be violated for any single clock cycle (i.e. accounting for all system jitter).
4. Average Tcyc is measured over any 1 µs period of time and must include all sources of clock variation.
33
41210 Bridge — Datasheet
5. Period jitter is the deviation between any single period of the clock, Tcyc, and the average period of the clock,
Tcyc(average).
34
Datasheet — 41210 Bridge
3.5.4
41210 Bridge Clock Timings
Table 27.
41210 Bridge Clock Timings
Symbol
Parameter
Min
Max
Units
Notes
Tperiod
Average Period
10.0
10.2
ns
6
Trise
Rise time across 600 mV
300
600
ps
7,8
Tfall
Fall time across 600 mV
300
600
ps
7,8
—
Rise/Fall Matching
CLK100
—
Cross point at 1 V
Tccjitter
Cycle to Cycle jitter
—
Duty Cycle
—
Maximum voltage allowed at input
—
Minimum voltage allowed at input
—
Rising edge ringback
—
Falling edge ring back
20%
0.51
45
7,9
0.76
V
200
ps
55
%
1.45
V
-200
mV
0.85
V
0.35
V
CLK133
Tperiod
Average Period
7.5
7.65
ns
6
Trise
Rise time across 600 mV
300
600
ps
7,8
Tfall
Fall time across 600 mV
300
600
ps
7,8
—
Rise/Fall Matching
—
Cross point at 1V
Tccjitter
20%
0.51
Cycle to Cycle jitter
45
7,9
0.76
V
125
ps
55
%
—
Duty Cycle
—
Maximum voltage allowed at input
1.45
V
—
Minimum voltage allowed at input
-200
mV
—
Rising edge ringback
—
Falling edge ring back
0.85
10
V
0.35
V
CLK33
CLK period
30.0
N/A
ns
1,2
Thigh
CLK high time
12.0
N/A
ns
3
Tlow
CLK low time
12.0
N/A
ns
4
—
Rising edge rate
1.0
4.0
V/ns
5
—
Falling edge rate
1.0
4.0
V/ns
5
Trise
CLK rise time
0.5
2.0
ns
5
Tfall
CLK fall time
0.5
2.0
ns
5
Tperiod
1. Period, jitter, offset and skew measured on rising edge @ 1.5V for 3.3V clocks.
35
41210 Bridge — Datasheet
2.
3.
4.
5.
The average period over any 1 us period of time must be greater than the minimum specified period.
Thigh is measured at 2.4V for non-host outputs.
Tlow is measured at 0.4V for all outputs.
For 3.3V clocks Trise and Tfall are measured as a transition through the threshold region Vol = 0.4V and Voh =
2.4V (1 mA) JEDEC Specification.
6. Measured at crossing point.
7. Measured from Vol = 0.2V to Voh = 0.8V.
8. Still simulating to determine [0.2–0.8 V] or [0.3–0.9 V].
9. Determined as a fraction of 2*(Trise – Tfall) / (Trise + Tfall).
10.Period jitter is the deviation between any single period of the clock, Tcyc, and the average period of the clock,
Tcyc(average).
3.5.4.1
Spread Spectrum Clocking
Spread spectrum clocking can be used on the 41210 Bridge to reduce energy. Spread Spectrum
clocking is a common technique used by system designers to meet FCC emissions, where the
frequency is deliberately shifted around to spread the energy off of the peak. The following is to be
observed when using Spread Spectrum clocking:
• All device timings (including jitter, skew, min/max clock period, output rise/fall time) MUST
meet the existing non-spread spectrum specifications
• All non-spread Host and PCI functionality must be maintained in the spread spectrum mode
(includes all power management functions.)
• The minimum clock period cannot be violated. The preferred method is to adjust the spread
technique to not allow for modulation above the nominal frequency. This technique is often
called “down-spreading”. The modulation profile in a modulation period can be expressed as:
Equations:

 (1 − δ ) f nom + 2 f m ⋅ δ ⋅ f nom ⋅ t
f =
(1 + δ ) f nom − 2 f m ⋅ δ ⋅ f nom ⋅ t

1
;
2 fm
1
1
<t <
,
when
fm
2 fm
when 0 < t <
where:
fnom is the nominal frequency in the non-SSC mode
fm is the modulation frequency
fm is the modulation amount
t is time.
3.6
41210 Bridge Power Consumption
Table 28 provides details on the maximum draw from the power planes by the 41210 Bridge for
use in voltage regulation.
36
Datasheet — 41210 Bridge
Table 28.
41210 Bridge Maximum Voltage Plane Currents
Power Plane
Maximum Voltage Plane Current (Amps)
Frequency (MHz)
133
100
66
Number of Slots
1
2
4
IVCC15 (core 1.5V)
1.68
1.61
1.55
IVCC15 (I/O 1.5V)
0.22
0.22
0.22
VCCBGPE
0.005
0.005
0.005
0.70
0.70
0.70
1.05
1.14
1.22
IVCCPE (PCI Express 1.5V)
IVCC33 (PCI/PCI-X Mode 1 3.3V)
1.
1
Per PCI-X Bus segment
Table 29 provides details on the maximum nominal draw from the power planes by the 41210
Bridge for use in thermal design.
Table 29.
41210 Bridge Thermal Voltage Plane Currents
Power Plane
Thermal Voltage Plane Current (Amps)
Frequency (MHz)
133
100
66
Number of Slots
1
2
4
IVCC15 (core 1.5V)
1.24
1.18
1.11
IVCC15 (I/O 1.5V)
0.22
0.22
0.22
VCCBGPE
0.005
0.005
0.005
0.69
0.69
0.69
0.99
1.04
1.10
IVCCPE (PCI Express 1.5V)
IVCC33 (PCI/PCI-X Mode 1 3.3V)
1.
3.7
1
Per PCI-X Bus segment
Power Delivery Guidelines
Please refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide.
3.8
Reference and Compensation Pins
The 41210 Bridge has one reference pin and three compensation pins:
• PE_RCOMP[1:0] are two separate pins that provide voltage compensation for the PCI
Express interface on the 41210 Bridge. The nominal compensation voltage is 0.5V. An
external 24.9 ±1% pull-up resistor should be used to connect to VCC15. A single pull-up
resistor can be used to for both of these signals.
37
41210 Bridge — Datasheet
• RCOMP is an analog PCI interface compensation pin to the 41210 Bridge. A 100 ±1% pulldown resistor should be used to connect the RCOMP pin to ground.
All three of these implementations are shown in Figure 8.
Figure 8.
41210 Bridge Reference and Compensation Circuit Implementations
3.9
Thermal Specifications
3.9.1
Power
For TDP specifications, see 41210 Bridge Thermal Specifications for the 41210 Bridge
component. FC-BGA packages have poor heat transfer capability into the board and have minimal
thermal capability without thermal solutions. Intel recommends that system designers plan for a
heatsink when using the 41210 Bridge component.
3.9.2
Die Temperature
To ensure proper operation and reliability of the 41210 Bridge component, the die temperatures
must be at or below the values specified in Table 30. System and/or component level thermal
solutions are required to maintain die temperatures below the maximum temperature
specifications.
38
Datasheet — 41210 Bridge
Table 30.
Note:
41210 Bridge Thermal Specifications
Parameter
Maxinum
Tcase
105×C
TDPMode#1/Mode#1
8.70W
TDPMode#1/No Connect
8.30W
TDPDDR/No Connect
8.10W
Mode 1: PCI-X 66MHz, 64-bit, 4 slots/devices
No Connect: Unused PCI segment (no slots/devices on PCI bus segment)
3.9.3
Thermal Solution Component Suppliers
3.9.3.1
Torsional Clip Heatsink Thermal Solution
Part
Intel Part Number
Supplier
(Part Number)
Heatsink Assembly includes:
Unidirectional Fin Heatsink
Thermal Interface Material
C76435-001
CCI/ACK
C76434-001
CCI/ACK
Torsional Clip
Unidirectional Fin Heatsink
(31.0 x 31.0 x 12.2mm)
Thermal Interface
(Chomerics T-710)
A69230-001
Chomerics
69-12-22066-T710
Heatsink Attach Clip
C17725-001
CCI/ACK
Solder-Down Anchor
A13494-005
Foxconn
(HB96030-DW)
Contact Information
Harry Lin (USA)
714-739-5797
[email protected]
Monica Chih (Taiwan)
866-2-29952666, x131
[email protected]
Harry Lin (USA)
714-739-5797
[email protected]
Monica Chih (Taiwan)
866-2-29952666, x131
[email protected]
Todd Sousa (USA)
360-606-8171
[email protected]
Harry Lin (USA)
714-739-5797
[email protected]
Monica Chih (Taiwan)
866-2-29952666, x131
[email protected]
Julia Jiang (USA)
408-919-6178
[email protected]
Note:
The enabled components may not be currently available from all suppliers. Contact the supplier
directly to verify time of component availability.
39
41210 Bridge — Datasheet
4
Package Specification and Ballout
4.1
Package Specification
The 41210 Bridge is in a 567-ball FCBGA package, 31mm X 31mm in size, with a 1.27mm ball
pitch (see Figure 9 and Figure 10).
Figure 9.
41210 Bridge Package Dimensions (Top View)
Handling
Exclusion
Area
0.550 in.
Die Area
21.00 mm
0.550 in.
17.00 mm
31.00 mm
17.00 mm
21.00 mm
31.00 mm
Pkg_567-Ball_Top
40
Datasheet — 41210 Bridge
Figure 10.
41210 Bridge Package Dimensions (Side View)
Note:
Primary datum -C- and seating plane are defined by the spherical crowns of the solder balls.
Note:
All dimensions and tolerances conform to ANSI Y14.5M-1982
41
41210 Bridge — Datasheet
4.2
Ball Map
24
AD
22
AC
A_
A_
A_
REQ64# AD[0] AD[2]
AB
A_
ACK64# AA
A_
A_
CBE2# AD[18]
21
20
19
A_
A_
AD[5] AD[7]
A_
A_
AD[21] CBE3# A_
AD[16]
V
A_
IRDY#
U
T
NC17
R
A_
A_
AD[34] AD[35] A_
A_
AD[36] AD[37]
16
15
A_
A_
AD[26] RST#
14
13
A_
A_
AD[13] AD[14]
A_
A_
AD[9] AD[11] A_
A_
CBE1# AD[15]
A_
A_
A_
AD[29] AD[12] VCC33 PAR
A_
A_
AD[31] GNT4#
A_
A_
LOCK# AD[50]
A_ AD[51] A_
A_
PERR# AD[52] A_
A_
AD[38] AD[39] A_
AD[53] A_
A_
A_
AD[54] REQ3# AD[55] A_
A_
A_
A_
AD[40] AD[41] NC15 VCC33 AD[56] AD[57] M
L
17
A_
A_
A_
A_
AD[27] AD[28] VCC33 GNT2# GNT3#
A_
A_
A_
A_
A_
A_
A_
CLKO AD[30]
REQ1# REQ0# REQ5#
GNT0# AD[25] [1]
A_
A_
A_
A_
A_
A_
A_
CLKO CLKO FRAME# PME# 133EN REQ2# CLKO
[2]
[6]
[0]
A_
A_
A_
A_
A_ A_
A_
A_
CLKO CLKO DEV
CLKO CLKIN
GNT5# TRDY#
[5]
[3]
SEL# STOP#
[4]
A_
A_
A_
A_
VCC33 AD[32]
AD[33] VCC33 SERR# M66EN VCC33 W
N
A_
A_
A_
A_
AD[20] AD[3] AD[24] AD[8]
A_
A_
A_
A_
VCC33 AD[17]
AD[19] VCC33 AD[22] AD[23]
18
A_
A_
A_
A_
AD[4] AD[6] VCC33 CBE0# AD[10] Y
P
A_
A_
AD[42] REQ4# A_
AD[59] A_
AD[44]
J
A_
A_
GNT1# AD[46]
H
A_
A_
A_
A_
A_
VCC33 AD[48] AD[49] VCC33 CBE7#
CBE6# VCC33 CBE4# VCCPE PETN
[3]
G
PETP
[3]
E
D
C
B
A
A_
AD[45] NC13
A_
A_
AD[43] AD[58] K
F
A_
A_
AD[47] PAR64
A_NC7 A_NC5 A_
A_
A_
AD[62] AD[61] AD[60] A_
A_
CBE5# AD[63] NC12 NC11
RES
A_
A_NC4 A_NC9 ERVED STRAP6 NC1 4
PE_ PERP
A_
A_
VCC33 A_NC8 NC10 NC6 PCIX RCOMP [0]
CAP
[0]
RES A_
PETP
PETN
A_
A_NC3 A_NC6 ERVED
STRAP5 STRAP1
[1]
[1]
3
RES
A_
A_
REF REF
VCC33 ERVED STRAP3 STRAP0 CLKN CLKP VCCPE
1
A_ RES B_ VCC33 PE_
PETP
A_NC1 STRAP2
RCOMP ERVED STRAP3
[2]
[1]
2
PERP PERN
B_
B_ A_NC2 NC3 STRAP4
[1]
[1]
STRAP0 24
42
23
A_
AD[1]
23
22
21
20
19
18
17
16
15
VCCPE PETP PETN
[0]
[0]
PERN
[0]
PERP
[2]
PERN
[2]
PETN
[2]
VCCPE 14
13
B3552-01
Datasheet — 41210 Bridge
12
VSS
11
10
8
VSS
B_AD B_AD
[12] [10]
B_
PAR
B_AD
[14]
VSS
B_
CBE1# VSS
7
VSS
6
5
B_AD B_AD
[7]
[6]
4
VSS
B_AD B_AD
[31] [28]
VSS
B_AD
[24]
B_
i3#
B_AD B_AD
[20]
[3]
VSS
B_ B_AD
B_AD B_AD
B_AD B_AD
GNT2# [30] VCC33 [27]
[26] VCC15 [22]
[21]
B_
B_ B_AD
GNT4# VCC33 CLKO[0] [29]
3
2
B_AD B_AD
[2]
[1]
1
VSS
AD
B_ B_AD VCC33 B_AD B_AD VCC15 B_AD B_
[0] REQ64# AC
CBE0# [9]
[4]
[5]
B_AD B_AD VCC33 B_AD B_
[13] [11]
[8] REQ1# VSS
B_
B_
REQ5# GNT3# VSS
VSS
9
B_AD
[15]
B_
ACK64# AB
B_AD B_AD VCC33
AA
[19]
[18]
VSS
B_AD B_
[17] CBE2# Y
B_AD
B_
B_
TRDY# LOCK# VCC33 [16]
W
B_
B_
B_
B_
B_
B_
VCC15 RCOMP VSS CLKO[1] CLKO[2] VSS CLKO[4] REQ4# VCC33 STOP# SERR# VSS
V
VSS
B_AD B_AD
[25] [23]
VSS
VSS
B_
B_
B_
B_
STRAP3 CLKIN VCC33 CLKO[6] CLKO[5] VSS
VSS
VCC15 VSS VCC15
VCC15 VSS VCC15 VSS
VSS
VCC
APC12
B_
B_
B_
B_
IRDY# FRAME# VSS PERR# M66EN U
B_
B_
B_
B_
CLKO[3] REQ2# VCC33 NC10 DEVSEL# VSS REQ3# T
B_
B_
AD[36] AD[35]
R_
B_
B_
RST# AD[53] AD[52] VSS
VCC15 VSS VCC15 NC14
B_
B_
AD[33] AD[32] VSS
B_
VCC33 NC16 PME#
B_
B_
VCC15 VSS VCC15 AD[51] AD[50] VSS
VCC15 VSS VCC15 VSS
VSS
VSS
VSS
VSS
VSS
B_
B_
133EN AD[34] P
B_
B_
AD[35] AD[35] VSS
B_
B_
AD[55] AD[54] VSS
N
B_
B_
AD[40] AD[39]
M
B_
B_
B_
B_
B_
B_
VCC15 VSS VCC15 VSS GNT5#
AD[57] VCC33 AD[56] REQ0# VCC15 AD[42] AD[41]
VSS
VCC15 VSS VCC15 VSS
VCCPE VSS VCCPE VSS
VCC
APC11
B_
B_
B_
B_
AD[59] AD[58] VSS AD[44] AD[43]
R
VSS
B_
B_
B_
B_
B_
AD[61] AD[60] GNT0# VSS AD[46] AD[45]
L
B_
GNT1# K
VSS
J
B_
PERP VCCPE VSS
B_
B_
B_
B_
B_
B_
[3]
CBE5# AD[63] PAR64 VSS AD[62] AD[47] VCC33 AD[49] AD[48] H
PERN VSS
[3]
PERN B_
B_
B_
[7] CBE4# VSS CBE7# CBE6# VSS
PERP
VCCPE PETN
[7] TRST#
[7]
B_
NC8
PERN PETP
[6]
[7]
VSS
VSS
TDI
PETP PETN
[6]
[6]
SMB
DAT
VCCPE PERP PERN PERN
[4]
[4]
[5]
VSS
PERP
[6]
VSS
B_
NC8
B_
NC5
VSS
B_
INTB#
SMB
CLK
NC18
VSS
NC4
B_
TEST1
VSS
B_
INTD#
RES
B_
B_
PETP PETN VSS PERP CFG TCK NC19 B_ ERVED
B_
[5] RETRY
[4]
STRAP6 6 STRAP1 NC1 NC7
[4]
RES
PETP PETN VSS
B_
VCC33 TDO NC2 VSS ERVED STRAP5
[5]
[5]
5
12
11
10
9
8
G
B_ RES B_
B_
B_
NC7 ERVED NC10 INTC# INTA# VCC33 F
8
B_
B_
B_
B_
TMS
STRAP4 VSS NC2 NC9 VSS NC4 E
RES
B_
B_ VCC33 ERVED
B_
B_
B_
PCIX NC5
NC6 NC3 TEST2 D
7
CAP
B_
NC9
7
6
5
4
3
2
1
C
B
A
B3553-01
43
41210 Bridge — Datasheet
4.3
Signal List, sorted by Ball Location
Table 31.
Ball
Signal List, sorted by Ball Name (Sheet 1 of 4)
Signal Name
A1
44
Ball
Signal Name
Ball
Signal Name
C1
B_INTD#
E1
B_NC4
A2
B_STRAP5
C2
VSS
E2
VSS
A3
RESERVED5
C3
B_TEST1
E3
B_NC9
A4
VSS
C4
NC4
E4
B_NC2
A5
NC2
C5
VSS
E5
VSS
A6
TDO
C6
NC18
E6
B_STRAP4
A7
VCC33
C7
SMBCLK
E7
TMS
A8
VSS
C8
VSS
E8
VSS
A9
PETN[5]
C9
PERN[5]
E9
TDI
A10
PETP[5]
C10
PERN[4]
E10
VSS
A11
C11
PERP[4]
E11
PETP[7]
A12
C12
VCCPE
E12
PERN[6]
A13
VSSBGPE
C13
PERN[2]
E13
VSS
A14
VCCPE
C14
VCCBGPE
E14
PERN[0]
A15
PERN[1]
C15
VCCPE
E15
PERP[0]
A16
PERP[1]
C16
REFCLKP
E16
PE_RCOMP[0]
A17
VSS
C17
REFCLKN
E17
A_PCIXCAP
A18
SMBUS[3]
C18
A_STRAP0
E18
CFGRST#
A19
B_STRAP0
C19
A_STRAP3
E19
NC6
A20
VSS
C20
VSS
E20
VSS
A21
A_STRAP4
C21
RESERVED1
E21
A_NC10
A22
NC3
C22
VCC33
E22
A_NC8
A23
A_NC2
C23
VSS
E23
VSS
A24
VSS
C24
A_INTD#
E24
VCC33
B1
B_NC7
D1
B_TEST2
F1
VCC33
B2
B_NC1
D2
B_NC3
F2
B_INTA#
B3
B_STRAP1
D3
B_NC6
F3
B_INTC#
B4
RESERVED6
D4
RESERVED7
F4
B_NC10
B5
B_STRAP6
D5
VCC33
F5
RESERVED8
B6
NC19
D6
NC5
F6
NC7
B7
TCK
D7
B_PCIXCAP
F7
NC9
B8
CFGRETRY
D8
SMBDAT
F8
NC8
B9
PERP[5]
D9
PETN[6]
F9
TRST#
B10
VSS
D10
PETP[6]
F10
PERP[7]
B11
PETN[4]
D11
VSS
F11
PETN[7]
B12
PETP[4]
D12
PERP[6]
F12
VCCPE
B13
VSS
D13
PERP[2]
F13
PETN[0]
B14
PETN[2]
D14
VSS
F14
PETP[0]
B15
PETP[2]
D15
PETN[1]
F15
VSS
B16
VSS
D16
PETP[1]
F16
VSSAPE
B17
PE_RCOMP[1]
D17
VSS
F17
PERST#
B18
VCC33
D18
A_STRAP1
F18
NC1
B19
B_STRAP2
D19
A_STRAP5
F19
A_STRAP6
RESERVED4
B20
SMBUS[2]
D20
SMBUS[5]
F20
B21
RESERVED2
D21
RESERVED3
F21
A_NC9
B22
A_STRAP2
D22
A_NC6
F22
A_TEST1
B23
A_TEST2
D23
A_INTC#
F23
A_NC4
B24
A_NC1
D24
A_NC3
F24
A_INTB#
Datasheet — 41210 Bridge
Table 31.
Signal List, sorted by Ball Name (Sheet 2 of 4)
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
G1
B_INTB#
J1
VSS
L1
B_AD[41]
G2
VSS
J2
B_AD[45]
L2
B_AD[42]
G3
B_NC5
J3
B_AD[46]
L3
VCC15
G4
B_NC8
J4
VSS
L4
B_REQ0#
B_AD[56]
G5
VSS
J5
B_GNT0#
L5
G6
B_CBE6#
J6
B_AD[60]
L6
VCC33
G7
B_CBE7#
J7
B_AD[61]
L7
B_AD[57]
B_GNT5#
G8
VSS
J8
VCCAPCI1
L8
G9
B_CBE4#
J9
VSS
L9
VSS
G10
PERN[7]
J10
VCCPE
L10
VCC15
G11
VSS
J11
VSS
L11
VSS
G12
PERN[3]
J12
VCCPE
L12
VCC15
G13
PETP[3]
J13
VSS
L13
VSS
G14
VSS
J14
VCCPE
L14
VCC15
G15
VCCAPE
J15
VSS
L15
VSS
G16
SMBUS[1]
J16
VCC15
L16
VCC15
G17
VSS
J17
A_AD[63]
L17
A_AD[59]
G18
NC11
J18
A_CBE5#
L18
VSS
G19
NC12
J19
VSS
L19
A_AD[58]
G20
VSS
J20
A_PAR64
L20
A_AD[43]
G21
A_NC5
J21
A_AD[47]
L21
VSS
G22
A_NC7
J22
VSS
L22
A_REQ4#
G23
VSS
J23
A_AD[46]
L23
A_AD[42]
G24
A_INTA#
J24
A_GNT1#
L24
VSS
H1
B_AD[48]
K1
B_GNT1#
M1
H2
B_AD[49]
K2
VSS
M2
B_AD[39]
H3
VCC33
K3
B_AD[43]
M3
B_AD[40]
H4
B_AD[47]
K4
B_AD[44]
M4
VSS
H5
B_AD[62]
K5
VSS
M5
B_AD[54]
H6
VSS
K6
B_AD[58]
M6
B_AD[55]
H7
B_PAR64
K7
B_AD[59]
M7
VSS
H8
B_AD[63]
K8
VSS
M8
NC14
VCC15
H9
B_CBE5#
K9
VCC15
M9
H10
VSS
K10
VSS
M10
VSS
H11
VCCPE
K11
VCC15
M11
VCC15
H12
PERP[3]
K12
VSS
M12
VSS
H13
PETN[3]
K13
VCC15
M13
VCC15
H14
VSS
K14
VSS
M14
VSS
H15
VCCPE
K15
VCC15
M15
VCC15
H16
RSTIN#
K16
VSS
M16
VSS
H17
A_CBE4#
K17
A_AD[61]
M17
A_AD[57]
H18
VCC33
K18
A_AD[60]
M18
A_AD[56]
H19
A_CBE6#
K19
A_AD[62]
M19
VCC33
H20
A_CBE7#
K20
VSS
M20
NC15
H21
VCC33
K21
NC13
M21
A_AD[41]
H22
A_AD[49]
K22
A_AD[45]
M22
VCC15
H23
A_AD[48]
K23
VSS
M23
A_AD[40]
H24
VCC33
K24
A_AD[44]
M24
45
41210 Bridge — Datasheet
Table 31.
Ball
Signal List, sorted by Ball Name (Sheet 3 of 4)
Signal Name
N1
Signal Name
Ball
R1
VSS
U1
Signal Name
B_M66EN
B_PERR#
N2
VSS
R2
B_AD[32]
U2
N3
B_AD[37]
R3
B_AD[33]
U3
VSS
N4
B_AD[38]
R4
VSS
U4
B_FRAME#
N5
VSS
R5
B_PME#
U5
B_IRDY#
N6
B_AD[52]
R6
NC16
U6
VSS
N7
B_AD[53]
R7
VCC33
U7
B_CLKO[5]
N8
B_RST#
R8
VCCAPCI2
U8
B_CLKO[6]
N9
VSS
R9
VSS
U9
VCC33
N10
VCC15
R10
VCC15
U10
B_CLKIN
B_STRAP3
N11
VSS
R11
VSS
U11
N12
VCC15
R12
VCC15
U12
VSS
N13
VSS
R13
VSS
U13
A_CLKIN
N14
VCC15
R14
VCC15
U14
A_CLKO[4]
N15
VSS
R15
VSS
U15
VSS
N16
VCC15
R16
VCC15
U16
A_CLKO[5]
N17
A_AD[55]
R17
VCCAPCI3
U17
A_CLKO[3]
N18
A_REQ3#
R18
A_AD[51]
U18
VSS
N19
A_AD[54]
R19
VSS
U19
A_STOP#
N20
VSS
R20
A_AD[50]
U20
A_DEVSEL#
N21
A_AD[39]
R21
A_LOCK#
U21
VSS
N22
A_AD[38]
R22
VSS
U22
A_TRDY#
N23
VSS
R23
A_AD[35]
U23
A_GNT5#
R24
A_AD[34]
U24
VSS
N24
46
Ball
P1
B_AD[34]
T1
B_REQ3#
V1
VSS
P2
B_133EN
T2
VSS
V2
B_SERR#
B_STOP#
P3
VSS
T3
B_DEVSEL#
V3
P4
B_AD[35]
T4
NC10
V4
VCC33
P5
B_AD[36]
T5
VCC33
V5
B_REQ4#
P6
VSS
T6
B_REQ2#
V6
B_CLKO[4]
P7
B_AD[50]
T7
B_CLKO[3]
V7
VSS
P8
B_AD[51]
T8
VSS
V8
B_CLKO[2]
B_CLKO[1]
P9
VCC15
T9
VCC15
V9
P10
VSS
T10
VSS
V10
VSS
P11
VCC15
T11
VCC15
V11
RCOMP
VCC15
P12
VSS
T12
VSS
V12
P13
VCC15
T13
VCC15
V13
VSS
P14
VSS
T14
VSS
V14
A_CLKO[0]
P15
VCC15
T15
VCC15
V15
A_CLKO[6]
P16
VSS
T16
VSS
V16
VCC15
P17
A_AD[53]
T17
VCC33
V17
A_CLKO[2]
P18
VSS
T18
A_M66EN
V18
A_REQ2#
P19
A_AD[52]
T19
A_SERR#
V19
VSS
P20
A_PERR#
T20
VCC33
V20
A_133EN
P21
VSS
T21
A_AD[33]
V21
A_PME#
P22
A_AD[37]
T22
A_AD[32]
V22
VSS
P23
A_AD[36]
T23
VCC33
V23
A_FRAME#
P24
VSS
T24
NC17
V24
A_IRDY#
Datasheet — 41210 Bridge
Table 31.
Signal List, sorted by Ball Name (Sheet 4 of 4)
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
W1
B_AD[16]
AA1
VCC33
AC1
B_REQ64#
W2
VCC33
AA2
B_AD[18]
AC2
B_AD[0]
W3
B_LOCK#
AA3
B_AD[19]
AC3
VCC15
W4
B_TRDY#
AA4
VSS
AC4
B_AD[4]
W5
VSS
AA5
B_CBE3#
AC5
B_AD[5]
W6
B_AD[23]
AA6
B_AD[24]
AC6
VCC33
W7
B_AD[25]
AA7
VSS
AC7
B_AD[9]
W8
VSS
AA8
B_AD[28]
AC8
B_CBE0#
W9
B_AD[29]
AA9
B_AD[31]
AC9
VSS
W10
B_CLKO[0]
AA10
VSS
AC10
B_AD[14]
B_PAR
W11
VCC33
AA11
B_GNT3#
AC11
W12
B_GNT4#
AA12
B_REQ5#
AC12
VSS
W13
A_REQ5#
AA13
VSS
AC13
A_AD[15]
W14
VSS
AA14
A_GNT4#
AC14
A_CBE1#
W15
A_AD[30]
AA15
A_AD[31]
AC15
VSS
W16
A_CLKO[1]
AA16
VSS
AC16
A_AD[11]
W17
VSS
AA17
A_RST#
AC17
A_AD[9]
W18
A_AD[25]
AA18
A_AD[26]
AC18
VSS
W19
A_GNT0#
AA19
VSS
AC19
A_AD[7]
A_AD[5]
W20
VSS
AA20
A_CBE3#
AC20
W21
A_REQ0#
AA21
A_AD[21]
AC21
VSS
W22
A_REQ1#
AA22
VSS
AC22
A_AD[2]
W23
VSS
AA23
A_AD[18]
AC23
A_AD[0]
W24
A_AD[16]
AA24
A_CBE2#
AC24
A_REQ64#
Y1
B_CBE2#
AB1
B_ACK64#
AD1
VSS
Y2
B_AD[17]
AB2
VSS
AD2
B_AD[1]
Y3
VSS
AB3
B_AD[20]
AD3
B_AD[2]
Y4
B_AD[21]
AB4
B_AD[3]
AD4
VSS
Y5
B_AD[22]
AB5
VSS
AD5
B_AD[6]
B_AD[7]
Y6
VCC15
AB6
B_REQ1#
AD6
Y7
B_AD[26]
AB7
B_AD[8]
AD7
VSS
Y8
B_AD[27]
AB8
VCC33
AD8
B_AD[10]
B_AD[12]
Y9
VCC33
AB9
B_AD[11]
AD9
Y10
B_AD[30]
AB10
B_AD[13]
AD10
VSS
Y11
B_GNT2#
AB11
VSS
AD11
B_AD[15]
Y12
VSS
AB12
B_CBE1#
AD12
Y13
A_GNT3#
AB13
A_PAR
AD13
Y14
A_GNT2#
AB14
VCC33
AD14
A_AD[14]
Y15
VCC33
AB15
A_AD[12]
AD15
A_AD[13]
Y16
A_AD[28]
AB16
A_AD[29]
AD16
VSS
Y17
A_AD[27]
AB17
VSS
AD17
A_AD[10]
Y18
VSS
AB18
A_AD[8]
AD18
A_CBE0#
Y19
A_AD[23]
AB19
A_AD[24]
AD19
VCC33
Y20
A_AD[22]
AB20
VCC15
AD20
A_AD[6]
A_AD[4]
Y21
VCC33
AB21
A_AD[3]
AD21
Y22
A_AD[19]
AB22
A_AD[20]
AD22
VSS
Y23
A_AD[17]
AB23
VSS
AD23
A_AD[1]
Y24
VCC33
AB24
A_ACK64#
AD24
VSS
47
41210 Bridge — Datasheet
4.4
Signal List, sorted by Signal Name
Table 32. Signal List, sorted by Signal Name (Sheet 1 of 4)
48
Ball
Signal Name
Ball
Signal Name
Ball
V20
A_133EN
J23
A_AD[46]
A23
Signal Name
A_NC2
AB24
A_ACK64#
J21
A_AD[47]
D24
A_NC3
AC23
AD23
A_AD[0]
A_AD[1]
H23
H22
A_AD[48]
A_AD[49]
F23
G21
A_NC4
A_NC5
AC22
A_AD[2]
R20
A_AD[50]
D22
A_NC6
AB21
A_AD[3]
R18
A_AD[51]
G22
A_NC7
AD21
A_AD[4]
P19
A_AD[52]
E22
A_NC8
AC20
A_AD[5]
P17
A_AD[53]
F21
A_NC9
AD20
A_AD[6]
N19
A_AD[54]
E21
A_NC10
AC19
AB18
A_AD[7]
A_AD[8]
N17
M18
A_AD[55]
A_AD[56]
R21
T18
A_LOCK#
A_M66EN
AC17
A_AD[9]
M17
A_AD[57]
AB13
A_PAR
AD17
A_AD[10]
L19
A_AD[58]
J20
A_PAR64
AC16
A_AD[11]
L17
A_AD[59]
E17
A_PCIXCAP
AB15
A_AD[12]
K18
A_AD[60]
P20
A_PERR#
AD15
AD14
A_AD[13]
A_AD[14]
K17
K19
A_AD[61]
A_AD[62]
V21
W21
A_PME#
A_REQ0#
A_REQ1#
AC13
A_AD[15]
J17
A_AD[63]
W22
W24
A_AD[16]
AD18
A_CBE0#
V18
A_REQ2#
Y23
AA23
A_AD[17]
A_AD[18]
AC14
AA24
A_CBE1#
A_CBE2#
N18
L22
A_REQ3#
A_REQ4#
Y22
A_AD[19]
AA20
A_CBE3#
W13
A_REQ5#
AB22
A_AD[20]
H17
A_CBE4#
AC24
A_REQ64#
AA21
Y20
A_AD[21]
A_AD[22]
J18
H19
A_CBE5#
A_CBE6#
AA17
T19
A_RST#
A_SERR#
Y19
AB19
A_AD[23]
A_AD[24]
H20
U13
A_CBE7#
A_CLKIN
U19
C18
A_STOP#
A_STRAP0
W18
AA18
A_AD[25]
A_AD[26]
V14
W16
A_CLKO[0]
A_CLKO[1]
D18
B22
A_STRAP1
A_STRAP2
Y17
Y16
A_AD[27]
A_AD[28]
V17
U17
A_CLKO[2]
A_CLKO[3]
C19
A21
A_STRAP3
A_STRAP4
AB16
W15
A_AD[29]
A_AD[30]
U14
U16
A_CLKO[4]
A_CLKO[5]
D19
F19
A_STRAP5
A_STRAP6
AA15
T22
A_AD[31]
A_AD[32]
V15
U20
A_CLKO[6]
A_DEVSEL#
F22
B23
A_TEST1
A_TEST2
T21
R24
A_AD[33]
A_AD[34]
V23
W19
A_FRAME#
A_GNT0#
U22
P2
A_TRDY#
B_133EN
R23
P23
A_AD[35]
A_AD[36]
J24
Y14
A_GNT1#
A_GNT2#
AB1
AC2
B_ACK64#
B_AD[0]
P22
N22
A_AD[37]
A_AD[38]
Y13
AA14
A_GNT3#
A_GNT4#
AD2
AD3
B_AD[1]
B_AD[2]
N21
M23
A_AD[39]
A_AD[40]
U23
V24
A_GNT5#
A_IRDY#
AB4
AC4
B_AD[3]
B_AD[4]
M21
L23
A_AD[41]
A_AD[42]
G24
F24
A_INTA#
A_INTB#
AC5
AD5
B_AD[5]
B_AD[6]
L20
K24
A_AD[43]
A_AD[44]
D23
C24
A_INTC#
A_INTD#
AD6
AB7
B_AD[7]
B_AD[8]
K22
A_AD[45]
B24
A_NC1
AC7
B_AD[9]
Datasheet — 41210 Bridge
Table 32. Signal List, sorted by Signal Name (Sheet 2 of 4)
Ball
Signal Name
Ball
Signal Name
Ball
AD8
B_AD[10]
K6
B_AD[58]
H7
Signal Name
B_PAR64
AB9
B_AD[11]
K7
B_AD[59]
D7
B_PCIXCAP
AD9
AB10
B_AD[12]
B_AD[13]
J6
J7
B_AD[60]
B_AD[61]
U2
R5
B_PERR#
B_PME#
AC10
B_AD[14]
H5
B_AD[62]
L4
B_REQ0#
AD11
B_AD[15]
H8
B_AD[63]
AB6
B_REQ1#
W1
B_AD[16]
AC8
B_CBE0#
T6
B_REQ2#
Y2
B_AD[17]
AB12
B_CBE1#
T1
B_REQ3#
AA2
AA3
B_AD[18]
B_AD[19]
Y1
AA5
B_CBE2#
B_CBE3#
V5
AA12
B_REQ4#
B_REQ5#
AB3
B_AD[20]
G9
B_CBE4#
AC1
B_REQ64#
Y4
Y5
B_AD[21]
B_AD[22]
H9
G6
B_CBE5#
B_CBE6#
N8
V2
B_RST#
B_SERR#
W6
B_AD[23]
G7
B_CBE7#
V3
B_STOP#
AA6
B_AD[24]
U10
B_CLKIN
A19
B_STRAP0
W7
Y7
B_AD[25]
B_AD[26]
W10
V9
B_CLKO[0]
B_CLKO[1]
B3
B19
B_STRAP1
B_STRAP2
Y8
AA8
B_AD[27]
B_AD[28]
V8
T7
B_CLKO[2]
B_CLKO[3]
U11
E6
B_STRAP3
B_STRAP4
W9
Y10
B_AD[29]
B_AD[30]
V6
U7
B_CLKO[4]
B_CLKO[5]
A2
B5
B_STRAP5
B_STRAP6
AA9
B_AD[31]
U8
B_CLKO[6]
C3
B_TEST1
R2
B_AD[32]
T3
B_DEVSEL#
D1
B_TEST2
R3
P1
B_AD[33]
B_AD[34]
U4
J5
B_FRAME#
B_GNT0#
W4
B8
B_TRDY#
CFGRETRY
P4
B_AD[35]
K1
B_GNT1#
E18
CFGRST#
P5
B_AD[36]
Y11
B_GNT2#
F18
NC1
N3
N4
B_AD[37]
B_AD[38]
AA11
W12
B_GNT3#
B_GNT4#
A5
A22
NC2
NC3
M2
M3
B_AD[39]
B_AD[40]
L8
U5
B_GNT5#
B_IRDY#
C4
D6
NC4
NC5
L1
L2
B_AD[41]
B_AD[42]
F2
G1
B_INTA#
B_INTB#
E19
F6
NC6
NC7
K3
K4
B_AD[43]
B_AD[44]
F3
C1
B_INTC#
B_INTD#
F8
F7
NC8
NC9
J2
J3
B_AD[45]
B_AD[46]
B2
E4
B_NC1
B_NC2
T4
G18
NC10
NC11
H4
H1
B_AD[47]
B_AD[48]
D2
E1
B_NC3
B_NC4
G19
K21
NC12
NC13
H2
P7
B_AD[49]
B_AD[50]
G3
D3
B_NC5
B_NC6
M8
M20
NC14
NC15
P8
N6
B_AD[51]
B_AD[52]
B1
G4
B_NC7
B_NC8
R6
T24
NC16
NC17
N7
M5
B_AD[53]
B_AD[54]
E3
F4
B_NC9
B_NC10
C6
B6
NC18
NC19
M6
L5
B_AD[55]
B_AD[56]
W3
U1
B_LOCK#
B_M66EN
E16
B17
PE_RCOMP[0]
PE_RCOMP[1]
L7
B_AD[57]
AC11
B_PAR
E14
PERN[0]
49
41210 Bridge — Datasheet
Table 32. Signal List, sorted by Signal Name (Sheet 3 of 4)
50
Ball
Signal Name
Ball
Signal Name
Ball
A15
PERN[1]
A18
SMBUS[3]
F1
Signal Name
VCC33
C13
PERN[2]
D20
SMBUS[5]
H3
VCC33
G12
C10
PERN[3]
PERN[4]
B7
E9
TCK
TDI
H18
H21
VCC33
VCC33
C9
PERN[5]
A6
TDO
H24
VCC33
E12
PERN[6]
E7
TMS
L6
VCC33
G10
PERN[7]
F9
TRST#
M19
VCC33
E15
PERP[0]
J16
VCC15
R7
VCC33
A16
D13
PERP[1]
PERP[2]
K9
K11
VCC15
VCC15
T5
T17
VCC33
VCC33
H12
PERP[3]
K13
VCC15
T20
VCC33
C11
B9
PERP[4]
PERP[5]
K15
L3
VCC15
VCC15
T23
U9
VCC33
VCC33
D12
PERP[6]
L10
VCC15
V4
VCC33
F10
PERP[7]
L12
VCC15
W2
VCC33
F17
F13
PERST#
PETN[0]
L14
L16
VCC15
VCC15
W11
Y9
VCC33
VCC33
D15
B14
PETN[1]
PETN[2]
M9
M11
VCC15
VCC15
Y15
Y21
VCC33
VCC33
H13
B11
PETN[3]
PETN[4]
M13
M15
VCC15
VCC15
Y24
AA1
VCC33
VCC33
A9
PETN[5]
M22
VCC15
AB8
VCC33
D9
PETN[6]
N10
VCC15
AB14
VCC33
F11
F14
PETN[7]
PETP[0]
N12
N14
VCC15
VCC15
AC6
AD19
VCC33
VCC33
D16
PETP[1]
N16
VCC15
J8
VCCAPCI1
B15
PETP[2]
P9
VCC15
R8
VCCAPCI2
G13
B12
PETP[3]
PETP[4]
P11
P13
VCC15
VCC15
R17
G15
VCCAPCI3
VCCAPE
A10
D10
PETP[5]
PETP[6]
P15
R10
VCC15
VCC15
C14
A14
VCCBGPE
VCCPE
E11
V11
PETP[7]
RCOMP
R12
R14
VCC15
VCC15
C12
C15
VCCPE
VCCPE
C17
C16
REFCLKN
REFCLKP
R16
T9
VCC15
VCC15
F12
H11
VCCPE
VCCPE
C21
B21
RESERVED1
RESERVED2
T11
T13
VCC15
VCC15
H15
J10
VCCPE
VCCPE
D21
F20
RESERVED3
RESERVED4
T15
V12
VCC15
VCC15
J12
J14
VCCPE
VCCPE
A3
B4
RESERVED5
RESERVED6
V16
Y6
VCC15
VCC15
A4
A8
VSS
VSS
D4
F5
RESERVED7
RESERVED8
AB20
AC3
VCC15
VCC15
A17
A20
VSS
VSS
H16
C7
RSTIN#
SMBCLK
A7
B18
VCC33
VCC33
A24
B10
VSS
VSS
D8
G16
SMBDAT
SMBUS[1]
C22
D5
VCC33
VCC33
B13
B16
VSS
VSS
B20
SMBUS[2]
E24
VCC33
C2
VSS
Datasheet — 41210 Bridge
Table 32. Signal List, sorted by Signal Name (Sheet 4 of 4)
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
C5
VSS
L21
VSS
V10
VSS
C8
VSS
L24
VSS
V13
VSS
C20
C23
VSS
VSS
M4
M7
VSS
VSS
V19
V22
VSS
VSS
VSS
D11
VSS
M10
VSS
W5
D14
VSS
M12
VSS
W8
VSS
D17
VSS
M14
VSS
W14
VSS
E2
VSS
M16
VSS
W17
VSS
E5
E8
VSS
VSS
N2
N5
VSS
VSS
W20
W23
VSS
VSS
E10
VSS
N9
VSS
Y3
VSS
E13
VSS
N11
VSS
Y12
VSS
E20
VSS
N13
VSS
Y18
VSS
E23
F15
VSS
VSS
N15
N20
VSS
VSS
AA4
AA7
VSS
VSS
G2
VSS
N23
VSS
AA10
VSS
G5
VSS
P3
VSS
AA13
VSS
G8
VSS
P6
VSS
AA16
VSS
G11
VSS
P10
VSS
AA19
VSS
G14
VSS
P12
VSS
AA22
VSS
G17
VSS
P14
VSS
AB2
VSS
G20
G23
VSS
VSS
P16
P18
VSS
VSS
AB5
AB11
VSS
VSS
H6
H10
VSS
VSS
P21
P24
VSS
VSS
AB17
AB23
VSS
VSS
H14
J1
VSS
VSS
R1
R4
VSS
VSS
AC9
AC12
VSS
VSS
J4
J9
VSS
VSS
R9
R11
VSS
VSS
AC15
AC18
VSS
VSS
J11
J13
VSS
VSS
R13
R15
VSS
VSS
AC21
AD1
VSS
VSS
J15
J19
VSS
VSS
R19
R22
VSS
VSS
AD4
AD7
VSS
VSS
J22
K2
VSS
VSS
T2
T8
VSS
VSS
AD10
AD16
VSS
VSS
K5
K8
VSS
VSS
T10
T12
VSS
VSS
AD22
AD24
VSS
VSS
K10
K12
VSS
VSS
T14
T16
VSS
VSS
F16
A13
VSSAPE
VSSBGPE
K14
K16
VSS
VSS
U3
U6
VSS
VSS
A1
A11
K20
K23
VSS
VSS
U12
U15
VSS
VSS
A12
M1
L9
L11
VSS
VSS
U18
U21
VSS
VSS
M24
N1
L13
L15
VSS
VSS
U24
V1
VSS
VSS
N24
AD12
L18
VSS
V7
VSS
AD13
51
41210 Bridge — Datasheet
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52