L5996 5 BIT DYNAMIC DAC CONTROLLER FOR MOBILE CPU PRELIMINARY DATA DYNAMIC DAC DETECTION ON CHIP PROGRAMMABLE OUTPUT FROM 0.925V TO 2.0V WITH 0.05V AND 0.025V BINARY STEPS ULTRA HIGH EFFICIENCY SEPARATE 5V BIAS SUPPLY AVAILABLE FOR HIGH EFFICIENCY PERFORMANCE EXCELLENT OUTPUT ACCURACY ±1% OVER LINE, LOAD AND TEMPERATURE VARIATIONS HIGH PRECISION INTERNAL REFERENCE DIGITALLY TRIMMED OPERATING SUPPLY VOLTAGE FROM 4.75V TO 25V VERY FAST LOAD TRANSIENT REMOTE SENSING INPUTS INTERNAL LINEAR REGULATOR 2.5V /150mA, ±2% PRECISION POWER MANAGEMENT - PROGRAMMABLE POWER-UP TIME - POWER GOOD OUTPUT, SKIP MODE - OUTPUT OVERVOLTAGE PROTECTION - OUTPUT UNDERVOLTAGE LOCKOUT OPERATING FREQUENCY UP TO 1MHz MEETS INTEL MOBILE PENTIU III TQFP32 (7mm x 7mm) Application ADVANCED MICROPROCESSOR SUPPLIES POWERSUPPLYFOR PENTIUM III INTEL MOBILE DESCRIPTION The L5996 is a power supply controller that offers a complete power management for notebook CPUs of the next generation especially for mobile Pentium III. A high precise 5 bit digital to analog converter (DAC) allows to adjust the output voltage from 0.925V to 2.0V. Dynamic DAC code changes are detected on chip in order to switch the output voltage between 1.3V and 1.45V in less tahn 100µs.The high precision internal refer- TYPICAL APPLICATION CIRCUIT L5996 POWER SECTION 4.75V to 25V PWM SECTIONS VO 0.925V to 2.0V CPU CORE D0 D1 FREQ SETTING SYNC DAC D2 D3 Pentium III Mobile D4 NOSKIP POWER MANAGEMENT & SYSTEM SUPERVISOR 3.3V 2.5V LIN. REG. POWER GOOD ENABLE 2.5V CPU CLK D98IN997A July 1999 1/9 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. L5996 DESCRIPTION (Continued) ence, digitally trimmed, assures the selected output voltage to within +/-1% over temperature and battery voltage variations. Thanks to the remote sensing inputs and to the window comparator system, embedded in the error summing structure, the device provides excellent load transient performance. The high peak current gate drive affords to have fast switching to the external power mos, performing an high efficiency. A complete power management include on board a programmable power-up sequencing, power good signal, skip mode operation and undervoltege detection. The L5996 assures a fast protection against load overvoltage and load overcurrent. Linear regulator on-board is available with an output voltage of 2.5V (+/-2%) and a current capability of 150mA, useful for CPU CLOCK BUS. NOSKIP HSRC HGATE HSTRAP RSTRAP RGATE PWRGND POWERGOOD PIN CONNECTION 32 31 30 29 28 27 26 25 ENABLE 1 24 VID4 VIN 2 23 VID3 REG5 3 22 VID2 V5SW 4 21 VID1 DISPROT 5 20 VID0 SSTART 6 19 ICURLIM HRSNS 7 18 OSC LRSNS 8 17 FREQ VSS VBG VO2.5 VIN2.5 SNSGND VPROG VFB COMP 9 10 11 12 13 14 15 16 D98IN998 BLOCK DIAGRAM CSOFT VIN3.3V SSTART VID0 6 VFB 9 LRSNS 8 HRSNS 7 COMP + 10 21 VID2 VID3 22 VID4 23 VIN2.5 24 13 PROGRAMMABLE BANDGAP & REFERENCE - 14 VO2.5 15 VBG 11 VPROG SOFT START RSTRAP 29 HSTRAP 28 VPROG VIN HRSNS LRSNS OVER CURRENT COMPARATOR HGATE 27 HSRC 26 Hside INTERNAL SUPPLY 3 + REG5 - C5 ZERO CROSSING COMPARATOR CONTROL LOGIC Rsense L C VCPUCLK 2.5V LIN. REG. ERROR SUMMING + REG5 Cboot 20 WINDOW COMP + SLOPE VID1 RGATE Load 30 + PULSE SKIPPING COMPARATOR 31 VSS 4 V5SW 2 VIN Vdc 5.5V to 25V + PWRGND SNSGND LINEAR REGULATOR Lside 12 32 VPROG OSCILLATOR and SYNC 16 18 OSC OVER/UNDER VOLTAGE COMPARATOR POWER MANAGEMENT PWGOOD 1 ENABLE 17 FREQ 25 19 ICURLIM D98IN999 NOSKIP 5 5V DISPROT ABSOLUTE MAXIMUM RATINGS Symbol Parameter Unit -0.5 to 27 V PWRGND to VSS ±0.5 V 5 V VREFS to PWRGND HSTRAP, HGATE to PWRGND -0.5V to VIN+14V RSTRAP, RGATE to PWRGND -0.5V to 14V EABLE, FREQ, OSC, COMP, VFB, HRSNS, LRSNS VID0-3, NOSKIP 2/9 Value VIN to PWRGND 5 V 7 V Tj Junction Temperature Range -40 to 150 °C Tstg Storage Temperature Range -55 to 150 °C L5996 THERMAL DATA Symbol RTh j-amb Parameter Thermal Resistance Junction to Ambient Value Unit 60 °C/W ELECTRICAL CHARACTERISTICS ( VIN = 12V; Ti = 25°C, OSC = GND, unless otherwise specified) • = specifications referred to TJ from 0 to 70°C. Symbol Parameter Test Conditions DC CHARACTERISTICS VIN Input Supply Voltage IOP Operating Quiescent Current RGATE = HGATE = OPEN ENABLE = REG5 ISB Stand-By Current ENABLE = GND VIN = 12V VIN = 25V Min. • • Typ. Max. 25 V 0.9 1.1 mA 80 100 150 180 µA µA 5.0 5.1 V 60 mA mA 4.75 • Unit INTERNAL REGULATOR (VREG5) VREG5 Output Voltage VIN = 7.5V to 25V ILOAD = 0 to 5mA, C REG5 = 4.7µF IREG5 Total Current Capability CREG5 = 4.7µF VIN = 5.5V VIN ≥ 6V 4.9 25 Switch-Over Threshold Voltage Current Capability (internal switch on) 4.3 V5SW = 4.5 to 5.5V VREG5 ≥ 4.4V 2.5V REFERENCE VOLTAGE VO 2.5 Regulated Voltage VIN 2.5 = 3.3V C VO 2.5 = 47µF IO 2.5 = 10mA Regulation over Line and Load 6V < VIN < 25V VIN 2.5 = 3.3V IO 2.5 = 0-150mA IVO 2.5 MAX Current Limit VIN 2.5 = 3.3V PROGRAMMABLE REFERENCE VOLTAGE AND VBG VPROG VFB Accuracy VID0, VID1, VID2, VID3, VID4 see Table 1. Ouput Voltage Accuracy Line and Load Regulation included, VID0, VID1, VID2, VID3, VID4, see Table 1. VBG Band Gap reference POWER MANAGEMENT C VBG = 220nF 4.5 4.7 25 V mA • 2.45 2.5 2.55 V • 2.425 2.5 2.575 V 500 mA • -0.5% VPROG +0.5% V • -1% VPROG +1% V • 1.240 1.246 1.252 V Enable Voltage HIGH LEVEL Disable Voltage LOW LEVEL 2.4 0.8 V V Power Good Saturation Voltage Isink = 400µA 0.4 V NOSKIP Mode (Active high) High Level Low Level 0.8 2.4 V V Output UVLO Threshold OVP = GND 60 Output UVLO Lockout Time Depending on CSS value 70 775 80 % ms/µF 3/9 L5996 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Conditions PROTECTION FUNCTIONS V8-V7 Over-Current Threshold Voltage VSSTART = 3.1V Pulse Skipping Mode Threshold Voltage NOSKIP = HIGH • Min. Typ. Max. Unit 48 60 72 mV 7 11 15 mV Zero Crossing Threshold -4 +4 mV Under-Voltage Threshold Vprog -13% Vprog -10% Vprog -7% V Upper Over-Voltage Threshold Vprog +7% Vprog +10% Vprog +13% V Lower Over-Voltage Threshold Vprog -4.5% V Over-Voltage Propagation Time 1.5 µs Under-Voltage Propagation Time 1.5 µs 4.8 µA V SOFT START Soft start source current 3.2 Soft start clamp voltage 3.1 OSCILLATOR AND SYNC fosc Fixed frequency OSC =0V; FREQ = REG5 OSC = REG5 FREQ = REG5 f SINK MIN Minimum Synchronizzable external frequency FREQ = REG5 OSC = EXTERNAL SIGNAL Sync pulse width Rising edge mode Sync pulse amplitude fosc Operating switching frequency Rext connected between FREQ and GND, OSC connect to REG5 or GND Rext = 680kΩ Rext = 40kΩ HIGH AND LOW SIDE GATE DRIVERS 4/9 4 • • 225 250 275 KHz 180 200 220 KHz 120 KHz 200 • ns 3 5.5 V 100 1 kHz MHz IOH5 Output high source peak current HSTRAP = RSTRAP = REG5 550 mA R H5 Output high sink impedance Itest = 100mA, HSTRAP = RSTRAP = REG5 3.5 Ω IOH12 Output high source peak current HSTRAP = RSTRAP = 12V 2 A R H12 Output high sink impedance Itest = 100mA, HSTRAP - RSTRAP = 12V 2 Ω IOL5 Output low peak current HSTRAP = RSTRAP = 5V 500 mA RL5 Output low impedance Itest = 100mA, HSTRAP = RSTRAP = 5V 3 Ω IOL12 Output low peak current HSTRAP = RSTRAP = 12V 2 A R L12 Output low Impedance Itest = 100mA, HSTRAP = RSTRAP = 12V 2 Ω TCC Dead Time GATE low to high 60 ns L5996 FUNCTIONAL PIN DESCRIPTION ENABLE(pin1): Enable input. A high level (>2.4V) enables the device, a low level (<0.8V) shuts it down. As ENABLE drops below 0.8V, the drivers are turned off and all internal functions are disabled except REG5. In this condition the stand by current is less than 80µA at VIN = 12V. VIN(pin2): Device supply voltage. Input voltage range at this pin is 4.75V to 25V and the operating current requirement at 12V is 650µA. REG5(pin3): 5V Regulator supply. Used also to supply the bootstrap capacitor. A minimum 2.2µF ceramic capacitor connected to PWRGND is required. V5SW(pin4): 5V supply line. Connecting to 5V bus(4.75V to 5.5V) the device is no longer powered by VIN but by this pin and the internal linear regulator is disconnected increasing the efficiency. DISPROT (pin5) Disable Protection Functions. A high level (3.3V CMOS LOGIC) on this pin disables the undervoltage and the overvoltage protection. Tie this pin to VSS for normal operation. SSTART(pin6): Soft Start. The soft-start time is programmed by an external capacitor connected between this pin and SGND. The internal current generator forces 4µA through the capacitor implementing the soft start function. HRSNS(pin7): Error summing current sense non inverting input. LRSNS(pin8): Error summing current sense inverting input. VFB(pin9): Regulator voltage feedback input. Connect close to the CPU input supply pin realise an accurate voltage regulation. VFB internally is connected to the window comparator that is used to increase the performance during the load transient. COMP(pin10): Regulator stability compensation pin. The compensation is realised internally and normally it is not necessary to connect any external components to this pin. VPROG(pin11): Reference voltage test pin. This pin provides the DAC output and should be decoupled to ground using a 0.22µF ceramic capacitor. No load has to be connected. SNSGND(pin12): Remote ground sense. This pin is internally connected to the low power circuitry and for a precise output voltage regulation can be connected to the output capacitor negative terminal. VIN2.5(pin13): 2.5V linear supply voltage. Is available on-chip a linear regulator useful for the 2.5V bus. A max input voltage of 3.3V is recommended at Iomax (150mA). VO2.5(pin14): 2.5V linear regulator output. The linear regulator is realised with an internal NPN transistor with +/-2% output accuracy. A minimum of 47µF capacitor connected versus PWRGND is required. VBG(pin15): Band-gap reference voltage. A min 220nF ceramic capacitor is required to assure the band gap stability and noise immunity. VSS(pin16): Signal ground. This pin could be connected to the PWRGND pin. FREQ(pin17): Connecting an external resistor versus ground is possible to select the switching frequency between 100kHz and 1MHz. Using an Rext=680k the fsw is 100kHz, using an Rext = 40k the fsw is 1MHz. In this condition is recommended to connect the OSC pin to REG5 or to VSS. OSC(pin18): Connecting to REG5 is able to set the switching frequency at 200kHz, connecting to VSS is able to set the switching frequency at 250kHz. An external pulsed signal, with an amplitude higher than 2.4V, could synchronise the device. In all these conditions pin FREQ has to be connected to REG5. OVP/CURLIM(pin19): Over voltage protection and reduced current limit window. If the output voltage reaches the 10% above the programmed voltage (VPROG) this pin is driven low the high side driver is turned off and the low, side driver is turned on. All the internal blocks are active. The device uses OVP function to discharge the output during HIGH_TO_LOW core voltage transition. The pin is driven low also during LOW_TO_HIGH core voltage transition. The pin will stay low as 5/9 L5996 long as the current limit value is reduced with respect to the normal operating value. This is done to limit voltage overshoots during core voltage changes. Making this signal externally available simplifies system debugging. VID0-4(pin20-24): Voltage Identification code input. These open collector compatible inputs are used to program the output voltage as specified in Table 1. Every pin has an internal pull up. If all four pins are high or floating, the output voltage and the 2.5V regulator are suspended and the POWERGOOD is low. NOSKIP(pin25): Pulse skipping mode control. A high level (>2.4V) disables pulse skipping in low load condition, a low level (>0.8V) enables it. HSRC(pin26): High side N-Channel switch source connection. This pin provides the return path for the high side driver. HGATE(pin27): Gate driver output, high side NChannel switch. The driver internal impedance is about 4Ω at VIN=12V. HSTRAP(pin28):Bootstrap capacitor pin. This pin provide to supply the high side driver sinking the current by the bootstrap capacitor. RSTRAP(pin29): Synchronous rectifier gate driver supply voltage. This pin could be connected to REG5 to reduce the switching losses due to the external Mosfets gate capacitance. This is useful to maintain an high efficiency at light load. RGATE(pin30): Gate driver output, low side NChannel switch. The driver internal impedance is about 3Ω at VIN=12V. PWRGND(pin31): Power ground. This pin has to be connected closely to the low side mosfet source in order to reduce the noise injected into the IC. POWER GOOD(pin32): Open drain power good output. This pin is pulled low if the output voltage is not within ±10% and the 2.5V output is lower than 2.175V (-13%). The pin is pulled low also if REG5, VPROG and VBG have not reached the expected values. This test could be useful in an assembling fault condition. Table 1. VID [4:0] AND corresponding +VCC_CPU_CORE ranges 6/9 VID[4:0] +VCC_CPU_CORE VID[4:0] +VCC_CPU_CORE 00000 2.00V 10000 1.275V 00001 1.95V 10001 1.250V 00010 1.90V 10010 1.225V 00011 1.85V 10011 1.200V 00100 1.80V 10100 1.175V 00101 1.75V 10101 1.150V 00110 1.70V 10110 1.125V 00111 1.65V 10111 1.100V 01000 1.60V 11000 1.075V 01001 1.55V 11001 1.050V 01010 1.50V 11010 1.025V 01011 1.45V 11011 1.000V 01100 1.40V 11100 0.975V 01101 1.35V 11101 0.950V 01110 1.30V 11110 0.925V 01111 No CPU 11111 No CPU L5996 Figure 1. Application Circuit Vin 4.5V to 25V REG5 SSTART 6 VBG NOSKIP VSS OSC FREQ DISPROT VPROG 3 VIN 2 RSTRAP 29 28 15 27 25 Vin2 3.3V Vo 0.925V to 2.0V HSRC 18 17 L5996 30 5 31 11 8 V5SW HGATE 26 16 7 5V BUS HSTRAP 12 4 9 13 19 14 20÷24 1 RGATE Pentium III Mobile PWRGND HRSNS LRSNS SNSGND VFB Vo2.5 Vo2 2.5V/150mA 32 PWRGOOD ICURLIM D98IN1000B ENABLE VID 5 Figure 2. Output voltage transition between 1.3V and 1,5V measured at 200mA load current. CH1: VID 2 transition. CH2: Output voltage transition between 1.3V and 1.5V measured at 200mA load current. 7/9 L5996 mm DIM. MIN. inch TYP. MAX. A MIN. TYP. 1.60 A1 0.05 A2 1.35 B 0.30 C 0.09 0.063 0.15 0.002 0.006 1.40 1.45 0.053 0.055 0.057 0.37 0.45 0.012 0.015 0.018 0.20 0.004 0.008 D 9.00 0.354 D1 7.00 0.276 D3 5.60 0.220 e 0.80 0.031 E 9.00 0.354 E1 7.00 0.276 E3 5.60 0.220 L 0.45 0.60 L1 0.75 OUTLINE AND MECHANICAL DATA MAX. 0.018 0.024 1.00 0.030 0.039 TQFP32 0°(min.), 7°(max.) K D A D1 A2 D3 24 A1 17 25 16 0.10 mm .004 B E E1 B E3 Seating Plane 9 32 8 1 C L L1 e K TQFP32 8/9 L5996 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 9/9