PM6685 DUAL STEP-DOWN CONTROLLER WITH AUXILARY VOLTAGES FOR NOTEBOOK SYSTEM POWER Preliminary Data Features ■ CONSTANT ON TIME TOPOLOGY ALLOWS VERY FAST LOAD TRANSIENTS ■ 6V TO 28V INPUT VOLTAGE RANGE ■ FIXED 5V-3.3V OUTPUT VOLTAGES ■ 5V AND 3.3V ALWAYS VOLTAGES AVAILABLE DELIVER 100mA PEAK CURRENT ■ 1.23V ± 1% REFERENCE VOLTAGE AVAILABLE ■ NO RSENSE CURRENT SENSING USING LOW SIDE MOSFETs’ RDS(on) ■ ACCURATE CURRENT SENSE WITH RSENSE ■ NEGATIVE CURRENT LIMIT ■ SOFT START INTERNALLY FIXED AT 2ms ■ SOFT OFF FOR OUTPUT DISCHARGE ■ LATCHED OVP AND UVP ■ SELECTABLE PULSE SKIPPING AT LIGHT LOADS ■ SELECTABLE MINIMUM FREQUECY (25kHz) IN PULSE SKIP MODE ■ 4 mW MAXIMUM QUIESCENT POWER ■ INDIPENDENT POWER GOOD SIGNALs ■ OUTPUT VOLTAGE RIPPLE COMPENSATION VFQFPN-32 5X5 Description PM6685 is a dual step-down controller specifically designed to provide extremely high efficiency conversion, with lossless current sensing technique. The constant on-time architecture assures fast load transient response and the embedded voltage feed-forward provides nearly constant switching frequency operation. An embedded integrator control loop compensates the DC voltage error due to the output ripple. Pulse skipping technique increases efficiency at very light load. Moreover a minimum switching frequency of 25kHz is selectable to avoid audio noise issues. The PM6685 provides a selectable switching frequency, allowing either 200kHz/ 300kHz, 300kHz/400Khz or 400kHz/500kHz operation of the 5V/3.3V switching sections... Applications ■ NOTEBOOK COMPUTERS ■ TABLET PC OR SLATES ■ MOBILE SYSTEM POWER SUPPLY ■ 3-4 CELLS Li+ BATTERY POWERED DEVICES Order codes Part number Marking Package Packing PM6685 PM6685 VFQFPN-32 5X5 TAPE & REEL September 2005 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Rev 1 1/16 www.st.com 16 PM6685 Contents 1 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Block & pin connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Functional & block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/16 PM6685 1 Figure 1. 1 Typical application circuit Typical application circuit Circuit 3/16 PM6685 2 Electrical ratings 2 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter SGND1 to SGND2 Symbol COMPx, FSEL, LDO3_SEL, VREF, SKIP to SGND1, SGND2 -0.3 to V CC + 0.3 Enx, SHDN, PGOD_LDO3, OUTx, PGOODx, V CC to SGND1, SGND2 -0.3 to 6 V LDO3 to SGND1, SGND2 -0.3 to LDO5 + 0.3 V LGATEx to PGND -0.3 to LDO5 + 0.3 V HGATEx and BOOTx, to PHASEx -0.3 to 6 V PHASEx to PGND -0.6 to 36 V CSENSEx, to PGND -0.6 to 42 V CSENSEx to BOOTx -6 to 0.3 V V5SW, LDO5 to PGND -0.3 to 0.6 V VIN to PGND -0.3 to 36 V PGND to SGND1, SGND2 -0.3 to 0.3 V 2 W Value Unit 45 °C/W Thermal data Description RthJA Thermal Resistance Junction to ambient (mounted on demoboard) TSTG Storage temperature range -40 to 150 °C Junction operating temperature range -10 to 125 °C TJ 4/16 Unit Shorted Power dissipation at Tamb = 25°C Table 2. Value PM6685 3 Figure 2. 3 Block & pin connection diagrams Block & pin connection diagrams Pin connection diagram (top view) 5/16 PM6685 3 Block & pin connection diagrams Table 3. Pin No PM6685 1 SGND 2 COMP3 3 FSEL Frequency selection pin. It provides a selectable switching frequency, allowing either 200kHz/300kHz, 300kHz/400kHz or 400kHz/500kz operation of the 5V/ 3.3V switching sections. EN3 3.3V SMPS enable input. The 3.3V section is enabled appling a high logic level (>2.4V) to this pin, while is disabled appling a low logic level (<0.8V). When the section is disabled the High Side gate driver goes low and Low Side gate driver goes high. If both EN3 and EN5 pins are low and SHDN pin is high the device enters in standby mode. 4 5 6 SHDN Function Signal ground. Reference for internal logic circuitry. DC voltage error compensation pin for the 3.3V switching section. Shutdown control input. The device enters its shutdown mode with 9µA of supply current if VSHDN is less than the device off threshold voltage and doesn't restart until VSHDN is greater than the device on threshold voltage. The SHDN pin can be connected to Vbatt through a voltage divider to program an undervoltage lockout. In shutdown mode, the gate drivers of the two switching sections are in high impedance. Power Good ouput signal for the 3.3V linear regulator. This pin is an open drain PGOOD LDO3 output. It is shorted to GND if LDO3_SEL pin is at its low level or if the ouput voltage on LDO3 pin is lower than 2.6V. 7 LDO3 3.3V Linear regulator output. LDO3 can provide 100mA peak current. If LDO3_SEL pin is connected to VREF and OUT3 is greater than the LDO3 bootstrap switch threshold, the LDO3 regulator shuts down and the LDO3 pin will be directly connected to OUT3 through a 3 (max) switch. If LDO3_SEL pin is at its low level the LDO3 is always OFF. If LDO3_SEL pin is at its high level the LDO3 is always ON. 8 OUT3 Output voltage sense for the 3.3V switching section.This pin must be directly connected to the output voltage of the switching section. 9 BOOT3 Bootstrap capacitor connection for the switching 3.3V section. It supplies the highside gate driver. 10 HGATE3 High-side gate driver ouput for the 3.3V section. 11 PHASE3 Switch node connection and return path for the high side driver for the 3.3V section. Current sense input for the switching 3.3V section. This pin must be connected through a resistor to the drain of the synchronous rectifier (RDSON sensing) or to the source of the synchronous rectifier (RSENSE sensing) to set the current limit threshold. 12 CSENSE3 13 LGATE3 14 PGND 15 LGATE5 Low-side gate driver output for the 5V section. 16 SGND2 Signal ground for analog circuitry. 17 6/16 Pin description V5SW Low-side gate driver output for the 3.3V section. Power ground. Internal 5V regulator bypass connection. When the main 5V ouput voltage is greater than the boostrap switch threshold, the LDO5 regulator shuts down and the LDO5 pin will be directly connected to OUT5 through a 3 (max) switch. If not used, it must be tied to ground. PM6685 Table 3. 3 Block & pin connection diagrams Pin description 5V internal regulator output. LDO5 pin supplies all gate drivers, the internal circuitry and an external load. It can provide up to 100mA peak current. 18 LDO5 19 VIN Device input supply voltage. A bypass filter (4 Ω and 4.7 µF) between the battery and this pin is recommended. 20 CSENSE5 Current sense input for the switching 5V section. This pin must be connected through a resistor to the drain of the synchronous rectifier (RDSON sensing) or to the source of the synchronous rectifier (RSENSE sensing) to set the current limit threshold. 21 PHASE5 Switch node connection and return path for the high side driver for the 5V section. 22 HGATE5 High-side gate driver ouput for the 5V section. 23 BOOT5 Bootstrap capacitor connection for the switching 5V section. It supplies the highside gate driver. SKIP Pulse skipping mode control input. It is a three states pin. If the pin is at its high level(e.g. cnnected to LDO5) the PWM mode is enabled. If the pin is at its low level (e.g. connected to GND), the pulse skip mode is enabled. If the pin is at its middle level (e.g. connected to Vref) the pulse skip mode is enabled but limiting the min frequency to 25KHz. 25 EN5 5V SMPS enable input. The 5V section is enabled appling a high logic level (>2.4V) to this pin, while is disabled appling a low logic level (<0.8V). When the section is disabled the High Side gate driver goes low and Low Side gate driver goes high. If both EN3 and EN5 pins are low and SHDN pin is high the device enters in standby mode. 26 PGOOD5 Power Good ouput signal for the 5V section. This pin is an open drain ouput. The pin is pulled low if the output is disabled or is out of the specified window (approximately +/- 10% of its nominal value). 27 PGOOD3 Power Good ouput signal for the 3.3V section. This pin is an open drain ouput. The pin is pulled low if the output is disabled or is out of the specified window (approximately +/- 10% of its nominal value). 28 LDP3SEL Control pin for the 3.3V internal linear regulator. This pin determines three operative modes for the LDO3. If LDO3_SEL pin is at its low level the LDO3 is always OFF. If LDO3_SEL pin is at its high level the LDO3 is always ON If LDO3_SEL pin is connected to VREF and OUT3 is greater than the LDO3 bootstrap switch threshold, the LDO3 regulator shuts down and the LDO3 pin will be directly connected to OUT3 through a 3 (max) switch. 29 OUT5 30 COMP5 31 VCC 32 VREF 24 Output voltage sense for the 5V switching section.This pin must be directly connected to the output voltage of the switching section. DC voltage error compensation pin for the 5V switching section. Device Supply Voltage pin. Connect this pin to LDO5 High accuracy output voltage reference (1.237V). It can deliver 50uA. Bypass to SGND with a 100nF capacitor. 7/16 PM6685 4 Electrical characteristics 4 Electrical characteristics (VIN = 12V; Tamb = 0°C to 85°C unless otherwise specified) Table 4. Supply section Simbol Parameter VIN Input voltage range VCC IC supply voltage Test Condition Vout=Vref, LDO5 in regulation Min. Max. Unit 6 28 V 4.5 5.5 V 4.9 V Turn-on voltage threshold VV5SW 4.8 Turn-off voltage threshold 4.6 Hysteresis VV5SW Maximum operating range RDS(on) LDO5 Internal Bootstrap Switch Resistance V5SW >4.9V LDO3 Internal Bootstrap Switch Resistance VOUT3 = 3.3V RDS(on) OUT_ Discharge-Mode On-resistance OUT3, OUT5_ Discharge-Mode Synchronuos Rectifier Turn-on level 0.2 4.75 V 50 mV 5.5 V 1.8 3 Ω 1.8 3 Ω 12 25 Ω 0.35 0.5 V 4 mW Pin Operating Power consumption VOUT5>5.1V,VOUT3>3.34V V5SW to 5V LDO5, LDO3 no load Ish VIN Shutdown Current SHDN connected to GND, 14 18 µA Isb VIN Standby Current ENx to GND, V5SW to GND 150 250 µA Min. Typ. Max. Unit Device ON threshold 0.95 1.35 1.6 V Device OFF threshold 0.8 0.85 0.9 V Table 5. Simbol VSHDN 8/16 Typ. Shutdown section Parameter Test Condition PM6685 Table 6. Simbol ICSENSE Electrical characteristics (continued) Parameter Test Condition Min. Soft Start Ramp time 2 Input bias current limit 90 Typ. 100 Max. Unit 6 ms 110 µA Comparator offset VCSENSE - VPGND -5 5 mV Zero Crossing Comparatot Offset VPGND - V PHASE -5 5 mV Fixed Negative current limit Threshold VPGND - V PHASE -120 OUT5=5V 2083 OUT3=3.3V 917 OUT5=5V 1390 OUT3=3.3V 688 OUT5=5V 1040 OUT3=3.3V 550 mV FSEL to GND TON ON-Time duration FSEL to VREF ns FSEL to LDO5 TOFFMIN VREF Minimum OFF-Time Voltage Accuracy 4.2V < VLDO5 < 5.5V Load regulation -100µA < IREF < 100µA Undervoltage Lockout fault threshold Falling edge of REF 1.224 300 350 ns 1.237 1.249 V 4 mV 0.95 V -4 COMP Over voltage clamp 250 COMP Under voltage clamp -150 mV Line regulation LDO5 linear Output Voltage VLDO5 Both SMPS, 6V< V IN <28V 6V < V IN < 28V, 0 < ILDO5 < 50mA LDO5 line regulation 6V < V IN < 28V, ILDO5 = 50mA LDO3_SEL tied to GND ILDO5 LDO5 Current limit VLDO5 > UVLO, ILDO3 = 0A VOUT5 > 5.1V, V OUT3 > 3.34V UVLO Under Voltage Lockout of LDO5 VLDO3 LDO3 linear Ouput Voltage ILDO3 LDO3 Current limit 4.9 5.0 0.004 %/V 5.1 V 0.004 %/V 300 350 400 mA 3.94 4 4.13 V 0 < ILDO3 < 50mA 3.23 3.3 3.37 V VLDO5 > UVLO 130 200 mA HGATEx high state(pullup) 2.0 3 Ω HGATEx low state (pulldown) 1.8 2.7 Ω LGATEx high state(pullup) 1.4 2.1 Ω LGATEx low state (pulldown) 0.6 0.9 Ω HGATE driver on-resistance LGATE driver on-resistance 9/16 PM6685 4 Electrical characteristics Table 6. Electrical characteristics (continued) Simbol Parameter High side rise time High side fall time Low side rise time OVP Over voltage threshold UVP Under voltage threshold Test Condition Min. Typ. Max. Unit 20 HGATEx-PHASE from 1V to 4V CLOAD = 3.3nF ns 20 40 LGATEx-PGND from 1V to 4V CLOAD = 8.2nF ns 40 113 116 120 % 66 70 72 % Upper threshold (VFB-VREF) 107 110 113 % Lower threshold (VFB-VREF) 90 92 94 % 1 µA 250 mV Both SMPS sections with respect to VREF. PGOOD3,5 IPGOOD3,5 PGOOD leakeage current VPGOOD3,5 Ouput Low Voltage PGOOD LDO3 VPGOOD3,5 forced to 5.5V ISink = 4mA 150 Rising voltage threshold 2.58 V Falling voltage threshold 2.55 V 25 mV Hytseresis IPGOOD_LD O3 VPGOOD_LD O3 TSDN 1 µA 250 mV Shutdown Temperature 150 °C SMPS disabled level 0.8 PGOOD leakeage current VPGOOD LDO3 forced to 5.5V Ouput Low Voltage ISink = 4mA 150 EN3,5 V SMPS enabled level 2.4 Low level FSEL Frequency selection range Middle level High level 0.5 1.0 Boostrap level Always-on level 0.5 1.0 PWM Mode Ultrasonic Mode 10/16 VLDO5 -1.5 V VLDO5 -0.8 Pulse Skip Mode SKIP V VLDO5 -0.8 Always-off level 3.3V Linear Regulator Selection LDO3 SEL Pin VLDO5 -1.5 0.5 1.0 VLDO5 -0.8 VLDO5 -1.5 V PM6685 Table 6. Simbol ILEAK 4 Electrical characteristics Electrical characteristics (continued) Parameter Input leakage current Test Condition Min. Typ. Max. VEN3,4 = 0 to 5V TBV VSKIP = 0 to 5V TBV VSHDN = 0 to 5V TBV VFSEL= 0 to 5V TBV VLDO3_SEL = 0 to 5V TBV Unit µA 11/16 5 Functional & block diagram 5 Figure 3. 12/16 Functional & block diagram Block diagram PM6685 PM6685 6 6 Package Mechanical Data Package Mechanical Data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 13/16 PM6685 6 Package Mechanical Data Table 7. VFQFPN 5x5x1.0 32L Pitch 0.50 Databook (mm.) Drawing (mm.) Dim. Min. Typ. Max Min. A 0.80 0.90 1.00 0.80 1.00 A1 0 0.02 0.05 0 0.05 A3 0.20 0.18 0.25 0.30 0.225 D(3) 4.85 5.00 5.15 4.90 D2(5) 3.65 3.95 3.65 E(3) 4.85 5.15 4.90 E2(5) 3.65 3.95 3.65 e L 0.50 0.30 0.40 0.50 0.35 ___Very thin: A = 1.00mm Max. 2. – The leads size have been increased by Pb/Sn thickness in tin plating electrolytic process. 3. – Dimensions D & E do not include mold protusion, not to exceed 0,15mm. 5. – Dimensions D2 & E2 are not in accordance with JEDEC. Figure 4. 14/16 Scheme Drawings 0.275 5.00 5.10 3.95 5.00 5.10 3.95 0.50 1. – VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead. 4. – Package outline exclusive of metal burr dimensions. Max 0.25 b 5.00 Typ. 0.45 PM6685 7 7 Revision history Revision history Date Revision 23-Sep-2005 1 Changes Initial release. 15/16 PM6685 7 Revision history Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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