STMICROELECTRONICS L6208

L6208
DMOS DRIVER FOR BIPOLAR STEPPER MOTOR
■
■
■
■
■
■
■
■
■
■
■
■
■
OPERATING SUPPLY VOLTAGE FROM 8 TO 52V
5.6A OUTPUT PEAK CURRENT (2.8A RMS)
RDS(ON) 0.3Ω TYP. VALUE @ Tj = 25°C
OPERATING FREQUENCY UP TO 100KHz
NON DISSIPATIVE OVERCURRENT
PROTECTION
DUAL INDEPENDENT CONSTANT tOFF PWM
CURRENT CONTROLLERS
FAST/SLOW DECAY MODE SELECTION
FAST DECAY QUASI-SYNCHRONOUS
RECTIFICATION
DECODING LOGIC FOR STEPPER MOTOR
FULL AND HALF STEP DRIVE
CROSS CONDUCTION PROTECTION
THERMAL SHUTDOWN
UNDER VOLTAGE LOCKOUT
INTEGRATED FAST FREE WHEELING DIODES
TYPICAL APPLICATIONS
■ BIPOLAR STEPPER MOTOR
DESCRIPTION
The L6208 is a DMOS Fully Integrated Stepper Motor
Driver with non-dissipative Overcurrent Protection,
realized in MultiPower-BCD technology, which com-
PowerDIP24
(20+2+2)
PowerSO36
SO24
(20+2+2)
ORDERING NUMBERS:
L6208N (PowerDIP24)
L6208PD (PowerSO36)
L6208D (SO24)
bines isolated DMOS Power Transistors with CMOS
and bipolar circuits on the same chip. The device includes all the circuitry needed to drive a two-phase
bipolar stepper motor including: a dual DMOS Full
Bridge, the constant off time PWM Current Controller
that performs the chopping regulation and the Phase
Sequence Generator, that generates the stepping
sequence. Available in PowerDIP24 (20+2+2),
PowerSO36 and SO24 (20+2+2) packages, the
L6208 features a non-dissipative overcurrent protection on the high side Power MOSFETs and thermal
shutdown.
BLOCK DIAGRAM
VBOOT
VCP
VBOOT
VBOOT
VBOOT
10V
10V
OCDA
OCDB
OVER
CURRENT
DETECTION
THERMAL
PROTECTION
EN
OUT1A
SENSEA
PWM
HALF/FULL
RESET
OUT2A
GATE
LOGIC
CONTROL
CLOCK
VSA
CHARGE
PUMP
STEPPING
SEQUENCE
GENERATION
ONE SHOT
MONOSTABLE
CW/CCW
MASKING
TIME
+
SENSE
COMPARATOR
VREFA
RCA
BRIDGE A
VOLTAGE
REGULATOR
10V
5V
VSB
OVER
CURRENT
DETECTION
OUT1B
OUT2B
SENSEB
GATE
LOGIC
VREFB
BRIDGE B
RCB
D01IN1225
September 2003
1/27
L6208
ABSOLUTE MAXIMUM RATINGS
Symbol
VS
VOD
VBOOT
Parameter
Test conditions
Value
Unit
Supply Voltage
VSA = VSB = VS
60
V
Differential Voltage between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
VSA = VSB = VS = 60V;
VSENSEA = VSENSEB = GND
60
V
Bootstrap Peak Voltage
VSA = VSB = VS
VS + 10
V
VIN,VEN
Input and Enable Voltage Range
-0.3 to +7
V
VREFA,
VREFB
Voltage Range at pins VREFA
and VREFB
-0.3 to +7
V
-0.3 to +7
V
-1 to +4
V
VRCA, VRCB Voltage Range at pins RCA and
RCB
VSENSEA,
VSENSEB
Voltage Range at pins SENSEA
and SENSEB
IS(peak)
Pulsed Supply Current (for each
VS pin), internally limited by the
overcurrent protection
VSA = VSB = VS;
tPULSE < 1ms
7.1
A
RMS Supply Current (for each
VS pin)
VSA = VSB = VS
2.8
A
-40 to 150
°C
IS
Tstg, TOP
Storage and Operating
Temperature Range
RECOMMENDED OPERATING CONDITIONS
Symbol
VS
VOD
VREFA,
VREFB
VSENSEA,
VSENSEB
IOUT
2/27
Parameter
Test Conditions
Supply Voltage
VSA = VSB = VS
Differential Voltage Between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
VSA = VSB = VS;
VSENSEA = VSENSEB
Voltage Range at pins VREFA
and VREFB
Voltage Range at pins SENSEA
and SENSEB
(pulsed tW < trr)
(DC)
MIN
MAX
Unit
8
52
V
52
V
-0.1
5
V
-6
-1
6
1
V
V
2.8
A
+125
°C
100
KHz
RMS Output Current
Tj
Operating Junction Temperature
fsw
Switching Frequency
-25
L6208
THERMAL DATA
Symbol
Description
Rth-j-pins
Maximum Thermal Resistance Junction-Pins
Rth-j-case
Maximum Thermal Resistance Junction-Case
PowerDIP24
SO24
PowerSO36
Unit
18
14
-
°C/W
-
-
1
°C/W
43
51
-
°C/W
Rth-j-amb1
Maximum Thermal Resistance Junction-Ambient
Rth-j-amb1
Maximum Thermal Resistance Junction-Ambient (2)
-
-
35
°C/W
Rth-j-amb1
Maximum Thermal Resistance Junction-Ambient (3)
-
-
15
°C/W
Rth-j-amb2
Maximum Thermal Resistance Junction-Ambient (4)
58
77
62
°C/W
(1)
(2)
(3)
(4)
(1)
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6cm2 (with a thickness of 35µm).
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35µm).
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35µm), 16 via holes
and a ground layer.
Mounted on a multi-layer FR4 PCB without any heat sinking surface on the board.
PIN CONNECTIONS (Top View)
CLOCK
1
24
VREFA
CW/CCW
2
23
RESET
SENSEA
3
22
VCP
GND
1
36
GND
N.C.
2
35
N.C.
N.C.
3
34
N.C.
VSA
4
33
VSB
OUT2A
5
32
OUT2B
RCA
4
21
OUT2A
N.C.
6
31
N.C.
OUT1A
5
20
VSA
VCP
7
30
VBOOT
GND
6
19
GND
RESET
8
29
EN
GND
7
18
GND
VREFA
9
28
CONTROL
OUT1B
8
17
VSB
CLOCK
10
27
HALF/FULL
RCB
9
16
OUT2B
CW/CCW
11
26
VREFB
12
25
SENSEB
10
15
VBOOT
SENSEA
SENSEB
RCB
VREFB
11
14
EN
HALF/FULL
12
13
CONTROL
D99IN1083
RCA
13
24
N.C.
14
23
N.C.
OUT1A
15
22
OUT1B
N.C.
16
21
N.C.
N.C.
17
20
N.C.
GND
18
19
GND
D99IN1084
PowerDIP24/SO24
(5)
PowerSO36 (5)
The slug is internally connected to pins 1,18,19 and 36 (GND pins).
3/27
L6208
PIN DESCRIPTION
PACKAGE
SO24/
PowerDIP24
PowerSO36
PIN #
PIN #
1
Name
Type
10
CLOCK
Logic Input
Step Clock input. The state machine makes one step on
each rising edge.
2
11
CW/CCW
Logic Input
Selects the direction of the rotation. HIGH logic level sets
clockwise direction, whereas LOW logic level sets
counterclockwise direction.
If not used, it has to be connected to GND or +5V.
3
12
SENSEA
Power Supply
Bridge A Source Pin. This pin must be connected to Power
Ground through a sensing power resistor.
4
13
RCA
RC Pin
5
15
OUT1A
Power Output
6, 7,
18, 19
1, 18,
19, 36
GND
GND
8
22
OUT1B
Power Output
9
24
RCB
RC Pin
10
25
SENSEB
Power Supply
Bridge B Source Pin. This pin must be connected to Power
Ground through a sensing power resistor.
11
26
VREFB
Analog Input
Bridge B Current Controller Reference Voltage.
Do not leave this pin open or connected to GND.
12
27
HALF/FULL
Logic Input
Step Mode Selector. HIGH logic level sets HALF STEP
Mode, LOW logic level sets FULL STEP Mode.
If not used, it has to be connected to GND or +5V.
13
28
CONTROL
Logic Input
Decay Mode Selector. HIGH logic level sets SLOW DECAY
Mode. LOW logic level sets FAST DECAY Mode.
If not used, it has to be connected to GND or +5V.
14
29
EN
Logic Input (6)
Chip Enable. LOW logic level switches OFF all Power
MOSFETs of both Bridge A and Bridge B. This pin is also
connected to the collector of the Overcurrent and Thermal
Protection to implement over current protection.
If not used, it has to be connected to +5V through a
resistor.
15
30
VBOOT
Supply
Voltage
16
32
OUT2B
Power Output
Bridge B Output 2.
17
33
VSB
Power Supply
Bridge B Power Supply Voltage. It must be connected to
the Supply Voltage together with pin VSA
20
4
VSA
Power Supply
Bridge A Power Supply Voltage. It must be connected to
the Supply Voltage together with pin VSB
4/27
Function
RC Network Pin. A parallel RC network connected
between this pin and ground sets the Current Controller
OFF-Time of the Bridge A.
Bridge A Output 1.
Ground terminals. In PowerDIP24 and SO24 packages,
these pins are also used for heat dissipation toward the
PCB. On PowerSO36 package the slug is connected to
these pins.
Bridge B Output 1.
RC Network Pin. A parallel RC network connected
between this pin and ground sets the Current Controller
OFF-Time of the Bridge B.
Bootstrap Voltage needed for driving the upper Power
MOSFETs of both Bridge A and Bridge B.
L6208
PIN DESCRIPTION (continued)
PACKAGE
SO24/
PowerDIP24
PowerSO36
PIN #
PIN #
21
(6)
Name
Type
Function
5
OUT2A
Power Output
22
7
VCP
Output
23
8
RESET
Logic Input
24
9
VREFA
Analog Input
Bridge A Output 2.
Charge Pump Oscillator Output.
Reset Pin. LOW logic level restores the Home State
(State 1) on the Phase Sequence Generator State
Machine.
If not used, it has to be connected to +5V.
Bridge A Current Controller Reference Voltage.
Do not leave this pin open or connected to GND.
Also connected at the output drain of the Over current and Thermal protection MOSFET. Therefore, it has to be driven putting in series
a resistor with a value in the range of 2.2KΩ - 180KΩ, recommended 100KΩ.
ELECTRICAL CHARACTERISTICS
(Tamb = 25°C, Vs = 48V, unless otherwise specified)
Symbol
Min
Typ
Max
Unit
VSth(ON) Turn-on Threshold
6.6
7
7.4
V
VSth(OFF) Turn-off Threshold
5.6
6
6.4
V
5
10
mA
IS
Tj(OFF)
Parameter
Quiescent Supply Current
Test Conditions
All Bridges OFF;
Tj = -25°C to 125°C (7)
Thermal Shutdown Temperature
°C
165
Output DMOS Transistors
RDS(ON)
High-Side Switch ON Resistance Tj = 25 °C
Low-Side Switch ON Resistance
IDSS
Leakage Current
0.34
0.4
Ω
Tj =125 °C (7)
0.53
0.59
Ω
Tj = 25 °C
0.28
0.34
Ω
Tj =125 °C (7)
0.47
0.53
Ω
2
mA
EN = Low; OUT = VS
EN = Low; OUT = GND
-0.15
mA
Source Drain Diodes
VSD
Forward ON Voltage
ISD = 2.8A, EN = LOW
1.15
1.3
V
trr
Reverse Recovery Time
If = 2.8A
300
ns
tfr
Forward Recovery Time
200
ns
Logic Inputs (EN, CONTROL, HALF/FULL, CLOCK, RESET, CW/CCW)
VIL
Low level logic input voltage
-0.3
0.8
V
VIH
High level logic input voltage
2
7
V
5/27
L6208
ELECTRICAL CHARACTERISTICS (continued)
(Tamb = 25°C, Vs = 48V, unless otherwise specified)
Symbol
Parameter
Test Conditions
IIL
Low Level Logic Input Current
GND Logic Input Voltage
IIH
High Level Logic Input Current
7V Logic Input Voltage
Vth(ON)
Turn-on Input Threshold
Vth(OFF)
Turn-off Input Threshold
Vth(HYS)
Input Threshold Hysteresis
Min
Typ
Max
-10
Unit
µA
1.8
10
µA
2.0
V
0.8
1.3
V
0.25
0.5
V
Switching Characteristics
tD(ON)EN Enable to Output Turn-on Delay
Time (8)
ILOAD =2.8A, Resistive Load
100
250
400
ns
tD(OFF)EN Enable to Output Turn-off Delay
Time (8)
ILOAD =2.8A, Resistive Load
300
550
800
ns
tRISE
Output Rise Time (8)
ILOAD =2.8A, Resistive Load
40
250
ns
tFALL
Output Fall Time (8)
ILOAD =2.8A, Resistive Load
40
250
ns
tDCLK
Clock to Output Delay Time (9)
ILOAD =2.8A, Resistive Load
2
µs
tCLK(min)L Minimum Clock Time (10)
1
µs
tCLK(min) Minimum Clock Time (10)
1
µs
100
KHz
H
fCLK
Clock Frequency
tS(MIN)
Minimum Set-up Time (11)
1
µs
tH(MIN)
Minimum Hold Time (11)
1
µs
tR(MIN)
Minimum Reset Time (11)
1
µs
1
µs
tRCLK(MIN Minimum Reset to Clock Delay
)
Time (11)
tDT
Dead Time Protection
fCP
Charge Pump Frequency
0.5
1
0.6
Tj = -25°C to 125°C (7)
µs
1
MHz
PWM Comparator and Monostable
IRCA, IRCB Source Current at pins RCA and
RCB
Voffset
Offset Voltage on Sense
Comparator
tPROP
Turn OFF Propagation Delay (12)
tBLANK
Internal Blanking Time on
SENSE pins
tON(MIN)
6/27
Minimum On Time
VRCA = VRCB = 2.5V
VREFA, VREFB = 0.5V
3.5
5.5
mA
±5
mV
500
ns
1
µs
1.5
2
µs
L6208
ELECTRICAL CHARACTERISTICS (continued)
(Tamb = 25°C, Vs = 48V, unless otherwise specified)
Symbol
tOFF
IBIAS
Parameter
Test Conditions
PWM Recirculation Time
Min
Typ
Max
Unit
ROFF = 20KΩ; COFF = 1nF
13
µs
ROFF = 100KΩ; COFF = 1nF
61
µs
Input Bias Current at pins VREFA
and VREFB
10
µA
5.6
7.1
A
60
Ω
Over Current Protection
ISOVER
Input Supply Overcurrent
Protection Threshold
Tj = -25°C to 125°C (7)
ROPDR
Open Drain ON Resistance
I = 4mA
40
tOCD(ON) OCD Turn-on Delay Time (13)
I = 4mA; CEN < 100pF
200
ns
tOCD(OFF) OCD Turn-off Delay Time (13)
I = 4mA; CEN < 100pF
100
ns
(7)
(8)
(9)
(10)
(11)
(12)
(13)
4
Tested at 25°C in a restricted range and guaranteed by characterization.
See Fig. 1.
See Fig. 2.
See Fig. 3.
See Fig. 4.
Measured applying a voltage of 1V to pin SENSE and a voltage drop from 2V to 0V to pin VREF.
See Fig. 5.
Figure 1. Switching Characteristic Definition
EN
Vth(ON)
Vth(OFF)
t
IOUT
90%
10%
t
D01IN1316
tFALL
tD(OFF)EN
tRISE
tD(ON)EN
7/27
L6208
Figure 2. Clock to Output Delay Time
CLOCK
Vth(ON)
t
IOUT
t
D01IN1317
tDCLK
Figure 3. Minimum Timing Definition; Clock Input
CLOCK
Vth(ON)
Vth(OFF)
tCLK(MIN)L
Vth(OFF)
tCLK(MIN)H
D01IN1318
Figure 4. Minimum Timing Definition; Logic Inputs
CLOCK
Vth(ON)
LOGIC INPUTS
tS(MIN)
RESET
Vth(OFF)
Vth(ON)
tR(MIN)
8/27
tH(MIN)
tRCLK(MIN)
D01IN1319
L6208
Figure 5. Overcurrent Detection Timing Definition
IOUT
ISOVER
ON
BRIDGE
OFF
VEN
90%
10%
tOCD(ON)
tOCD(OFF)
D02IN1399
CIRCUIT DESCRIPTION
POWER STAGES and CHARGE PUMP
The L6208 integrates two independent Power MOS Full Bridges. Each Power MOS has an RDS(ON) = 0.3Ω (typical value @ 25°C), with intrinsic fast freewheeling diode. Switching patterns are generated by the PWM Current
Controller and the Phase Sequence Generator (see below). Cross conduction protection is achieved using a
dead time (tDT = 1µs typical value) between the switch off and switch on of two Power MOSFETSs in one leg of
a bridge.
Pins VSA and VSB MUST be connected together to the supply voltage VS. The device operates with a supply
voltage in the range from 8V to 52V. It has to be noticed that the RDS(ON) increases of some percents when the
supply voltage is in the range from 8V to 12V (see Fig. 34 and 35).
Using N-Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above the
power supply voltage. The bootstrapped supply voltage VBOOT is obtained through an internal Oscillator and few
external components to realize a charge pump circuit as shown in Figure 6. The oscillator output (VCP) is a
square wave at 600KHz (typical) with 10V amplitude. Recommended values/part numbers for the charge pump
circuit are shown in Table 1.
Table 1. Charge Pump External Components Values
CBOOT
220nF
CP
10nF
RP
100Ω
D1
1N4148
D2
1N4148
9/27
L6208
Figure 6. Charge Pump Circuit
VS
CBOOT
D1
D2
RP
CP
VCP
VBOOT
VSA VSB
D01IN1328
LOGIC INPUTS
Pins CONTROL, HALF/FULL, CLOCK, RESET and CW/CCW are TTL/CMOS and uC compatible logic inputs.
The internal structure is shown in Fig. 7. Typical value for turn-on and turn-off thresholds are respectively
Vth(ON)= 1.8V and Vth(OFF)= 1.3V.
Pin EN (Enable) has identical input structure with the exception that the drain of the Overcurrent and thermal
protection MOSFET is also connected to this pin. Due to this connection some care needs to be taken in driving
this pin. The EN input may be driven in one of two configurations as shown in Fig. 8 or 9. If driven by an open
drain (collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in Fig. 8. If the
driver is a standard Push-Pull structure the resistor REN and the capacitor CEN are connected as shown in Fig.
9. The resistor REN should be chosen in the range from 2.2KΩ to 180KΩ. Recommended values for REN and
CEN are respectively 100KΩ and 5.6nF. More information on selecting the values is found in the Overcurrent
Protection section.
Figure 7. Logic Inputs Internal Structure
5V
ESD
PROTECTION
D01IN1329
Figure 8. EN Pin Open Collector Driving
5V
5V
REN
OPEN
COLLECTOR
OUTPUT
EN
CEN
ESD
PROTECTION
D01IN1330
Figure 9. EN Pin Push-Pull Driving
5V
PUSH-PULL
OUTPUT
REN
EN
CEN
ESD
PROTECTION
D01IN1331
10/27
L6208
PWM CURRENT CONTROL
The L6208 includes a constant off time PWM current controller for each of the two bridges. The current control
circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the two lower power MOS transistors and ground, as shown in Figure 10. As the current in
the motor builds up the voltage across the sense resistor increases proportionally. When the voltage drop
across the sense resistor becomes greater than the voltage at the reference input (VREFA or VREFB) the sense
comparator triggers the monostable switching the bridge off. The power MOS remain off for the time set by the
monostable and the motor current recirculates as defined by the selected decay mode, described in the next
section. When the monostable times out the bridge will again turn on. Since the internal dead time, used to prevent cross conduction in the bridge, delays the turn on of the power MOS, the effective off time is the sum of the
monostable time plus the dead time.
Figure 10. PWM Current Controller Simplified Schematic
VSA (or B)
TO GATE LOGIC
BLANKING TIME
MONOSTABLE
1µs
FROM THE
LOW-SIDE
GATE DRIVERS
2H
5mA
S
Q
(0)
(1)
MONOSTABLE
SET
1H
IOUT
BLANKER
R
OUT2A(or B)
DRIVERS
+
DEAD TIME
-
DRIVERS
+
DEAD TIME
+
5V
2 PHASE
STEPPER MOTOR
OUT1A(or B)
2.5V
SENSE
COMPARATOR
2L
1L
+
COMPARATOR
OUTPUT
RCA(or B)
COFF
ROFF
-
VREFA(or B)
SENSEA(or B)
RSENSE
D01IN1332
Figure 11 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the RC pin voltage and the status of the bridge. More details regarding the Synchronous Rectification and
the output stage configuration are included in the next section.
Immediately after the Power MOS turns on, a high peak current flows through the sensing resistor due to the
reverse recovery of the freewheeling diodes. The L6208 provides a 1µs Blanking Time tBLANK that inhibits the
comparator output so that this current spike cannot prematurely re-trigger the monostable.
11/27
L6208
Figure 11. Output Current Regulation Waveforms
IOUT
VREF
RSENSE
tOFF
tON
tOFF
1µs tBLANK
1µs tBLANK
VSENSE
VREF
Slow Decay
0
Slow Decay
ay
ay
c
Fast De
c
Fast De
tRCRISE
VRC
tRCRISE
5V
2.5V
tRCFALL
tRCFALL
1µs tDT
1µs tDT
ON
OFF
SYNCHRONOUS OR QUASI
SYNCHRONOUS RECTIFICATION
D01IN1334
B
C
D
A
B
C
D
Figure 12 shows the magnitude of the Off Time tOFF versus COFF and ROFF values. It can be approximately
calculated from the equations:
tRCFALL = 0.6 · ROFF · COFF
tOFF = tRCFALL + tDT = 0.6 · ROFF · COFF + tDT
where ROFF and COFF are the external component values and tDT is the internally generated Dead Time with:
20KΩ ≤ ROFF ≤ 100KΩ
0.47nF ≤ COFF ≤ 100nF
tDT = 1µs (typical value)
Therefore:
tOFF(MIN) = 6.6µs
tOFF(MAX) = 6ms
These values allow a sufficient range of tOFF to implement the drive circuit for most motors.
The capacitor value chosen for COFF also affects the Rise Time tRCRISE of the voltage at the pin RCOFF. The
Rise Time tRCRISE will only be an issue if the capacitor is not completely charged before the next time the
monostable is triggered. Therefore, the on time tON, which depends by motors and supply parameters, has to
be bigger than tRCRISE for allowing a good current regulation by the PWM stage. Furthermore, the on time tON
can not be smaller than the minimum on time tON(MIN).
12/27
L6208
 t O N > t O N ( MIN ) = 1.5µ s (typ. value)

 t O N > t RCRISE – t DT
tRCRISE = 600 · COFF
Figure 13 shows the lower limit for the on time tON for having a good PWM current regulation capacity. It has to
be said that tON is always bigger than tON(MIN) because the device imposes this condition, but it can be smaller
than tRCRISE - tDT. In this last case the device continues to work but the off time tOFF is not more constant.
So, small COFF value gives more flexibility for the applications (allows smaller on time and, therefore, higher
switching frequency), but, the smaller is the value for COFF, the more influential will be the noises on the circuit
performance.
Figure 12. tOFF versus COFF and ROFF
4
1 .10
R off = 100kΩ
3
1 .10
R off = 47kΩ
toff [µs]
R off = 20kΩ
100
10
1
0.1
1
10
100
Coff [nF]
Figure 13. Area where tON can vary maintaining the PWM regulation.
ton(min) [µs]
100
10
1.5µs (typ. value)
1
0.1
1
10
100
Coff [nF]
13/27
L6208
DECAY MODES
The CONTROL input is used to select the behavior of the bridge during the off time. When the CONTROL pin
is low, the Fast Decay mode is selected and both transistors in the bridge are switched off during the off time.
When the CONTROL pin is high, the Slow Decay mode is selected and only the low side transistor of the bridge
is switched off during the off time.
Figure 14 shows the operation of the bridge in the Fast Decay mode. At the start of the off time, both of the
power MOS are switched off and the current recirculates through the two opposite free wheeling diodes. The
current decays with a high di/dt since the voltage across the coil is essentially the power supply voltage. After
the dead time, the lower power MOS in parallel with the conducting diode is turned on in synchronous rectification mode. In applications where the motor current is low it is possible that the current can decay completely to
zero during the off time. At this point if both of the power MOS were operating in the synchronous rectification
mode it would then be possible for the current to build in the opposite direction. To prevent this only the lower
power MOS is operated in synchronous rectification mode. This operation is called Quasi-Synchronous Rectification Mode. When the monostable times out, the power MOS are turned on again after some delay set by the
dead time to prevent cross conduction.
Figure 15 shows the operation of the bridge in the Slow Decay mode. At the start of the off time, the lower power
MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage across
the coil is low, the current decays slowly. After the dead time the upper power MOS is operated in the synchronous rectification mode. When the monostable times out, the lower power MOS is turned on again after some
delay set by the dead time to prevent cross conduction.
Figure 14. Fast Decay Mode Output Stage Configurations
A) ON TIME
B) 1µs DEAD TIME
D01IN1335
C) QUASI-SYNCHRONOUS
RECTIFICATION
D) 1µs SLOW DECAY
Figure 15. Slow Decay Mode Output Stage Configurations
A) ON TIME
B) 1µs DEAD TIME
D01IN1336
C) SYNCHRONOUS
RECTIFICATION
D) 1µs DEAD TIME
STEPPING SEQUENCE GENERATION
The phase sequence generator is a state machine that provides the phase and enable inputs for the two bridges
to drive a stepper motor in either full step or half step. Two full step modes are possible, the Normal Drive Mode
where both phases are energized each step and the Wave Drive Mode where only one phase is energized at a
14/27
L6208
time. The drive mode is selected by the HALF/FULL input and the current state of the sequence generator as
described below. A rising edge of the CLOCK input advances the state machine to the next state. The direction
of rotation is set by the CW/CCW input. The RESET input resets the state machine to state.
HALF STEP MODE
A HIGH logic level on the HALF/FULL input selects Half Step Mode. Figure 16 shows the motor current waveforms and the state diagram for the Phase Sequencer Generator. At Start-Up or after a RESET the Phase Sequencer is at state 1. After each clock pulse the state changes following the sequence 1,2,3,4,5,6,7,8,… if CW/
CCW is high (Clockwise movement) or 1,8,7,6,5,4,3,2,… if CW/CCW is low (Counterclockwise movement).
NORMAL DRIVE MODE (Full-step two-phase-on)
A LOW level on the HALF/FULL input selects the Full Step mode. When the low level is applied when the state
machine is at an ODD numbered state the Normal Drive Mode is selected. Figure Fig. 17 shows the motor current waveform state diagram for the state machine of the Phase Sequencer Generator. The Normal Drive Mode
can easily be selected by holding the HALF/FULL input low and applying a RESET. AT start -up or after a RESET the State Machine is in state1. While the HALF/FULL input is kept low, state changes following the sequence 1,3,5,7,… if CW/CCW is high (Clockwise movement) or 1,7,5,3,… if CW/CCW is low (Counterclockwise
movement).
WAVE DRIVE MODE (Full-step one-phase-on)
A LOW level on the pin HALF/FULL input selects the Full Step mode. When the low level is applied when the
state machine is at an EVEN numbered state the Wave Drive Mode is selected. Figure 18 shows the motor current waveform and the state diagram for the state machine of the Phase Sequence Generator. To enter the
Wave Drive Mode the state machine must be in an EVEN numbered state. The most direct method to select the
Wave Drive Mode is to first apply a RESET, then while keeping the HALF/FULL input high apply one pulse to
the clock input then take the HALF/FULL input low. This sequence first forces the state machine to sate 1. The
clock pulse, with the HALF/FULL input high advances the state machine from state 1 to either state 2 or 8 depending on the CW/CCW input. Starting from this point, after each clock pulse (rising edge) will advance the
state machine following the sequence 2,4,6,8,… if CW/CCW is high (Clockwise movement) or 8,6,4,2,… if CW/
CCW is low (Counterclockwise movement).
Figure 16. Half Step Mode
IOUTA
3
4
2
1
5
6
8
IOUTB
7
Start Up or Reset
CLOCK
1
2
3
4
5
6
7
8
D01IN1320
Figure 17. Normal Drive Mode
IOUTA
3
4
2
1
5
IOUTB
6
8
7
CLOCK
Start Up or Reset
1
3
5
7
1
3
5
7
D01IN1322
15/27
L6208
Figure 18. Wave Drive Mode
IOUTA
3
4
5
IOUTB
6
2
1
7
8
CLOCK
Start Up or Reset
2
4
6
8
2
4
6
8
D01IN1321
NON-DISSIPATIVE OVERCURRENT PROTECTION
The L6208 integrates an Overcurrent Detection Circuit (OCD). This circuit provides protection against a short
circuit to ground or between two phases of the bridge. With this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 19 shows a simplified schematic of the overcurrent detection circuit.
To implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power MOS. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference current IREF. When the output current reaches the detection threshold (typically 5.6A) the OCD comparator signals
a fault condition. When a fault condition is detected, the EN pin is pulled below the turn off threshold (1.3V typical) by an internal open drain MOS with a pull down capability of 4mA. By using an external R-C on the EN pin,
the off time before recovering normal operation can be easily programmed by means of the accurate thresholds
of the logic inputs.
Figure 19. Overcurrent Protection Simplified Schematic
OUT1A
VSA
OUT2A
POWER SENSE
1 cell
HIGH SIDE DMOSs OF
THE BRIDGE A
I1A
POWER DMOS
n cells
TO GATE
LOGIC
µC or LOGIC
POWER DMOS
n cells
POWER SENSE
1 cell
+
OCD
COMPARATOR
VDD
I2A
I1A / n
I2A / n
(I1A+I2A) / n
REN.
CEN.
EN
IREF
INTERNAL
OPEN-DRAIN
RDS(ON)
40Ω TYP.
OVER TEMPERATURE
OCD
COMPARATOR
FROM THE
BRIDGE B
D01IN1337
16/27
L6208
Figure 20 shows the Overcurrent Detection operation. The Disable Time tDISABLE before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by
CEN and REN values and its magnitude is reported in Figure 21. The Delay Time tDELAY before turning off the
bridge when an overcurrent has been detected depends only by CEN value. Its magnitude is reported in Figure 22.
CEN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of CEN
should be chosen as big as possible according to the maximum tolerable Delay Time and the REN value should
be chosen according to the desired Disable Time.
The resistor REN should be chosen in the range from 2.2KΩ to 180KΩ. Recommended values for REN and CEN
are respectively 100KΩ and 5.6nF that allow obtaining 200µs Disable Time.
Figure 20. Overcurrent Protection Waveforms
IOUT
ISOVER
VEN
VDD
Vth(ON)
Vth(OFF)
VEN(LOW)
ON
OCD
OFF
ON
tDELAY
BRIDGE
tDISABLE
OFF
tOCD(ON)
tEN(FALL)
tOCD(OFF)
tD(OFF)EN
tEN(RISE)
tD(ON)EN
D02IN1400
17/27
L6208
Figure 21. tDISABLE versus C EN and REN (VDD = 5V).
R EN = 220 kΩ
3
1 . 10
R EN = 100 k Ω
R EN = 4 7 k Ω
R EN = 3 3 k Ω
tDISABLE [µs]
R EN = 1 0 k Ω
100
10
1
1
10
1 00
C E N [n F ]
Figure 22. tDELAY versus CEN (VDD = 5V).
tdelay [µs]
10
1
0.1
1
10
Cen [nF]
100
THERMAL PROTECTION
In addition to the Ovecurrent Protection, the L6208 integrates a Thermal Protection for preventing the device
destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible
element integrated in the die. The device switch-off when the junction temperature reaches 165°C (typ. value)
with 15°C hysteresis (typ. value).
18/27
L6208
APPLICATION INFORMATION
A typical Bipolar Stepper Motor Driver application using L6208 is shown in Fig. 23. Typical component values
for the application are shown in Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should
be placed between the power pins (VSA and VSB) and ground near the L6208 to improve the high frequency
filtering on the power supply and reduce high frequency transients generated by the switching. The capacitor
connected from the EN input to ground sets the shut down time when an over current is detected (see Overcurrent Protection). The two current sensing inputs (SENSEA and SENSEB) should be connected to the sensing
resistors with a trace length as short as possible in the layout. The sense resistors should be non-inductive resistors to minimize the di/dt transients across the resistor. To increase noise immunity, unused logic pins (except
EN) are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin description). It is recommended to keep Power Ground and Signal Ground separated on PCB.
Table 2. Component Values for Typical Application
C1
100µF
D1
1N4148
C2
100nF
D2
1N4148
CA
1nF
RA
39KΩ
CB
1nF
RB
39KΩ
CBOOT
220nF
REN
100KΩ
CP
10nF
RP
100Ω
CEN
5.6nF
RSENSEA
0.3Ω
CREF
68nF
RSENSEB
0.3Ω
Figure 23. Typical Application
VSA
+
VS
8-52VDC
C1
POWER
GROUND
-
SIGNAL
GROUND
VSB
C2
D1
CBOOT
RP
CP
20
17
VCP
VBOOT
RSENSEB
11
VREFA
VREF = 0-1V
VREFB
CREF
22
D2
RSENSEA
24
SENSEA
SENSEB
OUT1A
OUT2A
23
14
3
10
5
21
13
GND
GND
GND
GND
18
12
1
HALF/FULL
CLOCK
FAST/SLOW DECAY
HALF/FULL
CLOCK
CW/CCW
CW/CCW
CA
4
RCA
RA
19
CB
6
7
ENABLE
CONTROL
8
16
RESET
REN
CEN
2
OUT2B
EN
15
M
OUT1B
RESET
9
RCB
D01IN1341
RB
19/27
L6208
Output Current Capability and IC Power Dissipation
In Fig. 24, 25, 26 and 27 are shown the approximate relation between the output current and the IC power dissipation using PWM current control driving a two-phase stepper motor, for different driving sequences:
– HALF STEP mode (Fig. 24) in which alternately one phase / two phases are energized.
– NORMAL DRIVE (FULL-STEP TWO PHASE ON) mode (Fig. 25) in which two phases are energized
during each step.
– WAVE DRIVE (FULL-STEP ONE PHASE ON) mode (Fig. 26) in which only one phase is energized at
each step.
– MICROSTEPPING mode (Fig. 27), in which the current follows a sine-wave profile, provided through
the Vref pins.
For a given output current and driving sequence the power dissipated by the IC can be easily evaluated, in order
to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125°C maximum).
Figure 24. IC Power Dissipation versus Output Current in HALF STEP Mode.
HALF STEP
IA
10
8
I OUT
IB
6
I OUT
PD [W]
4
Test Conditions:
Supply Voltage = 24V
No PWM
f SW = 30 kHz (slow decay)
2
0
0
0.5
1
1.5
2
2.5
3
I OUT [A]
Figure 25. IC Power Dissipation versus Output Current in NORMAL Mode (full step two phase on).
NORM AL DRIVE
IA
10
8
I OUT
IB
6
I OUT
PD [W ]
4
Test Conditions:
Supply Volt age =24 V
2
0
0
0.5
1
1.5
I OUT [A ]
20/27
2
2.5
3
No PWM
f SW = 30 kHz (slow decay)
L6208
Figure 26. IC Power Dissipation versus Output Current in WAVE Mode (full step one phase on).
WAVE DRIVE
IA
10
8
I OUT
IB
6
PD [W]
I OUT
4
Test Conditions:
Supply Voltage = 24V
2
0
0
0.5
1
1.5
2
2.5
No PW M
fSW = 3 0 kHz (slow decay)
3
I OUT [A]
Figure 27. IC Power Dissipation versus Output Current in MICROSTEPPING Mode.
MICROSTEPPING
IA
10
I OUT
8
I OUT
6
IB
PD [W]
4
2
0
0
0.5
1
1.5
I OUT [A]
2
2.5
3
Test Conditions:
Supply Voltage = 24V
f SW = 30 kHz (slow decay)
f SW = 50 kHz (slow decay)
Thermal Management
In most applications the power dissipation in the IC is the main factor that sets the maximum current that can
be delivered by the device in a safe operating condition. Therefore, it has to be taken into account very carefully.
Besides the available space on the PCB, the right package should be chosen considering the power dissipation.
Heat sinking can be achieved using copper on the PCB with proper area and thickness. Figures 28, 29 and 30
show the Junction-to-Ambient Thermal Resistance values for the PowerSO36, PowerDIP24 and SO24 packages.
For instance, using a PowerSO package with copper slug soldered on a 1.5mm copper thickness FR4 board
with 6cm2 dissipating footprint (copper thickness of 35µm), the Rth(j-amb) is about 35°C/W. Fig. 31 shows mounting methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance can be
reduced down to 15°C/W.
21/27
L6208
Figure 28. PowerSO36 Junction-Ambient Thermal Resistance versus On-Board Copper Area.
ºC / W
43
38
33
W ith o ut G ro u nd La yer
28
W ith Gro un d La yer
W ith Gro un d La yer+ 16 via
H o le s
23
On-Board Copper Area
18
13
1
2
3
4
5
6
7
8
9
10
11
12
13
s q. cm
Figure 29. PowerDIP24 Junction-Ambient Thermal Resistance versus On-Board Copper Area.
ºC / W
On-Board Copper Area
49
48
C o p pe r Are a is o n Bo tto m
S id e
47
C o p pe r Are a is o n To p S i de
46
45
44
43
42
41
40
39
1
2
3
4
5
6
7
8
9
10
11
12
s q . cm
Figure 30. SO24 Junction-Ambient Thermal Resistance versus On-Board Copper Area.
On-Board Copper Area
ºC / W
68
66
64
62
60
C o pp er A re a is o n T op S id e
58
56
54
52
50
48
1
2
3
4
5
6
7
8
9
10
11
12
s q. cm
Figure 31. Mounting the PowerSO Package.
Slug soldered
to PCB with
dissipating area
22/27
Slug soldered
to PCB with
dissipating area
plus ground layer
Slug soldered to PCB with
dissipating area plus ground layer
contacted through via holes
L6208
Figure 32. Typical Quiescent Current vs.
Supply Voltage
Figure 35. Typical High-Side RDS(ON) vs.
Supply Voltage
Iq [m A]
RDS(ON) [Ω]
5.6
fsw = 1kHz
0.380
Tj = 25°C
0.376
Tj = 85°C
5.4
0.372
Tj = 25°C
0.368
Tj = 125°C
0.364
5.2
0.360
0.356
5.0
0.352
0.348
4.8
0.344
0.340
0.336
4.6
0
10
20
30
V S [V]
40
50
0
60
5
10
15
20
25
30
VS [V]
Figure 33. Normalized Typical Quiescent
Current vs. Switching Frequency
Figure 36. Normalized RDS(ON) vs.Junction
Temperature (typical value)
Iq / (Iq @ 1 kHz)
R DS(ON) / (R DS(ON) @ 25 °C)
1.7
1.8
1.6
1.6
1.5
1.4
1.4
1.3
1.2
1.2
1.1
1.0
1.0
0.8
0.9
0
20
40
60
80
0
100
20
40
60
80
100
120
140
T j [°C ]
fSW [kHz]
Figure 34. Typical Low-Side RDS(ON) vs. Supply
Voltage
Figure 37. Typical Drain-Source Diode Forward
ON Characteristic
R DS(ON) [Ω]
ISD [A]
0.300
3.0
0.296
2.5
Tj = 25°C
Tj = 25°C
0.292
2.0
0.288
1.5
0.284
1.0
0.280
0.5
0.276
0.0
700
0
5
10
15
V S [V]
20
25
30
800
900
1000
1100
1200
1300
VSD [mV]
23/27
L6208
DIM.
A
a1
a2
a3
b
c
D (1)
D1
E
e
e3
E1 (1)
E2
E3
E4
G
H
h
L
N
S
MIN.
mm
TYP.
0.10
0
0.22
0.23
15.80
9.40
13.90
MAX.
3.60
0.30
3.30
0.10
0.38
0.32
16.00
9.80
14.50
inch
TYP.
MIN.
0.004
0
0.008
0.009
0.622
0.370
0.547
0.65
11.05
10.90
0.0256
0.435
11.10 0.429
2.90
6.20 0.228
3.20 0.114
0.10
0
15.90 0.610
1.10
1.10 0.031
10°(max.)
8 °(max.)
5.80
2.90
0
15.50
0.80
OUTLINE AND
MECHANICAL DATA
MAX.
0.141
0.012
0.130
0.004
0.015
0.012
0.630
0.385
0.570
0.437
0.114
0.244
0.126
0.004
0.626
0.043
0.043
PowerSO36
(1): "D" and "E1" do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)
- Critical dimensions are "a3", "E" and "G".
N
N
a2
e
A
DETAIL A
A
c
a1
DETAIL B
E
e3
H
DETAIL A
lead
D
slug
a3
36
BOTTOM VIEW
19
E3
B
E1
E2
D1
DETAIL B
0.35
Gage Plane
1
1
-C-
8
S
h x 45˚
24/27
b
⊕ 0.12
L
SEATING PLANE
G
M
AB
PSO36MEC
C
(COPLANARITY)
L6208
mm
DIM.
MIN.
TYP.
A
A1
inch
MAX.
MIN.
TYP.
4.320
0.380
A2
0.170
0.015
3.300
0.130
B
0.410
0.460
0.510
0.016
0.018
0.020
B1
1.400
1.520
1.650
0.055
0.060
0.065
c
0.200
0.250
0.300
0.008
0.010
0.012
D
31.62
31.75
31.88
1.245
1.250
1.255
E
7.620
8.260
0.300
e
2.54
E1
6.350
e1
L
6.600
M
0.325
0.100
6.860
0.250
0.260
0.270
0.300
7.620
3.180
OUTLINE AND
MECHANICAL DATA
MAX.
3.430
0.125
0.135
Powerdip 24
0˚ min, 15˚ max.
E1
A2
A
A1
L
B
B1
e
e1
D
24
13
c
1
12
M
SDIP24L
25/27
L6208
mm
inch
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.10
0.30
0.004
0.012
B
0.33
0.51
0.013
0.200
C
0.23
0.32
0.009
0.013
D (1)
15.20
15.60
0.598
0.614
E
7.40
7.60
0.291
0.299
e
1.27
10.0
10.65
0.394
0.419
h
0.25
0;75
0.010
0.030
L
0.40
1.27
0.016
0.050
ddd
Weight: 0.60gr
0.050
H
k
OUTLINE AND
MECHANICAL DATA
0˚ (min.), 8˚ (max.)
0.10
0.004
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO24
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2003 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
0070769 C
www.st.com
26/27
L6208
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2003 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
27/27