STMICROELECTRONICS L6226Q

L6226Q
DMOS dual full bridge driver
Features
■
Operating supply voltage from 8 to 52 V
■
2.8 A output peak current (1.4 A DC)
■
RDS(on) 0.73 Ω typ. value @ TJ = 25 °C
■
Operating frequency up to 100 kHz
■
Programmable high side overcurrent detection
and protection
■
Diagnostic output
■
Paralleled operation
■
Cross conduction protection
■
Thermal shutdown
■
Under voltage lockout
■
Integrated fast free wheeling diodes
VFQFPN32 5 mm x 5 mm
The L6226Q is a DMOS dual full bridge designed
for motor control applications, realized in
BCDmultipower technology, which combines
isolated DMOS power transistors with CMOS and
bipolar circuits on the same chip. Available in
QFN32 5x5 package, the L6226Q features
thermal shutdown and a non-dissipative
overcurrent detection on the high side power
MOSFETs plus a diagnostic output that can be
easily used to implement the overcurrent
protection.
Applications
■
Bipolar stepper motor
■
Dual or quad DC motor
Figure 1.
Description
Block diagram
VBOOT
VBOOT
VBOOT
VCP
VSA
VBOOT
CHARGE
PUMP
PROGCLA
OCDA
OCDA
OVER
CURRENT
DETECTION
OUT1A
10V
THERMAL
PROTECTION
OUT2A
10V
GATE
LOGIC
ENA
IN1A
SENSEA
IN2A
VOLTAGE
REGULATOR
10V
5V
BRIDGE A
OCDB
OCDB
OVER
CURRENT
DETECTION
VSB
PROGCLB
ENB
OUT1B
OUT2B
GATE
LOGIC
SENSEB
IN1B
IN2B
BRIDGE B
D99IN1088A
June 2008
Rev 2
1/28
www.st.com
28
Contents
L6226Q
Contents
1
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1
Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2
Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4
Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 11
4.5
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
Paralleled operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7
Output current capability and IC power dissipation . . . . . . . . . . . . . . 22
8
Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/28
L6226Q
Electrical data
1
Electrical data
1.1
Absolute maximum ratings
Table 1.
Absolute maximum ratings
Symbol
Parameter
VS
VOD
OCDA,OCDB
PROGCLA,
PROGCLB
VBOOT
VIN,VEN
60
V
Differential voltage between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
VSA = VSB = VS = 60 V,
VSENSEA = VSENSEB = GND
60
V
OCD pins voltage range
-0.3 to + 10
V
PROGCL pins voltage range
-0.3 to + 7
V
VS + 10
V
-0.3 to + 7
V
-1 to + 4
V
VSA = VSB = VS,
tPULSE < 1 ms
3.55
A
RMS supply current (for each VS pin) VSA = VSB = VS
2.8
A
-40 to 150
°C
Bootstrap peak voltage
VSA = VSB = VS
Input and enable voltage range
IS(peak)
Pulsed supply current (for each VS
pin), internally limited by the
overcurrent protection
Storage and operating temperature
range
1.2
Recommended operating conditions
Table 2.
Recommended operating conditions
Symbol
VS
Parameter
Parameter
Supply voltage
VSA = VSB = VS
VOD
Differential voltage between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
VSA = VSB = VS,
VSENSEA = VSENSEB
VSENSEA,
VSENSEB
Voltage range at pins SENSEA and
SENSEB
(pulsed tW < trr)
(DC)
IOUT
Unit
VSA = VSB = VS
Voltage range at pins SENSEA and
SENSEB
Tstg, TOP
Value
Supply voltage
VSENSEA,
VSENSEB
IS
Parameter
Min
Max
Unit
8
52
V
52
V
6
1
V
V
1.4
A
+125
°C
100
kHz
-6
-1
RMS output current
TJ
Operating junction temperature
fsw
Switching frequency
-25
3/28
Electrical data
1.3
L6226Q
Thermal data
Table 3.
Symbol
Rth(JA)
Thermal data
Parameter
Thermal resistance junction-ambient max. (1)
2
Value
Unit
22
°C/W
1. Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm on the top side plus 6
cm2 ground layer connected through 18 via holes (9 below the IC).
4/28
L6226Q
Pin connection
2
Pin connection
Figure 2.
Note:
Pin connection (top view)
1
The pins 2 to 8 are connected to die PAD.
2
The die PAD must be connected to GND pin.
5/28
Pin connection
Table 4.
L6226Q
Pin description
N°
Pin
Type
Function
1, 21
GND
GND
9
OUT1B
11
OCDB
Open drain
output
Bridge B overcurrent detection and thermal protection pin. An internal open
drain transistor pulls to GND when overcurrent on bridge B is detected or in
case of thermal protection.
12
SENSEB
Power supply
Bridge B source pin. This pin must be connected to power ground directly or
through a sensing power resistor.
13
IN1B
Logic input
Bridge B input 1
14
IN2B
Logic input
Bridge B input 2
Signal ground terminals.
Power output Bridge B output 1.
Bridge B overcurrent level programming. A resistor connected between this
pin and ground sets the programmable current limiting value for the bridge B.
By connecting this pin to ground the maximum current is set. This pin cannot
be left non-connected.
15
PROGCLB
R pin
16
ENB
Logic input
Bridge B enable. LOW logic level switches OFF all power MOSFETs of
bridge B.
If not used, it has to be connected to +5 V.
17
VBOOT
Supply
voltage
Bootstrap voltage needed for driving the upper power MOSFETs of both
bridge A and bridge B.
19
OUT2B
20
VSB
Power supply
Bridge B power supply voltage. It must be connected to the supply voltage
together with pin VSA.
22
VSA
Power supply
Bridge A power supply voltage. It must be connected to the supply voltage
together with pin VSB.
23
OUT2A
24
VCP
Output
25
ENA
Logic input
Power output Bridge B output 2.
Power output Bridge A output 2.
Charge pump oscillator output.
Bridge A enable. LOW logic level switches OFF all power MOSFETs of
bridge A.
If not used, it has to be connected to +5 V.
Bridge A overcurrent level programming. A resistor connected between this
pin and ground sets the programmable current limiting value for the bridge A.
By connecting this pin to ground the maximum current is set. This pin cannot
be left non-connected.
26
PROGCLA
R pin
27
IN1A
Logic input
Bridge A logic input 1.
28
IN2A
Logic input
Bridge A logic input 2.
29
SENSEA
Power supply
Bridge A source pin. This pin must be connected to power ground directly or
through a sensing power resistor.
30
OCDA
Open drain
output
Bridge A overcurrent detection and thermal protection pin. An internal open
drain transistor pulls to GND when overcurrent on bridge A is detected or in
case of thermal protection.
31
OUT1A
6/28
Power output Bridge A output 1.
L6226Q
Electrical characteristics
3
Electrical characteristics
Table 5.
Electrical characteristcs TA = 25 °C, Vs = 48 V, unless otherwise specified
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
VSth(ON)
Turn-on threshold
5.8
6.3
6.8
V
VSth(OFF)
Turn-off threshold
5
5.5
6
V
5
10
mA
IS
TJ(OFF)
All bridges OFF;
TJ = -25 °C to 125 °C (1)
Quiescent supply current
Thermal shutdown temperature
°C
165
Output DMOS transistors
RDS(on)
IDSS
TJ = 25 °C
High-side + low-side switch ON
resistance
TJ = 125
°C (1)
1.47
1.69
Ω
2.35
2.70
Ω
2
mA
EN = Low; OUT = VS
Leakage current
EN = Low; OUT = GND
-0.3
mA
Source drain diodes
VSD
Forward ON voltage
ISD = 2.8 A, EN = LOW
1.15
1.3
V
trr
Reverse recovery time
If = 1.4 A
300
ns
tfr
Forward recovery time
200
ns
Logic input
VIL
Low level logic input voltage
-0.3
0.8
V
VIH
High level logic input voltage
2
7
V
IIL
Low level logic input current
GND logic input voltage
IIH
High level logic input current
7 V logic input voltage
-10
µA
1.8
10
µA
2.0
V
Vth(ON)
Turn-on input threshold
Vth(OFF)
Turn-off input threshold
0.8
1.3
V
Vth(HYS)
Input threshold hysteresis
0.25
0.5
V
Switching characteristics
tD(on)EN
Enable to out turn ON delay time (2)
ILOAD =1.4 A, resistive load
tD(on)IN
Input to out turn ON delay time
ILOAD =1.4 A, resistive load
(dead time included)
tRISE
Output rise time (2)
(2)
500
1.9
ILOAD =1.4 A, resistive load
40
ILOAD =1.4 A, resistive load
500
tD(off)EN
Enable to out turn OFF delay time
tD(off)IN
Input to out turn OFF delay time
ILOAD =1.4 A, resistive load
500
Output fall time (2)
ILOAD =1.4 A, resistive load
40
tFALL
800
ns
µs
250
ns
800
1000
ns
800
1000
ns
250
ns
7/28
Electrical characteristics
Table 5.
L6226Q
Electrical characteristcs TA = 25 °C, Vs = 48 V, unless otherwise specified (continued)
Symbol
Parameter
tdt
Dead time protection
fCP
Charge pump frequency
Test condition
Min
Typ
0.5
1
Max
Unit
µs
-25 °C < TJ < 125 °C
0.6
1
MHz
Input supply over current detection
threshold
-25 °C<TJ<125 °C;RCL=39 kΩ
-25 °C<TJ<125 °C;RCL= 5 kΩ
-25 °C<TJ<125 °C;RCL= GND
0.29
2.21
2.8
Open drain ON resistance
I = 4 mA
40
I = 4 mA; CEN < 100 pF
200
ns
I = 4 mA; CEN < 100 pF
100
ns
Over current detection
Is over
ROPDR
tOCD(ON)
tOCD(OFF)
(3)
OCD turn-on delay time
OCD turn-off delay time
(3)
1. Tested at 25 °C in a restricted range and guaranteed by characterization.
2. See Figure 3.
3. See Figure 4.
8/28
A
A
A
60
Ω
L6226Q
Circuit description
4
Circuit description
4.1
Power stages and charge pump
The L6226Q integrates two independent power MOS full bridges. Each power MOS has an
RDS(on) = 0.73 Ω (typical value @ 25 °C), with intrinsic fast freewheeling diode. Cross
conduction protection is achieved using a dead time (td = 1 µs typical) between the switch
off and switch on of two power MOS in one leg of a bridge.
Using N-channel power MOS for the upper transistors in the bridge requires a gate drive
voltage above the power supply voltage. The bootstrapped (VBOOT) supply is obtained
through an internal oscillator and few external components to realize a charge pump circuit
as shown in Figure 3. The oscillator output (VCP) is a square wave at 600 kHz (typical) with
10 V amplitude. Recommended values/part numbers for the charge pump circuit are shown
in Table 6.
Table 6.
Charge pump external components values
Component
Value
CBOOT
220 nF
CP
10 nF
D1
1N4148
D2
1N4148
Figure 3.
Charge pump circuit
VS
D1
CBOOT
D2
CP
VCP
VBOOT
VSA
VSB
D01IN1328
9/28
Circuit description
4.2
L6226Q
Logic inputs
Pins IN1A, IN2A, IN1B, IN2B, ENA and ENB are TTL/CMOS and microcontroller compatible
logic inputs. The internal structure is shown in Figure 4. Typical value for turn-on and turn-off
thresholds are respectively Vthon = 1.8 V and Vthoff = 1.3 V.
Pins ENA and ENB are commonly used to implement overcurrent and thermal protection by
connecting them respectively to the outputs OCDA and OCDB, which are open-drain
outputs. If that type of connection is chosen, some care needs to be taken in driving these
pins. Two configurations are shown in Figure 5 and Figure 6. If driven by an open drain
(collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in
Figure 5. If the driver is a standard push-pull structure the resistor REN and the capacitor
CEN are connected as shown in Figure 6. The resistor REN should be chosen in the range
from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN are respectively 100 kΩ and
5.6 nF. More information on selecting the values is found in the overcurrent protection
section.
Figure 4.
Logic inputs internal structure
5V
ESD
PROTECTION
D01IN1329
10/28
Figure 5.
ENA and ENB pins open collector driving
Figure 6.
ENA and ENB pins push-pull driving
L6226Q
4.3
Circuit description
Truth table
Table 7.
Truth table
Inputs
Outputs
EN
IN1
IN2
OUT1
OUT2
L
X (1)
X
High Z (2)
High Z
H
L
L
GND
GND
H
H
L
Vs
GND
H
L
H
GND
Vs
H
H
H
Vs
Vs
1. X = Don't care
2. High Z = High impedance output
4.4
Non-dissipative overcurrent detection and protection
An overcurrent detection circuit (OCD) is integrated. This circuit can be used to provides
protection against a short circuit to ground or between two phases of the bridge as well as a
roughly regulation of the load current. With this internal over current detection, the external
current sense resistor normally used and its associated power dissipation are eliminated.
Figure 7 shows a simplified schematic of the overcurrent detection circuit for the bridge A.
bridge B is provided of an analogous circuit.
To implement the over current detection, a sensing element that delivers a small but precise
fraction of the output current is implemented with each high side power MOS. Since this
current is a small fraction of the output current there is very little additional power
dissipation. This current is compared with an internal reference current IREF. When the
output current reaches the detection threshold Isover the OCD comparator signals a fault
condition. When a fault condition is detected, an internal open drain MOS with a pull down
capability of 4 mA connected to OCD pin is turned on. Figure 8 shows the OCD operation.
This signal can be used to regulate the output current simply by connecting the OCD pin to
EN pin and adding an external R-C as shown in Figure 7. The off time before recovering
normal operation can be easily programmed by means of the accurate thresholds of the
logic inputs.
IREF and, therefore, the output current detection threshold are selectable by RCL value,
following the equations:
●
Isover = 2.8 A ± 30 % at -25 °C < TJ < 125 °C if RCL = 0 Ω
(PROGCL connected to GND)
●
Isover =
11050
---------------R CL
±10 % at -25 °C < TJ < 125 °C if 5 kΩ < RCL < 40 kΩ
Figure 9 shows the output current protection threshold versus RCL value in the range 5 kΩ
to 40 kΩ.
The disable time tDISABLE before recovering normal operation can be easily programmed by
means of the accurate thresholds of the logic inputs. It is affected whether by CEN and REN
11/28
Circuit description
L6226Q
values and its magnitude is reported in Figure 10. The delay time tDELAY before turning off
the bridge when an overcurrent has been detected depends only by CEN value. Its
magnitude is reported in Figure 11.
CEN is also used for providing immunity to pin EN against fast transient noises. Therefore
the value of CEN should be chosen as big as possible according to the maximum tolerable
Delay Time and the REN value should be chosen according to the desired Disable Time.
The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended
values for REN and CEN are respectively 100 kΩ and 5.6 nF that allow obtaining 200 µs
disable time.
Figure 7.
12/28
Overcurrent protection simplified schematic
L6226Q
Circuit description
Figure 8.
Overcurrent protection waveforms
IOUT
ISOVER
VEN
VDD
Vth(ON)
Vth(OFF)
VEN(LOW)
ON
OCD
OFF
ON
tDELAY
BRIDGE
tDISABLE
OFF
tOCD(ON)
tEN(FALL)
tOCD(OFF)
tEN(RISE)
tD(ON)EN
tD(OFF)EN
D02IN1400
Output current protection threshold versus RCL value
Figure 9.
2 .5
2 .2 5
2
1 .7 5
1 .5
1 .2 5
I SOVER
[A ]
1
0 .7 5
0 .5
0 .2 5
0
5k
10k
15k
20k
25k
R C L [Ω ]
30k
35k
40k
13/28
Circuit description
L6226Q
Figure 10. tDISABLE versus CEN and REN (VDD = 5 V)
1 .10
R EN = 220 k Ω
3
R EN = 100 k Ω
R EN = 47 k Ω
R EN = 33 k Ω
R EN = 10 k Ω
tDISABLE [µs]
100
10
1
1
10
100
C EN [nF]
Figure 11. tDELAY versus CEN (VDD = 5 V)
tdelay [µs]
10
1
0.1
14/28
1
10
Cen [nF]
100
L6226Q
4.5
Circuit description
Thermal protection
In addition to the ovecurrent detection, the L6226Q integrates a thermal protection for
preventing the device destruction in case of junction over temperature. It works sensing the
die temperature by means of a sensible element integrated in the die. The device switch-off
when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ.
value).
15/28
Application information
5
L6226Q
Application information
A typical application using L6226Q is shown in Figure 12. Typical component values for the
application are shown in Table 8. A high quality ceramic capacitor in the range of 100 to 200
nF should be placed between the power pins (VSA and VSB) and ground near the L6226Q
to improve the high frequency filtering on the power supply and reduce high frequency
transients generated by the switching. The capacitors connected from the ENA/OCDA and
ENB/OCDB nodes to ground set the shut down time for the bridge A and bridge B
respectively when an over current is detected (see overcurrent protection). The two current
sources (SENSEA and SENSEB) should be connected to power ground with a trace length
as short as possible in the layout. To increase noise immunity, unused logic pins are best
connected to 5 V (high logic level) or GND (low logic level) (see pin description). It is
recommended to keep power ground and Signal Ground separated on PCB.
Table 8.
16/28
Component values for typical application
Component
Value
C1
100 µF
C2
100 µF
CBOOT
220 µF
CP
10 µF
CENA
5.6 µF
CENB
5.6 µF
CREF
68 µF
D1
1N4148
D2
1N4148
RCLA
5 kΩ
RCLB
5 kΩ
RENA
100 kΩ
RENB
100 kΩ
L6226Q
Application information
Figure 12. Typical application
Note:
To reduce the IC thermal resistance, therefore improve the dissipation path, the NC pins can
be connected to GND.
17/28
Paralleled operation
6
L6226Q
Paralleled operation
The outputs of the L6226Q can be paralleled to increase the output current capability or
reduce the power dissipation in the device at a given current level. It must be noted,
however, that the internal wire bond connections from the die to the power or sense pins of
the package must carry current in both of the associated half bridges. When the two halves
of one full bridge (for example OUT1A and OUT2A) are connected in parallel, the peak
current rating is not increased since the total current must still flow through one bond wire on
the power supply or sense pin. In addition the over current detection senses the sum of the
current in the upper devices of each bridge (A or B) so connecting the two halves of one
bridge in parallel does not increase the over current detection threshold.
For most applications the recommended configuration is half bridge 1 of bridge A paralleled
with the half bridge 1 of the bridge B, and the same for the half bridges 2 as shown in
Figure 13. The current in the two devices connected in parallel will share very well since the
RDS(on) of the devices on the same die is well matched.
When connected in this configuration the over current detection circuit, which senses the
current in each bridge (A and B), will sense the current in upper devices connected in
parallel independently and the sense circuit with the lowest threshold will trip first. With the
enables connected in parallel, the first detection of an over current in either upper DMOS
device will turn of both bridges. Assuming that the two DMOS devices share the current
equally, the resulting over current detection threshold will be twice the minimum threshold
set by the resistors RCLA or RCLB in Figure 13. It is recommended to use RCLA = RCLB.
In this configuration the resulting bridge has the following characteristics.
18/28
●
Equivalent device: full bridge
●
RDS(on) 0.37 Ω typ. value @ TJ = 25 °C
●
2.8 A max RMS load current
●
5.6 A max OCD threshold
L6226Q
Paralleled operation
Figure 13. Parallel connection for higher current
To operate the device in parallel and maintain a lower over current threshold, half bridge 1
and the half bridge 2 of the bridge A can be connected in parallel and the same done for the
bridge B as shown in Figure 14. In this configuration, the peak current for each half bridge is
still limited by the bond wires for the supply and sense pins so the dissipation in the device
will be reduced, but the peak current rating is not increased.
When connected in this configuration the over current detection circuit, senses the sum of
the current in upper devices connected in parallel. With the enables connected in parallel,
an over current will turn of both bridges. Since the circuit senses the total current in the
upper devices, the over current threshold is equal to the threshold set the resistor RCLA or
RCLB in Figure 14. RCLA sets the threshold when outputs OUT1A and OUT2A are high and
resistor RCLB sets the threshold when outputs OUT1B and OUT2B are high.
It is recommended to use RCLA = RCLB.
In this configuration, the resulting bridge has the following characteristics.
●
Equivalent device: FULL BRIDGE
●
RDS(on) 0.37 Ω typ. value @ TJ = 25 °C
●
1.4 A max RMS load current
●
2.8 A max OCD threshold
19/28
Paralleled operation
L6226Q
Figure 14. Parallel connection with lower overcurrent threshold
It is also possible to parallel the four half bridges to obtain a simple half bridge as shown in
Figure 15. In this configuration the, the over current threshold is equal to twice the minimum
threshold set by the resistors RCLA or RCLB in Figure 15. It is recommended to use
RCLA = RCLB.
The resulting half bridge has the following characteristics.
20/28
●
Equivalent device: half bridge
●
RDS(on) 0.18 Ω typ. value @ TJ = 25 °C
●
2.8 A max RMS load current
●
5.6 A max OCD threshold
L6226Q
Paralleled operation
Figure 15. Paralleling the four half bridges
21/28
Output current capability and IC power dissipation
7
L6226Q
Output current capability and IC power dissipation
In Figure 16 and Figure 17 are shown the approximate relation between the output current
and the IC power dissipation using PWM current control driving two loads, for two different
driving types:
●
One full bridge ON at a time (Figure 16) in which only one load at a time is energized.
●
Two full bridges ON at the same time (Figure 17) in which two loads at the same time
are energized.
For a given output current and driving type the power dissipated by the IC can be easily
evaluated, in order to establish which package should be used and how large must be the
on-board copper dissipating area to guarantee a safe operating junction temperature
(125 °C maximum).
Figure 16. IC power dissipation vs output current with one full bridge ON at a time
ONE FULL BRIDGE ON AT A TIME
10
IA
I OUT
8
IB
6
PD [W]
I OUT
4
Test Conditions:
Supply Voltage = 24V
2
0
0
0.25 0.5 0.75 1
No PW M
fSW = 3 0 kHz (slow decay)
1.25 1.5
I OUT [A]
Figure 17. IC power dissipation vs output current with two full bridges ON at the
same time
TWO FULL BRIDGES ON AT THE SAME TIME
IA
10
8
I OUT
IB
6
I OUT
PD [W ]
4
Test Conditions:
Supply Volt age =24 V
2
0
0
0.25 0.5 0.75 1
I OUT [A ]
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1.25 1.5
No PWM
f SW = 30 kHz (slow decay)
L6226Q
8
Thermal management
Thermal management
In most applications the power dissipation in the IC is the main factor that sets the
maximum current that can be deliver by the device in a safe operating condition. Therefore,
it has to be taken into account very carefully. Besides the available space on the PCB, the
right package should be chosen considering the power dissipation. Heat sinking can be
achieved using copper on the PCB with proper area and thickness. For instance, using a
VFQFPN32L 5x5 package the typical Rth(JA) is about 22 °C/W when mounted on a doublelayer FR4 PCB with a dissipating copper surface of 0.5 cm2 on the top side plus 6 cm2
ground layer connected through 18 via holes (9 below the IC).
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Package mechanical data
9
L6226Q
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
Table 9.
VFQFPN32 5x5x1.0 pitch 0.50
Databook (mm)
Dim.
Min
Typ
Max
A
0.80
0.85
0.95
b
0.18
0.25
0.30
b1
0.165
0.175
0.185
D
4.85
5.00
5.15
D2
3.00
3.10
3.20
D3
1.10
1.20
1.30
E
4.85
5.00
5.15
E2
4.20
4.30
4.40
E3
0.60
0.70
0.80
e
L
ddd
Note:
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0.50
0.30
0.40
0.50
0.08
1
VFQFPN stands for thermally enhanced very thin profile fine pitch quad flat package no
lead. Very thin profile: 0.80 < A = 1.00 mm.
2
Details of terminal 1 are optional but must be located on the top surface of the package by
using either a mold or marked features.
L6226Q
Package mechanical data
Figure 18. Package dimensions
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Order codes
10
Order codes
Table 10.
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L6226Q
Order code
Order code
Package
Packaging
L6226Q
VFQFPN32 5x5x1.0
Tube
L6226Q
11
Revision history
Revision history
Table 11.
Document revision history
Date
Revision
Changes
18-Jan-2008
1
First release
10-Jun-2008
2
Updated: Figure 12 on page 17, Figure 13 on page 19, Figure 14 on
page 20 and Figure 15 on page 21
Added: Note 1 on page 4
27/28
L6226Q
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