STMICROELECTRONICS L8202

L8202
MULTIFUNCTION ANALOG ASIC
1
■
FEATURES
Figure 1. Package
Flexible Motor Driver configuration
– 4 DC Motor drivers (1.5A Peak Current) or
– 2 DC Motor drivers & 1 Dual Full Bridge Stepper Motor driver
■
2 Switching Voltage regulators
■
6 Open Drain Drivers
■
Serial Input Port
■
4 Operational amplifiers
■
Low voltage Supervisor
■
Thermal Protection
2
TQFP64
Table 1. Order Codes
Part Number
Package
L8202
TQFP64 (Exposed Pad Down)
The regulated Voltages are: VCC that can be either 3.3V or +5V and VDD, programmable by a resistor divider network from +3V to +17V
DESCRIPTION
L8202 is a multifunction analog ASIC designed for
MFP Inkjet printer applications.
It is possible to increase the Output Current capability of the VDD regulator by adding an external
discrete Power DMOS.
L8202 integrates 4 full H Bridge drivers, 2 switching Buck type voltage regulators, 4 operational
amplifiers, 6 open drain drivers, Reset Generation
circuitry and over temperature protection circuitry.
An internal regulator is present in the IC in order to
supply several internal blocks. The 5V output voltage is filtered on pin V5 (Typical filter capacitor =
100nF) .
Figure 2. Block Diagram
PWM gen.
L8202
DC motor
DC MTR #1 H
Drive
OP.
Amps
DC MTR #2 H
Drive
LM358
like
DC motor
Phase A H
Drive
VPH regulator
1 Stepper motor or
2 DC
motor
Phase B H
Drive
Vcc regulator
3.3V or 5V
SERIAL
INTERFACE
LED
Drivers
Reset gen.
Sleep mode
Vcc switch
February 2005
Rev. 2
1/15
L8202
Table 2. Pin Description
N°
Pin
1
PH_A+
2
R_Sense_A
3
PH_A-
4
Function
Stepper Motor Driver Output A plus
Phase A Stepper Motor Driver Current Sense Resistor
Stepper Motor Driver Output A minus
No Connection
5
Test
6
VDD_gate
7
VDD_source1
Source pin #1 for VDD internal FET. Used as differential input when external Power
DMOS is used.
8
VDD_source2
Source pin #2 for VDD internal FET. Used as differential input when external Power
DMOS is used.
9
VDD_drain1
Drain pin #1 for VDD internal FET. N/C when an external Power DMOS is used.
10
VDD_drain2
Drain pin #2 for VDD internal FET. N/C when an external Power DMOS is used.
11
Vs(VDD)
VDD regulator Supply voltage.
12
VDD_FB
Feedback for VDD Regulator
13
This pin is used to measure internal Temperature of ASIC.
Gate drive pin for external Power DMOS. N/C when internal FET is used.
No Connection
14
PH_B-
15
R_Sense_B
16
PH_B+
17
Vs(DC4)
DC4 or Stepper PH_B Supply voltage.
18
Vs(Vcc)
Source pin for Vcc Regulator. Internally tied to other Vs.
19
Vcc_out
Output pin for Vcc Regulator
20
ODD 6
Open Drain Driver #6
21
Vcc_Select
22
Vcc_FB
23
DC4_PWM
PWM input for DC motor driver #4
24
DC3_PWM
PWM input for DC motor driver #3
25
DC1_PWM
PWM input for DC motor driver #1
26
DC2_PWM
PWM input for DC motor driver #2
27
Analog_GND
28
Vcc_Switch_Out
29
Vcc_In
Vcc input pin.
30
V5
5V output pin.
31
Phase B Stepper Motor Driver Current Sense Resistor
Stepper Motor Driver Output B plus
This pin is used to select 5V or 3.3V for Vcc
Feedback for Vcc Regulator
Analog Ground.
Vcc switched output pin.
No Connection.
32
Vs(DC1)
33
DC1B
2/15
Stepper Motor Driver Output B minus
DC1 Supply voltage.
Negative output for DC motor driver #1
L8202
Table 2. (continued)
N°
Pin
Function
34
GND(DC1)
35
DC1A
Positive output for DC motor driver #1
36
ODD 5
Open Drain Driver #5.
37
ODD 4
Open Drain Driver #4.
38
ODD 3
Open Drain Driver #3.
39
ODD 2
Open Drain Driver #2.
40
ODD1
Open Drain Driver #1.
41
nCS
42
SCLK
43
SDI
Serial Data In
44
nRESET
nRESET pin.
45
GND(Logic)
Logic Ground
46
DC2A
47
GND(DC2)
48
DC2B
49
Vs(DC2)
DC2 Supply voltage.
50
OA_GND
Ground for Op-Amps
51
OA4-
Inverting Input for Op-Amp #4
52
OA4+
Non-Inverting Input For Op-Amp #4
53
OA4Out
54
OA3-
Inverting Input for Op-Amp #3
55
OA3+
Non-Inverting Input for Op-Amp #3
56
OA3Out
57
OA2-
Inverting Input for Op-Amp #2
58
OA2+
Non-Inverting Input for Op-Amp #2
59
OA2Out
60
OA1-
Inverting Input for Op-Amp #1
61
OA1+
Non-Inverting Input for Op-Amp #1
62
OA1Out
63
OA_Supply
64
Vs(DC3)
DC1 Ground.
Chip Select, active Low
Serial Clock
Positive output for DC motor driver #2
DC2 Ground.
Negative output for DC motor driver #2
Output for Op-Amp #4.
Output for Op-Amp #3
Output for Op-Amp #2.
Output for Op-Amp #1.
Op Amp Supply voltage.
DC3 or Stepper PH_A Supply voltage.
3/15
L8202
Table 3. Absolute Maximum Ratings
Symbol
Parameter
Vs
VOD
Vcc_IN, Vcc_FB
VDD Max
IVDD
VCCOpAmp
VDIFF OpAmp
Vmaxrst*
Value
Unit
Supply voltage, including ripple
44
V
Differential Voltage between Power pins, Supply pins and Ground
44
V
VCC
7
V
VDD Voltage (@IVDD = 0.0A)
17
V
VDD Output current
3
A
Op Amp Supply Voltage
7
V
Op Amp Differential Voltage
7
V
Vcc_in
V
Maximum voltage on nRESET
Tj
Junction Temperature
150
°C
Tstg
Storage Temperature
-55 to 150
°C
Table 4. Recommended Operating Conditions (Tj = 25°C, VS= 32V, unless otherwise specified)
Symbol
Parameter
Test Conditions
Vs
Supply voltage, including ripple
IVs
Vs Standby Current
In the stand by
mode(sleep=1)
Vcc_IN,
Vcc_FB
Vcc voltage
Vcc = 3.3V
Vcc = 5.0V
Ivcc_in
Vcc input current
nReset = 0, Ivcc_switch = 0
Vcc = 3.3V
Vcc = 5.0V
Min.
Typ.
Max.
Unit
24
30
38
V
3
15
mA
3.3
5.0
3.45
5.25
V
2
5
mA
3.15
4.8
Vs (DC2)
OA_GND
OA4-
OA4+
OA4OUT
OA3+
OA3-
OA3OUT
OA2-
OA2+
OA2OUT
OA1-
OA1+
OA1OUT
OA_SUPPLY
Vs (DC3)
Figure 3. Pin Connections
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PH_A+
1
48
DC2B
R_SENSE_A
2
47
GND (DC2)
PH_A-
3
46
DC2A
4
45
GND (LOGIC)
TEXT
5
44
nRESET
VDD_GATE
6
43
SDI
VDD_SOURCE1
7
42
SCLK
VDD_SOURCE2
8
41
nCS
VDD_DRAIN1
9
40
ODD1
VDD_DRAIN2
10
39
ODD2
Vs (VDD)
11
38
ODD3
VDD_FB
12
37
ODD4
13
36
ODD5
PHB-
14
35
DC1A
R_SENSE
15
34
GND (DC1)
PH_B
16
33
DC1B
Vs (DC1)
V5
Vcc_IN
Vcc_SWITCH_OUT
ANALOG_GND
DC2_PWM
DC1_PWM
DC3_PWM
DC4_PWM
VCC_FB
VCC_SELECT.
ODD6
VCC_OUT
Vs (DC4)
4/15
Vs_(VCC)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D04IN1529
L8202
3
SERIAL INTERFACE
L8202 Analog ASIC integrates an SPI interface (write only) for data exchange with the Digital ASIC.
The Input word is 19 bits long.
3 Input Pins are dedicated to the Serial Interface: nCS (Chip Select, active Low), SDI (Serial Data In),
SCLK (Serial Clock). nCS must be pulled low to activate a Serial Input command.
Data present at the SDI pin are shifted into the L8202 on the 19 rising edges of SCLK.
The first bit present at the SDI, after the nCS is pulled low, and shifted into the L8202 at the first SCLK
rising edge is the LSB. ( SDI will remain at the value presented with the last bit of data ). The low to high
transition of nCS, after the 19th Sclk rising edge, loads the data into the internal L8202 ASIC input register.
The serial interface is cleared by nRESET.
Figure 4. SPI Operation
LSB
SDI
0
MSB
1
2
3
4
5
6
7
17
18
nCS
Tdelay sck_cs
Tdelay cs_sck
Table 5. SPI Timing specifications
(Tamb = 25 °C, VS = 32 V, unless otherwise specified)
Symbol
Min.
Typ.
Max.
Unit
Serial clock frequency
6
8
12
MHz
Tckhw
SCLK high width
30
ns
Tcklw
SCLK low width
30
ns
Tdelay_cs-sck
Delay nCS falling to first SCLK rising
10
ns
Tdelay_sck-cs
Delay last SCLK rising edge to nCS rising
10
ns
Tdata_setup
Data valid to SCLK set up time
10
ns
Tdata_hold
Data hold time
10
ns
Tdelay_cs
Delay required from (n-1)CS to nCS
10
ns
Tr_data
SDI rise time
0
20
ns
Tf_data
SDI fall time
0
20
ns
Tr/f_sck
SCLK rise/fall time
0
20
ns
Fck
Parameter
5/15
L8202
Table 6. SPI Bit Definition
BIT #
Symbol
RESET
VALUE
0
STAND_BY
1
A Logic “1” inhibits OpAmps and Motors, and puts the L8202 into a lower power
state.
Chip must power up with Stand By Mode active.
VDD regulators operate independently from Stand By Mode.
1
VDD_EN
0
A logic "1" enables the VDD regulator. Chip must power up with the VDD
regulators inactive.
2
MDC1_D
0
Controls the direction of current flow through the DC motor windings. A high level
causes current to flow from DC1A(source) to DC1B(sink).
3
MDC2_D
0
Controls the direction of current flow through the DC motor windings. A high level
causes current to flow from DC2A(source) to DC2B(sink).
4
VSW_EN
1
A high level causes the 5V switch turn on. Chip must power up with the 5V switch
closed.
5
ODD 1
0
Controls Open Drain Driver. A high level causes Open Drain Driver Turn On.
6
ODD 2
0
Controls Open Drain Driver. A high level causes Open Drain Driver Turn On.
7
ODD 3
0
Controls Open Drain Driver. A high level causes Open Drain Driver Turn On.
8
ODD 4
0
Controls Open Drain Driver. A high level causes Open Drain Driver Turn On.
9
ODD 5
0
Controls Open Drain Driver. A high level causes Open Drain Driver Turn On.
10
ODD 6
0
Controls Open Drain Driver. A high level causes Open Drain Driver Turn On.
11
SEL_MTR
0
Selection of motor type. A high level selects DC motor. A logic 0 level selects
Step motor.
12
I1_PH_B
1
This input and I0_PH_B select the output of three comparators to set the current
level. Current also depends on the sensing resistor and reference voltage.
13
I0_PH_B
1
See I1_PH_B
14
D_PH_B
0
This TTL-compatible logic input sets the direction of current flow through the
load. A high level causs current to flow from OUT A (source) to OUT B(sink). A
Schmitt triger on this input provides good noise immunity and a delay circuit
prevents output stage short circuits during switching.
15
I1_PH_A
1
This input and I0_PH_A select the output of three comparators to set the current
level. Current also depends on the sensing resistor and reference voltage.
16
I0_PH_A
1
See I1_PH_A
17
D_PH_A
0
See D_PH_B
18
Test
0
A high level forces the device to enter in Test Mode.
6/15
DESCRIPTION
L8202
4
DC/DC CONVERTERS SPECIFICATION
L8202 contains 2 DC/DC converters.
VCC converter is programmable by the Vcc_Select pin for an Output Voltage rated at 3.3V or 5V (1.2A
max.). VDD voltage is programmable by a resistor divider network to voltages from +3V to +17V.
The switching frequency of the two converters is 200KHz.
The Vcc and the VDD regulators are protected by thermal protection circuit with thermal hysteresys (Output Voltages are switched off during thermal protection event). The output voltages, Vcc and VDD are
short circuit protected.
4.1 VCC Regulator
Table 7. Electrical Characteristcs (Tj = 25 °C, VS = 32 V, unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VCC_o
Vcc Regulator Output Voltage.
Vcc value selected by Vcc_select
pin.
Vcc = 3.3V From 10mA to 1.2A
Vcc = 5V From 10mA to 1.2A
3.23
4.90
3.3
5
3.37
5.20
V
V
4.8
A
IOC_detect
Over current Threshold level
IOC_BK time
Blankig time for overcurrent
detect
IVcc_load
fck
1.6
400
Vcc external load current
Operating frequency
10
Tamb = 10 to 55°C
175
200
ns
1200
mA
225
KHz
Max.
Unit
17
V
+2%
V
3.0
A
4.2 VDD Regulator
Table 8. Electrical Characteristcs (Tj = 25 °C, VS = 32 V, unless otherwise specified)
Symbol
VDD_O
Vref
Parameter
VDD Regulator Output Voltage
range
Test Conditions
24V≤ Vs ≤ 38V
Min.
Typ.
3
Internal reference voltage for error
amp
-2%
IVDD_load
Vcc external load current
0.01
IOC_det_SU
Over current detect level
During start up
2.0
3.2
A
IOC_det_SC
Over current detect level
During short circuit
4.0
5.5
A
VSen_VDD
Current sense voltage
Using external Power DMOS,
this is a voltage of Ext. resistor
between Vs and VDD_source
-20%
250
IOC_BK time
Blankig time for overcurrent detect
VGS_C
TFull_LOAD
IST_UP
fck
Vs-15
Vs high, ASIC receives
command to turn on VDD Reg
Tamb = 10 to 55°C
75
175
mV
ns
Vs-10
V
ms
Maximum load current appliable
during start up.
Operating Frequency
+20%
300
Gate to source clamp voltage
Transient time after which max load
can be applied to VDD regulator
1.24
200
1.2
A
225
KHz
7/15
L8202
5
DC MOTOR DRIVERS OPERATIONS
L8202 provides PWM bi-directional drive for two DC motors.
The PWM modulation is provided by the MDx_PWM input, and the current direction into the motor by the
MDCx_D bit in the serial input port.
The driver is protected versus overloads on the output lines to a max. current of 2 Amps peak.
The current protection circuit is implemented only on the High Side Drivers, so current protection is provided to motor currents only, but not to shorts between Motor Outputs to GND or Vs.
A blanking period following a current turn-on event is included to prevent false current protection.
The H Bridges are protected versus cross-conduction.
Thermal protection with hysteresys is provided to the Motor Drivers.
During thermal protection event the Bridge Outputs are forced into a high impedance status.
If nReset is low the motor drive outputs are forced in high impedance
Table 9. Absolute Maximum Ratings (Tj = 25°C, VS = 32V, unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Pulsed Output Current
DC Motor Overcurrent
Threshold
IDC_O
Typ.
Max.
Unit
1.5
A
A
Max.
Unit
2
Table 10. Electrical Characteristcs (Tj = 25 °C, VS = 32 V, unless otherwise specified)
Symbol
RDS(ON)
fPWM
Ton,Toff min.
DCPWM
Parameter
Test Conditions
ON Resistance
Min.
ILOAD = -0.75A (from output to
GND) or ILOAD = +0.75A (from
Vs to output) @Tamb =25°
Typ.
0.31
W
0.32
PWM frequency
10
Minimum Ton and Toff time
500
PWM Duty Cycle range
30
KHz
ns
1
99
%
Table 11. Truth Table
Internal
Thermal Bit
L
H
8/15
Inputs
Outputs
MDCx_D
DCx_PWM
DCxA
DCxB
L
L
H
H
L
H
L
H
H
L
H
H
H
H
H
L
X
X
All transistors turned off All transistors turned off
L8202
6
STEPPER MOTOR DRIVER OPERATIONS
Two H Bridges are provided to implement current control through the two widings of a Bipolar Stepper Motor.
The phase and current level information are programmed over the serial input port (see Serial Interface
Bits definition section).
Four current levels (0%,33%,66%,100%) are programmable through the status of IN0 and IN1 bits in the
Input Serial Port.
This drive enters the fast current decay mode when both the I0_PH_X and I1_PH_X inputs set to the high
logic level (current is recirculated from GND to Vs supply).
A blanking period following a current turn-on event is included to prevent false current protection.
The H Bridges are protected versus cross-conduction.
Thermal protection with hysteresys is provided to the Motor Drivers.
During thermal protection event the Bridge Outputs are forced into a high impedance status.
Table 12. Absolute Maximum Ratings (Tj = 25°C, VS = 32V, unless otherwise specified)
Symbol
Parameter
ISTEP_O
Pulsed Output Current
Test Conditions
Min.
Typ.
Max.
Unit
1.5
A
Table 13. Electrical Characteristcs (Tj = 25°C, VS = 32V, unless otherwise specified)
Symbol
RDS(ON)
Parameter
ON Resistance
Test Conditions
Min.
Typ.
ILOAD = -0.6 A (from output to
GND) or ILOAD = +0.6 A (from
Vs to output) @Tamb = 25°C
0.55
Max.
Unit
W
0.4
VComp_HT
Comparator High Threshold
Voltage
I0_PH_x = 0
I1_PH_x = 0
500
mV
VComp_MT
Comparator Medium Threshold
Voltage
I0_PH_x = 1
I1_PH_x = 0
333
mV
VComp_LT
Comparator Low Threshold
Voltage
I0_PH_x = 0
I1_PH_x = 1
167
mV
ILEAK_VOFF
VoOFF Output Leakage
Current for Stepper Motor
Driver Outputs
VoOFF = 5V
I0_PH_x = 1
I1_PH_x = 1
0.5
mA
Toff
Tj
Tj(enable_
hysterisys)
Off time
20
Thermal shutdown
140
Stepper Motor driver thermal
enable junction temperature
hysterisys
30
40
µs
°C
20
°C
Table 14. Truth Table
I0_PH_x
I1_PH_x
ISTEP_O_PH_x
L
L
100%
H
L
66 %
L
H
33 %
H
H
0%
Notes: 1. The 100% current is fixed by the sense resistor, and the Maximum Threshold of the Voltage Comparator
9/15
L8202
7
OPERATIONAL AMPLIFLIERS
L8202 contains four general purpose Op-Amps,with their own Supply rail and Gnd rail. OpAmps are inhibited when L8202 is in sleep mode
Table 15. Absolute Maximum Ratings (Tj = 25°C, VS = 32V, unless otherwise specified)
Symbol
Parameter
Vcc
Supply Voltage
Vid
Differential Input Voltage
Test Conditions
Min.
Typ.
3.2
Max.
Unit
5.2
V
5.2
V
Max.
Unit
9
mV
Table 16. Electrical Characteristcs (Tj = 25°C, VS = 32V, unless otherwise specified)
Symbol
Parameter
Test Conditions
Typ.
Vio
Input Offset Voltage
Avd
Large Signal Voltage Gain
Vicm
Input Common Mode Voltage
Range
Full range
0
CMR
Common Mode Rejection
Ratio
DC
70
Isource
Output Current Source
Vcc = 5/3.3V
Vo = Vcc-2V
10
20
mA
Isink
Output Sink Current
Vcc = 5/3.3V, Vo = 2V
10
20
mA
VOH
High Level Output Voltage
Sourcing 2mA, Vcc = 5.2V,
full range
VOL
Low Level Output Voltage
Sinking 2mA, Vcc=5.2V, full
range
SR
Slew Rate
Full Range
Cload = 100pF
GBP
Vinp = Vcc-1.5
Min.
-9
130
V/mV
Vcc1.5
V
dB
Vcc0.5
V
0.5
0.3
V
V/µs
Gain Bandwidth Product
* Guaranted by design
8
OPEN DRAIN DRIVERS
L8202 contains 6 open Drain Drivers. These drivers are controlled by the Serial Interface by the bit ODD1/
6, each driver is able to sink 30mA from either 3.3V or 5v Supply.
Table 17. Electrical Characteristics (Tj = 25°C, VS = 32V, unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
IODD_H
High State Output Current
ODDx = 0, Vcc = 5.0V or 3.3V
1
µA
VODD_L
Low State Output Voltage
ODDx = 1, Vcc = 5.0V or 3.3V,
Iload = 30mA
300
mV
10/15
L8202
9
VOLTAGE SUPERVISOR
nRESET is an Output/Input signal (active low), that is used both to provide the information about the status
of Vcc and Vs supplies, both to provide a Reset signal to the internal logic when driven "low" from an external source for a period > 30µs.
When nRESET is asserted, Motor Drivers and VDD regulator are forced in the inactive state and the Serial
Input Port is loaded with the "Reset Value".
To avoid false assertion due to glitches, nRESET is released to the "high" state with a delay of 100ms.
Delay period is calculated from the moment Vcc is passing the Vcc threshold.
At power down no delay is present, and nRESET is asserted low by Vcc or Vs falling low respect to their
thresholds
Figure 5.
Vs
A
V TH_VCC
Vcc
nRESET
Td
Tdeglitch
Td
Note A. L8202 ignores very brief transients.
This should be less than Tdeglitch
Table 18. Electrical Characteristics (Tj = 25°C, VS = 32V, unless otherwise specified)
Symbol
Vout_high
Vout_low
Rp_up
VTH_VCC
Parameter
High-level output voltage at
nRESET
Low-level output voltage at
nRESET
Internal pull-up resistance
between Vcc_in and nRESET
Threshold voltage at Vcc &
Vcc_in
VTH_Vs-
Low threshold voltage at Vs
VTH_Vs+
High threshold voltage at Vs
VHYST_Vs
Hysteresis Voltage
Test Conditions
Ioh = -0.1 mA
Min.
Vcc0.5V
Typ.
Max.
Unit
V
0.2
V
5
KΩ
2.87
2.82
4.35
2.87
18.0
3.07
3.10
4.65
3.10
20.0
V
V
19.25
21.25
V
Vcc< VTH_VCC
Vs=38V
2
Vcc = 3.3V
Vcc_in = 3.3V
Vcc = 5.0V
Vcc_in = 3.3V
Vcc > VTH_VCC
Vs decreasing
Vcc > VTH_VCC
Vs increasing
( VTH_Vs+ ) -( VTH_Vs-)
3
1.2
V
Table 19. Switching Characteristics (Tj = 25 °C, VS = 32V, unless otherwise specified)
Symbol
Td
Parameter
nRESET delay
Test Conditions
Vcc >= VTH_VCC
Tdeglitch
Vcc out of tolerance
persistence time
nRESET deasserted
Vcc < VTH_VCC
Rise Time at nRESET
Fall Time at nRESET
10 to 90%, 50pF Load
90 to 10%, 50pF Load
Trise
Tfall
Min.
70
Typ.
100
Max.
130
Unit
ms
10
20
30
µs
750
50
ns
ns
11/15
L8202
10 APPLICATION CIRCUIT
Figure 6.
V_bulk
U1
C2
Vcc
63
62
61
60
59
58
57
56
55
54
53
52
51
50
L1
VPH
C3
150uH 3A rms
1
R1
C4
2200uF
+
C5
D1
V_bulk
11
7
8
6
9
10
12
2
R2
L8202
+
C1
V_bulk
Vcc
18
19
21
22
OpAmp_Supply
OA1Out
OA1+
OA1OA2Out
OA2+
OA2OA3Out
OA3+
OA3OA4Out
OA4+
OA4OpAmp_GND
DC MTR #1 H
Drive
V_bulk(DC1)
DC1_PWM
DC1A
DC1B
GND(DC1)
DC MTR #2 H
Drive
V_bulk(DC2)
DC2_PWM
DC2A
DC2B
GND(DC2)
Phase A H
Drive
V_bulk(DC3)
DC3_PWM
PH_A+
PH_AR_Sense_A
Phase B H
Drive
V_bulk(DC4)
DC4_PWM
PH_B+
PH_BR_sense_B
OP.
Amps
V_bulk(VPH)
VPH_source1
VPH_source2
VPH_gate
VPH_drain1
VPH_drain2
VPH_FB
VPH regulator
3A DC Load
Vbulk(Vcc)
Vcc_drain
Vcc_select
Vcc_FB
Vcc regulator
3.3V or 5V
SCLK
SDATA
nCS
SERIAL
INTERFACE
LED1
LED2
LED3
LED4
LED5
LED6
L4
Vcc
SCLK
SDATA
nCS
1
220uH 1.2A rms, 4.8A sat
42
43
41
C6
1000uF
V_bulk
PWM2
64
24
1
3
2
V_bulk
DC motor
Stepper motor
V_bulk
17
23
16
14
15
40
39
38
37
36
20
R3
0.62 ohm
R4
0.62 ohm
V5
Test
5
Vcc_Switch_Out
28
Vcc_In
nRESET
44
29
Analog_GND
PAD
65
GND(logic)
45
27
SCLK
SDATA
nCS
PWM1
PWM2
1
2
3
4
5
49
26
46
48
47
DC motor
Reset
D2
2
From microcontroller
V_bulk
PWM1
30
+
C7
LED
Drivers
32
25
35
33
34
R5
1K
C8
100nF
Figure 7.
V_bulk
U1
C1
+
Vcc
L1
63
62
61
60
59
58
57
56
55
54
53
52
51
50
R1
VPH
C3
1
R2
+
C5
C4
L8202
C2
D1
V_bulk
11
7
8
6
9
10
12
2
R3
V_bulk
Vcc
18
19
21
22
OpAmp_Supply
OA1Out
OA1+
OA1OA2Out
OA2+
OA2OA3Out
OA3+
OA3OA4Out
OA4+
OA4OpAmp_GND
V_bulk(VPH)
VPH_source1
VPH_source2
VPH_gate
VPH_drain1
VPH_drain2
VPH_FB
DC MTR #1 H
Drive
V_bulk(DC1)
DC1_PWM
DC1A
DC1B
GND(DC1)
DC MTR #2 H
Drive
V_bulk(DC2)
DC2_PWM
DC2A
DC2B
GND(DC2)
Phase A H
Drive
V_bulk(DC3)
DC3_PWM
PH_A+
PH_AR_Sense_A
Phase B H
Drive
V_bulk(DC4)
DC4_PWM
PH_B+
PH_BR_sense_B
OP.
Amps
VPH regulator
3A DC Load
Vbulk(Vcc)
Vcc_drain
Vcc_select
Vcc_FB
Vcc regulator
3.3V or 5V
SCLK
SDATA
nCS
42
43
41
SCLK
SDATA
nCS
SERIAL
INTERFACE
LED
Drivers
1
220uH 1.2A rms, 4.8A sat
12/15
1
2
3
4
5
6
7
SCLK
SDATA
nCS
PWM1
PWM2
PWM3
PWM4
R4
1K
V5
30
5
Vcc_In
29
nRESET
44
Analog_GND
PAD
65
27
45
GND(logic)
2
From microcontroller
Test
Reset
D2
Vcc_Switch_Out
+
28
C7
C6
1000uF
V_bulk
PWM1
49
26
46
48
47
V_bulk
PWM2
64
24
1
3
2
V_bulk
PWM3
17
23
16
14
15
DC motor
DC motor
DC motor
V_bulk
PWM4
DC motor
LED1
LED2
LED3
LED4
LED5
LED6
L2
Vcc
32
25
35
33
34
C8
100nF
40
39
38
37
36
20
L8202
Figure 8. TQFP64 Mechanical Data & Package Dimensions
mm
inch
DIM.
MIN.
TYP.
A
MAX.
MIN.
TYP.
1.20
A1
0.05
A2
0.95
b
0.17
c
0.09
D
11.80
D1
9.80
D2
2.00
D3
MAX.
0.0472
0.15
0.002
1.00
1.05
0.0374 0.0393 0.0413
0.22
0.27
0.0066 0.0086 0.0086
0.20
0.0035
12.00
12.20
0.464
0.472
0.480
10.00
10.20
0.386
0.394
0.401
0.006
0.0078
0.787
7.50
0.295
E
11.80
12.00
12.20
0.464
0.472
0.480
E1
9.80
10.00
10.20
0.386
0.394
0.401
E2
2.00
0.787
E3
7.50
0.295
e
0.50
0.0197
L
0.45
L1
k
ccc
0.60
0.75
0.0177 0.0236 0.0295
1.00
0˚
OUTLINE AND
MECHANICAL DATA
3.5˚
0.0393
7˚
0.080
0˚
3.5˚
7˚
TQFP64 (10x10x1.0mm)
Exposed Pad Down
0.0031
7278840 B
13/15
L8202
Table 20. Revision History
Date
Revision
January 2005
1
First Issue
February 2005
2
Changed the maturity from Preliminary Data to Final Datasheet.
14/15
Description of Changes
L8202
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