STMICROELECTRONICS L9929

L9929
SPI CONTROLLED H-BRIDGE
PRELIMINARY DATA
1
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Features
Figure 1. Package
OPERATING SUPPLY VOLTAGE 5V TO 28V
TYPICAL RDSon = 150 mΩ FOR EACH
OUTPUT TRANSISTOR (AT 25°C)
CONTINOUS DC LOAD CURRENT 5A
(Tcase < 100 °C)
OUTPUT CURRENT LIMITATION AT TYP.
8.6A
SHORT CIRCUIT SHUT DOWN FOR OUTPUT
CURRENTS OVER TYP. 10.6A
LOGIC- INPUTS TTL/CMOS-COMPATIBLE
OPERATING-FREQUENCY UP TO 30 kHz
OVER TEMPERATURE PROTECTION
SHORT CIRCUIT PROTECTION
UNDERVOLTAGE DISABLE FUNCTION
DIAGNOSTIC BY SPI OR STATUS-FLAG
(CONFIGURABLE)
ENABLE AND DISABLE INPUT
SO20 POWER PACKAGE
Description
The L9929 is an SPI controlled H-Bridge, designed for the control of DC and stepper motors in
safety critical applications and under extreme environmental conditions.
PowerSO20
PowerSSO24
Table 1. Order Codes
Part Number
Package
L9929
PowerSO20
L9929XP
PowerSSO24
The H-Bridge is protected against over temperature and short circuits and has an under voltage
lockout for all the supply voltages "VS" (Main DC
power supply). All malfunctions cause the output
stages to go tristate.
The H-Bridge contains integrated free-wheel diodes. In case of free-wheeling condition, the low
side transistor is switched on in parallel of its diode
to reduce the current injected into the substrate.
Switching in parallel is only allowed, if the voltage
level of the according output-stage is below the
ground-level. In this case it must be ensured, that
the upper transistor is switched off.
Figure 2. Block Diagram
VS
UNDERVOLTAGE
VS
INTERNAL 5V
SUPPLY
IN1
IN2
GATE CONTROL
1
OVERCURRENT
HIGH-SIDE
OUT1
DI
GATE CONTROL
2
EN
LOGIC
OUT2
DMS
SF/SCK
OVER
TEMPERATURE
OVERCURRENT
LOW-SIDE
SS
SI
SO
MAXIMUM
CURRENT
LIMITATION
GND
D01AT470A
May 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Rev. 2
1/23
L9929
Table 2. Pin Function PowerS020
N°
NAME
Description
1
GND
2
SCK/SF
3
IN1
Input 1
4
VS
Supply voltage
5
VS
Supply voltage
6
OU1
Output 1
7
OU1
Output 1
8
SO
serial out
9
SI
serial in
10
GND
Ground
11
GND
Ground
12
DMS
Diagnostic-Mode selection (+ Supply Voltage for SPI-Interface)
13
EN
14
OU2
Output 2
15
OU2
Output 2
16
VS
Supply voltage
17
SS
Slave select
18
DI
Disable
19
IN2
Input 2
20
GND
Ground
Ground
SPI-Clock/Status-flag
Enable
Figure 3. Pin Connection (Top view)
GND
1
20
GND
SCK
2
19
IN2
IN1
3
18
DI
VS
4
17
SS
VS
5
16
VS
OU1
6
15
OU2
OU1
7
14
OU2
SO
8
13
EN
SI
9
12
DMS
10
11
GND
GND
D01AT471
2/23
L9929
Table 3. Pin Function PowerSS024
N°
NAME
1
GND
2
SCK/SF
Description
Ground
SPI-Clock
3
IN1
Input 1
4
N.C.
Not Connected
5
VS
Supply voltage
6
VS
Supply voltage
7
OUT1
Output 1
8
OUT1
Output 1
9
SO
Serial Out
10
SI
Serial In
11
GND
Ground
12
GND
Ground
13
GND
Ground
14
GND
Ground
15
DMS
Diagnostic-Mode selection (+ Supply Voltage for SPI-Interface)
16
EN
17
OUT2
Output 2
Enable
18
OUT2
Output 2
19
VS
Supply voltage
20
SS
Slave select
21
DI
Disable
22
IN2
Input 2
23
N.C.
Not Connected
24
GND
Ground
Figure 4. Pin Connection (Top view)
GND
1
24
GND
SCK
2
23
NC
INPUT 1
3
22
INPUT 2
N.C.
4
21
DISABLE
VS
5
20
SS
VS
6
19
VS
OUT 1
7
18
OUT 2
OUT 1
8
17
OUT 2
SO
9
16
ENABLE
SI
10
15
DMS
GND
11
14
GND
GND
12
13
GND
D05AT527
3/23
L9929
Table 4. Absolute Maximum Ratings
The integrated circuit must not be destroyed by use at the limit values.
Each limit value can be used, as long as no other limit is violated.
Voltage reference point:
All values are, if not otherwise stated, relative to ground.
Direction of current flow:
Current flow into a pin is positive.
Rise-, fall- and delaytimes:
If not otherwise stated, all rise times are between 10% and 90%, fall times
between 90% and 10% and delay times at 50% of the relevant steps.
Symbol
VS
Parameter
Supply voltage
Max.
Unit
static destruction proof
Test Condition
Min.
-1
Typ.
40
V
dynamic destruction proof t <0.5s
(single pulse, Tj < 85°C)
-2
40
V
VLI
Logic inputs
IN1, IN2, DI, EN, SS, SI, SCK,DMS
-0.5
7
V
VLO
Logic outputs SF, SO
-0.5
7
V
Max.
Unit
-40
+150
+175
°C
°C
Table 5. Thermal Data
Symbol
Tj
Parameter
Test Condition
Junction temperature
Min.
Typ.
dynamic t < 1 s
Tstg
Storage temperature
-55
+125
°C
Tamb
Ambient temperature
-40
+125
°C
3
°C/W
Rth j-case Thermal resistance junction to
case (*)
Tj_sd
Thermal Shutdown Junction
Temperature Threshold
160
175
190
°C
Tj_reg
Start of Temperature dependent
Current Regulation
150
165
180
°C
Min.
Typ.
Max.
Unit
(*) Guaranteed by design and package characterization.
Table 6. Electrical Characteristcs
( Tj = -40 to +150°C; VS = 5 to 28V)
Symbol
Parameter
Test Condition
POWER SUPPLY
VS
Supply Voltage
Static Condition
4.5
28
V
40
V
Switch OFF voltage
4.4
V
Switch ON voltage
4.7
Dynamic Condition (t < 500ms)
Undervoltage Shutdown
(at least down to 2.5V) (*)
Hysteresis
VDMS
IS
200
SPI Undervoltage Shutdown
Device used in SPI mode
Supply current
f = 0 kHz, IO = 0 A
f = 20kHz, IO = 0 A
2.5
2.8
V
mV
3.1
V
13
30
mA
mA
(*) For supply voltages down to 2.5V the output stages are in tristate condition and the status flag is set to low. Below 2.5V the device
operates in undefined condition
4/23
L9929
Table 6. Electrical Characteristcs (continued)
( Tj = -40 to +150°C; VS = 5 to 28V)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Logic inputs
VIH
Logic Input Voltage High
IN1, IN2, DI, EN
VIL
Logic Input Voltage Low
IN1, IN2, DI, EN
VH
Logic Input Voltage Hysteresis
IN1, IN2, DI, EN
2.14
0.1
Logic Input Current
IN1, IN2, DI
VI ≤ 1V
IEN
Logic Input Current EN
VIEN ≥ 1V
tdt
Detection Time EN, DI
II
V
-200
0.86
V
0.6
V
µA
-125
100
µA
3
4
µs
150
250
mΩ
Power Outputs (OUT1, OUT2)
RS
|IOU|max
Switch on Resistance LS
ROUT-Vs, VS > 5 V
Switch on Resistance HS
ROUT-GND, VS > 5 V
Switch-off Current (*)
-40 °C < Tj < 165 °C
Tj < 175 °C
150
250
mΩ
7.8
8.6
2.5
10.5(tbd)
A
A
ta
Switch-off time
12
17
22
µs
tb
Blanking time
8
11.5
15
µs
1.7
Tracking
1.3
1.5
|IOUK|
ta/tb
Short circuit detection current (*)
8.9
10.6
-
A
∆|IOUK|
Short Circuit Current Trecking (*)
1.3
2.0
-
A
200
µs
1
mA
t
Reactivation time after internal
shut down
Overcurrent- or overtemperature
shut down to reactivation of the
output stage
IL
Leakage Current
Output stage switched off
VFD
Free-wheel diode forward voltage
IO = 3A, VS = 0V
2
V
ISF
Output„high“ (SF not set)
VSF = 5V
20
µA
ISF
Output„low“ (SF set)
VSF = 0.5V
350
µA
VSF = 0.8V
400
µA
VSF = 1V
400
µA
Timing
f
Maximum PWM Frequency
min. operating time 10µs
Device can not be controlled with
higher frequency (specify in max
ratings?)
2
30
kHz
fS
Switching Frequency during
current limitation
f = 1/(ta+tb)
20
50
kHz
tdon
Output ON-delay
IN1 --> OUT1 or IN2 --> OUT2
3
7.5
µs
tdoff
Output OFF-delay
3
5
µs
1
5
µs
1
3
µs
3
7
µs
1
ms
6
µs
tr
Output rise time
tf
Outout fall time
OUT1H--> OUT1L, OUT2H--> OUT2L,
IOUT = 3 A
OUT1L--> OUT1H, OUT2L--> OUT2H
tddis
Disable Delay Time
DI --> OUTn, En --> OUTn
tdp
Power on Delay Time
VS = on --> output stage active
terr
Delay time for fault detection
1
(*) In case of SC OUTx to gnd resp. to VS the SC switch off current is always higher than the start value of current regulation (∆|IOUK| = |IOUK|
- |IOUmax|
5/23
L9929
Figure 5. Output delay time
INn
50%
50%
tdon
tdoff
90%
OUTn
10%
D01AT472
Figure 6. Disable delay time
DIn
50%
tddis
OUTn
Z
10%
D01AT473
Figure 7. Output switching time
90%
90%
OUTn
10%
tr
tf
D01AT474
Figure 8. Current values to be inserted after characterization
LOAD
CURRENT
Reaching Switch-off
current, limitation phase
is started by triggering tb
OVERCURRENT
> typ.10.6 A
typ. 8.6A
A
CURRENT LIMITATION
PHASE
CONTROL
SIGNAL
STATUS
FLAG
OVERCURRENT
DETECTION
DETAIL A
ta
typ. 8.6A
tb
t a = SWITCH_OFF TIME IN CURRENT LIMITATION
t b = CURRENT LIMITATION BLANKING TIME
6/23
tb
L9929
Figure 9.
Temperature-depending current-limitation
Maximum rating for junction temperature
Overtemperature switch-off
Switch-off current in case of current limitation
For typical 165°C < Tj < 175°C the maximum current decreases
for < 1s 175°C
> typ. 175°C
typ. 8.6A Tj < typ. 165°C
Imax
Tolerance range of
temperature dependent
current reduction
typ. 8.6A
Range of
Overtemperature
switch-off
typ. 2.5A
165°C
175°C
Tj
Table 5. Electrical Characteristics (continued)
Spi Interface
The timing of L9929 is defined as follows:
- The change at output (SO) is forced by the rising edge of the SCK signal.
- The input signal (SI) is taken over on the falling edge of the SCK signal.
- SS = active without any clocks at SCK is not allowed
- The data received during a writing access is taken over into the internal registers on the rising edge of the SS
signal, if exactly 16 SPI clocks have been counted during SS = active.
Figure 10.
10
9
SS
11
2
3
1
SCK
8
12
4
SO
tristate
5
SI
Bit (n-3)
7
Bit (n-4)...1
Bit 0; LSB
6
MSB IN Bit (n-2) Bit (n-3)
Bit (n-4)...1 LSB IN
n = 16
7/23
L9929
Table 5. Electrical Characteristcs
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
1
V
Input SCK (SPI clock input)
VSCKL
Low Level
VSCKH
High Level
2
∆VSCK
Hysteresis
0.1
CSCK
Input Capacity
-ISCK
Input Current
Pull up current source connected
to VS
V
0.4
20
V
10
pF
50
µA
1
V
Input SS (Slave select signal)
VSSL
Low Level
L9929 is selected
VSSH
High Level
2
∆VSS
Hysteresis
0.1
CSS
Input Capacity
-ISS
Input Current
Pull up current source connected
to VS
V
20
0.4
V
10
pF
50
µA
1
V
Input SI (SPI data input)
VSIL
Low Level
VSIH
High Level
2
∆VSI
Hysteresis
0.1
CSI
Input Capacity
Guaranteed by design
-ISI
Input Current
Pull up current source connected
to VS
V
0.4
20
V
10
pF
50
µA
1
V
Output SO (Tristate output of the L9929 (SPI output); On active reset (DI) output SO is in tristate.)
VSOL
Low Level
ISO = 2mA
VSOH
High Level
ISO = -2mA
CSO
Capacity
Capacity of the pin in tristate
-ISO
Leakage Current
In tristate
2
-10
V
10
pF
10
µA
0.8
V
V
10
mA
Input DMS (Supply-Input for the SPI-Inteface and Selection Pin for SPI- or SF-Mode)
Vi
Ic
Input Voltage
Input Current
SPI-Mode
Status-Flag-Mode
4.5
SPI-Mode
Timing
tcyc
Cycle-Time (1)
200
ns
tlead
Enable Lead Time (2)
100
ns
tlag
Enable Lag Time (3)
150
ns
40
150
ns
ns
tv
Data Valid CL = 40pF (4)
Data Valid CL = 200pF
(referred to L9929)
tsu
Data Setup Time (5)
(referred to master)
50
ns
th
Data Hold Time (6)
20
ns
tdis
Disable Time (7)
(referred to L9929)
8/23
100
ns
L9929
Table 5. Electrical Characteristcs (continued)
Symbol
tdt
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Transfer Delay (8)
(referred to master)
150
ns
tSCKH
Serial clock high time (9)
(referred to master)
50
ns
tSCKL
Access time (10)
(referred to master)
8.35
µs
Clock inactive before
chipselect becomes valid (11)
200
ns
Clock inactive after
chipselect becomes valid (12)
200
ns
20
ns
trs
Rise-, fall time
Load on SO 50pF
TIMING
Diagnostic Threshold (Open Load Detection DMS > 3.1V, EN < 18V and/or DI > 2V)
VOUT1
VOUT2
Load is available
0.8
0.8
VOUT1
VOUT2
Load is missing
1
IOUT2
IOUT1
tD
3
Diagnostic Current
DMS > 3.1V, EN < 0.8V
EN < 18V and/or DI > 2V
Tracking Diagnostic Current
Delay Time
V
V
VS
0.8
V
V
µA
µA
700
1000
1000
1500
1350
2000
IOUT1 / IOUT2
1.4
1.5
1.6
* After disabling the device, the
load has to be demagnetized
during tD ,to avoid erroneous OL
detection
30
100
ms
Truth Table
Table 7. Truth Table
Pos.
DI
EN
IN1
1. Forward
L
H
2. Reverse
L
H
OUT2
SF 3)
IN2
OUT1
H
L
H
L
H
L
H
L
H
H
3. Free-wheeling low
L
H
L
L
L
L
H
4. Free-wheeling high
L
H
H
H
H
H
H
5. Disable
H
X
X
X
Z
Z
L
6. Enable
X
L
X
X
Z
Z
Z
7. IN1 disconnected
L
H
Z
X
H
X
H
8. IN2 disconnected
L
H
X
Z
X
H
L
9. DI disconnected
Z
X
X
X
Z
Z
L
10. EN disconnected
X
Z
X
X
Z
Z
L
11. Current limit. active
L
H
X
X
Z
Z
H
12. Undervoltage active1.)
X
X
X
X
Z
Z
L
X
X
X
X
Z
Z
L
X
X
X
X
Z
Z
L
13. Overtemperature
14. Overcurrent
2.)
2.)
SPI 4)
DIA_REG
See
Diagnostics
/ Encoding
of Failures
9/23
L9929
1.)
2.)
In case of undervoltage tristate and status-flag are reset automatically.
Whenever overcurrent or overtemperature is detected, the fault is stored (i.e. status-flag remains low).
The tristate conditions and the status-flag 3) are reset via DI or EN.
L = Low
H = High
X = High or Low
Z = High impedance
(all output stage transistors are switched off in static state. For more inform. see next page )
Overcurrent:
IOUT1,2
>10.6 A
3.)
4.)
Overtemperature:
Tj
>175°C
Undervoltage:
VVs-GND
<4.5V
(at least down to 2.5V)
If Mode „Status-Flag“ is selected (see chapter "Diagnostic / Status-Flag")
If Mode „SPI-Diagnosis is selected (see chapter "Diagnostic / SPI-Interface")
Description of the state „Z“
The state „Z“ has, depending on the previous operating condition different meaning.
1. dynamical
I. e. the inductive load is current carrying and is switched off according to Pos. 5, 6, 9, 10, 11, 12, 13, or
14 of the truth table
a.) All output stage transistors are switched off.
b.) The current flow is continued via the free wheeling diodes.
c.) Free wheeling is detected by a negative voltage-level at OUn.
d.) Switch on of the parallel-transistor of the current carrying diode.
f.) Free wheeling is finshed, if the voltage-level on OUn is positive again.
2. statical
g.) all output-stages switched off.
Figure 11.
CURRENT
CARRYNG
FREE WHEELING
HIGH IMPEDANCE
IVS
-IGND
ILOAD
VOUn
VSVS-VDS
Zº
-VS
10/23
Z
D01AT478
L9929
4
Diagnostic
The Diagnosis-Mode can be selected between SPI-Diagnosis and Status-Flag Diagnosis.
The choise of the Diagnosis-Mode is selected by the voltage-level on pin 12 (DMS Diagnosis Mode Selection).
DMS = GND
Status-Flag
DMS = Vcc
SPI-Diagnostic
For the connection of pins SI, SO, SS and SCK/SF see Fig. 13 respectively Fig. 14.
4.1
Status-Flag
The Status-Flag showes the condition „tristate“.
At the following fault-cases the output-stages switches in tristate and set the status-flag from high to low.
- Short circuit of OUT1 or OUT2 against VS or GND
- Short circuit between OUT1 and OUT2
- Overcurrent
- Overtemperature
- Undervoltage on VS
In cause of short circuit or overcurrent, the fault will be stored.
The output stage switches in tristate and the status-flag is set from high level to low-level if the specified value
is exceeded.
If the voltage level changes from high to low on DI or from low to high on EN, the output stage switches on again
and the status-flag is reset to high-level.
In cause of overtemperature the fault will be stored.
The output stage switches in tristate and the status-flag is set from high level to low-level if the specified value
is exceeded.
If the voltage level changes from high to low on DI or from low to high on EN, the output stage switches on again
and the status-flag is reset to high-level.
In cause of undervoltage on VBatt the output stage switches in tristate and the status-flag is set from high level
to low-level if the specified value is fallen. If the voltage has risen about the specified value again, the output
stage switches on again and the status-flag is reset to high-level.
The maximum current which can flow under normal operating conditions is limited to typical Imax. = 8.6A .
When the maximum current value is reached, the output stages are switched tristate for a fixed time.
According to the time-constant the current decreases exponentially until the next switch-on occurs.
At the end if the fixed time the output stage switches on again and the status-flag is reset to high-level.
5
5.1
SPI-INTERFACE
General Discription
The serial SPI interface establishes a communication link between L9929 and the systems microcontroller.
L9929 always operates in slave mode whereas the controller provides the master function.
The maximum baud rate is 2 MBaud (200pF).
Applying an active slave select signal at SS L9929 is selected by the SPI master. SI is the data input (Slave In),
SO the data output (Slave Out). Via SCK (Serial Clock Input) the SPI clock is provided by the master.
In case of inactive slave select signal (High) the data output SO goes into tristate.
11/23
L9929
Figure 12.
SPI Power Supply
DMS
SS
SI
SPI Control:
State Machine
Clock Counter
Control Bits
Parity Generator
Shift Register
DIA_REG
5.2
Power Supply of the SPI-Interface
SPI-Logic and I/O-Pins are alternativ supplied from DMS or Vcc internal, depending on which voltage is higher.
That is why diagnosis of the EN-/DI-Pins is always possible, even in case of missing H-Bridge-power supply e.g.
during „Vorlauf/Nauchlauf“.
5.3
Characteristics of the SPI Interface
1)
When DMS is > 3.1V, the SPI is active, independent of the state of EN or DI and the voltage on VS. During
active reset conditions (DMS < 2.5V) the SPI is driven into its default state. When reset becomes inactive,
the state machine enters into a waitstate for the next instruction.
2)
If the slave select signal at SS is inactive (high), the state machine is forced to enter the waitstate, i.e. the
state machine waits for the following instruction.
3)
During active (low) state of the select signal SS the falling edge of the serial clock signal SCK will be used
to latch the input data at SI. Output data at SO are driven with the rising edge of SCK. Further processing
of the data according to the instruction ( i.e. modification of internal registers) will be triggered by the rising
edge of the SS signal. (-> See Note)
4)
Chipaddress: In order to establish the option of extended addressing the uppermost two bits of the instruction-byte ( i.e the first two SI-bits of a Frame ) are reserved to send a chipaddress. To avoid a busconflict
the output SO must stay high impedant during the addressing phase of a frame (i.e. until the addressbits
are recognised as valid chipaddress). This tristate behavior should be realised in any case, regardless
wether the extended addressoption is used or not. If the chipaddress does not match, the according access will be ignored and SO remains high impedant for the complete frame regardless which frametype is
applied.
5)
Check byte: Simultaneously to the receipt of an SPI instruction L9929 transmitts a check byte via the output SO to the controller. This byte indicates regular or irregular operation of the SPI. It contains an initial
bitpattern and a flag indicating an invalid instruction of the previous access.
12/23
L9929
6)
7)
On the read access the databits at the SPI input SI are rejected.
Invalid instruction/access: An instruction is invalid, if one of the following conditions is fulfilled:
– An unused instruction code is detected (see tables with SPI instructions).
– In case the previous transmission is not completed in terms of internal data processing. ( Violation of
the minimum Access-Time. )
– In case of the previous transmission has detected more than 16 SCK pulses
– Reset has occurred (Undervoltage on DMS)
If an invalid instruction is detected, any modifications on registers of L9929 are not allowed.
In case an unused instruction code occured the databyte "ffh ex" will be transmitted after having sent the check
byte.
In addition any access is invalid if the number of SPI clock pulses (falling edge) counted during active SS differs
from exactly 16 clock pulses (-> See Note).
5.4
SPI Communication
Figure 13. Reading access / 8 bit
SS
SI
SPI INSTRUCTION
MSB
XXXX XXXX
SO
VERIFICATION BYTE
MSB
DATA/8 BIT
MSB
D01AT480
5.5
SPI Instruction
The uppermost 2 bit of the instruction byte contains the chipadress. The chipaddress of L9929 is 00.
MSB
7
6
5
4
3
2
1
0
0
0
INSTR5
INSTR4
INSTR3
INSTR2
INSR1
INSR0
Encoding
SPI Instruction
Description
bit 7,6
CPAD1,0
bit 5,4,3,2,1,0
INSTR(5...0)
RD_IDENT
00
000 000
Read identifier
RD_VERSION
00
000 011
Read version
RD_DIA
00
001 001
Read DIA_REG
All others
No function
13/23
L9929
5.6
Reset of the Diagnostic Register DIA_REG
On the following conditions DIA_REG is reset:
– With the rising edge of the SS-signal after the SPI-Instruction RD_DIA (only if error free while SS,
new errors will actualize DIA_REG with the rising edge of SS).
– When the voltage on DMS exceeds the threshold for detecting SPI-Mode. (after undervoltage condition or after power up)
– - If VS rises over about the undervoltage level, the Bits of DIA_REG are restored (when VS internal
or DMS > 3,1V)
Verification byte:
MSB
5.7
7
6
5
4
3
2
1
0
Z
Z
1
0
1
0
1
TRANS_F
Bit
Name
Description
0
TRANS_F
Bit = 1: error detected during previous transfer
Bit = 0: previous transfer was recognised as valid
1
Fixed to High
2
Fixed to Low
3
Fixed to High
4
Fixed to Low
5
Fixed to High
6
Send as high impedance
7
Send as high impedance
Diagnostics/Encoding of Failures
Description of the SPI Registers
Register:
(SPI Instructions: RD_DIA)
DIA_REG
7
6
5
4
3
2
1
0
Active
OT
CurrRed
CurrLim
DIA21
DIA20
Dia11
DIA10
State of Reset: FFH
Access by Controller:
Bit
Name
0
DIA 10
Diagnosis-Bit1 of OUT1
1
DIA 11
Diagnosis-Bit2 of OUT1
2
DIA 20
Diagnosis-Bit1 of OUT2
3
DIA 21
Diagnosis-Bit2 of OUT2
CurrLim
Is set to „0“ in case of current limitation
4
5
14/23
Read only
CurrRed
Description
Is set to „0“ in case of temperature dependet current limitation
6
OT
Is set to „0“ in case of overtemperature
7
Active
Shows the wired-or state of the Pins EN and DI
L9929
Encoding of the Diagnostic Bits of the Output-Stages OUT1 and OUT2
DIA21
DIA20
DIA11
DIA10
-
-
0
0
Short circuit over load (SCOL)
-
-
0
1
Short circuit to battery on OUT1 (SCB1)
-
-
1
0
Short circuit to ground on OUT1 (SCG1)
-
-
1
1
No error detected on OUT1
0
0
-
-
Open load
0
1
-
-
Short circuit to battery on OUT2 (SCB2)
1
0
-
-
Short circuit to ground on OUT2 (SCG2)
1
1
-
-
No error detected on OUT2
0
0
0
0
Undervoltage on Pin VS
Description of DIA_REG Bit7
5.8
EN
DI
DIA_REG Bit7
0
0
0
0
1
0
1
0
1
1
1
0
Device Identifier and Revision Number
The IC's identifier is used for production test purposes and features plug & play functionality depending on the
systems software release. It is made up on a device-number and a revision number each one read-only accessible via standardised instructions.
The Device number is defined once to allow indentification of different IC-Types by software.
The Revision number may be utilised to distinguish different states of hardware. The contents is divided into an
upper 4 bit field reserved to define revisions correspondending to specific softwarereleases. The lower 4 bit field
is utilised to indentify the actual maskset.
Both (SWR and MSR) will start with 0000b and are increased by 1 every time an according modification of the
hardware is introduced.
5.9
Reading the IC Identifier (SPI Instruction: RD_IDENT):
IC Identifier1 (Device ID)
7
6
5
4
3
2
1
0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Bit
Name
7...0
ID(7...0)
Description
ID-No.: 1010 0001
5.10 Reading the IC revision number (SPI Instruction: RD_VERSION):
IC’s revision number
7
6
5
4
3
2
1
0
SWR3
SWR2
SWR1
SWR0
MSR3
MSR2
MSR1
MSR0
Bit
Name
Description
7...4
SWR(3...0)
Revision corresponding to Software release: 0Hex
3...0
MSR(3...0)
Revision corresponding to Maskset: 8Hex
15/23
L9929
Figure 14. Application example with SPI-Interface
DMS
UB
IN1
VBATT
VOLTAGE
REGULATOR
VCC
IN2
DI
POWER-ON
RESET
RESET
µC
OUT1
SCK
M
SS
SO
OUT2
SI
I.E. WATCH
DOG µP
EN
GND
D01AT481
Figure 15. Application example with Status-Flag
DMS
47K
UB
SF
VBATT
VOLTAGE
REGULATOR
VCC
IN1
IN2
POWER-ON
RESET
RESET
µC
OUT1
DI
M
SS
SO
OUT2
SI
I.E. WATCH
DOG µP
EN
GND
16/23
D01AT482
L9929
Figure 16. Application examples for Overvoltage- and Reverse-Voltage Protection
Version 1 REVERSE POLARITY PROTECTION VIA MAIN RELAIS
H-BRIDGE
VS < 40V
VS
IGNITION
SWITCH
MAIN
RELAIS
BATTERY
Version 2 REVERSE POLARITY PROTECTION VIA ACTIVE DIODE
H-BRIDGE
VS < 40V
VS
BATTERY
D01AT483
6
ESD-SOLIDITY
The connection pins of the IC have to be protected against Electrostatic Discharge ESD) by suitable integrated
protection structures.
The integrated circuit has to meet the demand of the „Human-Body-Model“ with VC = ± 4kV
C = 100pF and R2 = 1,5kΩ (330Ω for OUT1 and OUT2).
Thereby any defect or destruction of the integrated circuit must not occur.
The protection structures realized to reach the ESD-strength have to be coordinated.
The ESD-strength has to be verified by the test circuit given as below.
Figure 17.
S2
R1
(1)
R2
(2)
S1
US
=
V
DCVOLTMETER
C
S3
OUT
D01AT484
For the Pins 4, 5, 6, 7, 14 and 15
UC = + 4kV
R1 = 100kΩ
R2 = 330Ω
C = 100pF
Number of pulses each pin: 18
Frequency: 1Hz
Arrangement and performance:
The requirements of MIL883D Methode 3015 have to be fulfilled.
17/23
L9929
7
ISO-PULSES
In the main-power-supply-system disturbance transients according to ISO 7637-1 First Edition 1990-06-01
may occur.
By means of external components (see Fig. 12) the following maximum ratings of the IC will not be exceeded.
statical
-1V ...... +40V
dynamical for t < 500 ms
-2V ...... +40V
APPENDIX A
Load available
OUT1
OUT2
1
1
Open Load
1
0
SC -> GND on OUT1 with Load
0
0
SC detected on normal operation
SC -> GND on OUT2 with Load
0
0
SC detected on normal operation
SC -> UB on OUT1 with Load
1
1
SC detected on normal operation
SC -> UB on OUT2 with Load
1
1
SC detected on normal operation
SC -> GND on OUT1 Open Load
0
0
OL not detected Double Fault
SC -> GND on OUT2 Open Load
1
0
OL detected
SC -> UB on OUT1 Open Load
1
0
OL detected
SC -> UB on OUT2 Open Load
1
1
OL not detected Double Fault
Figure 18.
VBatt
int 5V
IN1
IN2
1.5 mA
OUT1
OUT2
1 mA
18/23
L9929
8
APPENDIX B
Figure 19. Voltage Supply of SPI-Logic and EN/DI-Logic
VBatt
EN
DI
OutputStage
EN/DILogic
internal
Vcc
DMS = GND EN/DI-Logic is supplied from internal VCC
DMS = VCC EN/DI-Logic is supplied from DMS (OR int. VCC)
DMS
SO
SI
SCK
SS
Status
EN/DI
SPILogic
Undervoltage
on VBatt
Failure and Status
Output Stage
19/23
L9929
9
Package Information
Figure 20. PowerSO20 Mechanical Data & Package Dimensions
DIM.
mm
MIN.
TYP.
A
a1
inch
MAX.
MIN.
TYP.
3.6
0.1
0.3
a2
0.142
0.004
0.012
3.3
0.130
a3
0
0.1
0.000
0.004
b
0.4
0.53
0.016
0.021
c
0.23
0.32
0.009
0.013
D (1)
15.8
16
0.622
0.630
D1 (2)
9.4
9.8
0.370
0.386
E
13.9
14.5
0.547
e
1.27
e3
E1 (1)
0.570
0.450
11.1
E2
0.429
0.437
2.9
0.114
E3
5.8
6.2
0.228
G
0
0.1
0.000
0.004
H
15.5
15.9
0.610
0.626
0.031
0.043
h
L
0.244
1.1
0.8
1.1
0.043
N
8˚(typ.)
S
8˚(max. )
T
Weight: 1.9gr
0.050
11.43
10.9
OUTLINE AND
MECHANICAL DATA
MAX.
10
JEDEC MO-166
0.394
PowerSO20
(1) “D and E1” do not include mold flash or protusions.
- Mold flash or protusions shall not exceed 0.15mm (0.006”)
- Critical dimensions: “E”, “G” and “a3”.
(2) For subcontractors, the limit is the one quoted in jedec MO-166
N
R
N
a2
b
A
e
DETAIL A
c
a1
DETAIL B
E
e3
H
DETAIL A
lead
D
slug
a3
DETAIL B
20
11
0.35
Gage Plane
-C-
S
SEATING PLANE
L
G
E2
E1
BOTTOM VIEW
C
(COPLANARITY)
T
E3
1
h x 45˚
1
0
PSO20MEC
D1
0056635 I
20/23
L9929
Figure 21. PowerSSO24 Mechanical Data & Package Dimensions
DIM.
mm
MIN.
TYP.
inch
MAX.
MIN.
A
2.15
2.47
0.084
TYP.
MAX.
0.097
A2
2.15
2.40
0.084
0.094
a1
0
0.075
0
0.003
b
0.33
0.51
0.013
0.020
c
0.23
0.32
0.009
0.012
D
(1)
10.10
10.50
0.398
0.413
E
(1)
7.4
7.6
0.291
e
0.8
e3
8.8
0.299
0.031
0.346
G
0.10
0.004
G1
0.06
0.002
H
10.10
h
L
10.50
0.398
0.40
0.413
0.016
0.55
0.85
X
4.10
4.70
0.161
0.185
Y
6.50
7.10
0.256
0.279
N
OUTLINE AND
MECHANICAL DATA
0.022
0.033
10˚ (max)
(1) “D and E1” do not include mold flash or protusions.
Mold flash or protusions shall not exceed 0.15mm (0.006”)
(2) No intrusion allowed inwards the leads.
(3) Flash or bleeds on exposed die pad shall not exceed 0.4 mm
per side
PowerSSO24
7412828 A
21/23
L9929
10 Revision History
Table 8. Revision History
22/23
Date
Revision
Description of Changes
07-Mar-2005
1
First Issue
13-May-2005
2
Add package PowerSSO24
L9929
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23/23