75A, 600V MAGNUM MOTOR DRIVES SLEEP MODE FEATURES POWER SUPPLY I S O L A T I O N VCC • 600 Vdc Drive for 270 Vdc Motors VCC RTN • 75 Amps @25°C, 50 Amps @85°C UPPER • Operates with Brushless, Brush and Induction Motors SC FAULT DISABLE/RESET • Input to Output Ground Isolation with Floating Output Stage POWER SUPPLY VBUS+ HIGH DRIVE B A R R I E R GATE DRIVE AND FAULT CONTROL OUTPUT AUTO RESET LOW DRIVE LOWER VBUS- • Short Circuit Protection FIGURE 1A. PW-83075P6 BLOCK DIAGRAM • Trapezoidal or Sinusoidal Compatible • DSP/Microprocessor Compatible SLEEP MODE POWER SUPPLY I S O L A T I O N VCC • PW-83075P6 - Half-Bridge Drive VCC RTN • PW-84075P6 - Half-Bridge Drive with Current Sense UPPER SC FAULT • PW-85075P6 - Half-Bridge Drive with Regenerative Clamp DISABLE/RESET POWER SUPPLY VBUS+ HIGH DRIVE B A R R I E R GATE DRIVE AND FAULT CONTROL OUTPUT AUTO RESET LOW DRIVE LOWER VDD VDD RTN I_VOUT DESCRIPTION OC FAULT VREF The PW-83075P6, PW-84075P6 and PW-85075P6 are halfbridge drive modules which contain isolated switch drivers, a pair of solid state switches, an isolated power supply, current sensing feedback (PW-84075P6 only) and a regenerative clamp protection circuit (PW-85075P6 only). The three modules can be used, in any combination, to create drives for brush, brushless DC motors or AC induction motors. The logic inputs and current sense signal are compatible with DSP/microprocessors and/or FPGA/ASIC circuits used to control the motor drives. These modular drives are capable of operating from either ±135Vdc or 270Vdc power source that is totally isolated from the logic input signals. The modules are fault tolerant from output shorts, loss of any or all power supplies and power supply sequencing. VBUSRSENSE+ CURRENT AMP RSENSE RSENSE- I_ABSVAL FIGURE 1B. PW-84075P6 BLOCK DIAGRAM REGEN LOW REGEN STATUS VBUS+ OV AMP OV ADJ REGEN BUSSLEEP MODE POWER SUPPLY VCC VCC RTN UPPER APPLICATIONS SC FAULT The high reliability and flexibility of these drives make them suitable for Military and Aerospace applications. Among the many applications are: actuator systems for primary and secondary flight controls on aircraft; fan and compressor motor drives for environmental conditioning; pump motors for fuel and hydraulic fluid; antenna and radar positioning; and thrust vector position control of missiles, drones, and RPV’s. DISABLE/RESET GATE DRIVE AND FAULT CONTROL I S O L A T I O N POWER SUPPLY REGEN BUS- VBUS+ HIGH DRIVE B A R R I E R OUTPUT AUTO RESET LOWER LOW DRIVE VBUS- FIGURE 1C. PW-85075P6 BLOCK DIAGRAM 1 June 13, 2000 Data Device Corporation CURRENT AMP TABLE 1. PW-8X075P6 ABSOLUTE MAXIMUM RATINGS (TC = +25°C UNLESS OTHERWISE SPECIFIED) PARAMETER Drive Supply Voltage SYMBOL VBUS+ to VBUS- VALUE 600 UNITS Vdc Logic Power-In Supply Voltage Input Logic Voltage VCC 5.5 Vdc UPPER, LOWER, DISABLE/RESET, SLEEPMODE, AUTO RESET 5.5 Vdc IO 75 A Continuous Output Current Peak Output Current (10 ms) IPEAK 150 A Storage Temperature Range Tcs -65 to +125 °C Intermittent Case Operating Temperature TCI -55 to +125 °C Continuous Case Operating Temperature Tc -55 to +100 °C Junction Temperature, Power Devices Tj +150 °C TJ +125 °C VISO 2500 Vdc Junction Temperature, Other Components Ground Isolation Voltage (Note 2) TABLE 2. PW-8X075P6 SPECIFICATIONS (TC = +25°C, VCC = VDD = 5V UNLESS OTHERWISE SPECIFIED) PARAMETER OUTPUT STAGE Drive Supply Voltage (motor) Output Switch Transistors (each) Continuous Current Drive Peak Current Short Circuit Trip Current (note 1) Output Voltage Drop (IGBT) FLYBACK DIODE Instant Forward Voltage Reverse Recovery Time @ Tj = +125° C Reverse recovery Peak Current Reverse Leakage Current @ Tj = +25° C Reverse Leakage Current @Tj = +125° C OUTPUT SWITCHING CHARACTERISTICS (See FIGURE 5) Turn-on Propagation Delay Turn-off Propagation Delay Disable Propagation Delay Turn-on Rise Time Turn-off Fall Time Sleep_Mode Delay Output Switching Frequency POWER AND LOGIC SUPPLY (PW83075P6 ONLY) Voltage Current Control Inputs UPPER, LOWER, DISABLE/RESET AUTO RESET High Level Input Voltage Low Level Input Voltage Hysteresis Voltage UPPER, LOWER High Level Input Current Low Level Input Current RESET/DISABLE High Level Input Current Low Level Input Current AUTO_RESET High Level Input Current Low Level Input Current SLEEP_MODE High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VBUS+ TO VBUS- Unipolar/Bipolar 0 270 600 Vdc IO +25°C case +85°C case +85°C case,≤15 ms ≤5 µs IO = 50A 350 2.2 75 50 100 400 2.6 A A A A Vdc 1.7 175 19 1.9 33 Vdc ns A 30 325 17 µA mA 470 840 ns ns µs ns ns ms KHz IPEAK ISC VCE(SAT) VF Trr Irm Ir Ir IO = 50A IO = 50A di/dt = 480A/µs IF = 50A (90 °C) VBUS = 480Vdc VBUS = 480Vdc td(on) td(off) tsd tr tf tsleepu fPWM 390 740 100 100 140 200 200 3.7 0 VCC ICC 35 4.5 5.0 110 5.5 Vdc mA 1.55 0.9 0.4 2.5 1.6 0.9 3.15 2.45 2.1 Vdc Vdc Vdc f = 25 KHz VCC = 4.5V VIH VIL VHYST IIH IIL Vin = VCC Vin = 0V 22 0 23 0.1 24 100 µA nA IIH IIL Vin = VCC Vin = 0V 22 0 23 24 µA µA IIH IIL Vin = VCC Vin = 0V VCC = 4.5V 1.3 0 1.4 1.5 µA mA VIH VIL IIH IIL 2.4 0.8 Vin = VCC Vin = 0V 2 June 13, 2000 Data Device Corporation 200 0.1 0.4 0.5 Vdc Vdc µA mA TABLE 2. PW-8X075P6 SPECIFICATIONS (TC = +25°C, VCC = VDD = 5V UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL UPPER-LOWER DEADTIME AUTO_RESET Delay to output off AUTO_RESET Delay to output enabled RESET pulsewidth to clear SC_FAULT Cycle time between AUTO_RESET retries CONTROL OUTPUTS SC_FAULT High Level Current Low Level Current tdead tdoff.auto tdon.auto tpw.reset tcycle.auto TEST CONDITION MIN TYP MAX 1.0 µs ms ms ns ms 202 3.0 ISCFLTH ISCFLTL Vo = VCC Vo = 0.4V θjc θjc Tj Tc Tcs Each Output Switch UNITS 100 40 100 22 5 23 10 24 µA mA 0.5 0.8 0.55 +150 +100 +125 °C/W °C/W °C °C °C +250 3 TBD °C in-lbs oz (gr) MAX UNITS THERMAL Maximum Thermal Resistance - IGBT - Diode Junction Temperature Range Case Operating Temperature Case Storage Temperature -55 -55 -65 MECHANICAL Maximum Lead Soldering Temp Mounting Torque Weight Ts Notes: 1. VBUS+ to VBUS- must be ≥ 10V (during short circuit) for short circuit protection to operate. 2. From VCC RTN to VBUS+, VBUS-, OUTPUT, REGEN LOW, RSENSE+, RSENSE-. TABLE 3. PW-84075P6 SPECIFICATIONS (TC= +25°C VCC = VDD = 5V UNLESS OTHERWISE SPECIFIED) PARAMETER Current Amplifier I_Vout Trasnfer Ratio I_Vout Gain Error I_Vout Offset I_Vout Offset Drift I_Vout Gain % I_Vout Offset % I_Vout Offset % Drift I_VABS Gain I_VABS Gain Error I_VABS Offset I_VABS Offset Drift I_VABS Gain % I_VABS Offset % I_VABS Offset % Drift Delay Time Bandwidth Linear Range OC_FAULT trip level Reference voltage input current SYMBOL TEST CONDITION Gvout Evout Vos TCVos Gvout% Vos%Vref TCVos% Gvabs Evabs Vosabs TCVosabs Gvout% Vosabs% Vref TCVosabs% tdelay fBW Irange IOC Ivref Vref = 5.0V OC_FAULT High Level Input Current Low Level Input Current IOCFLTH IOCFLTL Vo = VDD Vo = 0.8V Power and Logic Supply Voltage Logic Supply Current VCC, VDD ICC Current Amplifier Supply Current Vref = 5.0V Vref = 5.0V 0A = Vref/2 TYP 29.76 -6 -30 -90 6 30 110 0.595 -0.6 -18 0A = 0V Vref = 5.0V Vref = 5.0V 0A = 0V 0.6 22 59.52 -8 -131 -90 8 131 110 1.19 -2.6 -18 20 ±75 4.5 IDD 2.6 22 20 8 mV/A % mV ppm/°C %Vref/A %Vref ppm/Vref/°C mV/A % mV ppm/°C %Vref/A %Vref ppm/Vref/°C µs kHz A A mA 9 30 ±50 ±85 0.26 ±95 1 0.2 15 uA mA 5 11 136 10 5.5 V mA mA mA 4 Gate Off / SLEEP MODE 25Khz Gate Pulsing 3 June 13, 2000 Data Device Corporation MIN 200 20 TABLE 4. PW-85075P6 SPECIFICATIONS (TC = +25°C, VCC = VDD = 5V UNLESS OTHERWISE SPECIFIED) PARAMETER Over Voltage Transistor Continuous Current Drive Io Peak Current Output Voltage Drop (IGBT) Reverse Leakage @ TJ = +25°C Reverse Leakage @ TJ = +125°C IPEAK VCE(SAT) Ir Ir Over Voltage flyback Diode Reverse Leakage @ Tc = +25°C Reverse Leakage @ Tc = +125°C Over Voltage Trip Trip Level Hysteresis Ir Ir Vtrip Vhyst Power and Logic Supply Voltage Current REGEN STATUS (ref. to REGEN BUS-) High Level Output Voltage Low Level Output Voltage Output resistance Vtrip rise to status ON Delay Vtrip fall status OFF Delay THERMAL Maximum Thermal Resistance TEST CONDITION SYMBOL VCC ICC TYP MAX UNITS 35 30 60 3.0 250 1.0 A A A Vdc µA mA 20 1 400 40 50 7 430 45 µA mA Vdc Vdc 5 11 137 5.5 V mA mA +25°C Case +85°C Case +85°C Case, 15 ms 2.0 600 Vdc 600 Vdc 480 Vdc 480 Vdc no external adjustments 370 35 4.5 Gate Off/ Sleep Mode 25Khz Gate Pulsing VOHstatus VOLstatus Rstatus tdon.status tdoff.status I0 = 0 I0 = 0 θjc Over Voltage Switch 13.8 4.2 INTRODUCTION 250 15 0.2 4.75 36 48 15.6 0.4 4.8 Vdc Vdc KΩ µs µs 0.7 0.85 °C/W URE 2, between UPPER and LOWER inputs is necessary to prevent output cross conduction. The PW-8X075P6 is a universal modular half-bridge motor drive intended for use with brush, brushless DC and AC induction motors in aerospace applications. SC FAULT The SC FAULT output signal indicates when the output of the motor drive has experienced a short circuit condition. The signal is normally at a logic high (H). A transition to a logic low (L) will occur once a short circuit condition is detected. See SHORT CIRCUIT OPERATION for more detail. The isolation barrier, which separates the power and control stage, attenuates the ground noise generated from high speed, high power switching. All signals from the control to the power sections are isolated from power and ground of the other section. This eliminates false triggering of the input signals and the need for creative grounding schemes. The isolation barrier also allows the user to operate the output stage from either unipolar or bipolar power supplies without level shifting the input signals. DISABLE / RESET The DISABLE/RESET control input is CMOS Schmitt-trigger input and enables (reset) or disables the controller. When the DISABLE/RESET input receives a logic low (L) pulse for at least 0.1 µs, the SC FAULT output will go high (H) indicating that the internal circuitry has been enabled or reset. To reset the motor drive, a logic low (L) must be presented to the DISABLE/RESET inputs when the AUTO RESET is inactive or at a logic high (H). A built in power supply located in the control stage provides power to all electronics in the power stage. This eliminates the need for refresh cycles or external power supplies for the gate drive circuitry and allows switching duty cycles from 0 - 100%. PW-84075P6 provides current sensing of either motor current or DC bus current. This current signal can be used as a feedback signal in a servo drive to create a torque loop. AUTO RESET When the AUTO RESET is tied to SC FAULT, the protection circuit will reset automatically after the short circuit fault has occurred, enabling the output to respond to the input commands. See SHORT CIRCUIT OPERATION for more detail. The output power transistors are protected from a short circuit or overvoltage condition (requires PW-85075P6) applied to the output pins. When a short circuit condition is detected, the output transistor is shut down and a flag is active indicating a short has occurred. When an overvoltage condition is detected, the overvoltage switch is enabled and a external load dump resistor is connected across the high voltage bus. A status flag is active indicating an overvoltage condition has occurred. SHORT CIRCUIT OPERATION The PW-8X075P6 outputs are completely short-circuit-protected from either a hard or soft short (required PW-84075 and some external circuit) to the VBUS+ or VBUS- lines. Each output transistor is individually short-circuit (hard) protected by circuitry that detects the desaturation voltage for that transistor during a short condition. Once a hard short circuit condition is detected, the active output transistors are shutdown. If the AUTO RESET is tied to SC FAULT, the circuit will auto reset, remove the short circuit flag, and reactivate the output transistor within 40 to 100ms. FUNCTIONAL AND PIN DESCRIPTIONS: (FOR PW-83075P6, PW-84075P6 AND PW-85075P6 UNLESS NOTED) UPPER, LOWER The UPPER and LOWER are CMOS Schmitt-trigger inputs and control the gate drives of the output transistors. Each input is electrically isolated from the output. A deadband, as shown in FIG4 June 13, 2000 Data Device Corporation MIN power supply is shut down (SLEEP MODE input high), the voltage at I_VOUT will indicate 0V. 50% 50% VREF (APPLIES TO PW-84075P6 ONLY) UPPER 50% A voltage reference from an external source is connected to the VREF pin to set the output voltage scale for I_VOUT. 50% RSENSE+, RSENSE- (APPLIES TO PW-84075P6 ONLY) LOWER 0.6 µs Min. 0.6 µs Min. These pins are across RSENSE and can be connected in series with the output, VBUS+ or VBUS- to measure current. The internal connections to RSENSE are Kelvin to minimize errors. However, these pins can be connected absolutely anywhere within the isolation restrictions on the pins (600V to power pins, 2500V to logic pins). FIGURE 2. PW-8X075P6 DEAD BAND REQUIREMENT If the short is still present, the circuit will repeat the shut down and auto reset until the short is clear. The users can use the DISABLE/RESET (H) to shut down the gate drivers if a short persists. The AUTO RESET is inactive when it presented a logic high (H). Protecting against a soft-short requires a PW-84075 (current sensing) and external circuitry. When a soft-short occurs, the external circuit can activate the SLEEPMODE (H) and shut down the gate drivers. I _ABSVAL (APPLIES TO PW-84075P6 ONLY) The I_ABSVAL output voltage is the absolute value of the I_VOUT voltage signal. The scale is 0 to VREF for +/- current in RSENSE. OC FAULT (APPLIES TO PW-84075P6 ONLY) SLEEP MODE The OC FAULT output is an open drain output which indicates that current flowing through RSENSE has exceeded the overcurrent threshold. Once the fault threshold is exceeded, the output transitions from open drain to low within 6 µs. The SLEEP MODE input turns the internal power supply on or off. A logic high (H) on the SLEEP MODE input disables the internal power supply, disabling the motor drive output. No damage will occur to the motor drive during turn on or turn off of the power supply. Additionally, no special power up sequence is required. A logic low (L) turns the power supply on and allows the motor drive to operate normally. REGEN STATUS (APPLIES TO PW-85075P6 ONLY) The REGEN STATUS pin is referenced to REGEN BUS-. It indicates the state of the regen clamp switch, H = on, L = off. An external opto-isolator input can be connected between REGEN STATUS and REGEN BUS- to translate this status to logic circuits, if desired. VCC, VCC RTN The VCC and VCC RTN are power connections that supply input power to the internal power supply, the gate drive and fault control circuits. OV ADJ (APPLIES TO PW-85075P6 ONLY) The PW-85075P6 is internally set for a trip voltage of 400V. To set a different trip voltage, an external resistor is connected from the OV ADJ pin to either REGEN BUS- or VBUS+ pins (See FIGURES 4A and 4B). These pins are available on the control pins. This resistor should be selected for the voltage, Vmax, for the overvoltage switch to turn on. VBUS+, VBUSVBUS+ and VBUS- are the high voltage power connections to the output stage. The high voltage can be either unipolar, +V and ground or bipolar, +/- V. External capacitor filtering will be required. See DDC applications note AN/H-6. OUTPUT 75 70 Output Phase Current, IAVG (amps) The output connects to one input of the motor and applies VBUS+, VBUS-, or high impedance to the motor based on the state of the control inputs. It is capable of sourcing or sinking up to 75 Amps, and the output can withstand a short circuit to VBUS+ or VBUSwithout any damage by automatically turning itself off (Zstate). VDD, VDD RTN (APPLIES TO THE PW-84075P6 ONLY) The VDD and VDD RTN supply input power to the current amplifier. I_VOUT (APPLIES TO PW-84075P6 ONLY) The voltage on the I_VOUT pin represents current passing through RSENSE in the direction shown in the block diagram.This I_VOUT voltage is scaled by the input voltage at VREF, where 60 55 50 45 40 35 30 5 kHz 25 20 10 kHz VBUS+ = 270 Vdc 15 15 kHz 20 kHz 25 kHz 35 kHz Duty Cycle = 50% 10 Tj(max) = 150°C 5 0 I_VOUT = (VREF/2) + (VREF/150) * I_RSENSE 25 35 45 55 65 75 85 95 105 115 125 Maximum Operating Case Temperature, Tc °C where, I_RSENSE is current through RSENSE FIGURE 3. PW-8X075P6 OUTPUT PHASE CURRENT VS. MAXIMUM OPERATING CASE TEMPERATURE I_VOUT is electrically isolated from the output stage. When the 5 June 13, 2000 Data Device Corporation 65 NOTE: VBUS+ (27) and REGEN BUS- (26) on the power-pin side are also connected to pin 22 and 17 on the control-pin side, respectively, for ease of connecting the external resistor. ADJ, the internal clamp circuit will apply the load dump resistor from VBUS+ to the VBUS-, thereby dissipating the regenerative energy in the external resistor. In addition, REGEN BUS- has to be externally connected to VBUS- for the clamp circuit to work properly. This connection (PCB traces or wire) has to be able to carry the regenerative current. REGEN LOW, REGEN BUS-(APPLIES TO PW-85075P6 ONLY) An external load dump resistor is connected between REGEN LOW and VBUS+. When VBUS+ reaches the level set by the OV OV Switch on V OV Switch off OV Switch off OV Switch on NOTE: VH = HYSTERESIS VOLTAGE NOTE: FIGURE 4A. PW-8X075P6 TYPICAL OVER VOLTAGE TRIP VS. OV ADJUST SETTING WITH EXTERNAL RESISTOR CONNECTED TO REGEN BUS- VH = HYSTERESIS VOLTAGE FIGURE 4B. PW-8X075P6 TYPICAL OVER VOLTAGE TRIP VS. OV ADJUST SETTING WITH EXTERNAL RESISTOR CONNECTED TO VBUS+ TABLE 5. PW-8X075P6 TRUTH TABLE UPPER/LOWER UPPER LOWER DISABLE/ RESET SLEEPMODE OUTPUT 0 0 0 1 Z 1 0 0 1 VBUS+ 0 1 0 1 VBUS- 1 1 0 1 * X X 1 X Z X X X 0 Z 50% tr tf OUTPUT 90% 50% 10% t d (ON) t d (OFF) X = Indicates that this input is irrelevant Z = High Impedance (off). * = Illegal command that will cause one of the outputs to fault. FIGURE 5. PW-8X075P6 INPUT/OUTPUT TIMING RELATIONSHIP 6 June 13, 2000 Data Device Corporation HALL SIGNALS 3 POSITION ERROR + POSITION COMMAND - POSITION AMP VELOCITY COMMAND + VELOCITY ERROR VELOCITY AMP - TORQUE COMMAND + TORQUE ERROR CURRENT ERROR AMP - 6 PWM 3-PHASE MOTOR PW-8X075P6 3-MODULE SET TORQUE LOOP VELOCITY LOOP POSITION LOOP FIGURE 6. TYPICAL POSITION AND VELOCITY CONTROL LOOP EOFF = ts2 x VBUS x IOB / 6 EOFF = 200ns x 270V x 50A / 6 EOFF = .00036J PS = 10000 x (.00045 + .00036) PS = 8.1W POWER DISSIPATION (see FIGURE 7) There are three major contributors to power dissipation in the motor driver: conduction losses, switching losses, and flyback diode losses. Consider the following operating conditions VBUS = +270V IOA = 40A (see FIGURE 7); IOB = 50A (see FIGURE 7) ton = 50µs (see FIGURE 7); T = 100µs ( period ) VCE(SAT) = 2.0V (see TABLE 2, IO = 50A, TC = +25°C) ts1 = 200ns (see Figure 7); ts2 = 200ns (see FIGURE 7) fo = 10kHz (switching frequency) VF is the diode forward voltage, TABLE 2, Io = 50A, TC = +25°C VF(avg) = 1.35V 3. Flyback diode Losses (Pd) Pd = IAVE x VF(avg) x (1- (ton / T)) Pdf = 45A x 1.35V x [1 - (50µs / 100µs)] Pdf = 30.38W Transistor Power Dissipation (PT) To calculate the maximum power dissipation of the output transistor / diode pair as a function of the case temperature, use the following equation. 1. Conduction Losses (PC) PC = IAVE x VCE(SAT) x (ton / T) IAVE = (IOB + IOA ) / 2 IAVE = (50A + 40A) / 2 = 45 PC = 45A x 2.0V x (50µs / 100µs) PC = 45W PQ = PC + PS + Pdf Total Hybrid Power Dissipation (PHybrid) To calculate Total Power Dissipated in the hybrid add the power dissipation of each conducting transistor / diode pair. Typically, only two transistor / diode pairs are conducting at any given time. 2. Switching Losses (PS) PS = (EON + EOFF) x fo EON = ts1 x VBUS x IOA / 6 EON = 200ns x 270V x 40A / 6 EON = .00045J 6 PTOTAL = Σ [ PQi] where i = each transistor/diode pair i =1 ton VBUS IOB IOA IO t s2 ts1 FIGURE 7. OUTPUT CHARACTERISTICS 7 June 13, 2000 Data Device Corporation APPLICATIONS: TABLE 5: PIN ASSIGNMENTS - PRELIMINARY (contact factory for latest pin assignment) PIN # 1 Figure 9A shows an example of position and/or velocity control hook-up with inner torque loop using the Digital Signal Processor (DSP) for motor control. Using software, the DSP can be implemented with one of a range of several motor control algorithms, such as SVM (Space Vector modulation) or other FO (Field Oriented) control depending on the specific application. FUNCTIONS DESCRIPTION PW-83075P6 PW-84075P6 PW-85075P6 DISABLE/RESET DISABLE/RESET DISABLE/RESET 2 VCC VCC VCC 3 UPPER UPPER UPPER 4 VCC RTN VCC RTN VCC RTN 5 LOWER LOWER LOWER 6 SLEEP MODE SLEEP MODE SLEEP MODE 7 SC FAULT SC FAULT SC FAULT 8 AUTO RESET AUTO RESET AUTO RESET 17 NC VREF REGEN BUS- 18 NC I_VOUT REGEN STATUS 19 NC I_ABSVAL NC 20 NC VDD OV ADJ 21 NC VDD RTN NC 22 NC OC FAULT VBUS+ 23 NC NC NC 24 NC NC NC 25 NC RSENSE- REGEN LOW 26 NC RSENSE+ REGEN BUS- 27 VBUS+ VBUS+ VBUS+ 28 OUTPUT OUTPUT OUTPUT 29 VBUS- VBUS- VBUS- Figure 9B shows an example of torque control loop with regenerative clamp protection using UC-1625, two PW-84075P6 and one PW-85075P6. Two PW-84075P6 (½ bridge with current sense) sense the current in motor phase A and C. I_ABSVAL pins on each of the PW-84075P6 can be tied together to generate a single composite analog output which is compared to the torque commanded input to produce an error signal. UC1625 use this error signal to regulate the output current (or torque) by controlling the duty cycle of the output transistors. For the case when the resolver/syncho are available instead of Hall-effect devices, the circuit shown in Figure 9C converts the resolver (sin and cos) signals to Hall signals which can used to commutate the output transistors. 8 June 13, 2000 Data Device Corporation 0.100 (2.54) 0.100 (TYP) (2.54) 16 EQ. PIN 0.100 CENTERS (2.54 CENTERS) 1 2 3 4 5 6 7 8 0.115 DIA (#4 SCREW) (2 PLACES) (2.92 DIA) TOP VIEW 0.120 (3.04) MOLDED IN METAL INSERT (2 PLACES) 29 28 TM MAGNUM MOTOR DRIVE 1.48 MAX (37.59) 0.800 (20.32) 0.738 (18.74 0.250 (6.35) 0.188 (4.77) 0.125 ( 3.17) 17 18 19 20 21 22 23 24 27 .940 1.140 (23.87) (28.95) PW-8X075P6-XXXX 26 S/N XXXX D/C XXXX 25 0.200 (5.08) 2.36 (59.94) 0.168 (4.26) 2.52 (64.00) 2.89 MAX (73.40) 0.250 X 0.03(THK) (5 PLACES) (6.35 X 0.76) 0.025 SQ. (16 PLACES) (0.635) SIDE VIEW 0.230 (5.84) 0.35 (8.89) 0.65 MAX (16.51) 0.220 (5.58) NOTES: 1. Dimensions are in inches (MM). FIGURE 8. PW-8X075P6 OUTLINE 9 June 13, 2000 Data Device Corporation June 13, 2000 Data Device Corporation MOTOR POWER SUPPLY +270V +5V POSITION OR VELOCITY COMMAND DSP MOTOR CONTROLLER C11 VCC UA LA C10 + SLEEP MODE VCC VCC RTN UPPER LOWER SC FAULT DISABLE/RESET AUTO RESET VBUS+ OUTPUT VBUS- PW-85075P6 REGEN BUSREGEN LOW REGEN STATUS OV ADJ (4) R20 R21(4) UB LB UC LC I_VOUT (A) VREF 10 VDD VDD RTN I_VOUT (C) SLEEP MODE VCC VBUS+ VCC RTN UPPER OUTPUT LOWER SC FAULT VBUSDISABLE/RESET AUTO RESET RSENSE+ I_VOUT RSENSEOCFAULT VREF PW-84075P6 VDD VDD RTN SLEEP MODE VBUS+ VCC VCC RTN OUTPUT UPPER LOWER VBUSSC FAULT DISABLE/RESET RSENSE+ AUTO RESET RSENSEI_VOUT OCFAULT VREF PW-84075P6 VDD VDD RTN RESOLVER C8 + C9 MOTOR POWER RTN R/D CONVERTER (see FIGURE 8D) NOTES: 1. C8 is a ceramic capacitor and should be selected per DDC Application Note AN/H-6, PW-82351 Motor Drive Power Supply, equation 1. 2. C9 is an electrolytic capacitor and should be selected per DDC Application Note AN/H-6, PW-82351 Motor Drive Power Supply, equation 1. 3. C10 is 22 µF, 15 V electolytic capacitor. C11 is 0.1 µF, 50 V ceramic capacitor. 4. Resistance and power of R20, R21 is application specific. FIGURE 9A. PW-8X075P6 POSITION OR VELOCITY HOOK-UP USING DSP MOTOR CONTROLLER June 13, 2000 Data Device Corporation +15V +5V C6 0.1µF (11) 11 R13 10K R14 10K (11) +5V R15 10K 14 +5V +5V R5 CD4050 2K R11 (10) (11) 1/6 (11) 1N746 3.3V 1N746 3.3V 10K CR5 (11) CR4 10M R6 1K R17 V- C7 10K 0.01µF LM741 R22 UC-1625 11 (10) 10K CD4049 R18 5K R12 10K (11) V- R23 100Ω 1/6 10K R8 Q1(9) V- 10K (8) R9 (10) LM741 10K(8) R21 10K (8) (11) VBUS+ OUTPUT VBUS- REGEN BUSREGEN LOW REGEN STATUS OV ADJ SLEEP MODE VCC VBUS+ VCC RTN UPPER OUTPUT LOWER SC FAULT VBUSDISABLE/RESET AUTO RESET RSENSE+ I_VOUT RSENSEOCFAULT VREF PW-84075P6 VDD VDD RTN I_ABSVAL (4) R20 HALL SUPPLY +5V R21(4) HB C8 + C9 HC HA MOTOR R19 10K (8) R10 10K (8) LM741 (10) (11) 10K (8) SLEEP MODE VCC VCC RTN UPPER LOWER SC FAULT DISABLE/RESET AUTO RESET PW-85075P6 1/6 CD4049 1/6 1M C10 + C11 19 18 MOTOR POWER SUPPLY +270V +5V SLEEP MODE VBUS+ VCC VCC RTN UPPER OUTPUT LOWER VBUSSC FAULT DISABLE/RESET RSENSE+ AUTO RESET RSENSEI_VOUT OCFAULT VREF PW-84075P6 VDD VDD RTN I_ABSVAL HALL RTN POWER RTN 5K COMMAND SIGNAL INPUT 10K (11) V- NOTES: 1. C8 is a ceramic capacitor and should be selected per DDC Application Note AN/H-6, PW-82351 Motor Drive Power Supply, equation 1. 2. C9 is an electrolytic capacitor and should be selected per DDC Application Note AN/H-6, PW-82351 Motor Drive Power Supply, equation 1. 3. C10 is 22 µF, 15 V electrolytic capacitor. C11 is 0.1 µF, 50 V ceramic capacitor. 4. Resistance and power of R20 and R21 is application specific. 5. All resistors have a tolerance of ±10%, unless otherwise specified. 6. The CD4050 converts the +15V logic output of the UC-1625 to +5V logic signals. 7. The CD4049 (or equivalent) inverts the upper signal from the UC-1625. 8. 1% or better, depending on required accuracy. 9. Q1 can be either IRML2402 or IRMU014 ir IRLD014. 10. These high impedance inputs and summing junctions of the operational amplifiers are highly sensitive to noise. 11. These grounds should be closely tied together to reduce ground noise effect. FIGURE 9B. PW-8X075P6 TORQUE HOOK-UP USING UC-1625 MOTOR CONTROLLER June 13, 2000 Data Device Corporation -5V +5V 40 15 C27 22µF C26 0.1µF CB 22 C29 22µF C28 0.1µF +5V +5V DDC RDC-19220 1 27 22 20 2 23 21 VPP PGM OE CE A12 A11 A10 24 A9 25 A8 3 A7 4 A6 5 A5 C30 0.1µF R27 120k C25 560pF R28 2.8 M -VCO 8 VEL C24 56pF 7 10 COS 11 -C 9 1 -VSUM 23 25 27 BIT 8 37 24 BIT 9 BIT 10 BIT 11 BIT 12 BIT 13 BIT 14 BIT 15 BIT 16 +C 2 12 RESOLVER INPUTS BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 29 31 6 A4 7 A3 8 A2 9 A1 10 A0 33 35 26 31 R33 10K 07 19 06 18 17 05 04 16 15 03 11 CLK 1 D7 18 D7 17 D6 14 D5 13 D4 8 D3 02 13 01 12 00 11 7 D2 4 D1 3 D0 35 37 24 19 16 15 12 9 6 Q2 5 Q1 2 Q0 74HCT374 27C64 33 Q7 Q6 Q5 Q4 Q3 HC HB HA HALL OUTPUTS R24 20K 6 26 +5V 13 R25 20K 3 4 SIN 14 -S 12 +S 19 AGND INH/ EL/ EM/ 20 R26 20K 5 4 2 16 1 +15 -15 +15V GND 1 C21 0.1µF SIN -15V +15V U6 4 C20 0.1µF DIGITAL POSITION & VELOCITY INFORMATION WHICH CAN BE USED BY THE DSP (FIGURE 8A) TO CLOSE THE POSITION AND/OR VELOCITY LOOPS +REF -REF BIT/ 21 R31 10K 2N2907 GND +15V 3 18 U3 5 EL2009 39 +15V R35 10K 6 3 GND SENSE 1 A 2 B CR7 13 8 RS 16 R29 0.1K 10 11 C22 0.1µF RC 17 R32 1K R30 0.1K C23 0.1µF 2 19 20 FIGURE 9C. RESOLVER TO HALL SIGNAL CONVERSION CIRCUIT ORDERING INFORMATION PW - 8 X 075 PX - X X 0 Process Requirements: 0 = Standard DDC Procedures no, Burn-In 2 = High Reliability Processing with Burn-In Temperature Grade/Data Requirements: 1 = -55°C to +125°C 3 = -0°C to +70°C 4 = -55°C to +125°C with Variables Test Data 8 = 0°C to +70°C with Variables Test Data 9 = -55°C to 85°C Voltage Rating 6 = 600V Current Rating 075 = 75A Features 3 = Standard ½ Bridge 4 = Standard ½ Bridge w/ current sense 5 = Standard ½ Bridge w/ regenerative voltage clamp The information in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. 105 Wilbur Place, Bohemia, New York 11716-2482 For Technical Support - 1-800-DDC-5757 ext. 7420 Headquarters - Tel: (631) 567-5600 ext. 7420, Fax: (631) 567-7358 Southeast - Tel: (703) 450-7900, Fax: (703) 450-6610 West Coast - Tel: (714) 895-9777, Fax: (714) 895-4988 Europe - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 Asia/Pacific - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 World Wide Web - http://www.ddc-web.com RM ® I FI REG U ST ERED DATA DEVICE CORPORATION REGISTERED TO ISO 9001 FILE NO. A5976 PRINTED IN THE U.S.A. 13 June 13, 2000 Data Device Corporation