STMICROELECTRONICS M27128A-20F1

M27128A
NMOS 128K (16K x 8) UV EPROM
FAST ACCESS TIME: 200ns
EXTENDED TEMPERATURE RANGE
SINGLE 5 V SUPPLY VOLTAGE
LOW STANDBY CURRENT: 40mA max
TTL COMPATIBLE DURING READ and
PROGRAM
28
FAST PROGRAMMING ALGORITHM
1
FDIP28W (F)
ELECTRONIC SIGNATURE
PROGRAMMING VOLTAGE: 12V
DESCRIPTION
The M27128A is a 131,072 bit UV erasable and
electrically programmable memory EPROM. It is
organized as 16,384 words by 8 bits.
The M27128A is housed in a 28 Pin Window Ceramic Frit-Seal Dual-in-Line package. The transparent lid allows the user to expose the chip to
ultraviolet light to erase the bit pattern. A new
pattern can then be written to the device by following the programming procedure.
Figure 1. Logic Diagram
VCC
VPP
14
8
A0-A13
Table 1. Signal Names
A0 - A13
Address Inputs
Q0 - Q7
Data Outputs
E
Chip Enable
G
Output Enable
P
Program
VPP
Program Supply
VCC
Supply Voltage
VSS
Ground
March 1995
P
Q0-Q7
M27128A
E
G
VSS
AI00769B
1/10
M27128A
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
Ambient Operating Temperature
grade 1
grade 6
0 to 70
–40 to 85
°C
TBIAS
Temperature Under Bias
grade 1
grade 6
–10 to 80
–50 to 95
°C
TSTG
Storage Temperature
–65 to 125
°C
VIO
Input or Output Voltages
–0.6 to 6.25
V
VCC
Supply Voltage
–0.6 to 6.25
V
VA9
A9 Voltage
–0.6 to 13.5
V
VPP
Program Supply
–0.6 to 14
V
TA
Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause
permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those
indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.
Figure 2. DIP Pin Connections
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7
22
M27128A
21
8
20
9
19
10
18
11
17
12
16
13
15
14
VCC
P
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5
Q4
Q3
AI00770
DEVICE OPERATION
The seven modes of operation of the M27128A are
listed in the Operating Modes table. A single 5V
power supply is required in the read mode. All
inputs are TTL levels except for VPP and 12V on A9
for Electronic Signature.
2/10
Read Mode
The M27128A has two control functions, both of
which must be logically satisfied in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, independent of device selection.
Assuming that the addresses are stable, address
access time (tAVQV) is equal to the delay from E to
output (tELQV). Data is available at the outputs after
the falling edge of G, assuming that E has been low
and the addresses have been stable for at least
tAVQV-tGLQV.
Standby Mode
The M27128A has a standby mode which reduces
the maximum active power current from 85mA to
40mA. The M27128A is placed in the standby mode
by applying a TTL high signal to the E input. When
in the standby mode, the outputs are in a high
impedance state, independent of the G input.
Two Line Output Control
Because EPROMs are usually used in larger memory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
M27128A
DEVICE OPERATION (cont’d)
For the most efficient use of these two control lines,
E should be decoded and used as the primary
device selecting function, while G should be made
a common connection to all devices in the array
and connected to the READ line from the system
control bus.
This ensures that all deselected memory devices
are in their low power standby mode and that the
output pins are only active when data is required
from a particular memory device.
System Considerations
The power switching characteristics of fast
EPROMs require careful decoupling of the devices.
The supply current, ICC, has three segments that
are of interest to the system designer: the standby
current level, the active current level, and transient
current peaks that are produced by the falling and
rising edges of E. The magnitude of this transient
current peaks is dependent on the capacitive and
inductive loading of the device at the output. The
associated transient voltage peaks can be suppressed by complying with the two line output
control and by properly selected decoupling capacitors. It is recommended that a 1µF ceramic
capacitor be used on every device between VCC
and VSS. This should be a high frequency capacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7µF bulk electrolytic capacitor should be used
between VCC and GND for every eight devices. The
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.
Programming
When delivered (and after each erasure for UV
EPPROM), all bits of the M27128A are in the “1"
state. Data is introduced by selectively programming ”0s" into the desired bit locations. Although
only “0s” will be programmed, both “1s” and “0s”
can be present in the data word. The only way to
change a “0" to a ”1" is by ultraviolet light erasure.
The M27128A is in the programming mode when
VPP input is at 12.5V and E and P are at TTL low.
The data to be programmed is applied 8 bits in
parallel, to the data output pins. The levels required
for the address and data inputs are TTL.
Fast Programming Algorithm
Fast Programming Algorithm rapidly programs
M27128A EPROMs using an efficient and reliable
method suited to the production programming environment. Programming reliability is also ensured
as the incremental program margin of each byte is
Table 3. Operating Modes
Mode
E
G
P
A9
VPP
Q0 - Q7
Read
VIL
VIL
VIH
X
VCC
Data Out
Output Disable
VIL
VIH
VIH
X
VCC
Hi-Z
Program
VIL
VIH
VIL Pulse
X
VPP
Data In
Verify
VIL
VIL
VIH
X
VPP
Data Out
Program Inhibit
VIH
X
X
X
VPP
Hi-Z
Standby
VIH
X
X
X
VCC
Hi-Z
Electronic Signature
VIL
VIL
VIH
VID
VCC
Codes Out
Note: X = VIH or VIL, VID = 12V ± 0.5%.
Table 4. Electronic Signature
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer’s Code
VIL
0
0
1
0
0
0
0
0
20h
Device Code
VIH
1
0
0
0
1
0
0
1
89h
3/10
M27128A
Figure 4. AC Testing Load Circuit
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
≤ 20ns
Input Pulse Voltages
0.45V to 2.4V
Input and Output Timing Ref. Voltages
0.8V to 2.0V
1.3V
1N914
Note that Output Hi-Z is defined as the point where data
is no longer driven.
3.3kΩ
Figure 3. AC Testing Input Output Waveforms
DEVICE
UNDER
TEST
2.4V
OUT
2.0V
CL = 100pF
0.8V
0.45V
AI00827
CL includes JIG capacitance
AI00828
Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
CIN
COUT
Parameter
Test Condition
Min
Max
Unit
VIN = 0V
=
6
pF
VOUT = 0V
=
12
pF
Input Capacitance
Output Capacitance
Note: 1. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
VALID
A0-A13
tAVQV
tAXQX
E
tEHQZ
tGLQV
G
tGHQZ
tELQV
Q0-Q7
Hi-Z
DATA OUT
AI00771
4/10
M27128A
Table 6. Read Mode DC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol
Parameter
Test Condition
Min
Max
Unit
0 ≤ VIN ≤ VCC
±10
µA
VOUT = VCC
±10
µA
E = VIL, G = VIL
75
mA
E = VIH
35
mA
VPP = VCC
5
mA
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
Supply Current
ICC1
Supply Current (Standby)
IPP
Program Current
VIL
Input Low Voltage
–0.1
0.8
V
VIH
Input High Voltage
2
VCC + 1
V
VOL
Output Low Voltage
IOL = 2.1mA
=
0.45
V
VOH
Output High Voltage
IOH = –400µA
2.4
V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Table 7. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol
Alt
Parameter
Test
Condition
M27128A
-2, -20
Min
Max
blank, -25
Min
Max
-3, -30
Min
Max
Unit
-4
Min
Max
tAVQV
tACC
Address Valid to
Output Valid
E = VIL,
G = VIL
200
250
300
450
ns
tELQV
tCE
Chip Enable Low to
Output Valid
G = VIL
200
250
300
450
ns
tGLQV
tOE
Output Enable Low
to Output Valid
E = VIL
75
100
120
150
ns
tEHQZ (2)
tDF
Chip Enable High to
Output Hi-Z
G = VIL
0
55
0
60
0
105
0
130
ns
tGHQZ (2)
tDF
Output Enable High
to Output Hi-Z
E = VIL
0
55
0
60
0
105
0
130
ns
tAXQX
tOH
Address Transition to
Output Transition
E = VIL,
G = VIL
0
0
0
0
ns
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
5/10
M27128A
Table 8. Programming Mode DC Characteristics (1)
(TA = 25 °C; VCC = 6V ± 0.25V; VPP = 12.5V ± 0.3V)
Symbol
Parameter
Test Condition
Min
VIL ≤ VIN ≤ VIH
Max
Unit
±10
µA
100
mA
50
mA
ILI
Input Leakage Current
ICC
Supply Current
IPP
Program Current
VIL
Input Low Voltage
–0.1
0.8
V
VIH
Input High Voltage
2
VCC + 1
V
VOL
Output Low Voltage
IOL = 2.1mA
0.45
V
VOH
Output High Voltage
IOH = –400µA
VID
A9 Voltage
E = VIL
2.4
V
11.5
12.5
V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Table 9. Programming Mode AC Characteristics (1)
(TA = 25 °C; VCC = 6V ± 0.25V; VPP = 12.5V ± 0.3V)
Symbol
Alt
tAVPL
tAS
Address Valid to Program Low
2
µs
tQVPL
tDS
Input Valid to Program Low
2
µs
tVPHPL
tVPS
VPP High to Program Low
2
µs
tVCHPL
tVCS
VCC High to Program Low
2
µs
tELPL
tCES
Chip Enable Low to Program
Low
2
µs
tPLPH
tPW
Program Pulse Width (Initial)
Note 2
0.95
1.05
ms
tPLPH
tOPW
Program Pulse Width
(Overprogram)
Note 3
2.85
78.75
ms
tPHQX
tDH
Program High to Input
Transition
2
µs
tQXGL
tOES
Input Transition to Output
Enable Low
2
µs
tGLQV
tOE
Output Enable Low to
Output Valid
tGHQZ (4)
tDFP
Output Enable High to
Output Hi-Z
0
tGHAX
tAH
Output Enable High to
Address Transition
0
Notes: 1.
2.
3.
4.
6/10
Parameter
Test Condition
Min
Max
Unit
150
ns
130
ns
ns
VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
The Initial Program Pulse width tolerance is 1 ms ± 5%.
The length of the Over-program Pulse varies from 2.85 ms to 78.95 ms, depending on the multiplication value of the iteration counter.
Sampled only, not 100% tested.
M27128A
Figure 6. Programming and Verify Modes AC Waveforms
VALID
A0-A13
tAVPL
Q0-Q7
DATA IN
tQVPL
DATA OUT
tPHQX
VPP
tVPHPL
tGLQV
tGHQZ
VCC
tVCHPL
tGHAX
E
tELPL
P
tPLPH
tQXGL
G
PROGRAM
VERIFY
AI00772
Figure 7. Programming Flowchart
DEVICE OPERATION (cont’d)
continually monitored to determine when it has
been successfully programmed. A flowchart of the
M27128A Fast Programming Algorithm is shown
on the last page. The Fast Programming Algorithm
utilizes two different pulse types: initial and overprogram.
VCC = 6V, VPP = 12.5V
n=1
P = 1ms Pulse
NO
++n
> 25
YES
NO
VERIFY
++ Addr
YES
The entire sequence of program pulses and byte
verifications is performed at VCC = 6V and VPP =
12.5V. When the Fast Programming cycle has been
completed, all bytes should be compared to the
original data with VCC = 5 and VPP = 5V.
P = 3ms Pulse by n
FAIL
Last
Addr
The duration of the initial P pulse(s) is 1ms, which
will then be followed by a longer overprogram pulse
of length 3ms by n (n is equal to the number of the
initial one millisecond pulses applied to a particular
M27128A location), before a correct verify occurs.
Up to 25 one-millisecond pulses per byte are provided for before the over program pulse is applied.
NO
Program Inhibit
YES
CHECK ALL BYTES
VCC = 5V, VPP 5V
AI00775B
Programming of multiple M27128A’s in parallel with
different data is also easily accomplished. Except
for E, all like inputs (including G) of the parallel
M27128A may be common. A TTL low pulse applied to a M27128A’s E input, with VPP = 12.5V, will
program that M27128A. A high level E input inhibits
the other M27128As from being programmed.
7/10
M27128A
Program Verify
A verify should be performed on the programmed
bits to determine that they were correctly programmed. The verify is accomplished with G = VIL,
E = VIL, P = VIH and VPP at 12.5V.
Electronic Signature
The Electronic Signature mode allows the reading
out of a binary code from an EPROM that will
identify its manufacturer and type. This mode is
intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
This mode is functional in the25°C ± 5°C ambient
temperature range that is required when programming the M27128A.
To activate this mode, the programming equipment
must force 11.5V to 12.5V on address line A9 of the
M27128A. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines
must be held at VIL during Electronic Signature
mode. Byte 0 (A0 = VIL) represents the manufacturer code and byte 1 (A0 = VIH) the device identifier
code. For the SGS-THOMSON M27128A, these
two identifier bytes are given below.
ERASURE OPERATION (applies to UV EPROM)
The erasure characteristic of the M27128A is such
that erasure begins when the cells are exposed to
light with wavelengths shorter than approximately
4000 Å. It should be noted that sunlight and some
type of fluorescent lamps have wavelengths in the
3000-4000 Å range. Research shows that constant
exposure to room level fluorescent lighting could
erase a typical M27128A in about 3 years, while it
would take approximately 1 week to cause erasure
when exposed to direct sunlight. If the M27128A is
to be exposed to these types of lighting conditions
for extended periods of time, it is suggested that
opaque labels be put over the M27128A window to
prevent unintentional erasure. The recommended
erasure procedure for the M27128A is exposure to
short wave ultraviolet light which has wavelength
2537 Å. The integrated dose (i.e. UV intensity x
exposure time) for erasure should be a minimum
of 15 W-sec/cm2. The erasure time with this dosage
is approximately 15 to 20 minutes using an ultraviolet lamp with 12000 µW/cm2 power rating. The
M27128A should be placed within 2.5cm (1 inch)
of the lamp tubes during the erasure. Some lamps
have a filter on their tubes which should be removed before erasure.
ORDERING INFORMATION SCHEME
Example:
M27128A
-2
Speed and VCC Tolerance
-2
200 ns, 5V ±5%
blank
250 ns, 5V ± 5%
-3
300 ns, 5V ± 5%
-4
450 ns, 5V ± 5%
-20
200 ns, 5V ± 10%
-25
250 ns, 5V ± 10%
-30
300 ns, 5V ± 10%
F
1
Package
F
FDIP28W
Temperature Range
1
0 to 70 °C
6
–40 to 85 °C
For a list of available options (Speed, VCC Tolerance, Package, etc...) refer to the current Memory Shortform
catalogue.
For further information on any aspect of this device, please contact SGS-THOMSON Sales Office nearest
to you.
8/10
M27128A
FDIP28W - 28 pin Ceramic Frit-seal DIP, with window
mm
Symb
Typ
inches
Min
Max
A
Typ
Min
5.71
Max
0.225
A1
0.50
1.78
0.020
0.070
A2
3.90
5.08
0.154
0.200
B
0.40
0.55
0.016
0.022
B1
1.17
1.42
0.046
0.056
C
0.22
0.31
0.009
0.012
D
38.10
1.500
E
15.40
15.80
0.606
0.622
E1
13.05
13.36
0.514
0.526
e1
2.54
–
–
0.100
–
–
e3
33.02
–
–
1.300
–
–
eA
16.17
18.32
0.637
0.721
L
3.18
4.10
0.125
0.161
S
1.52
2.49
0.060
0.098
∅
–
–
α
7.11
4°
15°
N
28
0.280
–
–
4°
15°
28
FDIP28W
A2
A1
B1
B
A
L
α
e1
eA
C
e3
D
S
N
∅
E1
E
1
FDIPW-a
Drawing is not to scale
9/10
M27128A
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
© 1995 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
10/10