M27V405 4 Mbit (512Kb x 8) Low Voltage OTP EPROM ■ LOW VOLTAGE READ OPERATION: 3V to 3.6V ■ FAST ACCESS TIME: 120ns ■ LOW POWER CONSUMPTION: – Active Current 15mA at 5MHz – Standby Current 20µA ■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V ■ PROGRAMMING TIMES: – Typical 48sec. (PRESTO II Algorithm) PLCC32 (K) TSOP32 (N) 8 x 20 mm – Typical 27sec. (On-Board Programming) ■ PIN COMPATIBLE with the 4 Mbit, Single Voltage Flash Memory ■ ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: B4 DESCRIPTION The M27V405 is a low voltage 4 Mbit EPROM offered in the OTP range (one time programmable). It is ideally suited for microprocessor systems requiring large data or program storage and is organised as 524,288 by 8 bits. The M27V405 operates in the read mode with a supply voltage as low as 3V. The decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery recharges. Figure 1. Logic Diagram VCC 19 A0-A18 Address Inputs Q0-Q7 Data Outputs E Chip Enable G Output Enable VPP Program Supply VCC Supply Voltage VSS Ground May 1998 8 A0-A18 E Table 1. Signal Names VPP Q0-Q7 M27V405 G VSS AI01800 1/13 M27V405 Figure 2B. TSOP Pin Connections A12 A15 A16 A18 VCC VPP A17 Figure 2A. LCC Pin Connections 1 32 A7 A6 A5 A4 A3 A2 A1 A0 Q0 9 M27V405 25 A14 A13 A8 A9 A11 G A10 E Q7 VSS Q3 Q4 Q5 Q6 Q1 Q2 17 AI01801 A11 A9 A8 A13 A14 A17 VPP VCC A18 A16 A15 A12 A7 A6 A5 A4 1 8 9 32 M27V405 (Normal) 25 24 16 17 G A10 E Q7 Q6 Q5 Q4 Q3 VSS Q2 Q1 Q0 A0 A1 A2 A3 AI01802 Table 2. Absolute Maximum Ratings (1) Symbol Value Unit Ambient Operating Temperature (3) –40 to 125 °C TBIAS Temperature Under Bias –50 to 125 °C TSTG Storage Temperature –65 to 150 °C VIO (2) Input or Output Voltage (except A9) –2 to 7 V Supply Voltage –2 to 7 V –2 to 13.5 V –2 to 14 V TA VCC VA9 (2) VPP Parameter A9 Voltage Program Supply Voltage Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is V CC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range. 2/13 M27V405 Table 3. Operating Modes E G A9 VPP Q0-Q7 Read VIL VIL X VCC or VSS Data Out Output Disable VIL VIH X VCC or VSS Hi-Z VIL Pulse VIH X VPP Data In Verify VIH VIL X VPP Data Out Program Inhibit VIH VIH X VPP Hi-Z Standby VIH X X VCC or VSS Hi-Z Electronic Signature VIL VIL VID VCC Codes Mode Program Note: X = VIH or VIL, V ID = 12V ± 0.5V. Table 4. Electronic Signature Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data Manufacturer’s Code VIL 0 0 1 0 0 0 0 0 20h Device Code VIH 1 0 1 1 0 1 0 0 B4h The M27V405 is pin compatible with the industry standard 4 Mbit, single voltage Flash Memory. It can be considered as a Flash Low Cost solution for production quantities. The M27V405 can also be operated as a standard 4 Mbit OTP EPROM (similar to M27C405) with a 5V power supply. The M27V405 is offered in PLCC32 and TSOP32 (12 x 20 mm) packages. DEVICE OPERATION The modes of operations of the M27V405 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for V pp and 12V on A9 for Electronic Signature. Read Mode The M27V405 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of t GLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. Standby Mode The M27V405 has a standby mode which reduces the active current from 15mA to 20µA with low voltage operation VCC ≤ 3.6V , see Read Mode DC Characteristics Table for details. The M27V405 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input. 3/13 M27V405 Table 5. AC Measurement Conditions High Speed Standard Input Rise and Fall Times ≤ 10ns ≤ 20ns Input Pulse Voltages 0 to 3V 0.4V to 2.4V 1.5V 0.8V and 2V Input and Output Timing Ref. Voltages Figure 3. AC Testing Input Output Waveform Figure 4. AC Testing Load Circuit 1.3V High Speed 1N914 3V 1.5V 3.3kΩ 0V DEVICE UNDER TEST Standard 2.4V OUT CL 2.0V 0.8V 0.4V AI01822 CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance AI01823B Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF Note: Sampled only, not 100% tested. Two Line Output Control Because OTP EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the 4/13 array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. System Considerations The power switching characteristics of Advanced CMOS OTP EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced M27V405 Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70°C, –20 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = V CC) Symbol Parameter Test Condition ILI Input Leakage Current ILO Output Leakage Current ICC Supply Current ICC1 Supply Current (Standby) TTL ICC2 Supply Current (Standby) CMOS IPP Program Current VIL Input Low Voltage VIH (2) Input High Voltage VOL Output Low Voltage Min Max Unit 0V ≤ VIN ≤ VCC ±10 µA 0V ≤ VOUT ≤ VCC ±10 µA E = VIL, G = VIL, IOUT = 0mA, f = 5MHz, VCC ≤ 3.6V 15 mA E = VIH 1 mA E > VCC – 0.2V, VCC ≤ 3.6V 20 µA VPP = VCC 10 µA –0.3 0.8 V 2 VCC + 1 V 0.4 V IOL = 2.1mA Output High Voltage TTL IOH = –400µA 2.4 V Output High Voltage CMOS IOH = –100µA VCC – 0.7V V VOH Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Maximum DC voltage on Output is VCC +0.5V. Table 8A. Read Mode AC Characteristics (1) (TA = 0 to 70°C, –20 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = V CC) M27V405 Symbol Alt Parameter Test Condition -120 Min -150 Max Min Unit Max E = VIL, G = VIL 120 150 ns Chip Enable Low to Output Valid G = VIL 120 150 ns tOE Output Enable Low to Output Valid E = VIL 60 80 ns tEHQZ (2) tDF Chip Enable High to Output Hi-Z G = VIL 0 50 0 50 ns tGHQZ (2) tDF Output Enable High to Output Hi-Z E = VIL 0 50 0 50 ns tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 0 tAVQV tACC Address Valid to Output Valid tELQV tCE tGLQV 0 ns Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested. by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between V CC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply connection point.The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. 5/13 M27V405 Table 8B. Read Mode AC Characteristics (1) (TA = 0 to 70°C, –20 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = V CC) M27V405 Symbol Alt Parameter Test Condition -180 Min -200 Max Min Unit Max E = VIL, G = VIL 180 200 ns Chip Enable Low to Output Valid G = VIL 180 200 ns tOE Output Enable Low to Output Valid E = VIL 90 100 ns tEHQZ (2) tDF Chip Enable High to Output Hi-Z G = VIL 0 50 0 70 ns tGHQZ (2) tDF Output Enable High to Output Hi-Z E = VIL 0 50 0 70 ns tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 0 tAVQV tACC Address Valid to Output Valid tELQV tCE tGLQV 0 ns Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested Figure 5. Read Mode AC Waveforms A0-A18 VALID tAVQV VALID tAXQX E tGLQV tEHQZ G tELQV Q0-Q7 tGHQZ Hi-Z AI00724B 6/13 M27V405 Table 9. Programming Mode DC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V) Symbol Parameter Test Condition Min 0 ≤ VIN ≤ VCC Max Unit ±10 µA 50 mA 50 mA ILI Input Leakage Current ICC Supply Current IPP Program Current VIL Input Low Voltage –0.3 0.8 V VIH Input High Voltage 2 VCC + 0.5 V VOL Output Low Voltage 0.4 V VOH Output High Voltage TTL VID A9 Voltage E = VIL IOL = 2.1mA IOH = –400µA 2.4 V 11.5 12.5 V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. Table 10. Programming Mode AC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V) Symbol Alt Parameter Test Condition Min Max tAVEL tAS Address Valid to Chip Enable Low 2 µs tQVEL tDS Input Valid to Chip Enable Low 2 µs tVPHEL tVPS VPP High to Chip Enable Low 2 µs tVCHEL tVCS VCC High to Chip Enable Low 2 µs tELEH tPW Chip Enable Program Pulse Width 95 tEHQX tDH Chip Enable High to Input Transition 2 µs tQXGL tOES Input Transition to Output Enable Low 2 µs tGLQV tOE Output Enable Low to Output Valid tGHQZ tDFP Output Enable High to Output Hi-Z 0 tGHAX tAH Output Enable High to Address Transition 0 105 Unit µs 100 ns 130 ns ns Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested. Programming The M27V405 has been designed to be fully compatible with the M27C405 and has the same electronic signature. As a result the M27V405 can be programmed as the M27C405 on the same programming equipments applying 12.75V on VPP and 6.25V on VCC by the use of the same PRESTO II algorithm. When delivered, all bits of the M27V405 are in the ’1’ state.Data is introduced by selectively programming ’0’s into the desired bit lo- cations. Although only ’0’s will be programmed, both ’1’s and ’0’s can be present in the data word. The M27V405 is in the programming mode when VPP input is at 12.75V, G is at VIH and E is pulsed to VIL. The data to be programmed is applied to 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. VCC is specified to be 6.25V±0.25V, but it can be set to lower values in case of On-Board Programming (see dedicated paragraph). 7/13 M27V405 Figure 6. Programming and Verify Modes AC Waveforms VALID A0-A18 tAVPL Q0-Q7 DATA IN tQVEL DATA OUT tEHQX VPP tVPHEL tGLQV tGHQZ VCC tVCHEL tGHAX E tELEH tQXGL G PROGRAM VERIFY AI00725 PRESTO II Programming Algorithm PRESTO II Programming Algorithm allows the whole array to be programmed with a guaranteed margin, in a typical time of 52.5 seconds. Programming with PRESTO II consists of applying a sequence of 100ms program pulses to each byte until a correct verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE circuit is automatically activated in order to guarantee that each cell is programmed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE provides the necessary margin to each programmed cell. Program Inhibit Programming of multiple M27V405s in parallel with different data is also easily accomplished. Except for E, all like inputs including G of the parallel M27V405 may be common. A TTL low level pulse applied to a M27V405’s E input, with VPP at 12.75V, will program that M27V405. A high level E input inhibits the other M27V405s from being programmed. 8/13 Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with G at VIL , E at VIH, VPP at 12.75V and VCC at 6.25V. On-Board Programming Programming the M27V405 may be performed directly in the application circuit, however this requires modification to the PRESTO II Algorithm (see Figure 8). For in-circuit programming VCC is determined by the user and normally is compatible with other components using the same supply voltage. It is recommended that the maximum value of VCC which remains compatible with the circuit is used. Typically V CC=5.5V for programming systems using VCC=5V, and VCC=3.5V for low voltage 3V systems is recommended. The value of VCC does not affect the programming, it gives a higher test capability in VERIFY mode. VPP must be kept at 12.75 volts to maintain and enable the programming. M27V405 Figure 7. Programming Flowchart Figure 8. On-Board Programming Flowchartt VPP = 12.75V VCC = 6.25V, VPP = 12.75V SET MARGIN MODE n=0 n=0 E = 100µs Pulse E = 10µs Pulse NO ++n = 25 YES FAIL NO NO VERIFY ++ Addr YES Last Addr ++n = 25 YES NO NO VERIFY ? YES ++ Addr E = 10µs Pulse FAIL YES Last Addr CHECK ALL BYTES 1st: VCC = 6V 2nd: VCC = 4.2V NO YES AI00760B CHECK ALL BYTES VPP = VCC AI01349 Warning: compatibility with Flash Memory Compatibility issues may arise when replacing the compatible Single Supply 4 Mbit Flash Memory (the M29F040) by the M27V405. The VPP pin of the M27V405 corresponds to the "W" pin of the M29F040. The M27V405 VPP pin can withstand voltages up to 12.75V, while the "W" pin of the M29F040 is a normal control signal input and may be damaged if a high voltage is applied; special precautions must be taken when programming in-circuit. However if an already programmed M27V405 is used, this can be directly put in place of the Flash Memory as the VPP input, when not in programming mode, is set to VCC or VSS. Changes to PRESTO II . The duration of the programming pulse is reduced to 20µs, making the programming time of the M27V405 comparable with the counterpart Flash Memory. Electronic Signature The Electronic Signature (ES) mode allows the reading out of a binary code from an OTP EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the M27V405. To activate the ES mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the M27V405 with V PP=VCC=5V. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from V IL to VIH. All other address lines must be held at V IL during Electronic Signature mode. Byte 0 (A0=V IL) represents the manufacturer code and byte 1 (A0=V IH) the device identifier code. For the STMicroelectronics M27V405, these two identifier bytes are given in Table 4 and can be read-out on outputs Q0 to Q7. 9/13 M27V405 Table 11. Ordering Information Scheme Example: M27V405 -120 K 1 TR Device Type Speed -120 = 120 -150 = 150 -180 = 180 -200 = 200 ns ns ns ns Package K = PLCC32 N = TSOP32: 8 x 20mm Temperature Range 1 = –0 to 70 °C 4 = –20 to 70 °C 5 = –20 to 85 °C 6 = –40 to 85 °C Option TR = Tape & Reel Packing For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 10/13 M27V405 Table 12. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data Symb mm Min Max Min Max A 2.54 3.56 0.100 0.140 A1 1.52 2.41 0.060 0.095 A2 – 0.38 – 0.015 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430 E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530 – – – – 0.00 0.25 0.000 0.010 – – – – e Typ inches 1.27 F R 0.89 Typ 0.050 0.035 N 32 32 Nd 7 7 Ne 9 9 CP 0.10 0.004 Figure 9. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline D D1 A1 A2 1 N B1 E1 E Ne e D2/E2 F B 0.51 (.020) 1.14 (.045) A Nd R CP PLCC Drawing is not to scale. 11/13 M27V405 Table 13. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data mm inches Symb Typ Min Max A Typ Min 1.20 0.047 A1 0.05 0.15 0.002 0.007 A2 0.95 1.05 0.037 0.041 B 0.15 0.27 0.006 0.011 C 0.10 0.21 0.004 0.008 D 19.80 20.20 0.780 0.795 D1 18.30 18.50 0.720 0.728 E 7.90 8.10 0.311 0.319 – – – – L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N 32 e 0.50 0.020 32 CP 0.10 0.004 Figure 10. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline A2 1 N e E B N/2 D1 A CP D DIE C TSOP-a Drawing is not to scale. 12/13 Max A1 α L M27V405 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 1998 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. 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