STMICROELECTRONICS M58PV001LE96ZB5

M58PR256LE
M58PR512LE M58PR001LE
256-Mbit, 512-Mbit or 1-Gbit (× 16, multiple bank, multilevel, burst)
1.8 V supply Flash memories
Features
■
Supply voltage
– VDD = 1.7 V to 2.0 V for program, erase
and read
– VDDQ = 1.7 V to 2.0 V for I/O buffers
– VPP = 9 V for fast program
■
Synchronous/asynchronous read
– Synchronous burst read mode:
108 MHz, 66 MHz
– Asynchronous page read mode
– Random access: 96 ns
■
Programming time
– 4.2 µs typical word program time using
Buffer Enhanced Factory Program
command
■
Memory organization
– Multiple bank memory array:
32 Mbit banks (256 Mb devices)
64 Mbit banks (512 Mb devices)
128 Mbit banks (1 Gb devices)
– Four EFA (extended flash array) blocks of
64 Kbits
■
Dual operations
– Program/erase in one bank while read in
others
– No delay between read and write
operations
■
Block locking
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WP for block lock-down
– Absolute Write protection with VPP = VSS
Wafer
■
Security
– 64 bit unique device number
– 2112 bit user programmable OTP cells
■
CFI (common Flash interface)
■
100 000 program/erase cycles per block
■
Electronic signature
– Manufacturer code: 20h
– 256 Mbit device: 8818
– 512 Mbit device: 8819
– 1 Gbit device: 880F
The M58PRxxxLE memories are only available as part of a multichip package device.
September 2007
Rev 2
1/119
www.st.com
1
Contents
M58PR256LE, M58PR512LE, M58PR001LE
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
4
2/119
2.1
Address inputs (A0-Amax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2
Data inputs/outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6
Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7
Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8
Deep power-down (DPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.9
Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.10
Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.11
Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.12
VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.13
VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.14
VPP program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.15
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.16
VSSQ ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1
Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2
Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3
Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7
Deep power-down (DPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1
Read Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2
Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M58PR256LE, M58PR512LE, M58PR001LE
5
Contents
4.3
Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4
Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5
Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.6
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.7
Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.8
Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.9
Buffer Enhanced Factory Program command . . . . . . . . . . . . . . . . . . . . . 27
4.9.1
Setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.9.2
Program and verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.9.3
Exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.10
Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.11
Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.12
Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.13
Set Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.14
Block Lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.15
Block Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.16
Block Lock-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.17
Blank Check command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.18
Set Enhanced Configuration Register command . . . . . . . . . . . . . . . . . . . 33
4.19
Read EFA Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.20
Program EFA Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.21
Erase EFA Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.22
Suspend EFA Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.23
Resume EFA Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.24
Lock EFA Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.25
Unlock EFA Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.26
Lock-down EFA Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1
Program regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2
Program modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.3
5.2.1
Control program mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2.2
Object program mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Program methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3/119
Contents
6
7
8
M58PR256LE, M58PR512LE, M58PR001LE
5.3.1
Single word program method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.2
Buffer program method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.3
Buffer enhanced factory program method . . . . . . . . . . . . . . . . . . . . . . . 45
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.1
Control program mode status bit (SR9) . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.2
Object program mode status bit (SR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.3
Program/Erase Controller status bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . 47
6.4
Erase suspend status bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.5
Erase status bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.6
Program status bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.7
VPP status bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.8
Program Suspend Status bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.9
Block protection status bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.10
Bank write/multiple word program status bit (SR0) . . . . . . . . . . . . . . . . . 49
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.1
Read select bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.2
X latency bits (CR14-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.3
Wait polarity bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.4
Wait configuration bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.5
Burst length bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Enhanced Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1
Deep power-down mode bit (ECR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.2
Deep power-down polarity bit (ECR14) . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.3
Output driver control bits (ECR2-ECR0) . . . . . . . . . . . . . . . . . . . . . . . . . 56
9
Extended Flash array (EFA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10
Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4/119
10.1
Asynchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.2
Synchronous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.3
Single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
M58PR256LE, M58PR512LE, M58PR001LE
Contents
11
Dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 61
12
Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.1
Reading a block’s lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.2
Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.3
Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.4
Lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.5
Locking operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . . . 64
13
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 66
14
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
15
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
16
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Appendix B Common Flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Appendix C Flowcharts and pseudocodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Appendix D Command interface state tables. . . . . . . . . . . . . . . . . . . . . . . . . . . 111
17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5/119
List of tables
M58PR256LE, M58PR512LE, M58PR001LE
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
6/119
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
M58PR256LE bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
M58PR512LE bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
M58PR001LE bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
EFA memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Factory Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Protection Register locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Program methods available with each program mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Relationships between program methods and program modes . . . . . . . . . . . . . . . . . . . . . 45
Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
X latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Enhanced Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Program/erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DC characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
DC characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Asynchronous read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Synchronous read AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Write AC characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Reset and power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Deep power-down AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
M58PR256LE - bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
M58PR512LE - bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
M58PR001LE - bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
M58PR256LE - block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
M58PR512LE - block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
M58PR001LE - block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Protection Register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Burst Read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
M58PR256LE, M58PR512LE, M58PR001LE
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
List of tables
Bank and erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Extended Flash array bank and erase block region information. . . . . . . . . . . . . . . . . . . . . 99
Extended Flash array bank and erase block region 1 information . . . . . . . . . . . . . . . . . . 100
Command interface states - modify table, next state 1. . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Command interface states - modify table, next state 2. . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Command interface states - modify table, next output 1 . . . . . . . . . . . . . . . . . . . . . . . . . 115
Command interface states - modify table, next output 2 . . . . . . . . . . . . . . . . . . . . . . . . . 116
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7/119
List of figures
M58PR256LE, M58PR512LE, M58PR001LE
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
8/119
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Main array architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Program regions configured in control or object program mode. . . . . . . . . . . . . . . . . . . . . 43
X latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Asynchronous random access read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Asynchronous page read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Synchronous burst read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Single synchronous read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Clock input AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Write AC waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Reset and power-up AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Deep power-down AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Reset during deep power-down AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Program and EFA block program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . 102
Buffer program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Program suspend and resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . 104
Block erase and EFA block erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . 105
Erase suspend and resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Main array and EFA locking operations flowchart and pseudocode . . . . . . . . . . . . . . . . . 107
Blank check flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Protection Register program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . 109
Buffer enhanced factory program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . 110
M58PR256LE, M58PR512LE, M58PR001LE
1
Description
Description
The M58PR256LE, M58PR512LE and M58PR001LE are 256 Mbit (16 Mbit x 16), 512 Mbit
(32 Mbit x 16) and 1 Gbit (64 Mbit x 16) non-volatile Flash memories. They are referred to
as M58PRxxxLE in the rest of the document, unless otherwise specified.
The M58PRxxxLE may be erased electrically at block level and programmed in-system on a
word-by-word basis using a 1.7 V to 2.0 V VDD supply for the circuitry and a 1.7 V to 2.0 V
VDDQ supply for the input/output pins. An optional 9 V VPP power supply is provided to
speed up factory programming.
The M58PRxxxLE has a uniform block architecture and is based on a multilevel cell
technology:
●
The M58PR256LE has an array of 128 blocks, and is divided into 32 Mbit banks. There
are 8 banks each containing 16 blocks of 128 KWords.
●
The M58PR512LE has an array of 256 blocks, and is divided into 64 Mbit banks. There
are 8 banks each containing 32 blocks of 128 KWords.
●
The M58PR001LE has an array of 512 blocks, and is divided into 128 Mbit banks.
There are 8 banks each containing 64 blocks of 128 KWords.
Each block contains 256 program regions of 1 Kbyte each, that are divided into 32
segments of 16 words. Each segment is split into two halves (A and B), according by the
value on address input A3.
The memory map is illustrated in Figure 2 and the main array architecture in Figure 3.
The multiple bank architecture allows dual operations. While programming or erasing in one
bank, read operations are possible in other banks. Only one bank at a time is allowed to be
in program or erase mode. It is possible to perform burst reads that cross bank boundaries.
The bank architecture is summarized in Table 2, and the memory maps are shown in
Figure 2.
Each block can be erased separately. Erase can be suspended to perform a program or
read operation in any other block, and then resumed. Program can be suspended to read
data at any memory location except for the one being programmed, and then resumed.
Each block can be programmed and erased over 100 000 cycles using the supply voltage
VDD. There is a buffer enhanced factory programming command available to speed up
programming.
Program and erase commands are written to the command interface of the memory. An
internal Program/Erase Controller takes care of the timings necessary for program and
erase operations. The end of a program or erase operation can be detected and any error
conditions identified in the Status Register. The command set required to control the
memory is consistent with JEDEC standards.
The device supports synchronous burst read and asynchronous read from all blocks of the
memory array; at power-up the device is configured for asynchronous read. In synchronous
burst read mode, data is output on each clock cycle at frequencies of up to 108 MHz.
The device features an Automatic standby mode and deep power-down mode. When the
bus is inactive during asynchronous read operations, the device automatically switches to
automatic standby mode. In this state the power consumption is reduced to the standby
value and the outputs are still driven.
9/119
Description
M58PR256LE, M58PR512LE, M58PR001LE
The DPD (deep power-down) mode starts when the device is properly configured (ECR bit
15 is set) and the DPD signal is asserted. In DPD mode the device has the lowest power
consumption.
The M58PRxxxLE features an instant, individual block locking scheme that allows any block
to be locked or unlocked with no latency, enabling instant code and data protection. All
blocks have three levels of protection. They can be locked and locked-down individually
preventing any accidental programming or erasure. There is an additional hardware
protection against program and erase. When VPP ≤ VPPLK all blocks are protected against
program or erase. All blocks are locked at power-up.
In addition to the main memory array, the M58PRxxxLE features an extended flash array
(EFA) divided into 4 blocks of 64 Kbits each.
The EFA blocks are accessed through a separate set of commands. The operations
available in the EFA blocks are asynchronous read (in non-page mode), single word
program, erase and block locking. See Section 4: Command interface for details of the EFA
commands set.
See Table 5 for an extended flash array memory map. Table 19 and Table 20 describe the
simultaneous operations allowed in the EFA blocks and the main memory array.
The device includes 17 protection registers and 2 protection register locks, one for the first
protection register and the other for the 16 OTP (one-time-programmable) protection
registers of 128 bits each. The first protection register is divided into two areas: a 64-bit area
containing a unique device number written by ST, and a 64-bit area one-time-programmable
by the user. The user programmable area can be permanently protected. Figure 4, shows
the Protection Register memory map.
The memory is supplied with all the bits erased (set to ’1’).
Note:
10/119
The M58PRxxxLE memories are only available as part of a MCP (multichip package)
device.
M58PR256LE, M58PR512LE, M58PR001LE
Figure 1.
Description
Logic diagram
VDD VDDQ VPP
16
A0-Amax
DQ0-DQ15
W
E
G
RP
WAIT
M58PR256LE
M58PR512LE
M58PR001LE
WP
L
K
DPD
VSS
Table 1.
VSSQ
AI12816b
Signal names
Signal name
Function
Direction
A0-Amax(1)
Address inputs
Inputs
DQ0-DQ15
Data input/outputs, command inputs
I/O
E
Chip Enable
Input
G
Output Enable
Input
W
Write Enable
Input
RP
Reset
Input
WP
Write Protect
Input
K
Clock
Input
L
Latch Enable
Input
WAIT
Wait
Output
DPD
Deep power-down
Input
VDD
Supply voltage
VDDQ
Supply voltage for input/output buffers
VPP
Optional supply voltage for fast program and erase
VSS
Ground
VSSQ
Ground input/output supply
1. Amax is equal to A23 in the M58PR256LE, to A24 in the M58PR512LE, and to A25 in the M58PR001LE.
11/119
Description
M58PR256LE, M58PR512LE, M58PR001LE
12/119
32 Mbits
16 blocks of 128 KWords
Bank 1
32 Mbits
16 blocks of 128 KWords
Bank 2
32 Mbits
16 blocks of 128 KWords
----
Bank 0
----
Blocks
----
Bank size
Bank 7
32 Mbits
16 blocks of 128 KWords
M58PR512LE bank architecture
Blocks
Bank 0
64 Mbits
32 blocks of 128 KWords
Bank 1
64 Mbits
32 blocks of 128 KWords
Bank 2
64 Mbits
32 blocks of 128 KWords
----
Bank size
----
Number
Bank 7
64 Mbits
32 blocks of 128 KWords
M58PR001LE bank architecture
Bank size
Blocks
Bank 0
128 Mbits
64 blocks of 128 KWords
Bank 1
128 Mbits
64 blocks of 128 KWords
Bank 2
128 Mbits
64 blocks of 128 KWords
----
Number
----
Table 4.
Number
----
Table 3.
M58PR256LE bank architecture
----
Table 2.
Bank 7
128 Mbits
64 blocks of 128 KWords
M58PR256LE, M58PR512LE, M58PR001LE
Figure 2.
Description
Memory map
M58PR512LE
Address lines A24-A0
M58PR256LE
Address lines A23-A0
000000h
01FFFFh
128 Kword
16 blocks
0000000h
001FFFFh
128 Kword
03E0000h
03FFFFFh
128 Kword
1C00000h
1C1FFFFh
128 Kword
1FE0000h
1FFFFFFh
128 Kword
32 blocks
Bank 0
Bank 0
1E0000h
1FFFFFh
128 Kword
E00000h
E1FFFFh
128 Kword
16 blocks
32 blocks
Bank 7
Bank 7
FE0000h
FFFFFFh
128 Kword
M58PR001LE
Address lines A25-A0
0000000h
001FFFFh
128 Kword
07E0000h
07FFFFFh
128 Kword
3800000h
381FFFFh
128 Kword
3FE0000h
3FFFFFFh
128 Kword
64 blocks
Bank 0
64 blocks
Bank 7
AI12817b
Table 5.
EFA memory map
EFA block
Size
Address range
3
4 KWords (64 Kbits)
0003000 - 0003FFF
2
4 KWords (64 Kbits)
0002000 - 0002FFF
1
4 KWords (64 Kbits)
0001000 - 0001FFF
0
4 KWords (64 Kbits)
0000000 - 0000FFF
13/119
Description
M58PR256LE, M58PR512LE, M58PR001LE
Figure 3.
Main array architecture
MAIN ARRAY
128 Kword block
..
.
Bank 0
128 Kword block
BLOCK
Program region 0
512 words
Program region 1
512 words
..
.
PROGRAM REGION
Segment 31 - 16 words
Segment 30 - 16 words
..
.
Segment 2 - 16 words
..
.
Program region 254
512 words
Program region 255
512 words
Segment 1 - 16 words
Segment 0 - 16 words
128 Kword block
Bank 7
..
.
128 Kword block
256 Mbits, 512 Mbits
or 1 Gbits
ai12886
14/119
M58PR256LE, M58PR512LE, M58PR001LE
2
Signal descriptions
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals
connected to this device.
2.1
Address inputs (A0-Amax)
Amax is the highest order address input. Amax is A23 in the M58PR256LE, A24 in the
M58PR512LE, and A25 in the M58PR001LE. The address inputs select the cells in the
memory array to access during bus read operations. During bus write operations they
control the commands sent to the command interface of the Program/Erase Controller.
2.2
Data inputs/outputs (DQ0-DQ15)
The data I/O output the data stored at the selected address during a bus read operation or
input a command or the data to be programmed during a bus write operation.
2.3
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active
mode. When Chip Enable is at VIH the memory is deselected, the outputs are high
impedance and the power consumption is reduced to the standby level.
2.4
Output Enable (G)
The Output Enable input controls data outputs during the bus read operation of the memory.
2.5
Write Enable (W)
The Write Enable input controls the bus write operation of the memory’s command interface.
The data and address inputs are latched on the rising edge of Chip Enable or Write Enable,
whichever occurs first.
2.6
Write Protect (WP)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is at VIL, the lock-down is enabled and the protection status of the lockeddown blocks cannot be changed. When Write Protect is at VIH, the lock-down is disabled
and the locked-down blocks can be locked or unlocked (refer to Table 22: Lock status).
15/119
Signal descriptions
2.7
M58PR256LE, M58PR512LE, M58PR001LE
Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the
memory is in reset mode, this means the outputs are high impedance and the current
consumption is reduced to the reset supply current IDD2. Refer to Table 27: DC
characteristics - currents for the value of IDD2. After Reset, all blocks are in the locked state
and the Configuration Register is reset. When Reset is at VIH, the device is in normal
operation. Exiting reset mode the device enters asynchronous read mode, but a negative
transition of Chip Enable or Latch Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3 V logic without any additional circuitry, and can be
tied to VRPH (refer to Table 28: DC characteristics - voltages).
2.8
Deep power-down (DPD)
The deep power-down input is used to put the device in deep power-down mode.
When the device is in Standby mode and the Enhanced Configuration Register bit ECR15 is
set, asserting the deep power-down input will cause the memory to enter the deep powerdown mode.
When the device is in the deep power-down mode, the memory cannot be modified and the
data is protected.
The polarity of the DPD pin is determined by ECR14. The deep power-down input is active
Low by default.
2.9
Latch Enable (L)
Latch Enable latches the address bits on its rising edge. The address latch is transparent
when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. Latch Enable can
be kept Low (also at board level) when the Latch Enable function is not required or
supported.
2.10
Clock (K)
The clock input synchronizes the memory to the microcontroller during synchronous read
operations; the address is latched on a Clock edge when Latch Enable is at VIL. Clock is
ignored during asynchronous read and in write operations.
2.11
Wait (WAIT)
Wait is an output signal used during synchronous read to indicate whether the data on the
output bus are valid. This output is high impedance when Chip Enable is at VIH, Output
Enable is at VIH, or Reset is at VIL. It can be configured to be active during the wait cycle or
one data cycle in advance.
16/119
M58PR256LE, M58PR512LE, M58PR001LE
2.12
Signal descriptions
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main
power supply for all operations (Read, Program and Erase).
2.13
VDDQ supply voltage
VDDQ provides the power supply to the I/O pins and enables all outputs to be powered
independently of VDD. VDDQ can be tied to VDD or can use a separate supply.
VDDQ is sampled at the beginning of program/erase operations. If VDDQ is lower than VLKOQ,
the device is reset.
2.14
VPP program supply voltage
VPP is both a control input and a power supply pin. The two functions are selected by the
voltage range applied to the pin.
If VPP is kept in a low voltage range (0 V to VDDQ) VPP is seen as a control input. In this case
a voltage lower than VPPLK gives an absolute protection against program or erase, while
VPP > VPP1 enables these functions (see Tables 27 and 28, DC characteristics for the
relevant values). VPP is only sampled at the beginning of a program or erase; a change in its
value after the operation has started does not have any effect and program or erase
operations continue.
If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be
stable until the program/erase algorithm is completed.
2.15
VSS ground
VSS ground is the reference for the core supply. It must be connected to the system ground.
2.16
VSSQ ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be
connected to VSS.
Note:
Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1 µF ceramic
capacitor close to the pin (high frequency, inherently low inductance capacitors should be as
close as possible to the package). See Figure 9: AC measurement load circuit. The PCB
track widths should be sufficient to carry the required VPP program and erase currents.
17/119
Bus operations
3
M58PR256LE, M58PR512LE, M58PR001LE
Bus operations
There are seven standard bus operations that control the device. These are Bus Read, Bus
Write, Address Latch, Output Disable, Standby, Reset and deep power-down. See Table 6:
Bus operations, for a summary.
Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the
memory and do not affect bus write operations.
3.1
Bus Read
Bus Read operations are used to output the contents of the memory array, the Electronic
signature, the Status Register and the common Flash interface. Both Chip Enable and
Output Enable must be at VIL in order to perform a read operation. The Chip Enable input
should be used to enable the device. Output Enable should be used to gate data onto the
output. The data read depends on the previous command written to the memory (see
Section 4: Command interface). See figures 10, 11, 12 and 13, Read AC waveforms, and
tables 29 and 30, Read AC characteristics, for details of when the output becomes valid.
3.2
Bus Write
Bus Write operations write commands to the memory or latch input data to be programmed.
A Bus Write operation is initiated when Chip Enable and Write Enable are at VIL with Output
Enable at VIH. Commands, input data and addresses are latched on the rising edge of Write
Enable or Chip Enable, whichever occurs first. The addresses can also be latched prior to
the Write operation by toggling Latch Enable. In this case the Latch Enable should be tied to
VIH during the Bus Write operation.
See figures 15 and 16, Write AC waveforms, and tables 31 and 32, Write AC characteristics,
for details of the timing requirements.
3.3
Address Latch
Address Latch operations input valid addresses. Both Chip Enable and Latch Enable must
be at VIL during Address Latch operations. The addresses are latched on the rising edge of
Latch Enable.
3.4
Output Disable
The outputs are high impedance when the Output Enable is at VIH.
18/119
M58PR256LE, M58PR512LE, M58PR001LE
3.5
Bus operations
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current
consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power
consumption is reduced to the standby level IDD3 and the outputs are set to high impedance,
independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH
during a program or erase operation, the device enters Standby mode when finished.
3.6
Reset
During Reset mode the memory is deselected and the outputs are high impedance. The
memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the
reset level, independently from the Chip Enable, Output Enable or Write Enable inputs. If
Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory
content is no longer valid.
3.7
Deep power-down (DPD)
The memory enters the deep power-down mode from the Standby mode (RP and E are deasserted, VIH) by setting ECR15 High (set to ‘1’) and asserting the DPD pin (these two
events can be done in any order).
The DPD pin polarity is determined by the value of ECR14 when:
●
ECR14 is cleared (‘0’) the DPD pin is active Low. The DPD pin is active Low by default.
●
ECR14 is set (‘1’), the DPD pin is active High.
While in DPD mode, the:
●
Values of the Configuration Register, Enhanced Configuration Register, block lock bits,
and bank states are preserved.
●
Status Register is reset to 80h.
If the Status Register contains errors before entering the DPD mode, the error bits are lost
after exiting DPD mode.
The device should not be put in deep power-down mode while a program, erase or suspend
operation is in progress, otherwise the operation aborts, and the memory contents are no
longer valid.
The deep power-down mode is exited tDPHEL after de-asserting the DPD pin. Upon exiting
the deep power-down mode, the memory reverts to standby mode.
If the RP pin is asserted while in DPD mode, the device exits DPD mode after tPHEL and
ECR15 is reset to 0.
19/119
Bus operations
Table 6.
M58PR256LE, M58PR512LE, M58PR001LE
Bus operations(1)
E
G
W
L
RP
DPD(2)
Bus Read
VIL
VIL
VIH
VIL(4)
VIH
Deasserted(5)
Data output
Bus Write
VIL
VIH
VIL
VIL(4)
VIH
Deasserted(5)
Data input
Address Latch
VIL
X
VIH
VIL
VIH
Deasserted(5)
Data output or Hi-Z(6)
Output Disable
VIL
VIH
VIH
X
VIH
Deasserted(5)
Hi-Z
Hi-Z
Standby
VIH
X
X
X
VIH
Deasserted(5)
Hi-Z
Hi-Z
X
X
X
X
VIL
Deasserted(5)
Hi-Z
Hi-Z
VIH
X
X
X
VIH
Asserted(7)
Hi-Z
Hi-Z
Operation
Reset
Deep Powerdown
WAIT(3)
DQ15-DQ0
1. X = Don't care.
2. The DPD signal polarity depends on the value of the ECR14 bit.
3. WAIT signal polarity is configured using the Set Configuration Register command.
4. L can be tied to VIH if the valid address has been previously latched.
5. If ECR15 is set to '0', the device cannot enter the deep power-down mode, even if DPD is asserted.
6. Depends on G.
7. ECR15 has to be set to ‘1’ for the device to enter deep power-down.
20/119
M58PR256LE, M58PR512LE, M58PR001LE
4
Command interface
Command interface
All bus write operations to the memory are interpreted by the command interface.
Commands consist of one or more sequential bus write operations. An internal
Program/Erase Controller handles all timings and verifies the correct execution of the
program and erase commands. The Program/Erase Controller provides a Status Register,
whose output may be read at any time to monitor the progress or the result of the operation.
The command interface is reset to read mode when power is first applied, when exiting from
Reset, or whenever VDD is lower than VLKO. Command sequences must be followed
precisely. Any invalid combination of commands are ignored.
Refer to Table 7: Command codes, Table 8: Standard commands, Table 9: Factory Program
command for a summary of the command interface.
Table 7.
Command codes
Hex code
Command
01h
Block Lock Confirm and EFA Block Lock Confirm
03h
Set Configuration Register Confirm
04h
Set Enhanced Configuration Register Confirm
20h
Block Erase Setup
24h
EFA Block Erase Setup
2Fh
Block Lock-down Confirm and EFA Block Lock-down Confirm
41h
Program Setup
44h
EFA Program Setup
50h
Clear Status Register
60h
Block Lock Setup, Block Unlock Setup, Block Lock-down Setup, Set Configuration
Register Setup and Enhanced Configuration Register Setup
64h
EFA Block Lock, EFA Block Lock-down, EFA Block Unlock
70h
Read Status Register
80h
Buffer Enhanced Factory Program
90h
Read Electronic Signature
94h
Read EFA
98h
Read CFI query
B0h
Program/Erase Suspend
BCh
Blank Check Setup
C0h
Protection Register Program
D0h
Program/Erase Resume, Block Erase Confirm, Block Unlock Confirm or Buffer
Program Confirm, Buffer Enhanced Factory Program Confirm, Blank Check Confirm,
Unlock EFA Block Confirm, EFA Block Erase Confirm
E9h
Buffer Program
FFh
Read Array
21/119
Command interface
4.1
M58PR256LE, M58PR512LE, M58PR001LE
Read Array command
The Read Array command returns the addressed bank to read array mode.
One bus write cycle is required to issue the Read Array command. Once a bank is in read
array mode, subsequent read operations output the data from the memory array.
A Read Array command can be issued to any banks while programming or erasing in
another bank.
If the Read Array command is issued to a bank currently executing a program or erase
operation, the bank returns to read array mode but the program or erase operation
continues. However, the data output from the bank is not guaranteed until the program or
erase operation has finished. The read modes of other banks are not affected.
4.2
Read Status Register command
The device contains a Status Register that monitors program or erase operations.
The Read Status Register command reads the contents of the Status Register for the
addressed bank.
One bus write cycle is required to issue the Read Status Register command. Once a bank is
in read Status Register mode, subsequent read operations output the contents of the Status
Register.
The Status Register data is latched on the falling edge of the Chip Enable or Output Enable
signals. Either Chip Enable or Output Enable must be toggled to update the Status Register
data.
The Read Status Register command can be issued at any time, even during program or
erase operations. The Read Status Register command only changes the read mode of the
addressed bank. The read modes of other banks are not affected. Only asynchronous read
and single synchronous read operations should be used to read the Status Register. A Read
Array command is required to return the bank to read array mode.
See Table 14 for the description of the Status Register bits.
22/119
M58PR256LE, M58PR512LE, M58PR001LE
4.3
Command interface
Read Electronic Signature command
The Read Electronic Signature command reads the manufacturer and device codes, the
lock status of the addressed bank, the Protection Register, the Configuration Register, and
the Enhanced Configuration Register.
One bus write cycle is required to issue the Read Electronic Signature command. Once a
bank is in read electronic signature mode, subsequent read operations in the same bank
output the manufacturer code, the device code, the lock status of the addressed bank, the
Protection Register, the Configuration Register, or the Enhanced Configuration Register
(see Table 10).
The Read Electronic Signature command can be issued at any time, even during program or
erase operations, except during protection register program operations. Dual operations
between the EFA and the electronic signature locations are not allowed (see Table 21: Dual
operation limitations for details).
If a Read Electronic Signature command is issued to a bank that is executing a program or
erase operation the bank goes into read electronic signature mode. Subsequent bus read
cycles output the electronic signature data and the Program/Erase Controller continues to
program or erase in the background.
The Read Electronic Signature command only changes the read mode of the addressed
bank. The read modes of other banks are not affected. Only asynchronous read and single
synchronous read operations should be used to read the electronic signature. A Read Array
command is required to return the bank to read array mode.
4.4
Read CFI Query command
The Read CFI Query command is used to read data from the CFI (common Flash interface).
One bus write cycle is required to issue the Read CFI Query command. Once a bank is in
read CFI query mode, subsequent bus read operations in the same bank output the
contents of the CFI.
The Read CFI Query command can be issued at any time, even during program or erase
operations.
If a Read CFI Query command is issued to a bank that is executing a program or erase
operation the bank goes into read CFI query mode. Subsequent bus read cycles output the
CFI data and the Program/Erase Controller continues to program or erase in the
background.
The Read CFI Query command only changes the read mode of the addressed bank. The
read modes of other banks are not affected. Only asynchronous read and single
synchronous read operations should be used to read from the CFI. A Read Array command
is required to return the bank to read array mode.
Dual operations between the EFA and the CFI memory space are not allowed (see Table 21:
Dual operation limitations for details).
23/119
Command interface
4.5
M58PR256LE, M58PR512LE, M58PR001LE
Clear Status Register command
The Clear Status Register command can be used to reset (set to ‘0’) all error bits (SR1,
SR3, SR4, SR5, SR8 and SR9) in the Status Register.
One bus write cycle is required to issue the Clear Status Register command. The Clear
Status Register command does not affect the read mode of the bank.
The error bits in the Status Register do not automatically return to ‘0’ when a new command
is issued. The error bits in the Status Register should be cleared before attempting a new
program or erase command.
4.6
Block Erase command
The Block Erase command erases a block. It sets all the bits within the selected block to ’1’,
and all previous data in the block is lost.
If the block is protected then the erase operation aborts, the data in the block is not
changed, and the Status Register outputs the error.
Two bus write cycles are required to issue the command.
●
The first bus cycle sets up the Block Erase command.
●
The second latches the block address and starts the Program/Erase Controller.
If the second bus cycle is not the block erase confirm code, Status Register bits SR4 and
SR5 are set and the command is aborted.
Once the command is issued, the bank enters Read Status Register mode and any read
operation within the addressed bank outputs the contents of the Status Register. A Read
Array command is required to return the bank to read array mode.
During block erase operations the bank containing the block being erased only accepts the
Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the
Program/Erase Suspend command; all other commands are ignored.
The block erase operation aborts if Reset, RP, goes to VIL. As data integrity cannot be
guaranteed when the block erase operation is aborted, the block must be erased again.
Refer to Chapter 11 for detailed information about simultaneous operations allowed in banks
not being erased.
Typical erase times are provided in Table 23: Program/erase times and endurance cycles.
See Appendix C, Figure 23: Block erase and EFA block erase flowchart and pseudocode for
a suggested flowchart for using the Block Erase command.
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M58PR256LE, M58PR512LE, M58PR001LE
4.7
Command interface
Program command
The Program command programs a single word to the memory array. It is supported only by
program regions configured in control program mode. If a Program command is issued to a
program region configured in object program mode, the program operation is aborted and
the SR4 and SR8 Status Register bits are set (see Section 5: Program operations).
Two bus write cycles are required to issue the Program command.
●
The first bus cycle sets up the Program command.
●
The second latches the address and data to be programmed and starts the P/EC
(Program/Erase Controller).
The Program command has to be written to the ’A’ segment halves (address bit A3 = 0) in
the 1 Kbyte program region, whereas the data to be programmed is written to the specific
address of the bank to be programmed.
Once the programming has started, read operations in the bank being programmed output
the Status Register contents. Programming can be performed in one bank at a time,
meanwhile the other banks must be in Read or Erase Suspend mode.
The Status Register P/EC bit, SR7, indicates the progress of the program operation. It
should be read to check whether the operation has completed or not.
After completion of the program operation (SR7 = 1), one of the error bits (SR4, SR3 and
SR1) going High means that an error was detecte. Either a failure occurred during
programming, VPP is outside the allowed voltage range, or an attempt to program a locked
block was made. See Section 6: Status Register for detailed information.
During a program operation, the bank containing the word being programmed only accepts
the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the
Program/Erase Suspend command; all other commands are ignored. A Read Array
command is required to return the bank to read array mode.
Refer to Chapter 11 for detailed information about simultaneous operations allowed in banks
not being programmed.
Typical program times are given in Table 23: Program/erase times and endurance cycles.
The program operation aborts if Reset, RP, goes to VIL. As data integrity cannot be
guaranteed when the program operation is aborted, the word must be reprogrammed.
See Appendix C, Figure 20: Program and EFA block program flowchart and pseudocode for
the flowchart for using the Program command.
25/119
Command interface
4.8
M58PR256LE, M58PR512LE, M58PR001LE
Buffer Program command
The Buffer Program command uses the device’s 1 Kbyte write buffer to speed up
programming. Up to 1 Kbyte can be loaded into the write buffer and programmed into the
specified 1 Kb aligned location in the main array. The Buffer Program command dramatically
reduces in-system programming time compared to the standard non-buffered program
command.
The Buffer Program command is supported in both object program mode and control
program mode.
When using the Buffer Program command in a region configured in object mode, the start
programming address must be aligned to the 1 Kb buffer.
When using the Buffer Program command in a region configured in control program mode,
the programmed address must be within the ’A’ segment halves of the program region
(addresses with A3 = 0) and the ’B’ segment halves of the program region (addresses with
A3 = 1) must be filled only with FFFFh data.
Before issuing the Buffer Program Setup command, the Status Register bit SR7 at the bank
address should be read to ensure that the buffer is available (SR7=1).
Four successive steps are required to issue the Buffer Program command:
1.
The first bus write cycle sets up the Buffer Program command. The setup code can be
addressed to any location within the targeted block.
2.
The second bus write cycle sets up the number of words to be programmed. Value n is
written to the same block address, where n+1 is the number of words to be
programmed. The maximum buffer count is 1FF (512 words).
3.
Use n+1 bus write cycles to load the address and data for each word into the write
buffer. Addresses must lie within the range from the start address to the start address +
n, where the start address is the location of the first data to be programmed. The start
address must be aligned to a 1 Kb boundary.
4.
The final bus write cycle confirms the Buffer Program command and starts the program
operation.
All the addresses used in the buffer program operation must lie within the same block.
The buffer program operation does not change the read status of the banks until the Buffer
Program Confirm command is issued. The Buffer Program Confirm command changes the
read status of the bank to read Status Register, therefore, after the Buffer Program Confirm
command, read operations in the bank output the contents of the Status Register.
Invalid address combinations or failure to follow the correct sequence of bus write cycles
sets an error in the Status Register and aborts the operation without affecting the data in the
memory array.
If the block being programmed is protected, an error is set in the Status Register and the
operation aborts without affecting the data in the memory array.
During buffer program operations the bank being programmed only accepts the Read Array,
Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase
Suspend commands; all other commands are ignored.
Refer to Chapter 11 for detailed information about simultaneous operations allowed in banks
not being programmed.
See Appendix C, Figure 21: Buffer program flowchart and pseudocode for a suggested
flowchart on using the Buffer Program command.
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M58PR256LE, M58PR512LE, M58PR001LE
4.9
Command interface
Buffer Enhanced Factory Program command
The Buffer Enhanced Factory Program command has been specially developed to speed up
programming in manufacturing environments where programming time is critical.
This command programs one or more write buffer(s) of 1 Kb to an aligned 1 Kb program
region. Once the device enters buffer enhanced factory program mode, the write buffer can
be reloaded any number of times as long as the address remains within the same main
array block. Only one block can be programmed at a time.
When programming a program region configured in control program mode with the Buffer
Enhanced Factory Program command, the ’B’ half segment addresses (A3 = 1) should not
contain ’0’ values. When writing to a program region configured in object program mode, the
B half may contain some ’0’ values.
If the number of bytes to program is less than 1 Kbyte, the remaining addresses must be
filled with FFFFh.
The use of the Buffer Enhanced Factory Program command requires the following operating
conditions:
●
VPP must be set to VPPH
●
VDD must be within operating range
●
Ambient temperature TA must be 30 °C ± 10 °C
●
The targeted block must be unlocked
●
The start address must be aligned with the start of a 1 Kb buffer boundary
●
The address must remain the start address throughout programming.
Dual operations are not supported during the Buffer Enhanced Factory Program operation,
and the command cannot be suspended.
The Buffer Enhanced Factory command programs one block at a time. All data to be
programmed must be contained in a single block. If the internal address counter is
incremented beyond the highest block address, addressing wraps around to the beginning
of the block.
The Buffer Enhanced Factory Program command consists of three phases: the setup
phase, the program and verify phase, and the exit phase (please refer to Table 9: Factory
Program command for detailed information).
4.9.1
Setup phase
The Buffer Enhanced Factory Program command requires two bus write cycles to initiate the
command.
●
The first bus write cycle sets up the Buffer Enhanced Factory Program command.
●
The second bus write cycle confirms the command.
After the confirm command is issued, read operations output the contents of the Status
Register. The Read Status Register command must not be issued or it is interpreted as data
to program.
The Status Register P/EC bit SR7 should be read to check that the P/EC is ready to
proceed to the next phase. If an error is detected, SR4 goes high (set to ‘1’) and the buffer
enhanced factory program operation is terminated. See Chapter 6: Status Register for
details on the error.
27/119
Command interface
4.9.2
M58PR256LE, M58PR512LE, M58PR001LE
Program and verify phase
The program and verify phase requires 512 cycles to program the 512 words to the write
buffer. The data is stored sequentially, starting at the first address of the write buffer, until the
write buffer is full (512 words). To program less than 512 words, the remaining words should
be programmed with FFFFh.
Three successive steps are required to issue and execute the program and verify phase of
the command.
1.
Use one bus write operation to latch the start address and the first word to be
programmed. The Status Register Bank write status bit SR0 should be read to check
that the P/EC is ready for the next word.
2.
Each subsequent word to be programmed is latched with a new bus write operation.
The address must remain the start address as the P/EC increments the address
location. If any address is given that is not in the same block as the start address, the
program and verify phase terminates. Status Register bit SR0 should be read between
each bus write cycle to check the P/EC is ready for the next word.
3.
Once the write buffer is full, the data is programmed sequentially to the memory array.
After the program operation the device automatically verifies the data and reprograms if
necessary.
The program and verify phase can be repeated, without re-issuing the command, to
program additional 512 word locations as long as the address remains in the same block.
4.
Finally, after all words, or the entire block have been programmed, write FFFFh to any
address outside the block containing the start address to terminate the program and
verify phase.
Status Register bit SR0 must be checked to determine whether the program operation is
finished. The Status Register may be checked for errors at any time but it must be checked
after the entire block has been programmed.
4.9.3
Exit phase
When Status Register P/EC bit SR7 is set to ‘1’ this indicates that the device has exited the
buffer enhanced factory program operation.
Upon exiting the buffered enhanced factory program algorithm by writing FFFFh to an
address outside the block containing the start address, the Read mode of the programmed
and addressed banks remains unchanged.
A full Status Register check should be done to ensure that the block has been successfully
programmed. See Chapter 6: Status Register for more details.
For optimum performance the Buffer Enhanced Factory Program command should be
limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the
internal algorithm continues to work properly but some degradation in performance is
possible. Typical program times are provided in Table 23.
See Appendix C, Figure 28: Buffer enhanced factory program flowchart and pseudocode for
a suggested flowchart on using the Buffer Enhanced Factory Program command.
28/119
M58PR256LE, M58PR512LE, M58PR001LE
4.10
Command interface
Program/Erase Suspend command
The Program/Erase Suspend command pauses a program or block erase operation. The
command can be addressed to any bank and is required to restart a suspended operation.
One bus write cycle is required to issue the Program/Erase Suspend command. Once the
Program/Erase Controller has paused, bits SR7, SR6 and/ or SR2 of the Status Register
are set to ‘1’.
The following commands are accepted during Program/Erase Suspend:
–
Program/Erase Resume
–
Read Array (data from erase-suspended block or program-suspended word is not
valid)
–
Read Status Register
–
Read Electronic Signature
–
Read CFI Query
–
Read EFA
Additionally, if the suspended operation is a block erase then the following commands are
also accepted:
–
Clear Status Register
–
Set Configuration Register
–
Program (except in erase-suspended block)
–
Buffer Program (except in erase-suspended blocks)
–
Block Lock
–
Block Lock-Down
–
Block Unlock
–
Program EFA
During an erase suspend the block being erased can be protected by issuing the Block Lock
or Block Lock-down commands. When the Program/Erase Resume command is issued the
operation completes.
It is possible to accumulate multiple suspend operations. For example, it is possible to
suspend an erase operation, start a program operation, suspend the program operation,
and then read the array.
If a program command is issued during a block erase suspend, the erase operation cannot
be resumed until the program operation has completed.
The Program/Erase Suspend command does not change the read mode of the banks. If the
suspended bank was in Read EFA, Read Status Register, Read Electronic Signature or
Read CFI Query mode, the bank remains in that mode and outputs the corresponding data.
Refer to Chapter 11 for detailed information about simultaneous operations allowed during
program/erase suspend.
During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip
Enable to VIH. Program/Erase is aborted if Reset, RP, goes to VIL.
See Appendix C, Figure 22: Program suspend and resume flowchart and pseudocode for
flowcharts for using the Program/Erase Suspend command.
29/119
Command interface
4.11
M58PR256LE, M58PR512LE, M58PR001LE
Program/Erase Resume command
The Program/Erase Resume command restarts the program or erase operation suspended
by the Program/Erase Suspend command. One bus write cycle is required to issue the
command. The command can be issued to any address.
The Program/Erase Resume command does not change the read mode of the banks. If the
suspended bank was in Read Status Register, Read Electronic Signature or Read CFI
Query mode, the bank remains in that mode and outputs the corresponding data.
If a Program command is issued during a block erase suspend, then the erase cannot be
resumed until the program operation is complete.
See Appendix C, Figure 22: Program suspend and resume flowchart and pseudocode and
Figure 24: Erase suspend and resume flowchart and pseudocode for flowcharts for using
the Program/Erase Resume command.
4.12
Protection Register Program command
The Protection Register Program command programs the user OTP area of the Protection
Register and the two Protection Register Locks.
The device features 16 OTP areas of 128 bits and one OTP area of 64 bits, as shown in
Figure 4: Protection Register memory map.
The areas are programmed one word at a time. When shipped, all bits in the area are set to
‘1’. Only the user can program the bits to ‘0’.
Two bus write cycles are required to issue the Protection Register Program command.
●
The first bus cycle sets up the Protection Register Program command.
●
The second latches the address and data to be programmed to the Protection Register
and starts the Program/Erase Controller.
Read operations to the bank being programmed output the Status Register content after the
program operation has started. Attempting to program a previously-protected Protection
Register results in a Status Register error.
The Protection Register Program cannot be suspended. Dual operations between the EFA
and the Protection Register memory space are not allowed (see Table 21: Dual operation
limitations for details).
The two Protection Register locks are used to protect the OTP areas from further
modification. The protection of the OTP areas is not reversible. Refer to Figure 4: Protection
Register memory map for details on the lock bits.
See Appendix C, Figure 27: Protection Register program flowchart and pseudocode for a
flowchart for using the Protection Register Program command.
30/119
M58PR256LE, M58PR512LE, M58PR001LE
4.13
Command interface
Set Configuration Register command
The Set Configuration Register command writes a new value to the Configuration Register.
Two bus write cycles are required to issue the Set Configuration Register command.
●
The first cycle sets up the Set Configuration Register command and the address
corresponding to the Configuration Register content.
●
The second cycle writes the Configuration Register data and the confirm command.
The Configuration Register data must be written as an address during the bus write cycles,
such as A0 = CR0, A1 = CR1, …, A15 = CR15. Addresses A16-Amax are ignored.
Read operations output the array content after the Set Configuration Register command is
issued.
The Read Electronic Signature command is required to read the updated contents of the
Configuration Register.
4.14
Block Lock command
The Block Lock command is used to lock a block and prevent program or erase operations
from changing the data in it. All blocks are locked after power-up or reset.
Two bus write cycles are required to issue the Block Lock command.
●
The first bus cycle sets up the Block Lock command.
●
The second bus write cycle latches the block address and locks the block.
The lock status can be monitored for each block using the Read Electronic Signature
command. Table 22 shows the lock status after issuing a Block Lock command.
Once set, the block lock bits remain set even after a hardware reset or power-down/powerup. They are cleared by a Block Unlock command.
Refer to Section 12: Block locking for a detailed explanation. See Appendix C, Figure 25:
Main array and EFA locking operations flowchart and pseudocode for a flowchart for using
the Lock command.
4.15
Block Unlock command
The Block Unlock command unlocks a block, allowing the block to be programmed or
erased.
Two bus write cycles are required to issue the Block Unlock command.
●
The first bus cycle sets up the Block Unlock command.
●
The second bus write cycle latches the block address and unlocks the block.
The lock status can be monitored for each block using the Read Electronic Signature
command. Table 22 shows the protection status after issuing a Block Unlock command.
Refer to Section 12: Block locking for a detailed explanation and Appendix C, Figure 25:
Main array and EFA locking operations flowchart and pseudocode for a flowchart for using
the Block Unlock command.
31/119
Command interface
4.16
M58PR256LE, M58PR512LE, M58PR001LE
Block Lock-down command
The Block Lock-down command locks down a locked or unlocked block.
A locked-down block cannot be programmed or erased. The lock status of a locked-down
block cannot be changed when WP is low, VIL. When WP is high, VIH, the lock-down function
is disabled and the locked blocks can be individually unlocked by the Block Unlock
command.
Two bus write cycles are required to issue the Block Lock-down command.
●
The first bus cycle sets up the Block Lock-down command.
●
The second bus write cycle latches the block address and locks-down the block.
The lock status can be monitored for each block using the Read Electronic Signature
command.
Locked-down blocks revert to the locked (and not locked-down) state when the device is
reset on power-down. Table 22 shows the Lock Status after issuing a Block Lock-down
command.
Refer to Section 12: Block locking for a detailed explanation and Appendix C, Figure 25:
Main array and EFA locking operations flowchart and pseudocode for a flowchart for using
the Lock-down command.
4.17
Blank Check command
The Blank Check command checks whether a main array block has been completely
erased. Only one block at a time can be checked. Two bus cycles are required to issue the
Blank Check command:
●
The first bus cycle writes the Blank Check command to any address in the block to be
checked.
●
The second bus cycle writes the Blank Check Confirm command (D0h) to any address
in the block to be checked and starts the blank check operation.
If the second bus cycle is not Blank Check Confirm, Status Register bits SR4 and SR5 are
set to ‘1’ and the command aborts.
Once the command is issued the addressed bank automatically enters the Status Register
mode and further reads within the bank output the Status Register contents.
The only operation permitted during blank check is Read Status Register. Dual operations
are not supported while a blank check operation is in progress. Blank check operations
cannot be suspended and are not allowed while the device is in program/erase suspend.
The SR7 Status Register bit indicates the status of the blank check operation in progress:
SR7 = ‘0’ means that the blank check operation is still ongoing. SR7 = ‘1’ means that the
operation is complete.
The SR5 Status Register bit goes High (SR5 = ‘1’) to indicate that a blank check operation
has failed.
At the end of the operation the bank remains in the Read Status Register mode until another
command is written to the command interface.
See Appendix C, Figure 26: Blank check flowchart and pseudocode for a suggested
flowchart for using the Blank Check command.
Typical Blank Check times are provided in Figure 23: Program/erase times and endurance
cycles.
32/119
M58PR256LE, M58PR512LE, M58PR001LE
4.18
Command interface
Set Enhanced Configuration Register command
The Set Enhanced Configuration Register command is used to write a new value to the
Enhanced Configuration Register. Two bus write cycles are required to issue the Set
Enhanced Configuration Register command.
●
The first cycle sets up the Set Enhanced Configuration Register command and the
address corresponding to the Enhanced Configuration Register contents.
●
The second cycle writes the Enhanced Configuration Register data and the Confirm
command.
The Enhanced Configuration Register data must be written as an address during the bus
write cycle, such as A0 = ECR0, A1 = ECR1, …, A15 = ECR15.
If the Set Enhanced Configuration Register setup write cycle is not followed by the Set
Enhanced Configuration Register Confirm command (04h), Status Register bits SR4 and
SR5 are set.
After successfully executing this command, the bank addressed returns to read array state.
4.19
Read EFA Block command
The Read EFA Block command places the addressed bank in the read EFA mode, where all
addresses in the addressed bank are remapped to EFA block addresses.
When the device is in read EFA mode, the main array blocks in the addressed bank can no
longer be accessed until a Read Array command is issued to the bank.
One bus write cycle is required to issue the Read EFA Block command. Once a bank is in
read EFA mode, subsequent read operations from any address within the EFA block output
the EFA data from the EFA block. See Table 5: EFA memory map for details.
EFA blocks can be read through asynchronous or single synchronous read operations only.
The Asynchronous page read mode cannot be used to read the EFA blocks.
If a Read EFA command is issued in a bank that is programming or erasing, the read mode
of the bank changes to Read EFA mode.
33/119
Command interface
4.20
M58PR256LE, M58PR512LE, M58PR001LE
Program EFA Block command
The Program EFA Block command programs a single word to an EFA block.
Two bus write cycles are required to issue the Program EFA Block command.
●
The first bus cycle sets up the Program EFA Block command.
●
The second cycle latches the address and data to be programmed and starts the
Program/Erase Controller.
Once the programming has started, read operations in the bank being programmed output
the Status Register contents.
Issuing the Program EFA Block command to an address outside the EFA block address
range generates a Program Error in the Status Register (SR4=1).
A Read EFA Block command is required to return the bank to Read EFA mode. Refer to
Section 11 for detailed information about simultaneous operations allowed in the banks not
being programmed. Typical EFA Program times are given in Table 23: Program/erase times
and endurance cycles.
The program operation aborts if Reset, RP, is at VIL. As data integrity cannot be guaranteed
when a program EFA block operation is aborted, the word must be reprogrammed. See
Appendix C, Figure 20: Program and EFA block program flowchart and pseudocode for the
flowchart for using the Program EFA Block command.
4.21
Erase EFA Block command
The Erase EFA Block command erases an EFA block. It sets all the bits within the selected
block to '1', and all previous data in the block is lost. If the EFA block is protected, then the
erase operation aborts, the data in the EFA block is not changed, and the Status Register
outputs the error.
Two bus write cycles are required to issue the command.
●
The first bus cycle sets up the Erase EFA Block command.
●
The second latches the EFA block address and starts the Program/Erase Controller.
The first cycle brings the EFA plane to the foreground and latches the address of the EFA
block to be erased. Reading from the bank when the EFA plane is in the foreground returns
the Status Register.
Once the Erase operation has started, read operations in the bank being erased output the
Status Register contents.
If the Erase EFA Block Confirm command code is not issued in the second bus cycle, Status
Register bits SR4 and SR5 are set, the command is aborted, and the addressed bank
remains in the Read Status Register mode.
Issuing the Erase EFA Block command outside the EFA block address range generates an
error in the Status Register (SR5=1).
The erase EFA block operation aborts if Reset, RP, is at VIL. As data integrity cannot be
guaranteed when the erase EFA block operation is aborted, the block must be erased again.
Refer to Section 11: Dual operations and multiple bank architecture section for detailed
information about simultaneous operations allowed with array and non-array blocks. Typical
erase times are provided in Table 23: Program/erase times and endurance cycles.
See Appendix C, Figure 23: Block erase and EFA block erase flowchart and pseudocode for
a suggested flowchart for using the Erase EFA Block command.
34/119
M58PR256LE, M58PR512LE, M58PR001LE
4.22
Command interface
Suspend EFA Block command
The Suspend EFA Block command pauses a program or erase EFA block operation. The
command can be addressed to any bank. The Resume EFA Block command is required to
restart the suspended operation.
One bus write cycle is required to issue the Suspend EFA Block command. Once the
Program/Erase Controller has paused, bits SR7, SR6 and/ or SR2 of the Status Register
are set to '1'.
The following commands are accepted during Suspend EFA Block:
–
Resume EFA Block
–
Read Array
–
Read EFA Block (data from erase-suspended blocks or program-suspended
words is not valid)
–
Read Status Register
–
Read Electronic Signature
–
Read CFI Query.
Additionally, if the suspended operation was an erase EFA block operation then the following
commands are also accepted:
–
Clear Status Register
–
Set Configuration Register
–
Program EFA Block (except in the erase-suspended block)
–
Program and Buffer Program in the main array
–
Block Lock
–
Block Lock-down
–
Block Unlock
–
EFA Block Lock
–
EFA Block Lock-down
–
EFA Block Unlock
During Suspend EFA Block the EFA block being erased can be protected by issuing the EFA
Block Lock or EFA Block Lock-down commands. When the Resume EFA Block command is
issued, the operation is resumed and completes. The suspend EFA block operation can be
repeated.
For example, it is possible to suspend an erase EFA block operation, to start a program EFA
block operation, to suspend the program operation, and then read EFA locations.
If a Program EFA Block command is issued during a suspend EFA block operation, the
erase EFA block operation cannot be resumed until the program operation has completed.
The state of the bank where the command was issued do not change.
Refer to Section 11 for detailed information about simultaneous operations allowed during a
suspend EFA block operation.
35/119
Command interface
M58PR256LE, M58PR512LE, M58PR001LE
During a suspend EFA block operation, the device can be placed in standby mode by taking
Chip Enable to VIH. Program/erase is aborted if Reset, RP, is VIL.
See Appendix C, Figure 22: Program suspend and resume flowchart and pseudocode and
Figure 24: Erase suspend and resume flowchart and pseudocode for flowcharts for using
the Suspend EFA Block command.
4.23
Resume EFA Block command
The Resume EFA Block command restarts the program or erase EFA block operation
suspended by the Suspend EFA Block command. One bus write cycle is required to issue
the command. The command can be issued to any address.
The Resume EFA Block command does not change the read mode of the banks.
If a Program EFA Block command is issued while an erase EFA block operation has been
suspended, then the erase operation cannot be resumed until the program operation has
completed.
See Appendix C, Figure 22: Program suspend and resume flowchart and pseudocode and
Figure 24: Erase suspend and resume flowchart and pseudocode for flowcharts for using
the Resume EFA Block command.
4.24
Lock EFA Block command
The Lock EFA Block command is used to lock an EFA block and prevent program or erase
operations from changing the data in it. All EFA blocks are locked after power-up or reset.
Two bus write cycles are required to issue the Lock EFA Block command.
●
The first bus cycle sets up the Lock EFA Block command.
●
The second bus cycle latches the Block address and locks the block.
The lock status can be monitored for each EFA block using the Read Electronic Signature
command.
Once set, the block lock bits remain set even after a hardware reset or a power-down/
power-up sequence. They are cleared by an Unlock EFA Block command.
Program or erase operations to a locked EFA block generates an error in the Status Register
(SR1=1).
Refer to Section 12: Block locking for a detailed explanation. See Appendix C, Figure 25:
Main array and EFA locking operations flowchart and pseudocode for a flowchart for using
the Lock EFA Block command.
36/119
M58PR256LE, M58PR512LE, M58PR001LE
4.25
Command interface
Unlock EFA Block command
The Unlock EFA Block command unlocks an EFA block, allowing the EFA block to be
programmed or erased.
Two bus write cycles are required to issue the Unlock EFA Block command.
●
The first bus cycle sets up the Unlock EFA Block command.
●
The second bus write cycle latches the block address and unlocks the block.
The lock status can be monitored for each EFA block using the Read Electronic Signature
command.
Refer to Section 12: Block locking for a detailed explanation and to Appendix C, Figure 25:
Main array and EFA locking operations flowchart and pseudocode for a flowchart for using
the Unlock EFA Block command.
4.26
Lock-down EFA Block command
The Lock-down EFA Block command is used to lock down a locked or unlocked EFA block.
A locked-down EFA block cannot be programmed or erased. The lock status of a lockeddown EFA block cannot be changed when WP is Low, VIL. When WP is High, VIH, the lockdown function is disabled and the locked EFA blocks can be individually unlocked by issuing
the Unlock EFA Block command.
Two bus write cycles are required to issue the Lock-down EFA Block command.
●
The first bus cycle sets up the Lock-down EFA Block command.
●
The second bus write cycle latches the block address and locks down the block.
The lock status can be monitored for each EFA block using the Read Electronic Signature
command.
Locked-down EFA blocks revert to the locked (and not locked-down) state when the device
is reset on power-down. Table 22 shows the lock status after issuing a Lock-down EFA Block
command.
Refer to Section 12: Block locking for a detailed explanation and to Appendix C, Figure 25:
Main array and EFA locking operations flowchart and pseudocode for a flowchart for using
the Lock-down EFA Block command.
37/119
Command interface
Table 8.
M58PR256LE, M58PR512LE, M58PR001LE
Standard commands
Commands
Cycles
Bus operations(1)
1st cycle
2nd cycle
Op.
Add
Data
Op.
Add
Data
Read Array
1+
Write
BKA
FFh
Read
WA
RD
Read Status Register
1+
Write
BKA
70h
Read
BKA(2)
SRD
Read
(2)
BKA
ESD
Read
BKA(2)
QD
Read Electronic Signature
1+
Write
BKA
90h
Read CFI Query
1+
Write
BKA
98h
Clear Status Register
1
Write
X
50h
Block Erase
2
Write
BKA or BA(3)
20h
Write
BA
D0h
Write
WA(3)
41h
Write
WA
PD
Program
Buffer Program
2
n+4
(4)
BKA or
Write
BA
E9h
Write
BA
n
Write
PA1
PD1
Write
PA2
PD2
Write
PAn+1
PDn+1
Write
X
D0h
Program/Erase Suspend
1
Write
X
B0h
Program/Erase Resume
1
Write
X
D0h
Protection Register Program
2
Write
PRA
C0h
Write
PRA
PRD
Set Configuration Register
2
Write
CRD
60h
Write
CRD
03h
60h
Write
BA
01h
60h
Write
ECRD
04h
(3)
Block Lock
2
Write
BKA or BA
Set Enhanced Configuration
Register
2
Write
ECRD
Block Unlock
2
Write
BKA or BA(3)
60h
Write
BA
D0h
(3)
60h
Write
BA
2Fh
BCh
Write
BA
D0h
Block Lock-down
2
Write
Blank Check
2
Write
BA
Read EFA Block
1+
Write
BKA
Program EFA Block
2
Write
BKA or BA
2
Write
Suspend EFA Block
1
Write
X
Resume EFA Block
1
Write
X
2
Write
Unlock EFA Block
2
Write
Lock-down EFA Block
2
Write
Read
WA
RD
44h
Write
WA
PD
(3)
24h
Write
BA
D0h
BKA or WA
Erase EFA Block
Lock EFA Block
94h
(3)
BKA or BA
B0h
D0h
(3)
64h
Write
BA
01h
BA(3)
64h
Write
BA
D0h
64h
Write
BA
2Fh
BKA or BA
BKA or
BA
1. X = Don't care, WA = Word Address in targeted bank, RD = Read Data, SRD = Status Register Data, ESD = Electronic
Signature Data, QD = Query Data, BA = Block Address, BKA = Bank Address, PA = Program Address, PD = Program
Data, PRA = Protection Register Address, PRD = Protection Register Data, CRD = Configuration Register Data, ECRD =
Enhanced Configuration Register Data.
2. Must be same bank as in the first cycle. The signature addresses are listed in Table 10.
3. Any address within the bank can be used.
4. n+1 is the number of words to be programmed.
38/119
M58PR256LE, M58PR512LE, M58PR001LE
Table 9.
Command interface
Factory Program command(1)
Command
Cycles
Bus write operations
Phase
Setup
2
Buffer
Enhanced
Program/ Verify(3) ≥512
Factory
Program
Exit
1
1st
2nd
3rd
Add
Data
Add Data Add
BKA or
WA(2)
80h
WA1
D0h
WA1
PD1
WA1
PD2
WA1
Final -1
Final
Data
Add
Data
Add
Data
PD3
WA1 PD511 WA1 PD512
NOT
FFFFh
BA1(4)
1. WA = Word Address in targeted bank, BKA = Bank Address, PD = Program Data, BA = Block Address, X = Don’t care.
2. Any address within the bank can be used.
3. The program/verify phase can be executed any number of times as long as the data is programmed to the same block.
4. WA1 is the start address, NOT BA1 = Not Block Address of WA1.
Table 10.
Electronic signature codes
Code
Manufacturer code
Address (h)
Data (h)
Bank address + 00
0020
256 Mbit
Device code
512 Mbit
Main block
8819
880F
Locked
DQ1, DQ0 = 01
Unlocked
DQ1, DQ0 = 00
Locked and Locked-down
DQ1, DQ0 = 11
Locked
EFA block
Bank address + 01
1 Gbit
Unlocked and Locked-down
Block
protection
8818
Block address + 02
DQ1, DQ0 = 10
DQ5, DQ4 = 01
Unlocked
DQ5, DQ4 = 00
Locked and Locked-down
DQ5, DQ4 = 11
Unlocked and Locked-down
DQ5, DQ4 = 10
Configuration Register
Bank address + 05
CR(1)
Enhanced Configuration Register
Bank address + 06
ECR(1)
Protection Register PR0
Lock
ST factory default
OTP area permanently locked
Bank address + 80
Bank address + 81
Protection Register PR0
Bank address + 84
Bank address + 85
Bank address + 88
Protection Register PR1 through PR16 Lock
Protection Registers PR1-PR16
Bank address + 89
Bank address + 8A
Bank address + 109
0002
0000
Unique device number
OTP area
PRLD(1)
OTP area
1. CR = Configuration Register, ECR = Enhanced Configuration Register, PRLD = Protection Register Lock Data.
39/119
Command interface
Figure 4.
M58PR256LE, M58PR512LE, M58PR001LE
Protection Register memory map
PROTECTION REGISTERS
109h
PR16
User Programmable OTP
102h
91h
PR1
User Programmable OTP
8Ah
89h
88h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR0
User Programmable OTP
85h
84h
Unique device number
81h
80h
Protection Register Lock
1 0
AI07563
Table 11.
Protection Register locks
Lock
Description
Number
Lock 1
Address
80h
Bits
Bit 0
Preprogrammed to protect unique device number, address 81h
to 84h in PR0
Bit 1
Protects 64 bits of OTP area, address 85h to 88h in PR0
Bits 2 to 15 Reserved
40/119
Bit 1
Protects 128 bits of OTP area PR2
Bit 2
Protects 128 bits of OTP area PR3
----
89h
Protects 128 bits of OTP area PR1
----
Lock 2
Bit 0
Bit 13
Protects 128 bits of OTP area PR14
Bit 14
Protects 128 bits of OTP area PR15
Bit 15
Protects 128 bits of OTP area PR16
M58PR256LE, M58PR512LE, M58PR001LE
5
Program operations
Program operations
The M58PR256LE, M58PR512LE and M58PR001LE have innovative features specially
developed to improve the storage flexibility and efficiency of NOR Flash memory arrays.
Data and code can be stored more efficiently by using the right combination of program
methods and program modes.
There are two types of program methods that use commands that consist of one or more
sequential bus write operations interpreted by the command interface:
●
Single word program method, which uses the Program command.
●
Buffered program method, which uses either the Buffer Program command or the
Buffer Enhanced Factory Program command.
There are two program modes:
●
Control program mode
●
Object program mode.
The control program mode supports the two program methods, whereas the object program
mode only supports the buffered program method.
This new logical organization of program operations is made possible by the device
architecture, and, in particular, by the new concept of program regions.
5.1
Program regions
Each Flash memory block is divided into 256 program regions (see Figure 5: Program
regions configured in control or object program mode). Erase operations have a block
granularity, whereas program operations have a program region granularity.
The user can configure each program region to be programmed either in the control
program mode or in the object program mode. A given block can contain program regions
configured in the control program mode and others configured in the object program mode.
Special care should be taken when selecting the programming mode for the program
regions because once the program regions are configured, their program mode cannot be
changed until the entire block is erased.
Each program region is split into 32 segments of 32 bytes and each segment is subdivided
into two halves, ’A’ and ’B’. Address bit A3 determines whether a bit belongs to the ’A’ half
(A3 = 0) or to the ’B’ half (A3 = 1).
41/119
Program operations
5.2
M58PR256LE, M58PR512LE, M58PR001LE
Program modes
There are two program modes, which allow the Flash memory to store different types of
data: control program mode and object program mode.
5.2.1
Control program mode
The control program mode is best suited to the storage of small, dynamic information.
Typically such data is contained within one program region and it is frequently updated
and/or new data is added to it.
Program regions are configured in the control program mode by programming data only to
the ’A’ halves (bit A3= 0) of the segments they contain. The ’B’ halves of the segments must
remain erased, meaning that they should not contain any zeros (see Figure 5: Program
regions configured in control or object program mode).
In a program region of 1 Kbyte configured in the control program mode, only 512 bytes of
data can be stored.
When the program regions are configured in the control program mode, any program
method can be used: the single word or the buffered program methods.
Once a program region has been configured in the control program mode, if a zero is written
to a ’B’ half of one of its segments, the program operation is terminated and an error is
generated. The Status Register bits SR4 and SR9 are set to ‘1’. (Refer to Status Register
and to Table 13: Relationships between program methods and program modes for details.)
The program mode of a program region configured in the control program mode can only be
changed by first erasing the block that contains the program region.
5.2.2
Object program mode
The object program mode is best suited to the storage of large amounts of static
information. In a program region of 1 Kbyte configured in the object program mode, 1 Kbyte
of data can be stored.
When a program region is configured in the object program mode, it cannot be reprogrammed or have new data added without first erasing the entire block that contains the
program region.
Program regions are configured in the object program mode simply by programming at least
one bit in the ’B’ half (A3 = 1) of one of the segments they contain.
If the programmed data is smaller than 1 Kbyte, the unused space remains in the erased
state (all the bits set to FFFFh), but can no longer be used to program data. See Figure 5:
Program regions configured in control or object program mode.
When the program regions are configured in the object program mode, only the buffered
program methods can be used. If an attempt is made to use the single word program
method, the program operation is aborted and Status Register Error bits SR4 and SR8 are
set to ‘1’. (Refer to Status Register and to Table 13: Relationships between program
methods and program modes, for details.)
42/119
M58PR256LE, M58PR512LE, M58PR001LE
Figure 5.
Program operations
Program regions configured in control or object program mode
Program region in control program mode
Data 1
128 Kword BLOCK
Program region 0
1 Kbyte (512 byte programmable)
Program region 1
1 Kbyte (512 byte programmable)
Data 2
Data 3
Data 4
SEGMENT 31
SEGMENT 30
F F F F F F F F
SEGMENT 3
F F F F F F F F
SEGMENT 2
F F F F F F F F
SEGMENT 1
F F F F F F F F
SEGMENT 0
...
Data (n – 4)
Data (n – 3)
Data (n – 2)
Data (n – 1)
Data n
:
:
:
:
:
F F F F F F F F
F F F F F F F F
A halves
(A3 = 0)
B halves
(A3 = 1)
Program region in object program mode
F F F F F F F F F F F F F F F F
SEGMENT 31
Program region 254
1 Kbyte (512 byte programmable)
F F F F F F F F F F F F F F F F
SEGMENT 30
Program region 255
1 Kbyte (512 byte programmable)
F F F F F F
...
SEGMENT 3
SEGMENT 2
Object
SEGMENT 1
SEGMENT 0
1 Kbyte
ai10135
5.3
Program methods
The device supports two types of program methods:
●
Single word program method, which is used to program a single word to a specific
address of the memory array.
●
Buffered program methods, which can be split into two different methods:
–
Buffer program method, which uses the device's write buffer to speed up
programming. The data is written into the write buffer and then programmed to the
specified block address.
–
Buffer enhanced factory program method, which is developed to speed up
programming in manufacturing environments where the programming time is
critical. The data is written in the write buffer and then programmed to the
specified block.
The following sections describe the relationship between program commands and program
methods in detail. See Table 13: Relationships between program methods and program
modes and Table 12: Program methods available with each program mode.
43/119
Program operations
5.3.1
M58PR256LE, M58PR512LE, M58PR001LE
Single word program method
The single word program method is based on the Program command. It is only supported by
program regions configured in the control program mode.
If the single word program method is attempted in a program region configured in the object
program mode, the program operation is aborted and Status Register bits SR4 and SR8 are
set.
See Section 4: Command interface for a detailed description of the Program command.
In program regions configured in the control program mode, the Program command can be
issued several times.
Using the single word program method to program one or more bits to '0' in the ’B’ halves of
the segments (A3 = 1) of an erased or already programmed program region generates an
error:
5.3.2
●
In the case of an erased program region, this is considered an illegal operation that
sets Status Register bits SR4 and SR9.
●
In the case of an already programmed program region, an error is always generated
because:
–
To be able to write to a program region configured in the object program mode, the
entire block that contains the program region must be erased first.
–
It is not allowed to write to the ’B’ halves of the segments of a program region
configured in the control program mode.
Buffer program method
The buffer program method is based on the Buffer Program command and uses a 1 Kbyte
write buffer to speed up programming. The data is written to the write buffer and then
programmed to the specified main array location.
The buffer program method is supported regardless of the program mode of the program
regions. When using the buffer program method in a program region configured in the object
program mode, the start address must be aligned to the 1 Kbyte write buffer.
When using the buffer program method in a program region configured in the control
program mode, the address to be programmed must be located inside the ’A’ halves of the
program region’s segments (addresses with A3 = 0) and the ’B’ halves of the segments
(addresses with A3= 1) must be filled only with FFFFh data.
The Buffer Program command can be issued several times to program regions configured in
the control program mode.
The Buffer Program command can only be issued once in program regions configured in the
object program mode. Attempts to program the same program regions by re-issuing the
Buffer Program command leads to data corruption.
See Section 4: Command interface for a detailed description of the Buffer Program
command.
44/119
M58PR256LE, M58PR512LE, M58PR001LE
5.3.3
Program operations
Buffer enhanced factory program method
The buffer enhanced factory program method is based on the Buffer Enhanced Factory
Program command.
The buffer enhanced factory program method is supported by the program regions,
regardless of the program mode in which they are configured.
In this program method, the program region (1 Kbyte) must be completely filled, regardless
of the program mode used. If the size of the data to be written is less than 1 Kbyte, the
remaining addresses in the program region must be filled with FFFFh.
When using the buffer enhanced factory program method in a program region configured in
the control program mode, the addresses to be programmed must be located in the ’A’ half
of the program regions’ segments (A3 = 0) and the ’B’ half of the segments (A3 = 1) must be
filled only with FFFFh.
See Section 4: Command interface for a detailed description of the Buffer Enhanced Factory
Program command.
Table 12.
Program methods available with each program mode
Program methods(1)
Program mode
Buffered program
Single word
program
Control program mode
X
Object program mode
Buffer program
Buffer enhanced factory
Program
X
X
X
X
1. X means available.
Table 13.
Relationships between program methods and program modes
Program method
Program region Address bit A3
status
value
Buffered program
Buffer
program
A3 = 0 (’A’ half)
Buffer enhanced
factory program
Program region configured in control
program mode
Erased
Program region configured in object
A3 = 1 (’B’ half)
program mode
Single word program
Program region
configured in control
program mode
Not allowed.
Program aborted, Status
Register Error bits SR4
and SR9 set
A3 = 0 (’A’ half) Program operation successful
Control program
mode
A3 = 1 (’B’ half)
Object program
mode
A3 = 0 (’A’ half) Subsequent program not allowed.
A3 = 1 (’B’ half) Program aborted, Status Register Error bits SR4 and SR8 set
Not allowed.
Program aborted, Status Register Error bits SR4 and SR9 set
45/119
Status Register
6
M58PR256LE, M58PR512LE, M58PR001LE
Status Register
The Status Register provides information on the current or previous program or erase
operations. Issue a Read Status Register command to read the contents of the Status
Register (refer to Section 4.2 for more details on the command itself).
To output the contents, the Status Register is latched and updated on the falling edge of the
Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable
returns to VIH.
The Status Register can only be read using single asynchronous or single synchronous
reads.
Bus read operations from any address within the bank always read the Status Register
during program and erase operations if no Read Array command has been issued.
The various bits convey information about the status and any errors of the operation. Bits
SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset
by the device. Bits SR9, SR8, SR5, SR4, SR3 and SR1 give information on errors. They are
set by the device but must be reset by issuing a Clear Status Register command or a
hardware reset. If an error bit is set to ‘1’ the Status Register should be reset before issuing
another command.
The bits in the Status Register are summarized in Table 14: Status Register bits. Refer to
Table 14 in conjunction with the following text descriptions.
6.1
Control program mode status bit (SR9)
The control program mode status bit, SR9, indicates whether an error occurred while writing
to a program region that is configured in control program mode.
The SR9 bit should be read once the Program/Erase Controller status bit SR7 is set to ‘1’
(Program/Erase Controller inactive).
SR9 is set to 1 when the user attempts to program object data in a control mode region.
When:
●
SR9 = 0, the program operation completed successfully.
●
SR9 = 1, the program operation failed.
Once set to ‘1’, SR9 can only be cleared by issuing a Clear Status Register command or
through a hardware reset.
SR9 should be cleared before a new program command is issued, otherwise the new
command appears to fail.
46/119
M58PR256LE, M58PR512LE, M58PR001LE
6.2
Status Register
Object program mode status bit (SR8)
The object program mode status bit, SR8, indicates whether an error occurred while writing
to a program region that was configured in the object program mode.
The SR8 bit should be read once the Program/Erase Controller status bit SR7 is set to ‘1’
(Program/Erase Controller inactive).
SR8 is set to 1 when the user attempts to rewrite an object mode region.
When:
●
SR8 = 0, the program operation completed successfully.
●
SR8 = 1, the program operation failed.
Once set, SR8 can only be cleared by issuing a Clear Status Register command or through
a hardware reset.
SR8 should be cleared before a new program command is issued, otherwise the new
command appears to fail.
6.3
Program/Erase Controller status bit (SR7)
The Program/Erase Controller status bit indicates whether the Program/Erase Controller is
active or inactive in any bank.
When:
●
SR7 = 0, the Program/Erase Controller is active.
●
SR7 = 1, the Program/Erase Controller is inactive, and the device is ready to process a
new command.
The Program/Erase Controller status bit is set to ’0’ immediately after a Program/Erase
Suspend command is issued until the Program/Erase Controller pauses. After the
Program/Erase Controller pauses, the bit is set to ’1’.
6.4
Erase suspend status bit (SR6)
The erase suspend status bit indicates that an erase operation has been suspended in the
addressed block.
When:
●
SR6 = 0, no Program/Erase Suspend command has been issued.
●
SR6 = 1, a Program/Erase Suspend command has been issued and the memory is
waiting for a Program/Erase Resume command.
The erase suspend status bit should only be considered valid when the Program/Erase
Controller status bit is set to ’1’ (Program/Erase Controller inactive). SR6 is set within the
erase suspend latency time of the Program/Erase Suspend command being issued,
therefore, the memory may still complete the operation rather than entering suspend mode.
When a Program/Erase Resume command is issued, the erase suspend status bit is reset
to ’0’.
47/119
Status Register
6.5
M58PR256LE, M58PR512LE, M58PR001LE
Erase status bit (SR5)
The erase status bit identifies if there is an error during a block erase operation.
When:
●
SR5 = 0, no error occurred.
●
SR5 = 1, the Program/Erase Controller applied the maximum number of pulses to the
block or bank and still failed to verify that it has erased correctly.
The erase status bit should be read once the Program/Erase Controller Status bit is set to ’1’
(Program/Erase Controller inactive). Once set, the erase status bit must be cleared by a
Clear Status Register command or a hardware reset. This must be done before a new erase
command is issued, otherwise the new command appears to fail.
6.6
Program status bit (SR4)
The program status bit identifies if there is an error during a program operation.
The program status bit should be read once the Program/Erase Controller status bit is set to
‘1’ (Program/Erase Controller inactive).
When:
●
SR4 = 0, no error occurred.
●
SR4 = 1, the Program/Erase Controller applied the maximum number of pulses to the
word and still failed to verify that it programmed correctly.
Attempting to program a '1' to an already programmed bit while VPP = VPPH also sets the
program status bit to ’1’. If VPP is different from VPPH, SR4 remains set to '0' and the attempt
is not shown.
Once set to '1', the program status bit must be cleared by a Clear Status Register command
or a hardware reset. This must be done before a new program command is issued,
otherwise the new command appears to fail.
6.7
VPP status bit (SR3)
The VPP status bit identifies an invalid voltage on the VPP pin during program and erase
operations. The VPP pin is only sampled at the beginning of a program or erase operation.
Program and erase operations are not guaranteed if VPP becomes invalid during an
operation.
When:
●
SR3 = 0, the voltage on the VPP pin is sampled at a valid voltage.
●
SR3 = 1, the VPP pin has a voltage that is below the VPP lockout voltage, VPPLK, the
memory is protected, and program and erase operations cannot be performed.
Once set to ‘1’, the VPP status bit must be cleared by a Clear Status Register command or a
hardware reset. This must be done before a new program or erase command is issued,
otherwise the new command appears to fail.
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M58PR256LE, M58PR512LE, M58PR001LE
6.8
Status Register
Program Suspend Status bit (SR2)
The program suspend status bit indicates that a program operation has been suspended in
the addressed block. The program suspend status bit is onlyconsidered valid when the
Program/Erase Controller status bit is set to ‘1’ (Program/Erase Controller inactive).
When:
●
SR2 = 0, no Program/Erase Suspend command has been issued.
●
SR2 = 1, a Program/Erase Suspend command has been issued and the memory is
waiting for a Program/Erase Resume command.
SR2 is set within the program suspend latency time of the Program/Erase Suspend
command being issued, therefore, the memory may still complete the operation rather than
entering suspend mode.
When a Program/Erase Resume command is issued, the program suspend status bit is
reset to ‘0’.
6.9
Block protection status bit (SR1)
The block protection status bit dentifies if a program or block erase operation has tried to
modify the contents of a locked block.
When:
●
SR1 = 0, no program or erase operation has been attempted on a locked block.
●
SR1 = 1, a program or erase operation has been attempted on a locked block.
Once set to ‘1’, the block protection status bit must be cleared by a Clear Status Register
command or a hardware reset. This must be done before a new program or erase command
is issued, otherwise the new command appears to fail.
6.10
Bank write/multiple word program status bit (SR0)
The bank write status bit indicates if the addressed bank is programming or erasing.
The bank write status bit is only considered valid when the Program/Erase Controller status
bit SR7 is set to ‘0’.
When:
●
SR0 = 0 and SR7 = 0, the addressed bank is executing a program or erase operation.
●
SR0 = 1 and SR7 = 0, a program or erase operation is being executed in a bank other
than the one being addressed.
During buffer enhanced factory program operations the multiple word program bit, SR0,
shows if the device is ready to accept a new word to be programmed to the memory array.
When:
●
SR0 = 0, the device is ready for the next word.
●
SR0 = 1, the device is not ready for the next word.
For further details on how to use the Status Register, see the flowcharts and pseudocodes
provided in Appendix C.
49/119
Status Register
M58PR256LE, M58PR512LE, M58PR001LE
Table 14.
Bit
Status Register bits
Name
Type
Logic
level(1)
Definition
1
Program error in program region configured in control
program mode
0
Program successful
1
Program error in program region configured in object
program mode
0
Program successful
1
Ready
0
Busy
1
Erase suspended
0
Erase in progress or completed
1
Erase error
0
Erase success
1
Program error
0
Program success
1
VPP invalid, abort
0
VPP OK
1
Program suspended
0
Program in progress or completed
1
Program/erase on protected block, abort
0
No operation to protected blocks
SR15Reserved(2)
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
Control program
mode status
Object program
mode status
P/EC status
Error
Error
Status
Erase suspend
status
Status
Erase status
Error
Program status
Error
VPP status
Error
Program
suspend status
Status
Block protection
status
Error
SR7 = ‘1’ Not allowed
1
SR7 = ‘0’
Program or erase operation in a bank
other than the addressed bank
SR7 = ‘1’
No program or erase operation in the
device
SR7 = ‘0’
Program or erase operation in addressed
bank
Bank write status Status
0
SR0
SR7 = ‘1’ Not allowed
Multiple word
program status
(buffer enhanced
factory program
mode)
1
SR7 = ‘0’
Status
The device is not ready for the next word
or is going to exit BEFP mode
SR7 = ‘1’ The device is exiting from BEFP
0
SR7 = ‘0’ The device is ready for the next word
1. Logic level '1' is High, '0' is Low.
2. Reserved bits should always be reset to ‘0’.
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M58PR256LE, M58PR512LE, M58PR001LE
7
Configuration Register
Configuration Register
The Configuration Register configures the type of bus access that the memory performs.
Refer to Section 10: Read modes for details on read operations.
The Configuration Register is set through the command interface using the Set
Configuration Register command. The Configuration Register is volatile: after a reset or a
power-down/power-up sequence, the register is set for asynchronous read (CR15=1) and all
bits return to their default value. The Configuration Register bits are described in Table 16.
They specify the selection of the burst length, burst X latency and the read operation. Refer
to Figure 6 and Figure 7 for examples of synchronous burst configurations.
7.1
Read select bit (CR15)
The read select bit, CR15, switches between asynchronous and synchronous read
operations.
When:
●
●
CR15 = 0:
–
Read operations in the main array are performed in synchronous burst mode,
–
Operations to read the Status Register, electronic signature, CFI and EFA are
performed in single synchronous mode (See Section 10.3: Single synchronous
read mode for details).
CR15 = 1:
–
Read operations in the main array are performed in Asynchronous page mode,
–
Operations to read the Status Register, electronic signature, CFI and EFA are
performed in asynchronous random access mode.
Synchronous burst read can be performed across banks.
On reset or power-up the read select bit is set to ’1’ for asynchronous access.
7.2
X latency bits (CR14-CR11)
The X latency bits are used during synchronous read operations to set the number of clock
cycles between the address being latched and the first data becoming available.
For correct operation the X latency bits can only assume the values in Table 16:
Configuration Register.
Table 15 shows how to set the X latency parameter, taking into account the frequency used
to read the Flash memory in synchronous mode.
Refer to Figure 6: X latency and data output configuration example for an example
waveform.
51/119
Configuration Register
Table 15.
7.3
M58PR256LE, M58PR512LE, M58PR001LE
X latency settings
fmax
tKmin
X latency
40 MHz
25 ns
4
54 MHz
19 ns
5
66 MHz
15 ns
6
108 MHz
9 ns
10
Wait polarity bit (CR10)
The wait polarity bit sets the polarity of the Wait signal used in synchronous burst read
mode.
When:
●
CR10 = 0, the Wait signal is active Low.
●
CR10 = 1, the Wait signal is active High.
During synchronous burst read mode the Wait signal indicates whether the data output is
valid or a Wait state must be inserted.
7.4
Wait configuration bit (CR8)
The wait configuration bit is used to control the timing of the Wait output pin, WAIT, in
synchronous burst read mode.
When:
●
CR8 = 0, the Wait output pin is asserted during the wait state.
●
CR8 = 1, the Wait output pin is asserted one data cycle before the wait state.
When WAIT is asserted, data is not valid and when WAIT is de-asserted, data is valid.
7.5
Burst length bits (CR2-CR0)
The burst length bits set the number of words to be output during a synchronous burst read
operation as result of a single address latch cycle.
They can be set for 8 words, 16 words, or continuous burst, where all the words are read
sequentially. In continuous burst mode the burst sequence can cross bank boundaries.
In continuous burst mode, the device asserts the Wait signal to indicate that a delay is
necessary before the data is output.
In continuous burst mode, if the starting address is not aligned to the 16-word boundary,
Wait is asserted when the burst sequence crosses the first 16-word boundary. This indicates
that the device needs an internal delay to read the successive words in the array.
52/119
M58PR256LE, M58PR512LE, M58PR001LE
Configuration Register
In the worst case scenario, the number of wait states is one clock cycle less than the latency
setting. Wait is asserted only once during a continuous burst access. See also Table 17:
Burst type definition.
CR9, CR7, CR6, CR5, CR4 and CR3 are reserved for future use.
Table 16.
Bit
CR15
CR14-CR11
Configuration Register
Description
Value
Description
0
Synchronous read
1
Asynchronous read (default at power-on)
0011
3 Clock latency
0100
4 Clock latency
0101
5 Clock latency
0110
6 Clock latency
0111
7 Clock latency
1000
8 Clock latency
1001
9 Clock latency
1010
10 Clock latency
1011
11 Clock latency
1100
12 Clock latency
1101
13 Clock latency
1110
14 Clock latency
1111
15 Clock latency (default)
Read Select
X latency
Other configurations reserved
CR10
Wait polarity
CR9
Reserved(1)
CR8
Wait
configuration
CR7-CR3
CR2-CR0
0
WAIT is active Low (default)
1
WAIT is active High
0
WAIT is active during wait state
1
WAIT is active one data cycle before wait state (default)1
010
8 words (wrap only)
011
16 words (wrap only)
111
Continuous (default, no wrap only)
Reserved(1)
Burst length
1. Reserved bits should be cleared to ‘0’.
53/119
Configuration Register
Table 17.
M58PR256LE, M58PR512LE, M58PR001LE
Burst type definition
Start address
8 words
16 words
Continuous burst
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
0-1-2-3-4-5-6...
1
1-2-3-4-5-6-7-0
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
1-2-3-4-5-6-7...
2
2-3-4-5-6-7-0-1
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
2-3-4-5-6-7-8...
3
3-4-5-6-7-0-1-2
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
3-4-5-6-7-8-9...
7-0-1-2-3-4-5-6
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
7-8-9-10-11-12-13...
12
12-13-14-15-8-9-10-11
12-13-14-15-0-1-2-3-4-5-6-7-8-9-10-11
12-13-14-15-16-17...
13
13-14-15-8-9-10-11-12
13-14-15-0-1-2-3-4-5-6-7-8-9-10-11-12
13-14-15-16-17-18...
14
14-15-8-9-10-11-12-13
14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13
14-15-16-17-18-19...
15
15-8-9-10-11-12-13-14
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
15-16-17-18-19-20...
...
7
...
Figure 6.
X latency and data output configuration example
X-latency
1st cycle
2nd cycle
3rd cycle
4th cycle
K
E
L
Amax-A0
VALID ADDRESS
tQVK_CPU
tKHKH
tKHQV
DQ15-DQ0
VALID DATA VALID DATA
AI08904b
1. The settings shown are X latency = 4. tQVK_CPU is the data setup time required by the system CPU.
54/119
M58PR256LE, M58PR512LE, M58PR001LE
Figure 7.
Configuration Register
Wait configuration example
E
K
L
Amax-A0
DQ15-DQ0
VALID ADDRESS
VALID DATA VALID DATA
NOT VALID
VALID DATA
WAIT
CR8 = '0'
CR10 = '0'
WAIT
CR8 = '1'
CR10 = '0'
WAIT
CR8 = '0'
CR10 = '1'
WAIT
CR8 = '1'
CR10 = '1'
AI12859
55/119
Enhanced Configuration Register
8
M58PR256LE, M58PR512LE, M58PR001LE
Enhanced Configuration Register
The ECR (Enhanced Configuration Register)enables the deep power-down mode and
configures the output driver strength. It is set through the command interface using the Set
Enhanced Configuration Register command.
The contents of the ECR can be read by issuing the Read Electronic Signature command,
and then by reading from the bank base address + 06h.
The ECR is volatile: after a reset or a power-down/power-up sequence the register is set to
the default value. The Configuration Register bits are described in Table 18.
8.1
Deep power-down mode bit (ECR15)
The deep power-down mode bit, ECR15, enable the deep power-down mode.
The device can only enter the deep power-down mode from standby, by, in any order,
asserting the DPD pin and setting ECR15 to ‘1’.
When the device is in the deep power-down mode, de-asserting the DPD pin and/or
resetting ECR15 causes the device to revert to standby mode.
8.2
Deep power-down polarity bit (ECR14)
The deep power-down polarity bit sets the polarity of the DPD signal.
When:
8.3
●
ECR14 = 0, the DPD signal is active Low (default).
●
ECR14 = 1, the DPD signal is active High.
Output driver control bits (ECR2-ECR0)
The output driver control bits, ECR0, ECR1 and ECR2, selects the output driver impedance
best suited to the system requirements.
After reset or power-up the output driver control bits are set to the Enhanced Configuration
Register default value (ECR2-ECR0 = 100, that is 30 Ω (30 pF) (default)). Optimum
performance is only achieved if the output driver impedance is properly configured.
Once a configuration has been selected, all data and wait output drivers are set to the same
setting.
Table 18 lists the output driver impedances at VDDQ/2 and the loads that correspond for
each ECR2-ECR0 bit configuration.
56/119
M58PR256LE, M58PR512LE, M58PR001LE
Table 18.
Enhanced Configuration Register
Enhanced Configuration Register
Bit
ECR15
ECR14
ECR13-ECR3
ECR2-ECR0
Description
Value
Description
0
DPD mode disabled (default)
1
DPD mode enabled
0
DPD is active Low (default)
1
DPD is active High
Deep power-down mode
DPD polarity
Reserved
(1)
Output driver Impedance
001
90 Ω (10 pF)
010
60 Ω (15 pF)
011
45 Ω (20 pF)
100
30 Ω (30 pF) (default)
101
20 Ω (35 pF)
110
15 Ω (40 pF)
Other configurations reserved
1. Reserved bits should be cleared to ‘0’.
57/119
Extended Flash array (EFA)
9
M58PR256LE, M58PR512LE, M58PR001LE
Extended Flash array (EFA)
In addition to its main array, the M58PRxxxLE features an EFA that is divided into 4 blocks of
4 KWords each. See Table 5: EFA memory map.
The EFA blocks are accessed through a separate set of commands (see Section 4:
Command interface for details).
The operations available on the EFA blocks are asynchronous random access read, single
synchronous read, (single word) program, erase, block lock, block unlock, and block lockdown.
The EFA blocks support program/erase suspend and dual operations with the main array.
Dual operations between the EFA and the OTP area are not supported. See Table 21: Dual
operation limitations for details.
58/119
M58PR256LE, M58PR512LE, M58PR001LE
10
Read modes
Read modes
Read operations can be performed in two different ways depending on the settings in the
Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read
operation is asynchronous. If the data output is synchronized with clock, the read operation
is synchronous.
The read mode and format of the data output are determined by the Configuration Register.
(See Section 7: Configuration Register for details). All banks support both asynchronous
and synchronous read operations.
10.1
Asynchronous read mode
In asynchronous read operations the clock signal is ‘don’t care’. The device outputs the data
corresponding to the address latched, such as the memory array, Status Register, common
Flash interface or electronic signature, depending on the command issued. CR15 in the
Configuration Register must be set to ‘1’ for asynchronous operations.
Asynchronous read operations can be performed in two different ways, asynchronous
random access read and asynchronous page read. Only asynchronous page read takes full
advantage of the internal page storage, therefore, different timings are applied.
In asynchronous read mode a page of data is internally read and stored in a page buffer.
The page has a size of 16 words and is addressed by address inputs A0, A1, A2 and A3.
During the page access, Amax-A4 and L must remain stable.
The first read operation within the page has a longer access time (tAVQV, Random access
time); subsequent reads within the same page have much shorter access times (tAVQV1,
page access time). If the page changes then the normal, longer timings apply again.
Read operations to read non-array data (Status Register, electronic signature, CFI) should
be performed in asynchronous single word mode. If the asynchronous page mode is used to
read non-array data, only the first output data is valid and all subsequent data is not
accurately determined.
The asynchronous page read mode is not available in the EFA.
The device features an Automatic Standby mode. During asynchronous read operations,
after a bus inactivity of 150 ns, the device automatically switches to automatic standby
mode. In this state the power consumption is reduced to the standby value and the outputs
are still driven.
In asynchronous read mode, the Wait signal is always de-asserted.
See Table 29: Asynchronous read AC characteristics, Figure 10: Asynchronous random
access read AC waveforms and Figure 11: Asynchronous page read AC waveforms for
details.
59/119
Read modes
10.2
M58PR256LE, M58PR512LE, M58PR001LE
Synchronous burst read mode
In synchronous burst read mode the data is output in bursts synchronized with the clock. It is
possible to perform burst reads across bank boundaries.
Synchronous burst read mode can only be used to read the memory array. For other read
operations, such as read Status Register, read CFI, read electronic signature and read EFA,
single synchronous read or asynchronous random access read must be used.
In synchronous burst read mode, the flow of the data output depends on parameters that
are configured in the Configuration Register. A burst sequence starts at the first clock edge
after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are
internally incremented and data is output on each data cycle after a delay which depends on
the X latency bits CR14-CR11 of the Configuration Register.
The number of words to be output during a synchronous burst read operation can be
configured as 8 words, 16 words or continuous (burst length bits CR2-CR0).
The Wait signal may be asserted to indicate to the system that an output delay will occur.
This delay depends on the starting address of the burst sequence and on the burst
configuration.
Wait is asserted during the X latency, the wait state, and at the end of an 8- and 16-word
burst. It is only de-asserted when output data is valid.
In continuous burst read mode, a wait state occurs when crossing the first 16-word
boundary if the start address is not 16-word aligned.
The Wait signal can be configured to be active Low or active High by setting CR10 in the
Configuration Register.
See Table 30: Synchronous read AC characteristics and Figure 12: Synchronous burst read
AC waveforms for details.
10.3
Single synchronous read mode
Single synchronous read operations are similar to synchronous burst read operations
except that the memory outputs the same data until the burst length requirements are
satisfied (according to Configuration Register bits CR2-CR0).
Single synchronous read operations are used to read the EFA, electronic signature, Status
Register, CFI, block protection status, Configuration Register status or Protection Register.
When the addressed bank is in read CFI, read Status Register or read electronic signature
mode, the Wait signal is asserted during the X latency, the wait state and at the end of a 4-,
8- and 16-word burst. It is only de-asserted when the output data is valid.
See Table 30: Synchronous read AC characteristics and Figure 12: Synchronous burst read
AC waveforms for details.
60/119
M58PR256LE, M58PR512LE, M58PR001LE
11
Dual operations and multiple bank architecture
Dual operations and multiple bank architecture
The multiple bank architecture of the M58PRxxxLE gives greater flexibility for software
developers to split the code and data spaces within the memory array. The dual operations
feature simplifies the software management of the device by allowing code to be executed
from one bank while another bank is being programmed or erased.
The dual operations feature means that while programming or erasing in one bank, read
operations are possible in another bank with zero latency (only one bank at a time is allowed
to be in program or erase mode).
If a read operation is required in a bank, which is programming or erasing, the program or
erase operation can be suspended.
Also, if the suspended operation was erase then a Program command can be issued to
another block. This means the device can have one block in erase suspend mode, one
programming and other banks in read mode.
Bus read operations are allowed in another bank between setup and confirm cycles of
program or erase operations.
By using a combination of these features, read operations are possible at any moment in the
M58PRxxxLE device.
Dual operations between the EFA and either of the CFI, the OTP, or the electronic signature
memory space are not allowed. Table 21 shows which dual operations are allowed or not
between the CFI, the OTP, the electronic signature locations and the memory array.
Table 19 and Table 20 show the dual operations possible in other banks and in the same
bank.
Table 19.
Dual operations allowed in other banks
Commands allowed in another bank
Status of bank
Read
Array
Read
Read
Read
Program,
Program/ Program/
Read
Block
Status
CFI Electronic
Buffer
Erase
Erase
EFA
Erase
Register Query Signature
Program
Suspend Resume
Idle
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Programming
Yes
Yes
Yes
Yes
Yes
–
–
Yes
–
Erasing
Yes
Yes
Yes
Yes
Yes
–
–
Yes
–
Program
suspended
Yes
Yes
Yes
Yes
Yes
–
–
–
Yes
Erase
suspended
Yes
Yes
Yes
Yes
Yes
Yes
–
–
Yes
61/119
Dual operations and multiple bank architecture
Table 20.
M58PR256LE, M58PR512LE, M58PR001LE
Dual operations allowed in same bank
Commands allowed in same bank
Status of
bank
Idle
Programming
Read
Array
Read
Status
Register
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
(1)
Yes
Yes
Yes
Yes
–
–
Yes
–
(1)
Yes
Yes
Yes
Yes
–
–
Yes
–
–
Erasing
–
Read
Read
Program,
Program/ Program/
Read
Block
CFI
Electronic
Buffer
Erase
Erase
EFA
Erase
Query Signature
Program
Suspend Resume
Program
suspended
Yes(2)
Yes
Yes
Yes
Yes
–
–
–
Yes
Erase
suspended
Yes(2)
Yes
Yes
Yes
Yes
Yes(1)
–
–
Yes
1. The Read Array command is accepted but the data output is not guaranteed until the program or erase has
completed.
2. Not allowed in the block that is being erased or in the program region that is being programmed.
Table 21.
Dual operation limitations
OTP, EFA or CFI
data
Main array
bank
Read
Program/erase
While programming or erasing in a main array bank, the OTP,
CFI data and EFA blocks may be read from any other bank.
Program
Read
While programming to the OTP area, read operations are only
allowed in the other main array banks. Access to EFA data or
CFI data is not allowed.
Read
While programming or erasing an EFA block, it is not allowed to
read OTP or CFI data. Read operations to the banks whose
addresses are not being used to address the EFA, are
supported.
Program/erase
62/119
Comments
M58PR256LE, M58PR512LE, M58PR001LE
12
Block locking
Block locking
The M58PRxxxLE features an instant, individual block locking scheme that allows any block
to be locked or unlocked with no latency. This locking scheme has three levels of protection.
●
Lock/unlock - this first level allows software only control of block locking.
●
Lock-down - this second level requires hardware interaction before locking can be
changed.
●
VPP ≤ VPPLK - the third level offers a complete hardware protection against program
and erase on all blocks.
The protection status of each block can be set to locked, unlocked, and locked-down.
Table 22 defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C,
Figure 25 shows a flowchart for the locking operations.
12.1
Reading a block’s lock status
The lock status of every block can be read in the read electronic signature mode of the
device. To enter this mode issue the Read Electronic Signature command. Subsequent
reads at the address specified in Table 10 output the protection status of that block.
The lock status is represented by DQ0 and DQ1. DQ0 indicates the block lock/unlock status
and is set by the Lock command and cleared by the Unlock command. DQ0 is automatically
set when entering lock-down. DQ1 indicates the lock-down status and is set by the lockdown command. DQ1 cannot be cleared by software, only by a hardware reset or powerdown.
The following sections explain the operation of the locking system.
12.2
Locked state
The default status of all blocks on power-up or after a hardware reset is locked (states
(0,0,1) or (1,0,1)). Locked blocks are fully protected from program or erase operations. Any
program or erase operations attempted on a locked block returns an error in the Status
Register. The status of a locked block can be changed to unlocked or locked-down using the
appropriate software commands. An unlocked block can be locked by issuing the Lock
command.
12.3
Unlocked state
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)) can be programmed or erased. All unlocked
blocks return to the locked state after a hardware reset or when the device is powered-down.
The status of an unlocked block can be changed to locked or locked-down using the
appropriate software commands. A locked block can be unlocked by issuing the unlock
command.
63/119
Block locking
12.4
M58PR256LE, M58PR512LE, M58PR001LE
Lock-down state
Blocks that are locked-down (state (0,1,x)) are protected from program and erase operations
(as for locked blocks) but their protection status cannot be changed using software
commands alone. A locked or unlocked block can be locked down by issuing the Lock-down
command. Locked-down blocks revert to the locked state when the device is reset or
powered-down.
The lock-down function is dependent on the Write Protect, WP, input pin.
When WP = 0 (VIL), the blocks in the lock-down state (0,1,x) are protected from program,
erase and protection status changes.
When WP = 1 (VIH) the lock-down function is disabled (1,1,x) and locked-down blocks can
be individually unlocked to the (1,1,0) state by issuing the software command, where they
can be erased and programmed.
When the lock-down function is disabled (WP=1) blocks can be locked (1,1,1) and unlocked
(1,1,0) as desired. When WP = 0 blocks that were previously locked-down return to the
Lock-down state (0,1,x) regardless of any changes that were made while WP = 1.
Device reset or power-down resets all blocks, including those in lock-down, to the locked
state.
12.5
Locking operations during erase suspend
Changes to block lock status can be performed during an erase suspend by using the
standard locking command sequences to unlock, lock or lock down a block. This is useful in
the case when another block needs to be updated while an erase operation is in progress.
To change block locking during an erase operation, first write the Erase Suspend command,
then check the Status Register until it indicates that the erase operation has been
suspended. Next, write the desired lock command sequence to a block and the lock status is
changed. After completing any desired lock, read, or program operations, resume the erase
operation with the Erase Resume command.
If a block is locked or locked-down during an Erase Suspend of the same block, the locking
status bits are changed immediately, but when the erase is resumed, the erase operation
completes. Locking operations cannot be performed during a program suspend.
64/119
M58PR256LE, M58PR512LE, M58PR001LE
Table 22.
Block locking
Lock status
Current protection status(1)
Next protection status(1)
(WP, DQ1, DQ0)
(WP, DQ1, DQ0)
Current
state
Program/erase
allowed
After Block
Lock
command
After Block
Unlock
command
After Block
Lock-down
command
After WP
transition
1,0,0
yes
1,0,1
1,0,0
1,1,1
0,0,0
no
1,0,1
1,0,0
1,1,1
0,0,1
1,1,0
yes
1,1,1
1,1,0
1,1,1
0,1,1
1,1,1
no
1,1,1
1,1,0
1,1,1
0,1,1
0,0,0
yes
0,0,1
0,0,0
0,1,1
1,0,0
no
0,0,1
0,0,0
0,1,1
1,0,1
no
0,1,1
0,1,1
0,1,1
1,1,1 or 1,1,0(3)
1,0,1
0,0,1
(2)
(2)
0,1,1
1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for
a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL.
2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.
3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
65/119
Program and erase times and endurance cycles
13
M58PR256LE, M58PR512LE, M58PR001LE
Program and erase times and endurance cycles
The program and erase times and the number of program/ erase cycles per block are shown
in Table 23. Exact erase times may change depending on the memory array condition. The
best scenario is when all the bits in the block are at ‘0’ (pre-programmed). The worst
scenario is when all the bits in the block are at ‘1’ (not preprogrammed). Usually, the system
overhead is negligible with respect to the Erase time. In the M58PRxxxLE the maximum
number of program/erase cycles depends on the VPP voltage supply used.
Table 23.
Program/erase times and endurance cycles(1) (2)
Typ
Typical after
100 kW/E Max
cycles
0.7
2.5
s
0.9
4
s
50
230
µs
250
500
µs
50
230
µs
250
500
µs
Buffer (512 words) (Buffer
Program)
2.15
4.3
ms
EFA block (4 KWord)
0.2
0.94
s
Main array block (128 KWord)
(Buffer Program)
0.55
1.1
s
Program
20
30
µs
Erase
20
30
µs
Parameter
Condition
Min
EFA block (4 KWord)
Unit
Erase
Main array block 128 KWord)
Single cell(4)
Word
Program(5)
Buffer Program
Single word(4)
Word
Program(5)
Buffer Program
VPP = VDD
Program(3)
Suspend Latency
Main array block
Program/Erase
cycles (per block) EFA block
Blank Check
66/119
Main array block
100 000
cycles
100 000
3.2
ms
M58PR256LE, M58PR512LE, M58PR001LE
Table 23.
Program and erase times and endurance cycles
Program/erase times and endurance cycles(1) (2) (continued)
Parameter
Condition
Min
EFA block (4 KWord)
Typ
Typical after
100 kW/E Max
cycles
0.7
2.5
s
Unit
Erase
Main array block (128 KWord)
(4)
Single cell
VPP = VPPH
Single word(4)
Program(3)
Buffer (512
words)
Main block
(128 KWords)
0.9
4
s
(5)
50
230
µs
Word Program(5)
50
230
µs
Buffer Enhanced
Factory
Program(4)
4.2
Buffer Program
2.15
Buffer Enhanced
Factory Program
2.15
Buffer Program
0.55
Buffer Enhanced
Factory Program
0.55
Word Program
EFA block (4 KWords)
Main array block (128 KWords)
Program/Erase
cycles (per block) EFA block (4 KWords)
Blank Check
Main array block
0.2
µs
4.3
ms
ms
1.1
s
s
0.94
100 000
cycles
100 000
3.2
ms
1. TA = –30 to 85 °C; VDD = 1.7 V to 2 V; VDDQ = 1.7 V to 2 V.
2. Values are liable to change with the external system-level overhead (command sequence and Status
Register polling execution).
3. Excludes the time needed to execute the command sequence.
4. This is an average value on the entire device.
5. The first Word Program in a program region will take 115 µs, the subsequent words will take 50 µs to
program.
67/119
Maximum ratings
14
M58PR256LE, M58PR512LE, M58PR001LE
Maximum ratings
Stressing the device above the ratings listed in Table 24: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 24.
Absolute maximum ratings
Value
Symbol
Unit
Min
Max
Ambient operating temperature
–30
85
°C
TBIAS
Temperature under bias
–30
85
°C
TSTG
Storage temperature
–65
125
°C
VIO
Input or output voltage
–1
3
V
VDD
Supply voltage
–1
3
V
Input/output supply voltage
–1
3
V
Program voltage
–1
10
V
Output short circuit current
100
mA
Time for VPP at VPPH
100
hours
TA
VDDQ
VPP
IO
tVPPH
68/119
Parameter
M58PR256LE, M58PR512LE, M58PR001LE
15
DC and AC parameters
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables in this
section are derived from tests performed under the measurement conditions summarized in
Table 25: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 25.
Operating and AC measurement conditions
Parameter
Min
Max
Units
VDD supply voltage
1.7
2.0
V
VDDQ supply voltage
1.7
2.0
V
VPP supply voltage (factory environment)
8.5
9.5
V
VPP supply voltage (application environment)
0.9
2.0
V
Ambient operating temperature
–30
85
°C
Load capacitance (CL)
30
pF
Input rise and fall times
3
Input pulse voltages
Input and output timing ref. voltages
Figure 8.
ns
0 to VDDQ
V
VDDQ/2
V
AC measurement I/O waveform
VDDQ
VDDQ/2
0V
AI06161
69/119
DC and AC parameters
Figure 9.
M58PR256LE, M58PR512LE, M58PR001LE
AC measurement load circuit
VDDQ
VDDQ
VDD
16.7 kΩ
DEVICE
UNDER
TEST
CL
0.1 µF
16.7 kΩ
0.1 µF
CL includes JIG capacitance
Table 26.
Symbol
CIN
COUT
Capacitance(1)
Parameter
Input capacitance
Output capacitance
1. Sampled only, not 100% tested.
70/119
AI06162
Test condition
Min
Max
Unit
VIN = 0 V
2
8
pF
VOUT = 0 V
4
8
pF
M58PR256LE, M58PR512LE, M58PR001LE
Table 27.
Symbol
DC and AC parameters
DC characteristics - currents
Parameter
ILI
Input leakage current
ILO
Output leakage current
Supply current
Asynchronous read (f=5 MHz)
Test condition(1)
Max
Unit
0 V ≤ VIN ≤ VDDQ
±1
µA
0 V ≤ VOUT ≤ VDDQ
±1
µA
25
35
mA
11
15
mA
8 word
22
32
mA
16 word
19
26
mA
Continuous
25
34
mA
8 word
26
36
mA
16 word
23
30
mA
Continuous
30
42
mA
256 Mbit
35
95
RP = VSS ± 0.2 V 512 Mbit
50
120
70
224
E = VIL, G = VIH
Supply current
Page read (f=13 MHz)
IDD1
Supply current
Synchronous read (f=66 MHz)
Supply current
Synchronous read (f = 108 MHz)
IDD2
Supply current (reset)
1 Gbit
IDD3
IDD4(1)
IDD5(2)
IDD6
(3)
IDD7(3)(4)
IDD8(3)
Supply current (standby)
Supply current (automatic
standby)
Typ
µA
256 Mbit
E = VDDQ ± 0.2 V
512 Mbit
K = VSS
1 Gbit
35
95
50
120
70
224
256 Mbit
35
95
512 Mbit
50
120
1 Gbit
70
224
2
45
µA
E = VIL, G = VIH,
RP = VIH
Supply current (deep powerdown)
µA
µA
Supply current (program)
VPP = VPPH, VPP = VDD
35
50
mA
Supply current (erase)
VPP = VPPH, VPP = VDD
35
50
mA
Supply current (blank check)
VPP = VPPH, VPP = VDD
35
50
mA
Program/erase in one bank,
asynchronous read in
another bank
60
80
mA
Program/erase in one bank,
synchronous read
(continuous, f = 108 MHz) in
another bank
65
92
mA
35
95
50
120
70
224
Supply current
(dual operations)
Supply current program/ erase
suspended (standby)
256 Mbit
E = VDDQ ± 0.2 V
512 Mbit
K = VSS
1 Gbit
µA
71/119
DC and AC parameters
Table 27.
M58PR256LE, M58PR512LE, M58PR001LE
DC characteristics - currents (continued)
Test condition(1)
Typ
Max
Unit
VPP = VPPH
8
22
mA
VPP = VDD
0.05
0.1
mA
VPP = VPPH
8
22
mA
VPP = VDD
0.05
0.1
mA
VPP supply current (read)
VPP ≤ VDD
2
15
µA
VPP supply current (standby,
program/erase suspend)
VPP ≤ VDD
0.2
5
µA
VPP = VPPH
0.05
0.1
mA
VPP = VPP1
0.05
0.1
mA
Symbol
Parameter
VPP supply current (program)
IPP1(3)
VPP supply current (erase)
IPP2
IPP3(3)
IPP4
VPP supply current (blank check)
1. All inputs stable.
2. The DPD current is measured 40 µs after entering the deep power-down mode.
3. Sampled only, not 100% tested.
4. VDD dual operation current is the sum of read and program or erase currents.
Table 28.
Symbol
72/119
DC characteristics - voltages
Parameter
Test condition
Min
Typ
Max
Unit
VIL
Input low voltage
0
0.4
V
VIH
Input high voltage
VDDQ –0.4
VDDQ + 0.4
V
VOL
Output low voltage
IOL = 100 µA
0.1
V
VOH
Output high voltage
IOH = –100 µA
VDDQ –0.1
VPP1
VPP program voltage-logic
Program, erase
1.1
1.8
3.3
V
VPPH
VPP program voltage factory
Program, erase
8.5
9.0
9.5
V
VPPLK
Program or erase lockout
0.4
V
VLKO
VDD lock voltage
VRPH
RP pin extended high
voltage
VLKOQ
VDDQ lock voltage
V
1
V
3.3
0.9
V
V
Hi-Z
Hi-Z
tELLH
tLLLH
tAVLH
tGLTV
tELQX
tELTV
tGLQV
tLHAX
tGLQX
tELQV
tLLQV
tAVQV
VALID
tEHQZ
tEHQX
tEHTZ
tGHQZ
tGHQX
tAXQX
VALID
VALID
tGHTZ
Notes: 1. WAIT is active Low.
2. Latch Enable, L, can be kept Low (also at board level) when the Latch Enable function is not required or supported.
WAIT(1)
DQ0-DQ15
G
E
L(2)
A0-Amax
tAVAV
AI12860
M58PR256LE, M58PR512LE, M58PR001LE
DC and AC parameters
Figure 10. Asynchronous random access read AC waveforms
73/119
74/119
Hi-Z
tAVAV
VALID ADDRESS
tELQV
Valid Address Latch
tGLQX
tGLQV
tELTV
tGLTV
tELQX
tELLH
tLLQV
tLLLH
tAVLH
Note 1. WAIT is active Low.
DQ0-DQ15
WAIT (1)
G
E
L
A0-A3
A4-Amax
Enabled
Outputs
tLHAX
VALID
DATA
VALID
DATA
tAVQV1
VALID
DATA
VALID
DATA
Valid Data
VALID
DATA
VALID
DATA
VALID
DATA
VALID
DATA
VALID ADD. VALID ADD. VALID ADD. VALID ADD. VALID ADD. VALID ADD. VALID ADD.
VALID ADDRESS
AI12861b
Standby
DC and AC parameters
M58PR256LE, M58PR512LE, M58PR001LE
Figure 11. Asynchronous page read AC waveforms
M58PR256LE, M58PR512LE, M58PR001LE
Table 29.
DC and AC parameters
Asynchronous read AC characteristics
Symbol
Alt
tAVAV
tRC
Address Valid to Next Address Valid
Min
96
96
ns
tAVQV
tACC
Address Valid to Output Valid (random)
Max
96
96
ns
tAVQV1
tPAGE
Address Valid to Output Valid (page)
Max
20
25
ns
tAXQX(1)
tOH
Address Transition to Output transition
Min
0
0
ns
Chip Enable Low to Wait Valid
Max
14
14
ns
Read timings
tELTV
108 MHz 66 MHz Unit
tELQV(2)
tCE
Chip Enable Low to Output Valid
Max
96
96
ns
tELQX(1)
tLZ
Chip Enable Low to Output transition
Min
0
0
ns
Chip Enable High to Wait Hi-Z
Max
9
14
ns
tEHTZ
tEHQX(1)
tOH
Chip Enable High to Output transition
Min
0
0
ns
(1)
tHZ
Chip Enable High to Output Hi-Z
Max
9
14
ns
tGLQV(2)
tOE
Output Enable Low to Output Valid
Max
20
20
ns
tGLQX(1)
tOLZ
Output Enable Low to Output transition
Min
0
0
ns
Output Enable Low to Wait Valid
Max
7
11
ns
tEHQZ
tGLTV
tGHQX(1)
tOH
Output Enable High to Output transition
Min
0
0
ns
(1)
tDF
Output Enable High to Output Hi-Z
Max
9
14
ns
Output Enable High to Wait Hi-Z
Max
9
17
ns
tGHQZ
tGHTZ
Latch timings
Parameter
tAVLH
tAVADVH
Address Valid to Latch Enable High
Min
5
5
ns
tELLH
tELADVH
Chip Enable Low to Latch Enable High
Min
9
10
ns
tLHAX
tADVHAX
Latch Enable High to Address transition
Min
5
5
ns
Min
7
7
ns
Max
96
96
ns
tLLLH
tLLQV
tADVLADVH Latch Enable Pulse width
tADVLQV
Latch Enable Low to Output Valid
(random)
1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
75/119
76/119
Hi-Z
tELKH
Hi-Z
tLLLH
Address
Latch
tKHAX
tAVKH
tLLKH
tAVLH
VALID ADDRESS
X Latency
tGLTV
tGLQX
Note 2
Note 1
VALID
Valid Data Flow
tKHTV
tKHQV
tKHQV
VALID
Note 2
tKHTX
tKHQX
tKHQX
VALID
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.
2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low.
3. Address latched and data output on the rising clock edge.
WAIT
G
E
K
L
A0-Amax
DQ0-DQ15
Boundary
Crossing
Note 2
NOT VALID
Data
Valid
tGHQZ
tGHQX
tEHQZ
tEHQX
AI12862
Standby
tEHTZ
tEHEL
VALID
DC and AC parameters
M58PR256LE, M58PR512LE, M58PR001LE
Figure 12. Synchronous burst read AC waveforms
M58PR256LE, M58PR512LE, M58PR001LE
DC and AC parameters
Figure 13. Single synchronous read AC waveforms
A0-Amax
VALID ADDRESS
tAVKH
L
tLLKH
K(2)
tELKH
tKHQV
tELQV
E
tGLQV
tGLQX
G
tELQX
DQ0-DQ15
tGHTZ
Hi-Z
VALID
tKHTV
tGLTV
WAIT(1,2)
Hi-Z
tLLTV
Note 1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
2. Address latched and data output on the rising clock edge.
AI12863b
Figure 14. Clock input AC waveform
tKHKL
tKHKH
tf
tr
tKLKH
AI06981
77/119
DC and AC parameters
Table 30.
Clock specifications
Synchronous Read timings
Symbol
M58PR256LE, M58PR512LE, M58PR001LE
Synchronous read AC characteristics
Alt
Parameter
108 MHz
66 MHz
Unit
tAVKH
tAVCLKH
Address Valid to Clock High
Min
5
5
ns
tELKH
tELCLKH
Chip Enable Low to Clock High
Min
5
5
ns
tEHEL
Chip Enable Pulse width (subsequent
synchronous reads)
Min
9
11
ns
tEHTZ
Chip Enable High to Wait Hi-Z
Max
9
11
ns
tKHAX
tCLKHAX
Clock High to Address transition
Min
5
5
ns
tKHQV
tKHTV
tCLKHQV
Clock High to Output Valid
Clock High to WAIT Valid
Max
7
11
ns
tKHQX
tKHTX
tCLKHQX
Clock High to Output transition
Clock High to WAIT transition
Min
2
3
ns
tLLKH
tADVLCLKH Latch Enable Low to Clock High
Min
5
5
ns
tLLTV
Latch Enable Low to WAIT Valid
Max
14
14
ns
Clock period (f=66 MHz)
Min
15
ns
Clock period (f=108 MHz)
Min
9
Clock High to Clock Low
Clock Low to Clock High
Min
2.5
3.5
ns
Min
0.3
-
ns
Max
2
3
ns
tKHKH
tKHKL
tKLKH
tf
tr
tCLK
Clock fall or rise time
1. Sampled only, not 100% tested.
2. For other timings please refer to Table 29: Asynchronous read AC characteristics.
78/119
ns
K
VPP
WP
DQ0-DQ15
W
G
E
L
A0-Amax
tWHDX
CONFIRM COMMAND
OR DATA INPUT
tVPHWH
tELKH
tWHVPL
tWHWPL
tWHQV
tWHEL
tWHGL
tWHAV
tWHAX
CMD or DATA
VALID ADDRESS
tAVWH
tWPHWH
tWHWL
tWHEH
tWHLL
tWLWH
tLHAX
COMMAND
tLLLH
SET-UP COMMAND
tDVWH
tGHWL
tELWL
tELLH
tAVLH
BANK ADDRESS
tAVAV
tQVVPL
tQVWPL
STATUS REGISTER
STATUS REGISTER
READ
1st POLLING
tELQV
VALID ADDRESS
PROGRAM OR ERASE
AI12864
M58PR256LE, M58PR512LE, M58PR001LE
DC and AC parameters
Figure 15. Write AC waveforms, write enable controlled
79/119
DC and AC parameters
M58PR256LE, M58PR512LE, M58PR001LE
Write AC characteristics, write enable controlled(1)
Table 31.
Symbol
Alt
tAVAV
96
96
ns
tAVLH
Address Valid to Latch Enable High
Min
5
5
ns
tAVWH(2)
Address Valid to Write Enable High
Min
40
40
ns
Data Valid to Write Enable High
Min
40
40
ns
Chip Enable Low to Latch Enable High
Min
9
10
ns
Chip Enable Low to Write Enable Low
Min
0
0
ns
tELQV
Chip Enable Low to Output Valid
Min
96
96
ns
tELKH
Chip Enable Low to Clock High
Min
5
5
ns
tGHWL
Output Enable High to Write Enable Low
Min
14
17
ns
tLHAX
Latch Enable High to Address transition
Min
5
5
ns
tLLLH
Latch Enable Pulse width
Min
7
7
ns
Write Enable High to Address Valid
Min
0
0
ns
tAH
Write Enable High to Address transition
Min
0
0
ns
tWHDX
tDH
Write Enable High to Input transition
Min
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
0
ns
Write Enable High to Chip Enable Low
Min
20
20
ns
tWHGL
Write Enable High to Output Enable Low
Min
0
0
ns
tWHLL(3)
Write Enable High to Latch Enable Low
Min
20
20
ns
tWPH Write Enable High to Write Enable Low
Min
20
20
ns
Write Enable High to Output Valid
Min
116
116
ns
Write Enable Low to Write Enable High
Min
40
40
ns
tQVVPL
Output (Status Register) Valid to VPP Low
Min
0
0
ns
tQVWPL
Output (Status Register) Valid to Write
Protect Low
Min
0
0
ns
VPP High to Write Enable High
Min
200
200
ns
tWHVPL
Write Enable High to VPP Low
Min
200
200
ns
tWHWPL
Write Enable High to Write Protect Low
Min
200
200
ns
tWPHWH
Write Protect High to Write Enable High
Min
200
200
ns
tELWL
Write Enable Controlled timings
Unit
Min
tDS
tELLH
tCS
tWHAV(2)
tWHAX
(2)
tWHEL(3)
tWHWL
tWHQV
tWLWH
Protection timings
108 MHz 66 MHz
Address Valid to Next Address Valid
tDVWH
tWC
Parameter
tVPHWH
tWP
tVPS
1. Sampled only, not 100% tested.
2. Meaningful only if L is always kept Low.
3. tWHELand tWHLL have this value when reading in the targeted bank or when reading after a Set
Configuration Register command. System designers should take this into account and may insert a
software No-Op instruction to delay the first read in the same bank after issuing any command and to delay
the first read to any address after issuing a Set Configuration Register command. If the first read after the
command is a Read Array operation in a different bank and no changes to the Configuration Register have
been issued, tWHEL is 0 ns.
80/119
K
VPP
WP
DQ0-DQ15
E
G
W
L
A0-Amax
tGHEL
tELEH
tLHAX
COMMAND
SET-UP COMMAND
tDVEH
tLLLH
tELLH
tWLEL
tAVLH
BANK ADDRESS
tEHDX
tEHEL
tEHWH
CMD or DATA
tEHAX
CONFIRM COMMAND
OR DATA INPUT
tVPHEH
tWPHEH
tAVEH
VALID ADDRESS
tAVAV
tELKH
tEHVPL
tEHWPL
tWHEL
tWHQV
tEHGL
tQVVPL
AI12865
tQVWPL
STATUS REGISTER
STATUS REGISTER
READ
1st POLLING
tELQV
VALID ADDRESS
PROGRAM OR ERASE
M58PR256LE, M58PR512LE, M58PR001LE
DC and AC parameters
Figure 16. Write AC waveforms, Chip Enable controlled
81/119
DC and AC parameters
M58PR256LE, M58PR512LE, M58PR001LE
Write AC characteristics, Chip Enable controlled(1)
Table 32.
Symbol
Alt
Chip Enable Controlled timings
108 MHz 66 MHz
Unit
tAVAV
tWC
Address Valid to Next Address Valid
Min
96
96
ns
tAVEH
tWC
Address Valid to Chip Enable High
Min
40
45
ns
Address Valid to Latch Enable High
Min
5
5
ns
tAVLH
tDVEH
tDS
Data Valid to Chip Enable High
Min
40
40
ns
tEHAX
tAH
Chip Enable High to Address transition
Min
0
0
ns
tEHDX
tDH
Chip Enable High to Input transition
Min
0
0
ns
tEHEL
tCPH Chip Enable High to Chip Enable Low
Min
20
20
ns
Chip Enable High to Output Enable Low
Min
0
0
ns
Chip Enable High to Write Enable High
Min
0
0
ns
Chip Enable Low to Clock High
Min
5
5
ns
Chip Enable Low to Chip Enable High
Min
40
45
ns
tELLH
Chip Enable Low to Latch Enable High
Min
9
10
ns
tELQV
Chip Enable Low to Output Valid
Min
96
96
ns
tGHEL
Output Enable High to Chip Enable Low
Min
14
17
ns
tLHAX
Latch Enable High to Address transition
Min
5
5
ns
tLLLH
Latch Enable Pulse width
Min
7
7
ns
Write Enable High to Chip Enable Low
Min
20
20
ns
Write Enable High to Output Valid
Min
116
116
ns
Write Enable Low to Chip Enable Low
Min
0
0
ns
tEHVPL
Chip Enable High to VPP Low
Min
200
200
ns
tEHWPL
Chip Enable High to Write Protect Low
Min
200
200
ns
tQVVPL
Output (Status Register) Valid to VPP Low
Min
0
0
ns
tQVWPL
Output (Status Register) Valid to Write
Protect Low
Min
0
0
ns
Min
200
200
ns
Min
200
200
ns
tEHGL
tEHWH
tCH
tELKH
tELEH
tWHEL
tCP
(2)
tWHQV
tWLEL
Protection timings
Parameter
tVPHEH
tWPHEH
tCS
tVPS VPP High to Chip Enable High
Write Protect High to Chip Enable High
1. Sampled only, not 100% tested.
2. tWHEL has this value when reading in the targeted bank or when reading after a Set Configuration Register
command. System designers should take this into account and may insert a software No-Op instruction to
delay the first read in the same bank after issuing any command and to delay the first read to any address
after issuing a Set Configuration Register command. If the first read after the command is a Read Array
operation in a different bank and no changes to the Configuration Register have been issued, tWHEL is
0 ns.
82/119
M58PR256LE, M58PR512LE, M58PR001LE
DC and AC parameters
Figure 17. Reset and power-up AC waveforms
tPHWL
tPHEL
tPHGL
tPHLL
W, E, G, L
tPLWL
tPLEL
tPLGL
tPLLL
RP
tVDHPH
tPLPH
VDD, VDDQ
Power-Up
Reset
AI06976
Table 33.
Symbol
Reset and power-up AC characteristics
Parameter
tPLWL
tPLEL
tPLGL
tPLLL
Reset Low to Write Enable Low,
Reset Low to Chip Enable Low,
Reset Low to Output Enable Low,
Reset Low to Latch Enable Low
tPHWL
tPHEL
tPHGL
tPHLL
tPLPH(1),(2)
tVDHPH(3)
Test condition
108 MHz / 66 MHz
Unit
During program
Min
25
µs
During erase
Min
30
µs
Other conditions
Min
80
ns
Reset High to Write Enable Low
Reset High to Chip Enable Low
Reset High to Output Enable Low
Reset High to Latch Enable Low
Min
30
ns
RP Pulse width
Min
50
ns
Supply voltages High to Reset High
Min
300
µs
1. The device reset is possible but not guaranteed if tPLPH < 50 ns.
2. Sampled only, not 100% tested.
3. It is important to assert RP to allow proper CPU initialization during power-up or reset.
83/119
DC and AC parameters
M58PR256LE, M58PR512LE, M58PR001LE
Figure 18. Deep power-down AC waveforms
tDPLDPH
DPD
E
tEHDPL
tDPHEL
Ai11625
Figure 19. Reset during deep power-down AC waveforms
DPD
E
tEHDPL
RP
Table 34.
Symbol
84/119
tPHEL
Ai11626
Deep power-down AC characteristics
Parameter
Test condition
108 MHz/66 MHz
Unit
tDPLDPH
Deep power-down asserted to
Deep power-down de-asserted
Min
50
ns
tEHDPL
Chip Enable Low to deep powerdown asserted
Min
0
µs
tDPHEL
Deep power-down de-asserted
to Chip Enable Low
Min
75
µs
tPHEL
Reset High to Chip Enable Low
Min
75
µs
During deep
power-down
M58PR256LE, M58PR512LE, M58PR001LE
16
Part numbering
Part numbering
Table 35.
Ordering information scheme
Example:
M58PR256L
E 96 ZB
5
Device type
M58
Architecture
P = Multilevel, multiple bank, large buffer
Operating voltage
R = VDD = 1.7 V to 2.0 V, VDDQ = 1.7 V to 2.0 V
Density
256 = 256 Mbit
512 = 512 Mbit
001 = 1 Gbit
Technology
L = 65 nm technology multilevel design
Memory organization
E = Uniform blocks
Speed
96 = 96 ns
Package
Not packaged separately(1)
Temperature range
5 = –30 to 85 °C
1. The M58PRxxxLE memories are only available as part of a multichip package device.
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact the ST Sales Office nearest to you.
85/119
Block address tables
Appendix A
M58PR256LE, M58PR512LE, M58PR001LE
Block address tables
The following set of equations can be used to calculate a complete set of block addresses
using the information contained in tables 36, 37, 38, 39, 40 and 41.
To calculate the block base address from the block number:
First it is necessary to calculate the bank number and the block number offset. This can be
achieved using the following formulas:
For the M58PR256LE:
Bank_Number = Block_Number / 16
Block_Number_Offset = Block_Number - (Bank_Number x 16)
For the M58PR512LE:
Bank_Number = Block_Number / 32
Block_Number_Offset = Block_Number - (Bank_Number x 32)
For the M58PR001LE:
Bank_Number = Block_Number / 64
Block_Number_Offset = Block_Number - (Bank_Number x 64)
The Block Base Address is calculated using the formula below:
Block_Base_Address = Bank_Base_Address + Block_Base_Address_Offset
To calculate the Bank number and the Block Number from the Block Base Address:
The Block Number, Bank Number and Block Number Offset can be calculated using the
formulas below:
For the M58PR256LE:
Block_Number = address / 216
Bank_Number = Block_Number / 16
Block_Number_Offset = Block_Number − (Bank_Number x 16)
For the M58PR512LE:
Block_Number = address / 232
Bank_Number = Block_Number / 32
Block_Number_Offset = Block_Number − (Bank_Number x 32)
For the M58PR001LE:
Block_Number = address / 264
Bank_Number = Block_Number / 64
Block_Number_Offset = Block_Number - (Bank_Number x 64)
86/119
M58PR256LE, M58PR512LE, M58PR001LE
Table 36.
Block address tables
M58PR256LE - bank base addresses
Bank number
Block numbers
Bank base address
0
0 - 15
000000
1
16 - 31
200000
2
32 - 47
400000
3
48 - 63
600000
4
64 - 79
800000
5
80 - 95
A00000
6
96 - 111
C00000
7
112 - 127
E00000
Table 37.
M58PR512LE - bank base addresses
Bank number
Block numbers
Bank base address
0
0 - 31
0000000
1
32 - 63
0400000
2
64 - 95
0800000
3
96 - 127
0C00000
4
128 - 159
1000000
5
160 - 191
1400000
6
192 - 223
1800000
7
224 - 255
1C00000
Table 38.
M58PR001LE - bank base addresses
Bank number
Block numbers
Bank base address
0
0 - 63
0
1
64 - 127
800000
2
128 - 191
1000000
3
192 - 255
1800000
4
256 - 319
2000000
5
320 - 383
2800000
6
384 - 447
3000000
7
448 - 511
3800000
87/119
Block address tables
Table 39.
88/119
M58PR256LE, M58PR512LE, M58PR001LE
M58PR256LE - block addresses
Block number offset
Block base address offset
0
0000000
1
0020000
2
0040000
3
0060000
4
0080000
5
00A0000
6
00C0000
7
00E0000
8
0100000
9
0120000
10
0140000
11
0160000
12
0180000
13
01A0000
14
01C0000
15
01E0000
M58PR256LE, M58PR512LE, M58PR001LE
Table 40.
Block address tables
M58PR512LE - block addresses
Block number offset
Block base address offset
0
0000000
1
0020000
2
0040000
3
0060000
4
0080000
5
00A0000
6
00C0000
7
00E0000
8
0100000
9
0120000
10
0140000
11
0160000
12
0180000
13
01A0000
14
01C0000
15
01E0000
16
0200000
17
0220000
18
0240000
19
0260000
20
0280000
21
02A0000
22
02C0000
23
02E0000
24
0300000
25
0320000
26
0340000
27
0360000
28
0380000
29
03A0000
30
03C0000
31
03E0000
89/119
Block address tables
Table 41.
90/119
M58PR256LE, M58PR512LE, M58PR001LE
M58PR001LE - block addresses
Block number
Block base address offset
0
0000000
1
0020000
2
0040000
3
0060000
4
0080000
5
00A0000
6
00C0000
7
00E0000
8
0100000
9
0120000
10
0140000
11
0160000
12
0180000
13
01A0000
14
01C0000
15
01E0000
16
0200000
17
0220000
18
0240000
19
0260000
20
0280000
21
02A0000
22
02C0000
23
02E0000
24
0300000
25
0320000
26
0340000
27
0360000
28
0380000
29
03A0000
30
03C0000
31
03E0000
32
0400000
33
0420000
34
0440000
M58PR256LE, M58PR512LE, M58PR001LE
Table 41.
Block address tables
M58PR001LE - block addresses (continued)
Block number
Block base address offset
35
0460000
36
0480000
37
04A0000
38
04C0000
39
04E0000
40
0500000
41
0520000
42
0540000
43
0560000
44
0580000
45
05A0000
46
05C0000
47
05E0000
48
0600000
49
0620000
50
0640000
51
0660000
52
0680000
53
06A0000
54
06C0000
55
06E0000
56
0700000
57
0720000
58
0740000
59
0760000
60
0780000
61
07A0000
62
07C0000
63
07E0000
91/119
Common Flash interface
Appendix B
M58PR256LE, M58PR512LE, M58PR001LE
Common Flash interface
The common Flash interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information, and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.
When the Read CFI Query command is issued the device enters CFI query mode and the
data structure is read from the memory. Tables 42, 43, 44, 45, 46, 47, 48, 49, 50, 51 and 52
show the addresses used to retrieve the data. The query data is always presented on the
lowest order data outputs (DQ0-DQ7), and the other outputs (DQ8-DQ15) are set to 0.
The CFI data structure also contains a security area where a 64-bit unique security number
is written (see Figure 4: Protection Register memory map). This area can only be accessed
in read mode by the final user. It is impossible to change the security number after it has
been written by ST. Issue a Read Array command to return to read mode.
Table 42.
Query structure overview(1)
Offset
Sub-section name
Description
000h
Reserved
Reserved for algorithm-specific information
010h
CFI query identification string
Command set ID and algorithm data offset
01Bh
System interface information
Device timing and voltage information
027h
Device geometry definition
Flash device layout
P
Primary algorithm-specific extended
query table
Additional information specific to the primary
algorithm (optional)
A
Alternate algorithm-specific extended
query table
Additional information specific to the alternate
algorithm (optional)
Security code area
Lock Protection Register
Unique device number and
user programmable OTP
080h
1. The Flash memory display the CFI data structure when CFI Query command is issued. In this table are
listed the main sub-sections detailed in tables 43, 44, 45 and 46. Query data is always presented on the
lowest order data outputs.
92/119
M58PR256LE, M58PR512LE, M58PR001LE
Table 43.
Common Flash interface
CFI query identification string
Offset
Sub-section name
Description
000h
0020h
Manufacturer code
001h
8818h
8819h
880Fh
Device code
002h00Fh
Reserved
010h
0051h
011h
0052h
012h
0059h
013h
0000h
014h
0002h
015h
offset = P = 000Ah
016h
0001h
017h
0000h
018h
0000h
019h
value = A = 0000h
01Ah
0000h
Value
ST
M58PR256LE
M58PR512LE
M58PR001LE
256 Mbits
512 Mbits
1 Gbit
Reserved
"Q"
Query unique ASCII string "QRY"
"R"
"Y"
Primary algorithm command set and control interface
ID code 16 bit ID code defining a specific algorithm
Address for primary algorithm extended query table
(see Table 46)
P = 10Ah
Alternate vendor command set and control interface
ID code second vendor - specified algorithm
supported
NA
Address for alternate algorithm extended query table
NA
93/119
Common Flash interface
Table 44.
CFI query system interface information
Offset
Data
01Bh
0017h
VDD logic supply minimum program/erase or write voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 millivolts
1.7 V
01Ch
0020h
VDD logic supply maximum program/erase or write voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 millivolts
2V
01Dh
0085h
VPP [programming] supply minimum program/erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 millivolts
8.5 V
01Eh
0095h
VPP [programming] supply maximum program/erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 millivolts
9.5 V
01Fh
0006h
Typical timeout per single byte/word program = 2n µs
64 µs
020h
000Bh
Description
Value
n
Typical timeout for buffer program = 2 µs
2048 µs
021h
000Ah
Typical timeout per individual block erase =
022h
0000h
Typical timeout for full chip erase = 2n ms
023h
024h
94/119
M58PR256LE, M58PR512LE, M58PR001LE
0002h
0002h
2n
ms
NA
n
Maximum timeout for word program = 2 times typical
Maximum timeout for buffer program =
2n
1s
256 µs
times typical
8192 µs
n
025h
0002h
Maximum timeout per individual block erase = 2 times typical
4s
026h
0000h
Maximum timeout for chip erase = 2n times typical
NA
M58PR256LE, M58PR512LE, M58PR001LE
Table 45.
Offset
Device geometry definition
Data
0019h
027h
Common Flash interface
001Ah
Description
M58PR256LE device size = 2n in number of bytes
Value
32 Mbytes
n
64 Mbytes
n
128 Mbytes
M58PR512LE device size = 2 in number of bytes
001Bh
M58PR001LE device size = 2 in number of bytes
028h
029h
0001h
0000h
Flash device interface code description
02Ah
02Bh
000Ah
0000h
Maximum number of bytes in multi-byte program or page = 2n
1024 bytes
02Ch
0001h
Number of identical sized erase block regions within the device
bit 7 to 0 = x = number of Erase block regions
1
007Fh
0000h
M58PR256LE erase block region 1 information
Number of identical-size erase blocks = 007Fh+1
127
00FFh
0000h
M58PR512LE erase block region 1 information
Number of identical-size erase blocks = 00FFh+1
255
01FFh
0000h
M58PR001LE erase block region 1 information
Number of identical-size erase blocks = 01FFh+1
511
0000h
0004h
Erase block region 1 information
Block size in region 1 = 0400h * 256 byte
02Dh
02Eh
02Fh
030h
031h
038h
Reserved Reserved for future erase block region information
x16
Async.
256 Kbyte
NA
95/119
Common Flash interface
Table 46.
M58PR256LE, M58PR512LE, M58PR001LE
Primary algorithm-specific extended query table
Offset
Data
Description
Value
(P)h = 10Ah
0050h
"P"
0052h Primary algorithm extended query table unique ASCII string “PRI”
"R"
0049h
"I"
(P+3)h =10Dh 0031h Major version number, ASCII
"1"
(P+4)h = 10Eh 0034h Minor version number, ASCII
"4"
(P+5)h = 10Fh 00E6h Extended query table contents for primary algorithm. Address (P+5)h
contains less significant byte (1 = Yes, 0 = No)
(P+6)h = 110h 0007h
(P+7)h = 111h 0000h
(P+8)h = 112h 0000h
bit 0 Chip Erase supported
bit 1 Erase Suspend supported
bit 2 Program Suspend supported
bit 3 Legacy Lock/Unlock supported
bit 4 Queued Erase supported
bit 5 Instant individual block locking supported
bit 6 Protection bits supported
bit 7 Page mode read supported
bit 8 Synchronous read supported
bit 9 Simultaneous operation supported
bit 10 Extended Flash Array Blocks supported
bit 11 to 29 reserved; undefined bits are ‘0’.
bit 30 CFI links to follow
bit 31 Optional features. If bit 31 is ’1’ then another 31 bit field of
optional features follows at the end of the bit-30 field.
Supported functions after suspend
Read Array, Read Status Register and CFI query
(P+9)h = 113h 0001h
bit 0 Program supported after erase suspend (1 = Yes, 0 = No)
bit 7 to 1 Reserved; undefined bits are ‘0’
(P+A)h = 114h 0033h Block protect status
Defines which bits in the Block Status Register section of the query
are implemented.
bit 0 Block protect Status Register lock/unlock
bit active (1 = Yes, 0 = No)
bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 =
No)
(P+B)h = 115h 0000h
bit 4 EFA Block protect Status Register Lock/Unlock bit active
(1=yes, 2=No)
bit 5 EFA Block Lock Status Register Lock-Down bit active (1=yes,
2=No)
bit 15 to 6 and 3 to 2 Reserved for future use; undefined bits are ‘0’
VDD logic supply optimum program/erase voltage (highest
performance)
(P+C)h = 116h 0018h
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
(P+D)h = 117h 0090h
96/119
VPP supply optimum program/erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
1.8 V
9V
M58PR256LE, M58PR512LE, M58PR001LE
Table 47.
Protection Register information
Offset
Data
(P+E)h = 118h
0002h
(P+F)h = 119h
0080h
(P+10)h = 11Ah
0000h
(P+ 11)h = 11Bh
0003h
(P+12)h = 11Ch
0003h
(P+13)h = 11Dh
0089h
(P+14)h = 11Eh
0000h
(P+15)h = 11Fh
0000h
(P+16)h = 120h
0000h
(P+17)h = 121h
0000h
(P+18)h = 122h
0000h
(P+19)h = 123h
0000h
(P+1A)h = 124h
0010h
(P+1B)h = 125h
0000h
(P+1C)h = 126h
0004h
Table 48.
Offset
Common Flash interface
Description
Number of protection register fields in JEDEC ID space.
0000h indicates that 256 fields are available.
Protection field 1: protection description
Bits 0-7 Lower byte of protection register address
Bits 8-15 Upper byte of protection register address
Bits 16-23 2n bytes in factory pre-programmed region
Bits 24-31 2n bytes in user programmable region
Value
2
80h
00h
8 bytes
8 bytes
89h
Protection Register 2: protection description
Bits 0-31 protection register address
Bits 32-39 n number of factory programmed regions (lower
byte)
Bits 40-47 n number of factory programmed regions (upper
byte)
Bits 48-55 2n bytes in factory programmable region
Bits 56-63 n number of user programmable regions (lower
byte)
Bits 64-71 n number of user programmable regions (upper
byte)
Bits 72-79 2n bytes in user programmable region
00h
00h
00h
0
0
0
16
0
16
Burst Read information
Data
Description
Page-mode read capability
n
(P+1D)h = 127h 0005h bits 0-7 ’n’ such that 2 HEX value represents the number of readpage bytes. See offset 0028h for device word width to determine
page-mode data output width.
(P+1E)h = 128h 0003h
Number of synchronous mode read configuration fields that
follow.
Value
32
bytes
3
Synchronous mode read capability configuration 1
bit 3-7 Reserved
bit 0-2 ’n’ such that 2n+1 HEX value represents the maximum
number of continuous synchronous reads when the device is
configured for its maximum word width. A value of 07h indicates
(P+1F)h = 129h 0002h that the device is capable of continuous linear bursts that will
output data until the internal burst counter reaches the end of the
device’s burstable address space. This field’s 3-bit value can be
written directly to the read configuration register bit 0-2 if the
device is configured for its maximum word width. See offset
0028h for word width to determine the burst data output width.
8
(P+20)h = 12Ah 0003h Synchronous mode read capability configuration 2
16
(P-21)h = 12Bh 0007h Synchronous mode read capability configuration 3
Cont.
97/119
Common Flash interface
Table 49.
M58PR256LE, M58PR512LE, M58PR001LE
Bank and erase block region information
Offset(1)
Data
(P+22)h = 12Ch
01h
Description
Number of bank regions within the device(2)
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There is one bank region, see tables 36, 37, 38, 39, 40 and 41 in Appendix A.
Table 50.
Bank and erase block region 1 information(1)
Offset
Data
(P+23)h = 12Dh
16h
(P+24)h = 12Eh
00h
(P+25)h = 12Fh
08h
(P+26)h = 130h
00h
Description
Data size of this bank region information section (addressable locations
including this one)
Number of identical banks within bank region 1
(P+27)h = 131h
(P+28)h = 132h
(P+29)h = 133h
(P+2A)h = 134h
(P+2B)h = 135h
(P+2C)h = 136h
(P+2D)h = 137h
00h
Number of program or erase operations allowed in other banks while a
bank in this region is being erased
Bits 0-3: number of simultaneous program operations
Bits 4-7: number of simultaneous erase operations
00h
Number of program or erase operations allowed in other banks while a
bank in this region is being erased
Bits 0-3: number of simultaneous program operations
Bits 4-7: number of simultaneous erase operations
01h
Types of erase block regions in bank region 1
n = number of erase block regions with contiguous same-size erase
blocks.
Symmetrically blocked banks have one blocking region(2)
0Fh(3)
1Fh(4)
3Fh(5) Bank region 1 Erase block type 1 information
00h Bits 0-15: n+1 = number of identical-sized erase blocks in each bank
Bits 16-31: n×256 = number of bytes in erase block region
00h
(P+2E)h = 138h
04h
(P+2F)h = 139h
64h
(P+30)h = 13Ah
00h
(P+31)h = 13Bh
98/119
11h
Number of program or erase operations allowed in bank region 1:
Bits 0-3: number of simultaneous program operations
Bits 4-7: number of simultaneous erase operations
12h
Bank region 1 (Erase block type 1)
Minimum block erase cycles × 1000
Bank region 1 (Erase block type 1): bits per cell, internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5-7: reserved
M58PR256LE, M58PR512LE, M58PR001LE
Table 50.
Common Flash interface
Bank and erase block region 1 information(1) (continued)
Offset
Data
(P+32)h = 13Ch
03h
(P+33)h = 13Dh
0Ah
(P+34)h = 13Eh
00h
(P+35)h = 13Fh
10h
(P+36)h = 140h
00h
(P+37)h = 141h
10h
(P+38)h = 142h
00h
Description
Bank region 1 (Erase block type 1): Page mode and Synchronous mode
capabilities
Bit 0: page-mode reads permitted
Bit 1: synchronous reads permitted
Bit 2: synchronous writes permitted
Bits 3-7: reserved
Bank region 1 (Erase block type 1) programming region information
Bit 0-7: aligned size of programming region in bytes
Bit 8-14: reserved
Bit 15: Legacy Flash operation (ignore bit 0-7)
Bit 16-23: Control mode valid size in bytes
Bit 24-31: reserved
Bit 32-39: Control mode invalid size in bytes
Bit 40-46: reserved
Bit 47: Legacy Flash operation (ignore bit 16-23 and 32-39)
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There is one bank region, see tables 36, 37, 38, 39, 40 and 41 in Appendix A.
3. Applies to M58PR256LE.
4. Applies to M58PR512LE.
5. Applies to M58PR001LE.
Table 51.
Extended Flash array bank and erase block region information
Offset (1)
Data
(P+39)h = 143h
01h
Description
Number of bank regions within the device(2)
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There is one EFA bank region.
99/119
Common Flash interface
Table 52.
Offset
M58PR256LE, M58PR512LE, M58PR001LE
Extended Flash array bank and erase block region 1 information
(1)
Data
Description
(P+3A)h = 144h
16h
(P+3B)h = 145h
00h
(P+3C)h = 146h
01h
(P+3D)h = 147h
00h
(P+3E)h = 148h
11h
Number of program or erase operations allowed in bank region 1:
Bits 0-3: number of simultaneous program operations
Bits 4-7: number of simultaneous erase operations
00h
Number of program or erase operations allowed in other banks while a
bank in this region is being erased
Bits 0-3: number of simultaneous program operations
Bits 4-7: number of simultaneous erase operations
00h
Number of program or erase operations allowed in other banks while a
bank in this region is being erased
Bits 0-3: number of simultaneous program operations
Bits 4-7: number of simultaneous erase operations
(P+41)h = 14Bh
01h
Types of erase block regions in bank region 1
n = number of erase block regions with contiguous same-size erase
blocks.
Symmetrically blocked banks have one blocking region(2).
(P+42)h = 14Ch
03h
(P+43)h = 14Dh
00h
(P+44)h = 14Eh
20h
(P+45)h = 14Fh
00h
(P+46)h = 150h
64h
(P+47)h = 151h
00h
Data size of this bank region information section (addressable locations
including this one)
Number of identical banks within bank region 1
(P+3F)h = 149h
(P+40)h = 14Ah
(P+48)h = 152h
(P+49)h = 153h
100/119
Bank region 1 Erase block type 1 information
Bits 0-15: n+1 = number of identical-sized erase blocks in each bank
Bits 16-31: n×256 = number of bytes in erase block region
Bank region 1 (Erase block type 1)
Minimum block erase cycles × 1000
01h
Bank region 1 (Erase block type 1): bits per cell, internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for internal ECC used
BIts 5-7: reserved
03h
Bank region 1 (Erase block type 1): page mode and synchronous mode
capabilities
Bit 0: page-mode reads permitted
Bit 1: synchronous reads permitted
Bit 2: synchronous writes permitted
Bits 3-7: reserved
M58PR256LE, M58PR512LE, M58PR001LE
Table 52.
Common Flash interface
Extended Flash array bank and erase block region 1 information
Offset(1)
Data
(P+4A)h = 154h
00h
(P+4B)h = 155h
80h
(P+4C)h = 156h
00h
(P+4D)h = 157h
00h
(P+4E)h = 158h
00h
(P+4F)h = 159h
80h
Description
Bank region 1 (Erase block type 1) programming region information
Bit 0-7: aligned size of programming region in bytes
Bit 8-14: reserved
Bit 15: legacy Flash operation (ignore bit 0-7)
Bit 16-23: control mode valid size in bytes
Bit 24-31: reserved
Bit 32-39: control mode invalid size in bytes
Bit 40-46: reserved
Bit 47: legacy Flash operation (ignore bit 16-23 and 32-39)
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There is one EFA bank region.
101/119
Flowcharts and pseudocodes
Appendix C
M58PR256LE, M58PR512LE, M58PR001LE
Flowcharts and pseudocodes
Figure 20. Program and EFA block program flowchart and pseudocode
program_command (addressToProgram, dataToProgram)
/* EFA_program_command (addressToProgram, dataToProgram) */
{
Start
writeToFlash (addressToProgram, 0x41);
/*writeToFlash (addressToProgram, 0x44);*/
/* 41h is the command for program array, while 44h
is the command for program EFA block */
/*see note (1)*/
Write 41h (Main Array)
or 44h (EFA) (1)
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
status_register=readFlash (addressToProgram);
/* see note (3)*/
/* E or G must be toggled*/
Read Status
Register (3)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (2, 3)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
NO
Program
Error (2, 3)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
NO
Program to Protected
Block Error (2, 3)
YES
SR4 = 0
YES
SR1 = 0
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI10515
1. Any address within the 'A' segment halves (A3=0) in a 1 Kbyte program region configured in control program mode.
If a Program command is issued to a program region configured in the Object Program mode, SR4 and SR8 are set.
2. Status check of SR1 (protected block), SR3 (VPP invalid) and SR4 (program error) can be made after each program
operation or after a sequence.
3. If an error is found, the Status Register must be cleared before further Program/Erase controller operations.
102/119
M58PR256LE, M58PR512LE, M58PR001LE
Flowcharts and pseudocodes
Figure 21. Buffer program flowchart and pseudocode
Start
Read Status
Register 70h command,
at Bank Address
SR7 = 1
NO
Buffer_Program_command (Start_Address, n, buffer_Program[] )
/*The start address must be aligned to a 1KB boundary
buffer_Program [] is an array structure used to store the address and
data to be programmed to the Flash memory (the address must be within
the segment Start Address and Start Address+n) */
{
status_register=readFlash (Bank_Address);
} while (status_register.SR7==0);
YES
Buffer Program E9h
command, Block Address
writeToFlash (Start_Address, n);
Write n(1),
Start Address
Write Buffer Data,
Start Address
writeToFlash (buffer_Program[0].address, buffer_Program[0].data);
/*buffer_Program[0].address is the start address*/
X=0
X=n
do {writeToFlash (Block_Address, 0xE9) ;
x = 0;
YES
while (x<n)
NO
Write Next Buffer Data,
Next Program Address(2)
{ writeToFlash (buffer_Program[x+1].address, buffer_Program[x+1].data);
x++;
X=X+1
}
Program
Buffer to Flash
Confirm D0h
writeToFlash (Start_Address, 0xD0);
Read Status
Register
SR7 = 1
do {status_register=readFlash (Start_Address);
NO
} while (status_register.SR7==0);
YES
Full Status
Register Check(3)
full_status_register_check();
}
End
AI10516b
1. n + 1 is the number of data being programmed. The maximum buffer count is 1FF (512 words).
2. Next Program data is an element belonging to buffer_Program[].data; Next Program address is an element belonging to
buffer_Program[].address. In a program region configured in Control Program mode buffer_Program[].data = FFFFh if A3 =
1.
3. Routine for error check by reading SR3, SR4 and SR1.
103/119
Flowcharts and pseudocodes
M58PR256LE, M58PR512LE, M58PR001LE
Figure 22. Program suspend and resume flowchart and pseudocode
Start
program_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
Write B0h
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
program has already completed */
Write 70h
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR2 = 1
NO
Program Complete
if (status_register.SR2==0) /*program completed */
{ writeToFlash (bank_address, 0xFF) ;
read_data ( ) ;
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
YES
Read Data
}
else
Write FFh
{ writeToFlash (bank_address, 0xFF) ;
Read data from
another address
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
Write D0h
writeToFlash (bank_address, 0x70) ;
/*read status register to check if program has completed */
Write 70h(1)
}
Program Continues with
Bank in Read Status
Register Mode
}
AI10117b
1. The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command.
104/119
M58PR256LE, M58PR512LE, M58PR001LE
Flowcharts and pseudocodes
Figure 23. Block erase and EFA block erase flowchart and pseudocode
erase_command ( blockToErase )
/* EFA_erase_command (blockToErase) { */
writeToFlash (blockToErase, 0x20) ;
/* writeToFlash (blockToErase, 0x24) */
/* 20h is the command for Block Erase while 24h is the
command for Erase EFA Block*/
/*see note (1) */
Start
Write 20h (Main Array)
or 24h (EFA) (1)
writeToFlash (blockToErase, 0xD0) ;
/* only A12-Amax are significannt */
/* Memory enters read status state after
the Erase Command */
Write Block
Address & D0h
do {
status_register=readFlash (blockToErase) ;
/* see note (1) */
/* E or G must be toggled*/
Read Status
Register (1)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (2)
YES
Command
Sequence Error (2)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
YES
SR4, SR5 = 1
if ( (status_register.SR4==1) && (status_register.SR5==1) )
/* command sequence error */
error_handler ( ) ;
NO
SR5 = 0
NO
Erase Error (2)
if ( (status_register.SR5==1) )
/* erase error */
error_handler ( ) ;
YES
SR1 = 0
NO
Erase to Protected
Block Error (2)
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI12858
1. Any address within the bank can equally be used.
2. If an error is found, the Status Register must be cleared before further program/erase operations.
105/119
Flowcharts and pseudocodes
M58PR256LE, M58PR512LE, M58PR001LE
Figure 24. Erase suspend and resume flowchart and pseudocode
Start
erase_suspend_command ( ) {
writeToFlash (bank_address, 0xB0) ;
Write B0h
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
erase has already completed */
Write 70h
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR6 = 1
NO
Erase Complete
if (status_register.SR6==0) /*erase completed */
{ writeToFlash (bank_address, 0xFF) ;
Write FFh
read_data ( ) ;
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Read Data
YES
Write FFh
}
else
{ writeToFlash (bank_address, 0xFF) ;
read_program_data ( );
Read data from another block
or
Program/Set Configuration Register
or
Block Lock/Unlock/Lock-Down
/*read or program data from another block*/
writeToFlash (bank_address, 0xD0) ;
/*write 0xD0 to resume erase*/
Write D0h
writeToFlash (bank_address, 0x70) ;
/*read status register to check if erase has completed */
Write 70h(1)
}
}
Erase continues with
bank in Read Status
Register mode
AI10116c
1. The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command.
106/119
M58PR256LE, M58PR512LE, M58PR001LE
Flowcharts and pseudocodes
Figure 25. Main array and EFA locking operations flowchart and pseudocode
Start
Write 60h (Main Array)
or 64h (EFA) (1)
locking_operation_command (address, lock_operation) {
/* EFA_locking_operation_command (address, lock_operation) { */
writeToFlash (address, 0x60) ; /*configuration setup*/
/* writeToFlash (address, 0x64) */
/* 60h is the command for Locking Operations on the array while 64h
is the command for Locking Operations on the EFA */
/* see note (1) */
if (lock_operation==LOCK) /*to protect the block*/
writeToFlash (address, 0x01) ;
else if (lock_operation==UNLOCK) /*to unprotect the block*/
writeToFlash (address, 0xD0) ;
else if (lock_operation==LOCK-DOWN) /*to lock the block*/
writeToFlash (address, 0x2F) ;
Write
01h, D0h or 2Fh
writeToFlash (address, 0x90) ;
/*see note (1) */
Write 90h (1)
Read Block
Lock States
Locking
change
confirmed?
if (readFlash (address) ! = locking_state_expected)
error_handler () ;
/*Check the locking state (see Read Block Signature table )*/
NO
YES
writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/
/*see note (1) */
Write FFh (1)
}
End
AI10518
1. Any address within the bank can equally be used.
107/119
Flowcharts and pseudocodes
M58PR256LE, M58PR512LE, M58PR001LE
Figure 26. Blank check flowchart and pseudocode
Start
blank_check_command (blockToCheck) {
writeToFlash (blockToCheck, 0xBC);
Write Block
Address & BCh
writeToFlash (blockToCheck, 0xD0);
/* Memory enters read status state after
the Blank Check Command */
Write Block
Address & D0h
do {
status_register = readFlash (blockToCheck);
/* see note (1) */
/* E or G must be toggled */
Read
Status Register (1)
} while (status_register.SR7==0);
SR7 = 1
NO
if (status_register.SR3==1)
/* VPP invalid error */
error_handler () ;
YES
SR3 = 0
SR4 = 1
SR5 = 1
SR5 = 0
SR1 = 0
NO
YES
NO
NO
VPP Invalid
Error (2)
if (status_register.SR4==1) && (status_register.SR5==1)
/* command sequence error */
error_handler () ;
Command Sequence
Error (2)
if (status_register.SR5==1)
/* erase error */
error_handler () ;
if (status_register.SR1==1)
/* protected block error */
error_handler () ;
Erase Error (2)
Protected Block
Error (2)
}
End
ai10520
1. Any address within the bank can equally be used.
2. If an error is found, the Status Register must be cleared before further program/erase operations.
108/119
M58PR256LE, M58PR512LE, M58PR001LE
Flowcharts and pseudocodes
Figure 27. Protection Register program flowchart and pseudocode
Start
protection_register_program_command (addressToProgram, dataToProgram) {:
writeToFlash (addressToProgram, 0xC0) ;
/*see note (1) */
Write C0h (1)
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
status_register=readFlash (addressToProgram) ;
/* see note (1) */
/* E or G must be toggled*/
Read Status
Register (1)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (2, 3)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
NO
Program
Error (2, 3)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
NO
Program to Protected
Block Error (2, 3)
YES
SR4 = 0
YES
SR1 = 0
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06177c
1. Status check of SR1 (protected block), SR3 (VPP invalid) and SR4 (program error) can be made after each program
operation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase controller operations.
109/119
Flowcharts and pseudocodes
M58PR256LE, M58PR512LE, M58PR001LE
Figure 28. Buffer enhanced factory program flowchart and pseudocode
Start
NO
writeToFlash (start_address, 0x80) ;
Write D0h to
Address WA1
writeToFlash (start_address, 0xD0) ;
Read Status
Register
do {
do {
status_register = readFlash (start_address);
SR7 = 0
Initialize count
X=0
SR4 = 1
Read Status Register
SR3 and SR1for errors
Write PDX (1)
Address WA1
Exit
Increment Count
X=X+1
NO
if (status_register.SR4==1) { /*error*/
if (status_register.SR3==1) error_handler ( ) ;/*VPP error */
if (status_register.SR1==1) error_handler ( ) ;/* Locked Block */
}
PROGRAM AND
while (status_register.SR7==1)
VERIFY PHASE
x=0; /* initialize count */
do {
writeToFlash (start_address, DataFlow[x]);
x++;
X = 512
}while (x<512)
do {
YES
Read Status
Register
NO
Buffer_Enhanced_Factory_Program_Command
(start_address, DataFlow[]) {
Write 80h to
Address WA1
YES
NO
SETUP PHASE
status_register = readFlash (start_address);
SR0 = 0
}while (status_register.SR0==1)
YES
NO
Last data?
} while (not last data)
YES
Write FFFFh to
Address = NOT BA1 (2)
Read Status
Register
NO
SR7 = 1
writeToFlash (another_block_address, FFFFh)
EXIT PHASE
do {
status_register = readFlash (start_address)
}while (status_register.SR7==0)
YES
Full Status Register
Check
End
full_status_register_check();
}
AI10519b
1. When programming a program region configured in Control Program mode, ’B’ half segment addresses (A3 = 1) should not
contain ’0’ values.
2. BA1 = block containing start address WA1.
110/119
M58PR256LE, M58PR512LE, M58PR001LE
Appendix D
Table 53.
Command interface state tables
Command interface state tables
Command interface states - modify table, next state 1
command input to chip and resulting chip next state (7)
Current chip state
Read
Array
FFh
ready
EFA
Read Program
Program
EFA
Setup
Setup
94h
ready
BP
Block
Erase
Setup
EFA
Block
Erase
Setup
BEFP
Confirm,
Resume
Program/
Erase
Suspend
Read
Status
D0h
B0h
70h
41h
44h
E9h(8,9,10)
20h
24h
80h
pgrm
setup
EFA block
pgrm
setup
BP setup
erase
setup
EFA block
erase
setup
BEFP
setup
Lock/CR/ECR Setup
ready
(unlock)
ready (sequence error)
Lock EFA Block Setup
setup
OTP
ready
(sequence error)
OTP busy
busy
OTP busy
IS in OTP busy
OTP busy
IS in OTP busy
IS in OTP busy
OTP busy
setup
WP busy
busy
program busy
IS in program busy
pgrm busy
IS in program busy
WP or
IS in program
EFA
busy
Block WP
suspend
PS
IS in PS
program
busy
WP
WP busy
suspend
pgrm
suspend
IS in PS
program
busy
WP suspend
WP suspend
(1), (2)
BP load 1
OTP busy
WP busy
IS in PS
setup
ready
BP load 1 (give word count load (N-1))
(2)
if N=0 go to BP confirm else go to BP load 2 (data load) (4)
BP load 2 (2)
BP confirm when count =0 else BP load 2
BP confirm
BP busy (3)
ready (sequence error)
BP
BP busy
BP busy
IS in BP busy
BP busy
BP suspend
IS in BP suspend
BP suspend
IS in BP busy
IS in BP busy
BP suspend
IS in ES
BP busy
IS in BP suspend
BP busy
BP suspend
erase busy
ready (sequence
error)
BP suspend
setup
suspend
BP
suspend
BP busy
IS in BP
suspend
busy
Erase or
EFA
IS in erase busy
Block
Erase
BP busy
ready (sequence
error)
ready (sequence error)
erase busy
IS in erase busy
erase busy
Is in erase busy
erase busy
erase
busy
ES
erase busy
ES
WP
EFA block BP setup in
setup in
WP in ES
ES
ES
IS in ES
erase busy
ES
ES
111/119
Command interface state tables
Table 53.
M58PR256LE, M58PR512LE, M58PR001LE
Command interface states - modify table, next state 1 (continued)
command input to chip and resulting chip next state (7)
Current chip state
Read
Array
FFh
EFA
Read Program
Program
EFA
Setup
Setup
94h
41h
44h
BP
Block
Erase
Setup
EFA
Block
Erase
Setup
BEFP
Confirm,
Resume
Program/
Erase
Suspend
Read
Status
E9h(8,9,10)
20h
24h
80h
D0h
B0h
70h
setup
WB busy in ES
busy
WP busy in ES
IS in program busy WP busy in
in ES
ES
WP in ES
or EFA
IS in program
Block WP
busy in ES
in ES
WP suspend
in ES
IS in PS in ES
IS in PS in ES
setup
BP load 2 (2)
BP confirm in ES when count = 0 else BP load 2 in ES
BP confirm
ES (sequence error)
BP suspend
BP busy in ES
IS in BP busy in ES
BP busy in
ES
IS in BP busy in ES
BP suspend in IS in BP suspend in BP suspend
ES
ES suspend
in ES
BP
BP busy in
suspend
ES
in ES
BP busy
in ES
IS in BP suspend in ES
BP busy in
ES
BP suspend in ES
BP suspend in ES
Lock/CR/ECR/Lock EFA
block setup in ES
ES (unlock
ES (sequence error)
block)
ES (sequence error)
setup
blank check
busy
ready (sequence error)
BC busy
IS in BC busy
BC busy
IS in blank
check busy
setup
BP busy in
ES (sequence error)
ES (3)
BP busy in ES
IS in BP
suspend in ES
blank check
busy
WP suspend is ES
if N=0 go to BP confirm in ES else go to BP load 2 in ES (data load) (4)
IS in BP busy in
ES
BEFP
mode
WP busy in
ES
BP load 1 in ES (give word count load (N-1))
(2)
BP in ES BP busy
Blank
Check
IS in PS in ES
WP suspend in ES
(1) (2)
BP load 1
WP
WP busy in
WP busy
suspend
ES
in ES
is ES
WP busy in ES
WP suspend in
ES
suspend
IS in program busy in ES
IS in BC busy
ready (sequence
error)
BC busy
BC busy
ready (sequence error)
BEFP
loading
data
ready (sequence
error)
BEFP Busy (5) (6) BEFP program and verify busy (in block address given matches on BEFP setup command). Commands treated as data
112/119
M58PR256LE, M58PR512LE, M58PR001LE
Table 54.
Command interface state tables
Command interface states - modify table, next state 2
command input to chip and resulting chip next state
Current chip state
Clear SR Read ID
50h
ready
90h 98h
ready
Lock, CR,
Lock EFA
ECR
Setup
Setup
Blank
Check
Setup
OTP
Setup
Block
Lock
Confirm
Lockdown
Confirm
Write
CR/ECR
Confirm
Illegal
Cmd or
BEFP
Data
01h
2Fh
03h 04h
others
60h
64h
BCh
C0h
lock/CR/E
CR setup
lock EFA
block
setup
blank
check
setup
OTP
setup
ready
ready
(lock)
Lock/CR/ECR Setup
ready (sequence error)
ready
(EFA lock)
Lock EFA Block Setup
setup
OTP
busy
IS in OTP busy
ready
(sequence
ready
error)
(sequence
error)
N/A
OTP busy
IS ready
WP busy
WP busy
WP busy
IS in program busy
IS
IS in
program
busy
suspend
ready (set
CR)
OTP busy
setup
WP or
EFA
Block
WP
ready
OTP busy
OTP busy
IS in OTP
busy
busy
ready
(lock
down)
WSM
Operation
Complete
WP busy
ready
WP busy
WP
suspend
WP
(error bits suspend
cleared)
IS in PS
N/A
IS ready
WP suspend
N/A
IS in PS
WP suspend
setup
BP load 1 (give word count load (N-1))
BP load 1
if N=0 go to BP confirm else go to BP load 2 (data load)
BP load 2
BP confirm
when
count = 0
else BP
load 2
BP confirm when count =0 else BP load 2
BP confirm
N/A
ready (sequence error)
BP
BP busy
BP busy
IS in BP busy
IS
IS in BP busy
BP suspend
BP
suspend
BP
(error bits suspend
cleared)
IS in BP suspend
IS in ES
BP suspend
BP suspend
setup
IS in erase
Erase or
busy
EFA
Block
Erase
suspend
ready
IS ready
N/A
IS in BP
suspend
busy
BP busy
BP busy
ready (sequence error)
erase busy
IS in erase busy
IS
N/A
erase busy
IS nonready
erase busy
ES (error
bits
cleared)
ES
lock EFA
Lock/CR/E
block
CR setup
setup in
in ES
ES
IS
ready
ES
N/A
ES
113/119
Command interface state tables
Table 54.
M58PR256LE, M58PR512LE, M58PR001LE
Command interface states - modify table, next state 2 (continued)
command input to chip and resulting chip next state
Current chip state
Clear SR Read ID
50h
90h 98h
Lock, CR,
Lock EFA
ECR
Setup
Setup
60h
64h
Blank
Check
Setup
OTP
Setup
Block
Lock
Confirm
Lockdown
Confirm
Write
CR/ECR
Confirm
Illegal
Cmd or
BEFP
Data
BCh
C0h
01h
2Fh
03h 04h
others
setup
busy
WP in
ES or
EFA
Block
WP in
ES
WP busy in ES
WP busy in ES
IS in
program
busy in ES
suspend
IS in PS in
ES
setup
WP busy in ES
WP busy in
ES
IS in WP suspend in ES
WP suspend in ES
N/A
WP
suspend in
ES
BP confirm
when
count = 0
else BP
load 2
BP confirm in ES when count = 0 else BP load 2 in ES
BP busy in ES
IS in BP busy in ES
IS
BP busy in ES
IS in BP
suspend in
ES
IS in ES
IS in BP suspend in ES
BP suspend in ES
N/A
BP
suspend in
ES
BP suspend in ES
Lock/CR/ECR setup in
ES
ES
ES (lock
block)
ES (sequence error)
Lock EFA block setup
in ES
setup
setup
BEFP
Mode
114/119
BEFP Busy
ES
BP busy in ES
BP
suspend in
BP
BP suspend ES (error suspend
bits
is ES
cleared)
IS in blank
check busy
N/A
ready (sequence error) in ES
IS in BP busy
in ES
blank check
busy
IS in ES
BP load 1 in ES (give word count load (N-1))
BP confirm
Blank
Check
ES
if N=0 go to BP confirm in ES else go to BP load 2 in ES (data load)
BP load 2
BP busy
IS
WP suspend in ES
BP load 1
BP in ES
N/A
WP busy in ES
WP
suspend is
WP
ES (error suspend
bits
in ES
cleared)
WSM
Operation
Complete
ES (lock
down)
ES
(sequence
error)
IS in BC busy
IS
N/A
ready
(error)
ready (sequence error)
BC busy
ES (lock
error)
BC busy
BC busy
ready
BC busy
ready (sequence error)
BEFP program and verify busy (in block address given matches on BEFP setup command).
Commands treated as data
IS ready
N/A
BEFP busy
ready
M58PR256LE, M58PR512LE, M58PR001LE
Table 55.
Command interface state tables
Command interface states - modify table, next output 1
command input to chip and resulting chip next state
Current chip state
Read
Array
Read
EFA
Block
WP
EFA WP
BP
Erase
Setup
EFA
Block
Erase
Setup
BEFP
Setup
Confirm,
Resume
Program/
Erase
Suspend
Read
Status
FFh
94h
41h
44h
E9h
20h
24h
80h
D0h
B0h
70h
BEFP Setup,
BEFP program and
verify busy,
Erase Setup,
Erase EFA setup
OTP Setup,
BP Confirm,
WP setup,
WP setup in ES,
BP confirm in ES,
blank check setup
status read
EFA block WP setup,
EFA block program
setup in ES
EFA block status read
Lock/CR/ECR setup,
Lock/CR/ECR setup in
ES
status read
EFA block lock setup,
EFA block lock setup in
ES
EFA block status read
OTP busy
ready, ES, BP suspend,
WP busy, erase busy, BP
busy, BP busy in ES,
WP suspend, WP busy in
ES,
PS in ES,
BP suspend in ES, Blank
Check busy
BP setup, BP load 1,
BP load 2, IS
read
array
read
EFA
blocks
status
read
EFA block
status
read
output state
does not
change
status
read
EFA
block
status
read
status
read
output state does not
change
status
read
output state does not change
115/119
Command interface state tables
Table 56.
M58PR256LE, M58PR512LE, M58PR001LE
Command interface states - modify table, next output 2
command input to chip and resulting chip next state
Current Chip State
Clear SR
Read ID
Lock,
CR, ECR
Setup
Lock
EFA
Setup
Blank
Check
OTP
Setup
Lock
Confirm
Lockdown
Confirm
Write
CR/
ECR
Confirm
Illegal
cmd or
BEFP
Data
50h
90h 98h
60h
64h
BCh
C0h
01h
2Fh
03h 04h
others
BEFP Setup,
BEFP program and verify
busy,
Erase Setup,
Erase EFA setup
OTP Setup,
BP Confirm,
WP setup,
WP setup in ES,
BP confirm in ES,
blank check setup
status read
EFA block WP setup,
EFA block program setup
in ES
EFA block status read
Lock/CR/ECR setup,
Lock/CR/ECR setup in ES
status read
array
read
status
read
EFA block lock setup, EFA
block lock setup in ES
EFA block status read
array
read
EFA
block
status
read
OTP busy
ready, ES, BP suspend, WP
busy, erase busy,
BP busy, blank check busy,
BP busy in ES,
WP suspend, WP busy in
ES, PS in ES,
BP suspend in ES
BP setup,
BP load 1,
BP load 2,
IS
Note:
116/119
output
state
does not
change
ID read
status
read
EFA
block
status
read
status read
output state does not change
output
state
does not
change
output state does not change
1
WP = Word Program, BP = Buffer program, cmd = command, SR = Status Register, pgrm =
program, IS = Illegal state, PS = Program suspend, ES = Erase suspend, CI = Command
Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C.
= Program/Erase Controller, WA0 = Address in a block different from first BEFP address,
ECR = Enhanced Configuration Register.
2
The output state shows the type of data that appears at the outputs if the bank address is
the same as the command address. A bank can be placed in Read Array, Read Status
Register, Read Electronic Signature or Read CFI mode, depending on the command issued.
Each bank remains in its last output state until a new command is issued to that bank. The
next state does not depend on the bank output state.
3
At Power-up, all banks are in Read Array mode. Issuing a Read Array command to a busy
bank results in undetermined data output.
4
The Clear Status Register command clears the Status Register error bits except when the
P/EC is busy or suspended.
5
BEFP is allowed only when Status Register bit SR0 is reset to ‘0’. BEFP is busy if the block
address is the first BEFP address. Any other commands are treated as data.
M58PR256LE, M58PR512LE, M58PR001LE
Command interface state tables
6
BEFP aborts when the block address is different from the first block address and data are
FFFFh.
7
BEFP Exit when block address is different from first block address and data are FFFFh.
8
During BP setup, while entering the number of words to be programmed and filling the
buffer, the read status of the partition does not change.
9
The BP confirm command changes the read status of the partition to Status Read.
10
Illegal commands are commands not defined in the command set.
117/119
Revision history
17
M58PR256LE, M58PR512LE, M58PR001LE
Revision history
Table 57.
Document revision history
Date
Revision
28-Apr-2006
0.1
Initial release.
0.2
1Gb density (M58PR001LE part number) added.
VPP range for application environment changed in Table 25:
Operating and AC measurement conditions.
IPP1 unit changed in Table 27: DC characteristics - currents.
15-May-2006
14-Nov-2006
06-Sep-2007
118/119
Changes
1
Document status promoted from Target Specification to Preliminary
Data.
Address lines modified in Figure 11: Asynchronous page read AC
waveforms. VPP max value modified in Table 24: Absolute maximum
ratings. Small text changes.
2
Modified Section 4.18: Set Enhanced Configuration Register
command and Section 4.22: Suspend EFA Block command.
Updated Table 23: Program/erase times and endurance cycles,
Table 24: Absolute maximum ratings, Table 27: DC characteristics currents, Table 29: Asynchronous read AC characteristics, and
Table 31: Write AC characteristics, write enable controlled.
Added tLLTV timing in Table 30: Synchronous read AC characteristics
and Figure 13: Single synchronous read AC waveforms.
Modified Figure 24: Erase suspend and resume flowchart and
pseudocode.
Document status promoted from Preliminary Data to Datasheet.
M58PR256LE, M58PR512LE, M58PR001LE
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