STMICROELECTRONICS M59P064110M1T

M59PW064
64 Mbit (4Mb x16, Uniform Block)
3V Supply LightFlash™ Memory
FEATURES SUMMARY
■
■
■
■
■
■
■
■
■
■
MASK-ROM PIN-OUT COMPATIBLE
SUPPLY VOLTAGE
– VCC= 2.7 to 3.6V for Read
– VPP = 11.4 to 12.6V for Program
ACCESS TIME
– 90ns at VCC = 3.0 to 3.6V
– 100, 110ns at VCC = 2.7 to 3.6V
PROGRAMMING TIME
– 9µs per Word typical
– Multiple Word Programming Option
(8s typical Chip Program)
SUITABLE FOR ON-BOARD
PROGRAMMING
ERASE TIME
– 41s typical Chip Erase
UNIFORM BLOCKS
– 32 blocks of 2 Mbits
PROGRAM/ERASE CONTROLLER
– Embedded Word Program algorithms
10,000 PROGRAM/ERASE CYCLES per
BLOCK
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code : 88AAh
March 2005
Figure 1. Packages
SO44 (M)
TSOP48 (N)
12 x 20mm
1/24
M59PW064
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2.
Table 1.
Figure 3.
Figure 4.
Table 2.
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Setup Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Program Phase.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Verify Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Exit Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 11
2/24
M59PW064
Figure 5. Multiple Word Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
VPP Status Bit (DQ4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Multiple Word Program Bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Status Register Bit DQ1 is reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 10. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10.Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 12. Chip Enable Controlled, Write AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12.SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Outline . . . . . . . . 20
Table 13. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Mechanical Data . 20
Figure 13.TSOP48 - 48 lead Plastic Thin Small Outline, 12x20mm, Package Outline . . . . . . . . . . 21
Table 14. TSOP48 - 48 lead Plastic Thin Small Outline, 12x20mm, Package Mechanical Data . . 21
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3/24
M59PW064
SUMMARY DESCRIPTION
The M59PW064 is a 64Mbit (4Mbx16), MaskROM pin-out compatible, non-volatile LightFlash
memory, that can be read, erased and
reprogrammed. Read operations can be
performed using a single low voltage (2.7 to 3.6V)
supply. Program and Erase operations require an
additional VPP (11.4 to 12.6V) power supply. On
power-up the memory defaults to its Read mode
where it can be read in the same way as a ROM or
EPROM.
The memory is divided into 32 uniform blocks that
can be erased independently so it is possible to
preserve valid data while old data is erased (see
Table 2., Block Addresses). Program and Erase
commands are written to the Command Interface
of the memory. An on-chip Program/Erase Controller (P/E.C.) simplifies the process of programming or erasing the memory by taking care of all of
the special operations that are required to update
the memory contents.
The M59PW064 features an innovative command,
Multiple Word Program, that is used to program
large streams of data. It greatly reduces the total
programming time when a large number of Words
are written to the memory at any one time. Using
this command the entire memory can be programmed in 8s, compared to 36s using the standard Word Program.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
Chip Enable and Output Enable signals control the
bus operation of the memory. They allow simple
connection to most microprocessors, often without
additional logic.
The memory is offered in SO44 and TSOP48 (12
x 20mm) packages. The memory is supplied with
all the bits set to ’1’).
Figure 2. Logic Diagram
Table 1. Signal Names
VCC
VPP
22
16
A0-A21
E
DQ0-DQ15
M59PW064
G
VSS
AI07230
4/24
A0-A21
Address Inputs
DQ0-DQ15
Data Inputs/Outputs
E
Chip Enable
G
Output Enable
VCC
Supply Voltage read
VPP
Supply Voltage program erase
VSS
Ground
NC
Not Connected Internally
M59PW064
Figure 3. SO Connections
A21
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11 M59PW064 34
12
33
13
32
14
31
15
30
16
29
28
17
27
18
26
19
25
20
21
24
22
23
Figure 4. TSOP Connections
VPP
A20
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
VPP
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
1
48
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
A21
A20
12
13
M59PW064
37
36
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
AI07231
E
24
25
VSS
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
VCC
NC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
VSS
AI07268
5/24
M59PW064
Table 2. Block Addresses
Block Number
Address Range
32
3E0000h-3FFFFFh
31
3C0000h-3DFFFFh
30
3A0000h-3BFFFFh
29
380000h-39FFFFh
28
360000h-37FFFFh
27
340000h-35FFFFh
26
320000h-33FFFFh
25
300000h-31FFFFh
24
2E0000h-2FFFFFh
23
2C0000h-2DFFFFh
22
2A0000h-2BFFFFh
21
280000h-29FFFFh
20
260000h-27FFFFh
19
240000h-25FFFFh
18
220000h-23FFFFh
17
200000h-21FFFFh
6/24
Block Number
Address Range
16
1E0000h-1FFFFFh
15
1C0000h-1DFFFFh
14
1A0000h-1BFFFFh
13
180000h-19FFFFh
12
160000h-17FFFFh
11
140000h-15FFFFh
10
120000h-13FFFFh
9
100000h-11FFFFh
8
0E0000h-0FFFFFh
7
0C0000h-0DFFFFh
6
0A0000h-0BFFFFh
5
080000h-09FFFFh
4
060000h-07FFFFh
3
040000h-05FFFFh
2
020000h-03FFFFh
1
000000h-01FFFFh
M59PW064
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table
1., Signal Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A21). The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the Program Controller.
Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the command
sent to the Command Interface of the Program
Controller. When reading the Status Register they
report the status of the ongoing algorithm.
Data Inputs/Outputs (DQ8-DQ15). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read operations to be
performed. It also controls the Bus Write operations, when VPP is in the VHH range.
Output Enable (G). The Output Enable, G, controls the Bus Read operations of the memory. It
also allows Bus Write operations, when VPP is in
the VHH range.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for Read operations.
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program operations, ICC3.
V PP Program Supply Voltage. VPP is both a
power supply and Write Protect pin. The two functions are selected by the voltage range applied to
the pin.
When the VPP is in the VHH range (see Table
10., DC Characteristics, for the relevant values)
the Program/Erase operation is enabled. During
such operations the VPP must be stable in the VHH
range.
If the VPP is kept under the VHH range, particularly
in the voltage range 0V to 3.6V, any Program/
Erase operation is disabled or stopped.
Note that VPP must not be left floating or unconnected as the device may become unreliable.
VSS Ground. The VSS Ground is the reference for
all voltage measurements.
7/24
M59PW064
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Output Disable, Standby, Automatic Standby and
Electronic Signature. See Table 3., Bus Operations, for a summary. Typically glitches of less
than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs and applying a Low signal, VIL, to Chip Enable and Output Enable. The Data Inputs/Outputs
will output the value, see Figure 10., Read AC
Waveforms, and Table 11., Read AC Characteristics, for details of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. Bus Write is enabled only
when VPP is set to VHH. A valid Bus Write operation begins by setting the desired address on the
Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable. The Data Inputs/Outputs are latched by
the Command Interface on the rising edge of Chip
Enable. Output Enable must remain High, VIH,
during the whole Bus Write operation. See Figure
11., Write AC Waveforms, Chip Enable Controlled, and Table 12., Chip Enable Controlled,
Write AC Characteristics, for details of the timing
requirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
level see Table 10., DC Characteristics.
During program operation the memory will continue to use the Program Supply Current, ICC3, for
Program operation until the operation completes.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Table 3., Bus Operations, once the Auto
Select Command is executed. To exit Electronic
Signature mode, the Read/Reset command must
be issued.
Table 3. Bus Operations
Address Inputs
A0-A21
Data Inputs/Outputs
DQ15-DQ0
E
G
VPP
Bus Read
VIL
VIL
XX(3)
Cell Address
Bus Write
VIL
VIH
VHH
Command Address
X
VIH
X
X
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Read Manufacturer
Code
VIL
VIL
VHH
A0 = VIL, A1 = VIL,
Others VIL or VIH
0020h
Read Device Code
VIL
VIL
VHH
A0 = VIH, A1 = VIL,
Others VIL or VIH
88AAh
Operation
Output Disable
Data Output
Note: 1. X = VIL or VIH.
2. XX = VIL, VIH or VHH
3. When reading Status Register during Program algorithm execution VPP must be kept at VHH.
8/24
Data Input
M59PW064
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus
Write operations will result in the memory returning to Read mode. The long command sequences
are imposed to maximize data security.
Refer to Tables 4 and 5, for a summary of the commands.
Read/Reset Command.
The Read/Reset command returns the memory to
its Read mode where it behaves like a ROM or
EPROM, unless otherwise stated. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
VPP must be set to VHH during the Read/Reset
command. If VPP is set to either VIL or VIH the command will be ignored. The command can be issued, between Bus Write cycles before the start of
a program operation, to return the device to read
mode. Once the program operation has started the
Read/Reset command is no longer accepted.
Auto Select Command.
The Auto Select command is used to read the
Manufacturer Code and the Device Code. VPP
must be set to VHH during the Auto Select command. If VPP is set to either VIL or VIH the command will be ignored. Three consecutive Bus
Write operations are required to issue the Auto Select command. Once the Auto Select command is
issued the memory remains in Auto Select mode
until a Read/Reset command is issued, all other
commands are ignored.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = VIL and A1 = VIL. The other address bits
may be set to either VIL or VIH.
The Device Code can be read using a Bus Read
operation with A0 = VIH and A1 = VIL. The other
address bits may be set to either VIL or VIH.
Word Program Command.
The Word Program command can be used to program a Word to the memory array. VPP must be
set to VHH during Word Program. If VPP is set to either VIL or VIH the command will be ignored, the
data will remain unchanged and the device will revert to Read/Reset mode. The command requires
four Bus Write operations, the final write operation
latches the address and data in the internal state
machine and starts the P/E.C.
During the program operation the memory will ignore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 6.. Bus Read operations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’.
Multiple Word Program Command
The Multiple Word Program command can be
used to program large streams of data. It greatly
reduces the total programming time when a large
number of Words are written in the memory at
once. VPP must be set to VHH during Multiple Word
Program. If VPP is set either VIL or VIH the command will be ignored, the data will remain unchanged and the device will revert to Read mode.
It has four phases: the Setup Phase to initiate the
command, the Program Phase to program the
data to the memory, the Verify Phase to check that
the data has been correctly programmed and reprogram if necessary and the Exit Phase.
Setup Phase. The Multiple Word Program command requires three Bus Write operations to initiate the command (refer to Table 4, Multiple Word
Program Command and Figure 8, Multiple Word
Program Flowchart).
The Status Register must be read in order to
check that the P/E.C. has started (see Table 7.
and Figure 6.).
Program Phase. The Program Phase requires
n+1 Bus Write operations, where n is the number
of Words, to execute the programming phase (refer to Table 5., Multiple Word Program Command,
and Figure 5., Multiple Word Program Flowchart).
Before any Bus Write operation of the Program
Phase, the Status Register must be read in order
to check that the P/E.C. is ready to accept the operation (see Table 7. and Figure 6.).
The Program Phase is executed in three different
sub-phases:
1. The first Bus Write operation of the Program
Phase (the 4th of the command) latches the
9/24
M59PW064
Start Address and the first Word to be
programmed.
2. Each subsequent Bus Write operation latches
the next Word to be programmed and
automatically increments the internal Address
Bus. It is not necessary to provide the address
of the location to be programmed but only a
Continue Address, CA (A17 to A21 equal to
the Start Address), that indicates to the PC
that the Program Phase has to continue. A0 to
A16 are ‘don’t care’.
3. Finally, after all Words have been
programmed, a Bus Write operation (the
(n+1)th) with a Final Address, FA (A17 or a
higher address pin different from the Start
Address), ends the Program Phase.
The memory is now set to enter the Verify Phase.
Verify Phase. The Verify Phase is similar to the
Program Phase in that all Words must be resent to
the memory for them to be checked against the
programmed data.
Before any Bus Write Operation of the Verify
Phase, the Status Register must be read in order
to check that the P/E.C. is ready for the next operation or if the reprogram of the location has failed
(see Table 7. and Figure 6.).
Three successive steps are required to execute
the Verify Phase of the command:
1. The first Bus Write operation of the Verify
Phase latches the Start Address and the Word
to be verified.
2. Each subsequent Bus Write operation latches
the next Word to be verified and automatically
increments the internal Address Bus. As in the
Program Phase, it is not necessary to provide
the address of the location to be programmed
but only a Continue Address, CA (A17 to A21
equal to the Start Address).
3. Finally, after all Words have been verified, a
Bus Write cycle with a Final Address, FA (A17
or a higher address pin different from the Start
Address) ends the Verify Phase.
Exit Phase. After the Verify Phase ends, the Status Register must be read to check if the command
has successfully completed or not (see Table 7.
and Figure 6.).
If the Verify Phase accomplishes successfully, the
memory returns to the Read mode and DQ6 stops
toggling.
On the contrary, if the P/E.C. fails to reprogram a
given location, the Verify Phase terminates, DQ6
continues toggling and error bit DQ5 is set in the
Status Register. If the error is due to a VPP failure
DQ4 is also set.
10/24
When the operation fails a Read/Reset command
must be issued to return the device to Read mode.
During the Multiple Word Program operation the
memory will ignore all commands. It is not possible
to issue any command to abort or pause the operation. Typical program times are given in Table 6..
Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status
Register for more details.
Note that the Multiple Word Program command
cannot change a bit set at ’0’ back to ’1’.
Block Erase Command.
The Block Erase command can be used to erase
a block. It sets all of the bits in the block to ’1’. All
previous data in the block is lost.
VPP must be set to VHH during Block Erase. If VPP
is set to either VIL or VIH the command will be ignored, the data will remain unchanged and the device will revert to Read/Reset mode.
Six Bus Write operations are required to select the
block . The Block Erase operation starts the P/E.C.
after the last Bus Write operation. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to
identify if the P/E.C. has started the Block Erase
operation.
During the Block Erase operation the memory will
ignore all commands. Typical block erase times
are given in Table 6.. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the
section on the Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
Chip Erase Command.
The Chip Erase command can be used to erase
the entire memory. It sets all of the bits in the memory to ’1’. All previous data in the memory is lost.
VPP must be set to VHH during Chip Erase. If VPP
is set to either VIL or VIH the command will be ignored, the data will remain unchanged and the device will revert to Read/Reset mode. Six Bus Write
operations are required to issue the Chip Erase
Command and start the P/E.C.
During the erase operation the memory will ignore
all commands. It is not possible to issue any command to abort the operation. Typical chip erase
times are given in Table 6.. All Bus Read operations during the Chip Erase operation will output
M59PW064
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.
Table 4. Standard Commands
Length
Command
Bus Write Operations
1st
2nd
Add
Data
1
X
F0
3
555
Auto Select
3
Word Program
3rd
4th
Add
Data
Add
Data
AA
2AA
55
X
F0
555
AA
2AA
55
555
90
4
555
AA
2AA
55
555
Block Erase
6
555
AA
2AA
55
Chip Erase
6
555
AA
2AA
55
5th
Add
Data
A0
PA
PD
555
80
555
555
80
555
6th
Add
Data
Add
Data
AA
2AA
55
BA
30
AA
2AA
55
555
10
Read/Reset
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The
Command Interface only uses A0-A10 and DQ0-DQ7 to verify the commands; A11-A21, DQ8-DQ15 are Don’t Care.
Phase
Length
Table 5. Multiple Word Program Command
Bus Write Operations
1st
2nd
3rd
4th
Add
Data
Add
Data
Add
Data
3
555
AA
2AA
55
555
20
Program
n+1
SA
PD1
CA
PD2
CA
Verify
n+1
SA
PD1
CA
PD2
CA
Set-Up
5th
nth
Final
Add
Data
Add
Data
Add
Data
Add
Data
PD3
CA
PD4
CA
PD5
CA
PAn
FA
X
PD3
CA
PD4
CA
PD5
CA
PAn
FA
X
Note: A Bus Read must be done between each Write cycle where the data is programmed or verified, to Read the Status Register and check
that the memory is ready to accept the next data. SA is the Start Address. CA is the Continue Address. FA is the Final Address. X Don’t
Care, n = number of Words to be programmed.
Table 6. Program, Erase Times and Program, Erase Endurance Cycles
Typ (1)
Typical after
10k W/E Cycles (1)
Max
Unit
Chip Erase
41
44
120
s
Block Erase (128 KWords)
1.5
6
s
Program (Word)
9
200
µs
Chip Program (Multiple Word)
8
144
s
Chip Program (Word by Word)
36
144
s
Parameter
Program/Erase Cycles (per Block)
Min
10,000
cycles
Note: 1. TA = 25°C, VPP = 12V.
11/24
M59PW064
Figure 5. Multiple Word Program Flowchart
Start
Setup
Phase
Write AAh
Address 555h
Read Status
Register
Write 55h
Address 2AAh
DQ0 = 0?
Write 20h
Address 555h
Verify
Phase
NO
Write Data1
Start Address
Read Status
Register
Read Status
Register
NO
NO
Setup time
exceeded?
NO
NO
DQ0 = 0?
YES
YES
EXIT (setup failed)
DQ6
toggling?
DQ5 = 1 ?
YES
YES
NO
Write Data 2
Continue Address
DQ0 = 0?
YES
Program
Phase
Write Data1
Start Address
Read Status
Register
NO
Read Status
Register
NO
DQ0 = 0?
DQ5 = 1?
YES
YES
DQ0 = 0?
NO
Write Data n
Continue Address
YES
Write Data 2
Continue Address
Read Status
Register
NO
Read Status
Register
NO
DQ0 = 0?
DQ5 = 1?
YES
YES
DQ0 = 0?
NO
Read Status
Register
Write XX
Final Address
YES
Write Data n
Continue Address
YES
Read Status
Register
DQ0 = 0?
DQ4 = 0?
Fail error
Read Status
Register
DQ6
toggling?
Exit
Phase
NO
Fail, VPP error
YES
NO
Write F0h
Address XX
NO
YES
Write XX
Final Address
Exit (read mode)
AI05954b
12/24
M59PW064
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. The bits in the Status Register
are summarized in Table 7., Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the P/E.C. has successfully completed its operation. The Data Polling Bit is output on DQ7 when the Status Register
is read.
During a Word Program operation the Data Polling
Bit outputs the complement of the bit being programmed to DQ7. After successful completion of
the Word Program operation the memory returns
to Read mode and Bus Read operations from the
address just programmed output DQ7, not its complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase operation the memory returns to Read Mode.
Figure 6., Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the P/E.C. has successfully completed its operation. The Toggle Bit is output on
DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After
successful completion of the operation the memory returns to Read mode.
Figure 7., Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the P/E.C. The Error Bit
is set to ’1’ when a Program, Block Erase or Chip
Erase operation fails to write the correct data to
the memory. If the Error Bit is set a Read/Reset
command must be issued before other commands
are issued. The Error bit is output on DQ5 when
the Status Register is read.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
VPP Status Bit (DQ4). The VPP Status Bit can be
used to identify if any Program or Erase operation
has failed due to a VPP error. If VPP falls below VHH
during any Program or Erase operation, the operation aborts and DQ4 is set to ‘1’. If VPP remains at
VHH throughout the Program or Erase operation,
the operation completes and DQ4 is set to ‘0’.
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of P/E.C. operation
during a Block Erase command. Once the P/E.C.
starts erasing the Erase Timer Bit is set to ’1’. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the P/E.C. during Block Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register
is read.
During Block Erase operations the Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc., with successive
Bus Read operations from addresses within the
block being erased. Once the operation completes
the memory returns to Read mode.
After an Erase operation that causes the Error Bit
to be set, the Alternative Toggle Bit can be used to
identify where the error occurred. The Alternative
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read Operations from addresses
within a block that has not erased correctly. The
Alternative Toggle Bit does not change if the addressed block has erased correctly.
Multiple Word Program Bit (DQ0). The Multiple
Word Program Bit can be used to indicate whether
the P/E.C. is active or inactive during Multiple
Word Program. When the P/E.C. has written one
Word and is ready to accept the next Word, the bit
is set to ‘0’.
Status Register Bit DQ1 is reserved.
13/24
M59PW064
Table 7. Status Register Bits
Command (1)
Multiple Word
Program
P/E.C. Status
Address
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ0
Programming
–
–
Toggle
0
–
0
–
1
Waiting for data
–
–
Toggle
0
–
0
–
0
Program fail
–
–
Toggle
1
(2)
0
–
1
Programming
–
DQ7
Toggle
0
–
0
–
–
Program error
–
DQ7
Toggle
1
(2)
0
–
–
In erasing block
0
Toggle
0
–
1
Toggle
–
Not in
erasing block
0
Toggle
0
–
1
No Toggle
–
In failed block
0
Toggle
1
(2)
1
Toggle
–
Not in
failed block
0
Toggle
1
(2)
1
No Toggle
–
Word Program
Erasing
Chip Erase/
Block Erase
Erase fail
Note: 1. Unspecified data bits should be ignored.
2. DQ4 = 0 if VPP ≥ VHH during Program/Erase algorithm execution; DQ4 = 1 if VPP < VHH during Program/Erase algorithm execution.
Figure 6. Data Polling Flowchart
Figure 7. Data Toggle Flowchart
START
START
READ
DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
READ DQ6
DQ7
=
DATA
YES
DQ6
=
TOGGLE
NO
NO
YES
NO
DQ5
=1
NO
YES
DQ5
=1
YES
READ DQ7
at VALID ADDRESS
READ DQ6
TWICE
DQ7
=
DATA
YES
DQ6
=
TOGGLE
NO
FAIL
PASS
AI03598
NO
YES
FAIL
PASS
AI01370B
14/24
M59PW064
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 8. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
TBIAS
Temperature Under Bias
–50
125
°C
TSTG
Storage Temperature
–65
150
°C
VIO
Input or Output Voltage (1,2)
–0.6
VCC +0.6
V
VCC
Read Supply Voltage
–0.6
4
V
VPP
Program/Erase Supply Voltage (3)
–0.6
13.5
V
Note: 1. Minimum voltage may undershoot to –2V for less than 20ns during transitions.
2. Maximum voltage may overshoot to VCC +2V for less than 20ns during transitions.
3. Maximum voltage may overshoot to 14.0V for less than 20ns during transitions. VPP must not remain at VHH for more than a total
of 80hrs.
15/24
M59PW064
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 9., Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 9. Operating and AC Measurement Conditions
M59PW064
Parameter
100, 110
Unit
Min
Max
VCC Read Supply Voltage
2.7
3.6
V
VPP Program/Erase Supply Voltage
11.4
12.6
V
Ambient Operating Temperature (TA)
0
70
°C
Load Capacitance (CL)
30
Input Rise and Fall Times
pF
10
Input Pulse Voltages
0 to 3
V
1.5
V
Input and Output Timing Ref. Voltages
Figure 8. AC Measurement I/O Waveform
ns
Figure 9. AC Measurement Load Circuit
1.3V
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
AI05546
OUT
CL
CL = 30pF
CL includes JIG capacitance
AI05447
Device Capacitance
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Note: Sampled only, not 100% tested.
16/24
Test Condition
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
M59PW064
Table 10. DC Characteristics
Symbol
Parameter (1)
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
0V ≤ VOUT ≤ VCC
±1
µA
ICC1
Supply Current (Read)
E = VIL, G = VIH,
f = 6MHz
10
mA
ICC2 (2)
Supply Current (Standby)
E = VCC ±0.2V
100
µA
ICC3
Supply Current (Program)
P/E.C. active
20
mA
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
0.7VCC
VCC +0.3
V
VOL
Output Low Voltage
IOL = 1.8mA
0.45
V
VOH
Output High Voltage
IOH = –100µA
VHH
VPP Program Voltage
IHH
VPP Current (Program)
VCC –0.4
11.4
P/E.C. Active
V
12.6
V
10
mA
Note: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. Average Value.
17/24
M59PW064
Figure 10. Read AC Waveforms
A0-A21
VALID
tAVQV
tAXQX
E
tEHQZ
tELQV
G
tGHQZ
tGLQV
DQ0-DQ15
VALID
AI07232
Table 11. Read AC Characteristics
M59PW064
Symbol
Alt
Parameter
(1)
Test Condition
100
110
Unit
VCC = 3.0 to 3.6V VCC = 2.7 to 3.6V VCC = 2.7 to 3.6V
tAVQV
tACC
Address Valid to
Output Valid
E = VIL,
G = VIL
Max
90
100
110
ns
tELQV
tCE
Chip Enable Low to
Output Valid
G = VIL
Max
90
100
110
ns
tGLQV
tOE
Output Enable Low to
Output Valid
E = VIL
Max
35
35
35
ns
tEHQZ (2)
tHZ
Chip Enable High to
Output Hi-Z
G = VIL
Max
30
30
30
ns
tGHQZ (2)
tDF
Output Enable High
to Output Hi-Z
E = VIL
Max
30
30
30
ns
tAXQX
tOH
Address Transition to
Output Transition
Min
0
0
0
ns
Note: 1. VPP must be applied after VCC and with the Chip Enable (E) at VIH.
2. Sampled only, not 100% tested.
18/24
M59PW064
Figure 11. Write AC Waveforms, Chip Enable Controlled
A0-A21
VALID
tELAX
tEHGL
tAVEL
G
tGHEL
tELEH
E
tEHEL
tDVEH
DQ0-DQ15
tEHDX
VALID
VCC
tVCHEL
VPP
tVPHEL
AI07233
Table 12. Chip Enable Controlled, Write AC Characteristics
Parameter (1)
Symbol
Alt
M59PW064
Unit
tELEH
tCP
Chip Enable Low to Chip Enable High
Min
50
ns
tDVEH
tDS
Input Valid to Chip Enable High
Min
50
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
Min
50
ns
tAVEL
tAS
Address Valid to Chip Enable Low
Min
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
Min
100
ns
Output Enable High Chip Enable Low
Min
10
ns
tGHEL
tEHGL
tOEH
Chip Enable High to Output Enable Low
Min
10
ns
tVCHEL
tVCS
VCC High to Chip Enable Low
Min
50
µs
tVPHEL(2)
tVCS
VPP High to Chip Enable Low
Min
500
ns
Note: 1. TA = 25°C; VPP = 11.4 to 12.6V; VCC = 2.7 to 3.6V.
VPP must be applied after VCC and with the Chip Enable (E) at VIH.
Sampled only, not 100% tested.
2. Not required in Auto Select or Read/Reset command sequences.
19/24
M59PW064
PACKAGE MECHANICAL
Figure 12. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Outline
D
23
44
c
E1 E
θ
1
22
A1
A2
b
L
A
L1
ddd
e
SO-F
Note: Drawing is not to scale.
Table 13. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
3.00
A1
0.10
A2
2.69
2.79
b
0.35
c
28.50
Max
0.118
0.004
2.56
D
0.101
0.110
0.50
0.014
0.020
0.18
0.28
0.007
0.011
28.37
28.63
1.117
1.127
ddd
0.106
1.122
0.10
0.004
E
16.03
15.77
16.28
0.631
0.621
0.641
E1
12.60
12.47
12.73
0.496
0.491
0.501
e
1.27
–
–
0.050
–
–
L
0.79
0.031
L1
1.73
0.068
θ
N
20/24
Max
8°
44
8°
44
M59PW064
Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12x20mm, Package Outline
1
48
e
D1
B
24
L1
25
A2
E1
E
A
α
A1
DIE
L
C
CP
TSOP-G
Note: Drawing is not to scale.
Table 14. TSOP48 - 48 lead Plastic Thin Small Outline, 12x20mm, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
Max
0.0472
A1
0.100
0.050
0.150
0.0039
0.0020
0.0059
A2
1.000
0.950
1.050
0.0394
0.0374
0.0413
B
0.220
0.170
0.270
0.0087
0.0067
0.0106
0.100
0.210
0.0039
0.0083
C
CP
0.080
0.0031
D1
12.000
11.900
12.100
0.4724
0.4685
0.4764
E
20.000
19.800
20.200
0.7874
0.7795
0.7953
E1
18.400
18.300
18.500
0.7244
0.7205
0.7283
e
0.500
–
–
0.0197
–
–
L
0.600
0.500
0.700
0.0236
0.0197
0.0276
L1
0.800
α
3
0
5
0.0315
0
5
3
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M59PW064
PART NUMBERING
Table 15. Ordering Information Scheme
Example:
M59P064
100 M
1
T
Device Type
M59P = LightFlash Memory
Operating Voltage
W = VCC = 2.7 to 3.6V
Device Function
064 = 64 Mbit (x16)
Speed
100 = 100 ns (1)
110 = 110 ns
Package
M = SO44, 500mils body width
N = TSOP48: 12 x 20 mm
Temperature Range
1 = 0 to 70 °C
Option
T = Tape & Reel Packing
Note: 1. This speed also guarantees 90ns access time at VCC = 3.0 to 3.6V.
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M59PW064
REVISION HISTORY
Table 16. Document Revision History
Date
Version
Revision Details
19-Jul-2002
1.0
First Issue
05-Aug-2002
1.1
Multiple Word Program Command Table clarified (Table 5.)
ICC1, ICC2 clarified (Table 10.)
28-Nov-2002
1.2
SO44 body width modified
Bus Operation table clarified (Table 3.)
Read/Reset, Auto Select and Multiple Word Program commands clarified
Mask-ROM pin-out compatible feature added
90ns speed class obtained from the 100ns at VCC = 3.0 to 3.6V (Tables 11 and 12)
Chip Enable, Output Enable, Program Supply Voltage clarified
07-Feb-2003
1.3
Document status changed to Datasheet
30-Jan-2004
2.0
TSOP48 Package specifications changed (see Figure 13. and Table 14.).
15-Mar-2005
3.0
Table 15., Ordering Information Scheme corrected.
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M59PW064
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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