M616Z08 128 Kbit (8 Kbit x 16) SRAM WITH OUTPUT ENABLE FEATURES SUMMARY ■ OPERATION VOLTAGE: 2.34V to 3.6V ■ 8 Kbit x 16 SRAM ■ EQUAL CYCLE and ACCESS TIMES: AS FAST AS 20ns ■ TRI-STATE COMMON I/O ■ TWO WRITE ENABLE PINS ALLOW WRITING TO UPPER AND LOWER BYTES Figure 1. 44-pin, Hatless SOIC Package 44 1 SO44 (MH) Figure 2. Logic Diagram Table 1. Signal Names A0-A12 VCC DQ0-DQ15 13 16 A0-A12 WE0 DQ0-DQ15 Address Inputs Data Input/Output CE Chip Enable OE Output Enable WE0 WRITE Enable DQ 0-7 WE1 WRITE Enable DQ 8-15 VCC Supply Voltage VSS Ground TO Time-Out Pin M616Z08 WE1 TO CE OE Note: TO Pin should be connected to VCC. VSS AI04213 July 2002 1/14 M616Z08 TABLE OF CONTENTS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 44-pin Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC and AC Measurement Conditions (Table 3.) . . . AC Testing Load Circuit (Figure 4.) . . . . . . . . . . . . . Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... .....5 .....5 .....5 .....6 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Controlled, READ Mode AC Waveforms (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip Enable or Output Enable Controlled, READ Mode AC Waveforms (Figure 6.). . . . . . . . . . . . . 7 READ Mode AC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE Enable Controlled, WRITE Mode AC Waveforms (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Enable Controlled, WRITE Mode AC Waveforms (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE Mode AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 “Operational” Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 WE(0,1) States during Access (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operating Modes (Table 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/14 M616Z08 DESCRIPTION The M616Z08 is a 128 Kbit (131,072 bit) CMOS SRAM, organized by 16 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.6V ± 10% or 3.3V ± 10% supply, and all inputs and outputs are TTL compatible. The M616Z08 is available in a 44-lead SOIC package. Figure 3. 44-pin Connections DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 VCC VSS DQ8 DQ9 DQ10 DQ11 VSS VCC DQ12 DQ13 DQ14 DQ15 44 1 43 2 3 42 4 41 40 5 39 6 38 7 37 8 36 9 35 10 34 11 M616Z08 33 12 32 13 31 14 30 15 29 16 28 17 27 18 26 19 25 20 24 21 23 22 A12 A11 A10 A9 VCC VSS A08 A07 TO CE OE WE1 WE0 A06 A05 A04 VSS VCC A03 A02 A01 A00 AI04212 Note: TO Pin should be connected to VCC. 3/14 M616Z08 MAXIMUM RATING Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 2. Absolute Maximum Ratings Symbol Value Unit Ambient Operating Temperature –40 to 125 °C TSTG(1) Storage Temperature –65 to 150 °C VIO(2,3) Input or Output Voltage –0.3 to VCC + 0.3 V TA Parameter VCC Supply Voltage –0.3 to 4.0 V IO(4) Output Current 10 mA Power Dissipation 270 mW PD Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 and 120 seconds). 2. Up to a maximum operating VCC of 3.6V only. 3. VIL(min) = VSS – 2.0V AC (pulse width ≤ 10% tAVAV(min)) VIH(max) = VCC + 2.0V AC (pulse width ≤ 10% tAVAV(min)) 4. One output at a time, not to exceed 1 second duration. 4/14 M616Z08 DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 3. DC and AC Measurement Conditions Parameter M616Z08 VCC Supply Voltage 2.34 to 3.0V or 3.0 to 3.6V Ambient Operating Temperature –40 to 125°C Load Capacitance (CL) 50pF Input Rise and Fall Times ≤ 5ns Input Pulse Voltages 0 to 3V Input and Output Timing Ref. Voltages 1.5V Note: Output High Z is defined as the point where data is no longer driven. Figure 4. AC Testing Load Circuit 3.0V 2.6 KΩ DEVICE UNDER TEST OUT 2.6 KΩ CL = 50 pF or 5pF AI05650 Table 4. Capacitance Parameter(1,2) Symbol CIN COUT(3) Min Max Unit Input Capacitance on all pins (except DQ) 10 pF Output Capacitance 10 pF Note: 1. Effective capacitance measured with power supply at 3.3V; sampled only, not 100% tested. 2. At 25°C; f = 1MHz. 3. Outputs deselected. 5/14 M616Z08 Table 5. DC Characteristics Sym ILI Test Condition(1) Parameter Input Leakage Current Min Typ Max Unit 65 125 µA ±1 µA 0V ≤ VOUT ≤ VCC ±1 µA VCC = 3.6V 75 mA VCC = 3.6V, CE ≥ VCC – 0.2V, f = 0 1 mA TO Pin(2) 0V ≤ VIN ≤ VCC All other inputs ILO Output Leakage Current ICC1(3) Supply Current ICC3(4) Supply Current (Standby) CMOS VIL Input Low Voltage –0.3 0.3VCC V VIH Input High Voltage 0.7VCC VCC + 0.3 V VOL Output Low Voltage 0.2 V VOH Output High Voltage Note: 1. 2. 3. 4. IOL = 1mA 2.34 to 3.0V VCC–0.2V 3.0 to 3.6V VCC–0.3V IOH = –1mA V Valid for Ambient Operating Temperature: TA = –40 to 125°C; VCC = 3.0 to 3.6V or 2.34 to 3.0V (except where noted). Input leakage on TO Pin due to internal pull-down to VSS. Average AC current, Outputs open, cycling at tAVAV minimum. All other Inputs at VIL ≤ 0.2V or VIH ≥ VCC –0.2V. OPERATION READ Mode The M616Z08 is in the READ Mode whenever WRITE Enable (WE0 or WE1) is High with Output Enable (OE) Low, and Chip Enable (CE) is asserted. This provides access to data from sixteen of the 131,072 locations in the static memory array, specified by the 13 address inputs. Valid data will be available at the sixteen output pins within tAVQV after the last stable address, providing OE is Low and CE is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV or tGLQV) rather than the address. Data out may be indeterminate at tELQX and tGLQX, but data lines will always be valid at tAVQV. Figure 5. Address Controlled, READ Mode AC Waveforms tAVAV VALID A0-A12 tAVQV DQ0-DQ15 tAXQX DATA VALID AI04210 Note: CE = Low, OE = Low, WE(0,1) = High. 6/14 M616Z08 Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms tAVAV VALID A0-A12 tAVQV tAXQX tELQV tEHQZ CE tELQX tGLQV tGHQZ OE tGLQX DQ0-DQ15 VALID AI05638 Table 6. READ Mode AC Characteristics M616Z08 Symbol Parameter(1) –20 2.34 to 3.0V Min Max 3.0 to 3.6V Min Unit Max tAVAV READ Cycle Time tAVQV Address Valid to Output Valid 36 20 ns tELQV Chip Enable Low to Output Valid 36 20 ns tGLQV Output Enable Low to Output Valid 20 10 ns tELQX Chip Enable Low to Output Transition 0 0 ns tGLQX Output Enable Low to Output Transition 0 0 ns tEHQZ (2) tGHQZ(2) tAXQX 36 20 ns Chip Enable High to Output Hi-Z 10 10 ns Output Enable High to Output Hi-Z 10 10 ns Address Transition to Output Transition 0 0 ns Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 125°C (except where noted). 2. CL = 5pF. 7/14 M616Z08 WRITE Mode The M616Z08 is in the WRITE mode whenever the WE0 (low memory addresses) or WE1 (high memory addresses) and CE pins are low (see Table 8, page 10). Either the Chip Enable input (CE) or the WRITE Enable input (WE0 or WE1) must be deasserted during Address transitions for subsequent WRITE cycles. WRITE begins with the concurrence of Chip Enable being active with WE0 or WE1 low. Therefore, address setup time is referenced to WRITE Enable and Chip Enable as tAVWL and tAVEH respectively, and is determined by the latter occurring edge. The WRITE cycle can be terminated by the earlier rising edge of CE, or WE0/WE1. if the Output is enabled (CE = Low and OE = Low), then WE0 or WE1 will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of WRITE Enable, or for tDVEH before the rising edge of CE, whichever occurs first, and remain valid for tWHDX or tEHDX. Note: When using MCP555 with TO Pin high, relaxed WRITE timing (CSNT = 1 in the chip select configuration register) should be selected. Figure 7. WRITE Enable Controlled, WRITE Mode AC Waveforms tAVAV VALID A0-A12 tAVWH tWHAX tAVEL CE tWLWH tAVWL WE (0,1) tWLQZ tWHQX tWHDX DATA INPUT DQ0-DQ15 tDVWH AI04211 Figure 8. Chip Enable Controlled, WRITE Mode AC Waveforms tAVAV VALID A0-A12 tAVEH tELEH tAVEL tEHAX CE tAVWL WE (0,1) tEHDX DQ0-DQ15 DATA INPUT tDVEH AI05639 Note: 1. Output Enable (OE) = High. 2. If CE goes High with WE0 or WE1 high, the output remains in a high-impedance state. 8/14 M616Z08 Table 7. WRITE Mode AC Characteristics M616Z08 Parameter(1) Symbol –20 Unit 2.34 to 3.0V Min Max 3.0 to 3.6V Min Max tAVAV WRITE Cycle Time 36 20 ns tAVWL Address Valid to WRITE Enable Low 2 2 ns tAVWH Address Valid to WRITE Enable High 34 18 ns tAVEH Address Valid to Chip Enable High 34 18 ns tWLWH WRITE Enable Pulse Width 25 11 ns tWHAX WRITE Enable High to Address Transition 2 2 ns tWHDX WRITE Enable High to Input Transition 2 2 ns tWHQX(3) WRITE Enable High to Output Transition 0 0 ns tWLQZ(2,3) WRITE Enable Low to Output Hi-Z tAVEL Address Valid to Chip Enable Low 2 2 ns tELEH Chip Enable Low to Chip Enable High 25 11 ns tEHAX Chip Enable High to Address Transition 2 2 ns tEHDX Chip Enable High to Input Transition 2 2 ns tDVWH Input Valid to WRITE Enable High 20 8 ns tDVEH Input Valid to Chip Enable High 20 8 ns 10 10 ns Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 125°C (except where noted). 2. CL = 5pF 3. At any given temperature and voltage condition, t WLQZ is less than tWHQX for any given device. 9/14 M616Z08 “Operational” Mode The M616Z08 has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (CE = High). An Output Enable (OE) signal provides a high speed tri-state control, allowing fast READ/WRITE cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs WE0 or WE1 and CE as summarized in “Operating Modes” (see Table 8 and Table 9). Noise Immunity When designing with high speed memory, proper power trace layout and capacitive decoupling must be maintained to ensure proper system operation. Power and ground line inductance should be reduced by providing separate power planes. The impedance of the decoupling path from the power pin through the decoupling capacitor should also be kept to a minimum. Small decoupling capacitors (10nF) should be located as close to the device pins as possible to limit the high frequency noise. Larger capacitor values (10uF and 1uF) are recommended to reduce low frequency noise and should be placed next to the power entry point of the board. Proper line termination should also be employed to minimize signal reflection. See Motorola Semiconductor Application Note AN2127/D for additional Electromagnetic Compatibility (EMC) system design guidelines. Table 8. WE(0,1) States during Access WRITE Enable Used during 16-bit Port Access WE0 WRITE Enable for DQ (0-7) WE1 WRITE Enable for DQ (8-15) Table 9. Operating Modes Operation CE OE WE0 WE1 DQ0–DQ7 DQ8–15 Deselect VIH X(1) X(1) X(1) Hi-Z Hi-Z Word WRITE VIL VIH VIL VIL Hi-Z Hi-Z Byte 0 WRITE VIL VIH VIL VIH Hi-Z Hi-Z Byte 1 WRITE VIL VIH VIH VIL Hi-Z Hi-Z Byte 0 WRITE, Byte 1 READ VIL VIL VIL VIH Hi-Z Data Byte 1 WRITE, Byte 0 READ VIL VIL VIH VIL Data Hi-Z Word READ VIL VIL VIH VIH Data Data Note: 1. X = '1' or '0' 10/14 M616Z08 PART NUMBERING Table 10. Ordering Information Example Example: M6 16Z08 –20 MH 3 TR Device Type M6 Device Function 16Z08 = 128Kbit (8 x16) Speed –20 = 20ns (3.0 to 3.6V) Package MH = 44-lead, Hatless SOIC Temperature Range 3 = –40 to 125°C Shipping Method for SOIC blank = Tubes TR = Tape & Reel For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 11/14 M616Z08 PACKAGE MECHANICAL INFORMATION Figure 9. SO44 – 44-Lead, Plastic, Hatless, Small Package Outline A2 A C B e CP D N E H A1 α L 1 SOH-C Note: Drawing is not to scale. Table 11. SO44 – 44-lead, Plastic, Hatless, Small Package Mechanical Data mm inches Symb Min Typ A Min Typ 3.05 Max 0.120 A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106 B 0.36 0.46 0.014 0.018 C 0.15 0.32 0.006 0.012 D 17.71 18.49 0.697 0.728 E 8.23 8.89 0.324 0.350 – – – – H 11.51 12.70 0.453 0.500 L 0.41 1.27 0.016 0.050 a 0° 8° 0° 8° N 44 e CP 12/14 Max 0.81 0.032 44 0.10 0.004 M616Z08 REVISION HISTORY Table 12. Document Revision History Date Rev. # Revision Details September 2001 1.0 First Issue 11/1901 2.0 Correction of Operating Modes text (Table 9); document status changed to “Data Sheet;” add text for Noise Immunity (page 10) 02/12/02 2.1 Add TO Pin (Figure 2, 3, Table 1); change WRITE Mode AC Characteristics (Table 7) 02/21/02 2.2 Changes for TO Pin (Table 5) and change characteristics (Table 6, 7) 05/13/02 2.3 Add reflow time and temperature footnote (Table 2) 07/22/02 2.4 Add “Hatless” to package description (Figure 1, 9 and Table 10, 11) 13/14 M616Z08 Automotive, Automotive, Automotive, Automotive, Automotive, Automotive, Automotive, Automotive, Automotive, Automotive, Automotive, Automotive, Automotive, Automotive, Automotive, Low, Power, Low, Power, Low, Power, Low, Power, Low, Power, Low, Power, Low, Power, Low, Power, Low, Power, Low, Power, Low, Power, Low, Power, Low, Power, Low, Power, Low, Power, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, LPSRAM, Auto, Auto, Auto, Auto, Auto, Auto, Auto, Auto, Auto, Auto, Auto, Auto, Auto, Auto, Auto, Auto, Auto, Auto, Auto, Auto, High, Temperature, Temp, Range, High, Temperature, Temp, Range, High, Temperature, Temp, Range, High, Temperature, Temp, Range, High, Temperature, Temp, Range, High, Temperature, Temp, Range, High, Temperature, Temp, Range, High, Temperature, Temp, Range, High, Temperature, Temp, Range, High, Temperature, Temp, Range Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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