M68AW512D 8 Mbit (512K x16) 3.0V Asynchronous SRAM FEATURES SUMMARY ■ SUPPLY VOLTAGE: 2.7 to 3.6V ■ 512K x 16 bits SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 55, 70ns ■ LOW STANDBY CURRENT ■ LOW VCC DATA RETENTION: 1.5V ■ TRI-STATE COMMON I/O ■ AUTOMATIC POWER DOWN November 2002 Figure 1. Packages BGA TFBGA48 (ZB) 8 x 10 mm 1/18 M68AW512D TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MAXIMUM RATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . 9 Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . 9 Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10. Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 11. Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 12. UB/LB Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Low VCC Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline . . . . . . . . . . . . 15 TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . . . . . . . . 15 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/18 M68AW512D SUMMARY DESCRIPTION The M68AW512D is an 8 Mbit (8,388,608 bit) CMOS SRAM, organized as 524,288 words by 16 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This device has a Chip Select pin (E2) for easy memory expansion; when it is active (E2 high) the device has an automatic power-down feature, reducing the power consumption by over 99%. The M68AW512D is available in TFBGA48 (0.75 mm ball pitch) package. Figure 2. Logic Diagram Table 1. Signal Names A0-A18 Address Inputs DQ0-DQ15 Data Input/Output E1 Chip Enable E2 Chip Select G Output Enable W W Write Enable E1 UB Upper Byte Enable Input LB Lower Byte Enable Input VCC Supply Voltage VSS Ground NC Not Connected DU Don’t Use as Internally Connected VCC 19 16 A0-A18 E2 DQ0-DQ15 M68AW512D G UB LB VSS AI04800b 3/18 M68AW512D Figure 3. TFBGA Connections (Top view through package) 1 2 3 4 5 6 A LB G A0 A1 A2 E2 B DQ8 UB A3 A4 E1 DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VSS DQ11 A17 A7 DQ3 VCC E VCC DQ12 VSS A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 NC A12 A13 W DQ7 H A18 A8 A9 A10 A11 DU AI03960 4/18 M68AW512D Figure 4. Block Diagram A18 ROW DECODER MEMORY ARRAY A8 DQ15 (8) I/O CIRCUITS UB COLUMN DECODER DQ0 E1 Ex (8) LB E2 UB LB A0 A7 (8) UB W (8) LB G AI05452 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for periods greater than 1 sec may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 2. Absolute Maximum Ratings Symbol Value Unit Ambient Operating Temperature –55 to 125 °C TSTG Storage Temperature –65 to 150 °C VCC Supply Voltage –0.5 to 4.6 V –0.5 to VCC +0.5 V 1 W TA VIO (1) PD Parameter Input or Output Voltage Power Dissipation Note: 1. Up to a maximum operating VCC of 3.6V only. 5/18 M68AW512D DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 3. Operating and AC Measurement Conditions Parameter M68AW512D VCC Supply Voltage 2.7 to 3.6V Range 1 0 to 70°C Range 6 –40 to 85°C Ambient Operating Temperature Load Capacitance (CL) 30pF Output Circuit Protection Resistance (R1) 3.0kΩ Load Resistance (R2) 3.1kΩ Input Rise and Fall Times ≤ 1ns/V Input Pulse Voltages 0 to VCC Input and Output Timing Ref. Voltages VCC/2 Output Transition Timing Ref. Voltages VRL = 0.3VCC; VRH = 0.7VCC Figure 5. AC Measurement I/O Waveform Figure 6. AC Measurement Load Circuit VCC I/O Timing Reference Voltage R1 VCC VCC/2 0V DEVICE UNDER TEST OUT CL Output Transition Timing Reference Voltage VCC 0V R2 0.7VCC 0.3VCC AI04831 CL includes probe and 1 TTLcapacitance AI05832 6/18 M68AW512D Table 4. Capacitance CIN COUT Test Condition Parameter(1,2) Symbol Max Unit VIN = 0V 8 pF VOUT = 0V 10 pF Max Unit 70ns 35 mA 55ns 40 mA 4 mA 20 µA Input Capacitance on all pins (except DQ) Output Capacitance Min Note: 1. Sampled only, not 100% tested. 2. At TA = 25°C, f = 1 MHz, VCC = 3.0V. Table 5. DC Characteristics Symbol Parameter ICC1 (1,2) Operating Supply Current ICC2 (3) Operating Supply Current ISB Standby Supply Current CMOS ILI Input Leakage Current ILO Output Leakage Current VIH Test Condition VCC = 3.6V, f = 1/tAVAV, IOUT = 0mA Min Typ VCC = 3.6V, f = 1MHz, IOUT = 0mA VCC = 3.6V, f = 0, E1 ≥ VCC –0.2V or E2 ≤ 0.2V or LB=UB ≥ VCC –0.2V 1 0V ≤ VIN ≤ VCC –1 1 µA 0V ≤ VOUT ≤ VCC (4) –1 1 µA Input High Voltage 2.2 VCC + 0.3 V VIL Input Low Voltage –0.3 0.6 V VOH Output High Voltage IOH = –1.0mA VOL Output Low Voltage IOL = 2.1mA Note: 1. 2. 3. 4. 2.4 V 0.4 V Average AC current, cycling at tAVAV minimum. E1 = V IL AND E2 = VIH, LB OR/AND UB = VIL, V IN = V IL OR VIH. E1 ≤ 0.2V AND E2 ≥ VCC –0.2V, LB OR/AND UB ≤ 0.2V, VIN ≤ 0.2V OR VIN ≥ VCC –0.2V. Output disabled. 7/18 M68AW512D OPERATION The M68AW512D has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E1 = High) or Chip Select is asserted (E2 = Low), or UB/LB are de-asserted (UB/LB = High). An Output Enable (G) signal provides a high speed tri-state con- trol, allowing fast read/write cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W, E1, LB and UB as summarized in the Operating Modes table (see Table 6). Table 6. Operating Modes Operation E1 E2 W G LB UB DQ0-DQ7 DQ8-DQ15 Power Deselected VIH X X X X X Hi-Z Hi-Z Standby (ISB) Deselected X VIL X X X X Hi-Z Hi-Z Standby (ISB) Deselected X X X X VIH VIH Hi-Z Hi-Z Standby (ISB) Lower Byte Read VIL VIH VIH VIL VIL VIH Data Output Hi-Z Active (ICC) Lower Byte Write VIL VIH VIL X VIL VIH Data Input Hi-Z Active (ICC) Output Disabled VIL VIH VIH VIH X X Hi-Z Hi-Z Active (ICC) Upper Byte Read VIL VIH VIH VIL VIH VIL Hi-Z Data Output Active (ICC) Upper Byte Write VIL VIH VIL X VIH VIL Hi-Z Data Input Active (ICC) Word Read VIL VIH VIH VIL VIL VIL Data Output Data Output Active (ICC) Word Write VIL VIH VIL X VIL VIL Data Input Data Input Active (ICC) Note: 1. X = VIH or VIL. Read Mode The M68AW512D, when Chip Select (E2) is High, is in the read mode whenever Write Enable (W) is High with Output Enable (G) Low, and Chip Enable (E1) is asserted. This provides access to data from eight or sixteen, depending on the status of the signal UB and LB, of the 8,388,608 locations in the static memory array, specified by the 19 address inputs. Valid data will be available at the eight or sixteen output pins within tAVQV after the last stable address, providing G is Low and E1 is Low and E2 is High. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV, tGLQV or t BLQV) rather than the address. Data out may be indeterminate at tELQX, tGLQX and tBLQX, but data lines will always be valid at tAVQV. Figure 7. Address Controlled, Read Mode AC Waveforms tAVAV A0-A18 VALID tAVQV DQ0-DQ7 and/or DQ8-DQ15 tAXQX DATA VALID AI05839 Note: E1 = Low, E2 = High, G = Low, W = High, UB = Low and/or LB = Low. 8/18 M68AW512D Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms tAVAV VALID A0-A18 tAVQV tAXQX tELQV tEHQZ E1 E2 tELQX tGLQV tGHQZ G tGLQX DQ0-DQ15 VALID tBLQV tBHQZ UB, LB tBLQX AI05981 Note: Write Enable (W) = High Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms E1, UB, LB E2 ICC ISB tPU tPD 50% AI05497 9/18 M68AW512D Table 7. Read and Standby Mode AC Characteristics M68AW512D Symbol Parameter Unit 55 70 tAVAV Read Cycle Time Min 55 70 ns tAVQV Address Valid to Output Valid Max 55 70 ns Data hold from address change Min 5 5 ns tBHQZ (2,3,4) Upper/Lower Byte Enable High to Output Hi-Z Max 20 25 ns tBLQV Upper/Lower Byte Enable Low to Output Valid Max 55 70 ns Upper/Lower Byte Enable Low to Output Transition Min 5 5 ns tEHQZ (2,3,4) Chip Enable High to Output Hi-Z Max 20 25 ns tELQV Chip Enable Low to Output Valid Max 55 70 ns Chip Enable Low to Output Transition Min 5 5 ns tGHQZ (2,3,4) Output Enable High to Output Hi-Z Max 20 25 ns tGLQV Output Enable Low to Output Valid Max 25 35 ns Output Enable Low to Output Transition Min 5 5 ns tPD (4) Chip Enable or UB/LB High to Power Down Max 0 0 ns tPU (4) Chip Enable or UB/LB Low to Power Up Min 55 70 ns tAXQX (1) tBLQX (1) tELQX (1) tGLQX (1) Note: 1. Test conditions assume transition timing reference level = 0.3VCC or 0.7VCC. 2. At any given temperature and voltage condition, t GHQZ is less than tGLQX , tBHQZ is less than tBLQX and t EHQZ is less than tELQX for any given device. 3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. Testested initially and after any design or process changes that may affect these parameters. 10/18 M68AW512D Write Mode The M68AW512D, when Chip Select (E2) is High, is in the Write Mode whenever the W and E1 are Low. Either the Chip Enable Input (E1) or the Write Enable input (W) must be de-asserted during Address transitions for subsequent write cycles. When E1 or W is Low, and UB or LB is Low, write cycle begins on the W or E1 falling edge. When E1 and W are Low, and UB = LB = High, write cycle begins on the first falling edge of UB or LB. Therefore, address setup time is referenced to Write Enable, Chip Enables and UB/LB as t AVWL, tAVEL and tAVBL respectively, and is determined by the latter occurring falling edge. The Write cycle can be terminated by the earlier rising edge of E1, W, UB and LB. If the Output is enabled (E1 = Low, E2 = High, G = Low, LB or UB = Low), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for t DVWH before the rising edge of Write Enable, or for tDVEH before the rising edge of E1 or for t DVBH before the rising edge of UB/LB, whichever occurs first, and remain valid for t WHDX, tEHDX and tBHDX respectively. Figure 10. Write Enable Controlled, Write AC Waveforms tAVAV VALID A0-A18 tAVWH tELWH tAVEL tWHAX E1 E2 tWLWH tAVWL W tWLQZ tWHQX tWHDX DATA INPUT DQ0-DQ15 tDVWH tBLBH UB, LB AI05982 Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied. 11/18 M68AW512D Figure 11. Chip Enable Controlled, Write AC Waveforms tAVAV VALID A0-A18 tAVEH tELEH tAVEL tEHAX E1 E2 tAVWL tWLEH W tEHDX DATA INPUT DQ0-DQ15 tDVEH tBLBH UB, LB AI05983 Figure 12. UB/LB Controlled, Write AC Waveforms tAVAV VALID A0-A18 tAVBH tBHAX E1 E2 tWLBH tAVWL W tWLQZ DQ0-DQ15 tBHDX DATA (1) DATA INPUT tDVBH tAVBL tBLBH UB, LB AI05984 Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied. 12/18 M68AW512D Table 8. Write Mode AC Characteristics M68AW512D Symbol Parameter Unit 55 70 tAVAV Write Cycle Time Min 55 70 ns tAVBH Address Valid to LB, UB High Min 45 60 ns tAVBL Addess Valid to LB, UB Low Min 0 0 ns tAVEH Address Valid to Chip Enable High Min 45 60 ns tAVEL Address valid to Chip Enable Low Min 0 0 ns tAVWH Address Valid to Write Enable High Min 45 60 ns tAVWL Address Valid to Write Enable Low Min 0 0 ns tBHAX LB, UB High to Address Transition Min 0 0 ns tBHDX LB, UB High to Input Transition Min 0 0 ns tBLBH LB, UB Low to LB, UB High Min 45 60 ns tBLEH LB, UB Low to Chip Enable High Min 45 60 ns tBLWH LB, UB Low to Write Enable High Min 45 60 ns tDVBH Input Valid to LB, UB High Min 25 30 ns tDVEH Input Valid to Chip Enable High Min 25 30 ns tDVWH Input Valid to Write Enable High Min 25 30 ns tEHAX Chip Enable High to Address Transition Min 0 0 ns tEHDX Chip enable High to Input Transition Min 0 0 ns tELBH Chip Enable Low to LB, UB High Min 45 60 ns tELEH Chip Enable Low to Chip Enable High Min 45 60 ns tELWH Chip Enable Low to Write Enable High Min 45 60 ns tWHAX Write Enable High to Address Transition Min 0 0 ns tWHDX Write Enable High to Input Transition Min 0 0 ns Write Enable High to Output Transition Min 5 5 ns tWLBH Write Enable Low to LB, UB High Min 45 60 ns tWLEH Write Enable Low to Chip Enable High Min 45 60 ns Write Enable Low to Output Hi-Z Max 20 20 ns Write Enable Low to Write Enable High Min 40 50 ns tWHQX (1) tWLQZ (1,2,3) tWLWH Note: 1. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device. 2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 3. Testested initially and after any design or process changes that may affect these parameters. 13/18 M68AW512D Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms DATA RETENTION MODE 3.6V VCC 2.7V VDR > 1.5V tCDR tR E1 ≥ VDR – 0.2V or UB = LB ≥ VDR – 0.2V E1 or UB/LB AI05985 Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms DATA RETENTION MODE 3.6V VCC 2.7V VDR > 1.5V tCDR tR E2 < 0.2V E2 AI05986B Table 9. Low V CC Data Retention Characteristics Symbol ICCDR (1) Parameter Test Condition Supply Current (Data Retention) VCC = 1.5V, E1 ≥ VCC –0.2V or E2 ≤ 0.2V or UB = LB ≥ VCC –0.2V, f=0 Chip Deselected to Data tCDR (1,2) Retention Time tR (2) VDR (1) Operation Recovery Time Supply Voltage (Data Retention) E1 ≥ VCC –0.2V or E2 ≤ 0.2V or UB = LB ≥ VCC –0.2V, f = 0 Min Typ Max Unit 5 10 µA 0 ns tAVAV ns 1.5 V Note: 1. All other Inputs at V IH ≥ VCC –0.2V or VIL ≤ 0.2V. 2. Tested initially and after any design or process that may affect these parameters. tAVAV is Read cycle time. 3. No input may exceed VCC +0.2V. 14/18 M68AW512D PACKAGE MECHANICAL Figure 15. TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline D D1 FD FE E SD SE E1 ddd BALL "A1" A e A2 b A1 BGA-Z28 Note: Drawing is not to scale. Table 10. TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data Symbol millimeters Typ Min A inches Max Typ Min 1.200 A1 0.0472 0.260 A2 0.0102 0.900 b Max 0.350 0.450 0.0354 0.0138 0.0177 D 8.000 7.900 8.100 0.3150 0.3110 0.3189 D1 3.750 – – 0.1476 – – ddd 0.100 0.0039 E 10.000 9.900 10.100 0.3937 0.3898 0.3976 E1 5.250 – – 0.2067 – – e 0.750 – – 0.0295 – – FD 2.125 – – 0.0837 – – FE 2.375 – – 0.0935 – – SD 0.375 – – 0.0148 – – SE 0.375 – – 0.0148 – – 15/18 M68AW512D PART NUMBERING Table 11. Ordering Information Scheme Example: M68AW512 D L 55 ZB 6 T Device Type M68 Mode A = Asynchronous Operating Voltage W = 2.7 to 3.6V Array Organization 512 = 8 Mbit (512K x16) Option 1 D = 2 Chip Enable; Write and Standby from UB and LB Option 2 L = L-Die N = N-Die Speed Class 55 = 55ns 70 = 70ns Package ZB = TFBGA48: 0.75 mm pitch Operative Temperature 1 = 0 to 70 °C 6 = –40 to 85 °C Shipping T = Tape & Reel Packing For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 16/18 M68AW512D REVISION HISTORY Table 12. Document Revision History Date Version Revision Details July 2001 -01 First Issue 06-Feb-2002 -02 70ns Speed Class added, Commercial Temperature Range added 14-Mar-2002 -03 Document status moved to Datasheet Tables 6, 7 and 9 clarified Figures 8, 9, 10, 11 and 12 clarified 17-Jun-2002 -04 Block Diagram clarified (Figure 4) ISB clarified (Table 5) ICCDR clarified (Table 9) 09-Oct-2002 4.1 Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 04 equals 4.0). Part number modified. 25-Nov-2002 4.2 Figure 14, E2 Controlled, Low VCC Data Retention AC Waveforms, corrected. 17/18 M68AW512D Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. © 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 18/18