M54/74HC564 M54/74HC574 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HC564 INVERTING - HC574 NON INVERTING . . . . . . . . HIGH SPEED fMAX = 62 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28% VCC (MIN) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOL = IOH= 6 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS564/574 DESCRIPTION The M54/74HC564 and M54HC574 are high speed CMOS OCTAL D-TYPE FLIP FLOP WITH 3-STATE 2 OUTPUTS fabricated with in silicon gate C MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power comsuption. These8-bit D-type flip-flops are controlled by a clock input (CK) and an ouput enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs (HC574) or their complements (HC564). While the OE input is low, the eight outputs will be in a normal logic state (high or low logic level), and while high level, the outputs will be in a high imped- B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HCXXXF1R M74HCXXXM1R M74HCXXXB1R M74HCXXXC1R ance state. The output control does not affect the internal operation of flip-flops. That is, the old data can be retained or the new data can be entered even while the outputs are off. The application engineer has a choice of combination of inverting and non-inverting outputs. The 3-state output configuration and the wide choice of outline make bus-organized systems simple. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION (top view) March 1993 1/13 M54/M74HC564/574 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION (HC564) PIN No SYMBOL 1 OE 2, 3, 4, 5, 6, 7, 8, 9, 10 D0 to D7 12, 13, 14, 15, 16, 17, 18, 19 Q0 to Q7 11 CLOCK 10 20 GND V CC NAME AND FUNCTION PIN DESCRIPTION (HC574) PIN No SYMBOL 1 OE Data Inputs 2, 3, 4, 5, 6, 7, 8, 9, 10 D0 to D7 Data Inputs 3 State outputs 12, 13, 14, 15, 16, 17, 18, 19 Q0 to Q7 3 State outputs Clock Input (LOW to HIGH, edge triggered) 11 CLOCK Ground (0V) Positive Supply Voltage 10 20 GND VCC 3 State output Enable Input (Active LOW) IEC LOGIC SYMBOLS HC564 2/13 HC574 NAME AND FUNCTION 3 State output Enable Input (Active LOW) Clock Input (LOW to HIGH, edge triggered) Ground (0V) Positive Supply Voltage M54/M74HC564/574 TRUTH TABLE INPUTS OE H L L L CK X OUTPUTS D X Q (HC574) Z Q (HC564) Z X L H NO CHANGE L H NO CHANGE H L LOGIC DIAGRAMS 3/13 M54/M74HC564/574 ABSOLUTE MAXIMUM RATINGS Symbol Value Unit VCC VI Supply Voltage DC Input Voltage -0.5 to +7 -0.5 to VCC + 0.5 V V VO DC Output Voltage -0.5 to VCC + 0.5 V IIK IOK DC Input Diode Current DC Output Diode Current ± 20 ± 20 mA mA IO DC Output Source Sink Current Per Output Pin ± 35 mA DC VCC or Ground Current ± 70 mA 500 (*) mW ICC or IGND Parameter PD Power Dissipation Tstg TL Storage Temperature Lead Temperature (10 sec) -65 to +150 300 o o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied. (*) 500 mW: ≅ 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage VI Input Voltage VO Top Output Voltage Operating Temperature: tr, tf Input Rise and Fall Time 4/13 M54HC Series M74HC Series VCC = 2 V Value 2 to 6 Unit V 0 to VCC V 0 to VCC -55 to +125 -40 to +85 0 to 1000 V C o C ns VCC = 4.5 V 0 to 500 VCC = 6 V 0 to 400 o M54/M74HC564/574 DC SPECIFICATIONS Test Conditions Symbol VIH V IL Parameter High Level Input Voltage Low Level Input Voltage Value VCC (V) TA = 25 oC 54HC and 74HC Min. Typ. Max. 2.0 1.5 1.5 1.5 4.5 6.0 3.15 4.2 3.15 4.2 3.15 4.2 High Level Output Voltage 0.5 0.5 0.5 4.5 1.35 1.35 1.35 2.0 4.5 6.0 4.5 VOL Low Level Output Voltage 6.0 2.0 4.5 6.0 4.5 6.0 II IOZ ICC Input Leakage Current 3 State Output Off State Current Quiescent Supply Current 1.8 1.8 Unit V 2.0 6.0 V OH -40 to 85 oC -55 to 125 oC 74HC 54HC Min. Max. Min. Max. V 1.8 1.9 2.0 1.9 1.9 VI = IO=-20 µA VIH or V IL IO=-6.0 mA 4.4 5.9 4.5 6.0 4.4 5.9 4.4 5.9 4.18 4.31 4.13 4.10 IO=-7.8 mA 5.68 5.8 0.0 5.63 5.60 V VI = IO= 20 µA VIH or V IL IO= 6.0 mA 0.1 0.1 0.1 0.0 0.1 0.1 0.1 0.0 0.17 0.1 0.26 0.1 0.33 0.1 0.40 IO= 7.8 mA 0.18 V 0.26 0.33 0.40 VI = VCC or GND ±0.1 ±1 ±1 µA VI = VIH or VIL VO = VCC or GND 6.0 VI = VCC or GND ±0.5 ±5.0 ±10 µA 4 40 80 µA 6.0 6.0 5/13 M54/M74HC564/574 AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = t f = 6 ns) Test Conditions o Symbol Parameter VCC (V) tTLH tTHL Output Transition Time 2.0 tPLH tPHL Propagation Delay Time (CLOCK - Q, Q) tPZL tPZH 3 State Output Enable Time tPLZ tPHZ 3 State Output Disable Time fMAX Maximum CLock Frequency tW(L) tW(H) Minimum Pulse Width (CLOCK) ts Minimum Set-up Time th Minimum Hold Time 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 50 50 150 50 RL = 1 KΩ 150 RL = 1 KΩ 50 RL = 1 KΩ 6.0 2.0 6.2 4.5 6.0 2.0 50 4.5 6.0 2.0 4.5 50 6.0 2.0 4.5 6.0 TA = 25 C 54HC and 74HC Min. Typ. Max. 25 60 CL (pF) 50 31 37 7 6 70 20 15 12 10 150 30 26 15 13 190 38 32 18 15 225 45 38 88 25 19 48 190 38 32 125 240 48 41 155 285 57 48 190 15 12 60 20 16 25 21 165 33 28 31 26 205 41 35 38 32 250 50 43 34 17 125 25 155 31 190 38 15 18 21 26 4.2 25 30 21 25 75 95 110 15 13 75 15 19 16 95 19 22 19 110 22 4 13 0 0 0 10 16 0 0 0 10 19 0 0 0 10 Input Capacitance 5 COUT Out put Capacitance Power Dissipation Capacitance 10 54 ns ns ns ns ns ns ns 6 6 25 6 50 Unit 32 5 75 90 15 CIN CPD (*) Value -40 to 85 oC -55 to 125 oC 74HC 54HC Min. Max. Min. Max. 75 90 ns ns ns pF pF pF (*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD •VCC •fIN + ICC 6/13 M54/M74HC564/574 SWITCHING CHARACTERISTICS TEST WAVEFORM tPLH, tPHL, ts, th, tw fMAX tPLZ, tPZL The 1KΩ load resistors should be connected between outputs and VCC line and the 50pF load capacitors should be connected between outputsand GND line. All inputs except OE input should be connected to VCC line or GND line such that outputs will be in low logic level while OE input is held low. tPHZ, tPZH The 1KΩ load resistors and the 50pF load capacitors should be connected between each output and GND line. All inputs except OE input should be connected to VCC or GND line such that output will be in high logic level while OE input is held low. 7/13 M54/M74HC564/574 TEST CIRCUIT ICC (Opr.) INPUT WAVEFORM IS THE SAME AS THAT IN CASE OF SWITCHING CHARACTERISTICS TEST. 8/13 M54/M74HC564/574 Plastic DIP20 (0.25) MECHANICAL DATA mm DIM. MIN. a1 0.254 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L Z 3.3 0.130 1.34 0.053 P001J 9/13 M54/M74HC564/574 Ceramic DIP20 MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 25 0.984 B 7.8 0.307 D E 3.3 0.5 e3 0.130 1.78 0.020 22.86 0.070 0.900 F 2.29 2.79 0.090 0.110 G 0.4 0.55 0.016 0.022 I 1.27 1.52 0.050 0.060 L 0.22 0.31 0.009 0.012 M 0.51 1.27 0.020 0.050 N1 P Q 4° (min.), 15° (max.) 7.9 8.13 5.71 0.311 0.320 0.225 P057H 10/13 M54/M74HC564/574 SO20 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 2.65 0.10 0.104 0.20 a2 MAX. 0.004 0.007 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C 0.50 0.020 c1 45° (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.299 L 0.50 1.27 0.19 0.050 M S 0.75 0.029 8° (max.) P013L 11/13 M54/M74HC564/574 PLCC20 MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 9.78 10.03 0.385 0.395 B 8.89 9.04 0.350 0.356 D 4.2 4.57 0.165 0.180 d1 2.54 0.100 d2 0.56 0.022 E 7.37 8.38 0.290 0.330 e 1.27 0.050 e3 5.08 0.200 F 0.38 0.015 G 0.101 0.004 M 1.27 0.050 M1 1.14 0.045 P027A 12/13 M54/M74HC564/574 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A 13/13