MK50H27 Signalling System 7 Link Controller SECTION 1 - FEATURES Complete Level 2 Implementation of SS7. Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols. Optional operation to comply with Japanese TTC JT-Q703 specification requirements Pin-for-pin and architecturally compatible with MK50H25 (X.25/LAPD), MK50H29 (SDLC), and MK50H28(Frame Relay). System clock rates up to 33 MHz (MK50H27 33), or 25 MHz (MK50H27 - 25). Data rate up to 4 Mbps continuous for SS7 protocol processing, 20 Mbps for transparent HDLC mode, or up to 51 Mbps bursted (gapped data clocks, non-continuous data). On chip DMA control with programmable burst length. DMA transfer rate of up to 13.3 Mbytes/sec using optional 5 SYSCLK DMA cycle (150 nS) at 33 MHz SYSCLK. Buffer Management includes: - Initialization Block - Separate Receive and Transmit Rings - Variable Descriptor Ring and Window Sizes. Selectable BEC or PCR retransmission methods, including forced retransmission for PCR. Handles all 7 SS7 Timers, plus the additional Signal Unit interval timers for Japanese SS7. Handles all SS7 frame formatting: - Zero bit insert and delete - FCS generation and detection - Frame delimiting with flags Programmable minimum Signal Unit spacing (number of flags between SU’s) Handles all sequencing and link control. Selectable FCS of 16 or 32 bits. Testing Facilities: - Internal Loopback - Silent Loopback - Optional Internal Data Clock Generation - Self Test. Programmable for full or half duplex operation Programmable Watchdog Timers for RCLK and TCLK (to detect absence of data clocks) September 1997 DIP48 PLCC 52 Available in 52 pin PLCC, 84 pin PLCC(for use with external ROM), or 48 pin DIP packages. SECTION 2 - INTRODUCTION The SGS - Thomson SS7 Signalling Link Controller (MK50H27) is a VLSI semiconductor device which provides a complete level 2 data communication control conforming to the CCITT, ANSI, BELLCORE, and AT&T versions of SS7, as well as options to allow conformance to TTC JT-Q703 (Japanese SS7). This includes signal unit formatting, transparency (so-called ”bit-stuffing”), error recovery by two types of retransmission, error monitoring, sequence number control, link status control, and fill in signal unit generation. One of the outstanding features of the MK50H27 is its buffer management which includes on-chip DMA. This feature allows users to handle multiple MSU’s of receive and transmit data at a time. (A conventional data link control chip plus a separate DMA chip would handle data for only a single block at a time.) The MK50H27 will move multiple blocks of receive and transmit data directly into 1/56 MK50H27 INTRODUCTION (Continued) and out of memory through the Host’s bus. A possible system configuration for the MK50H27 is shown in figure 1. For added flexibility a transparent mode provides an HDLC transport mechanism without link layer support. In this mode no protocol processing is done, all data received between opening flag and CRC is written to the shared memory buffer and it is up to the user to take care of the upper level software. The MK50H27 may be used with any of several popular microprocessors, such as: 68040 ... 68000, 6800, Z8000, Z80, 80486 ... 8086, i960, etc. The MK50H27 may be operated in either full or half duplex mode. In half duplex mode, the RTS and CTS modem control pins are provided. In full duplex mode, these pins become user programmable I/O pins. All signal pins on the MK50H27 are TTL compatible. This has the advantage of making the MK50H27 independent of the physical interface. As shown in figure 1, line drivers and receivers are used for electrical connection to the physical layer. DIP48 PIN CONNECTION (Top view) 1 48 VCC (+5V) DAL07 2 47 DAL08 DAL06 3 46 DAL09 DAL05 4 45 DAL10 DAL04 5 44 DAL11 DAL03 6 43 DAL12 DAL02 7 42 DAL13 DAL01 8 41 DAL14 DAL00 9 M 40 DAL15 READ 10 K 39 A16 INTR 11 38 A17 DALI 12 37 A18 DALO 13 0 36 A19 DAS 14 H 35 A20 34 A21 33 A22 32 A23 VSS-GND BMO, BYTE, BUSREL BMI, BUSAKO 16 HOLD, BUSRQ 17 2 7 ALE, AS 18 31 RD HLDA 19 30 DSR, CTS CS 20 29 TD ADR 21 28 SYSCLK READY 22 27 RCLK RESET 23 26 DTR, RTS 24 25 TCLK VSS-GND 2/56 15 5 MK50H27 No Connect DAL03 DAL04 DAL05 DAL06 DAL07 VSS VCC DAL08 DAL09 DAL10 DAL11 DAL12 PLCC52 PIN CONNECTION (Top view) DAL02 DAL01 DAL00 READ INTR DALI DALO 8 7 1 52 47 46 MK50H27Q DAS 20 21 34 TCLK DTR/RTS RCLK SYSCLK TD DSR/CTS VSS(GND) No Connect RESET 33 ADR READY HLDA CS BMO/BYTE/BUSREL No Connect BM1/BUSAKO HOLD/BUSRQ ALE/AS DAL13 DAL14 DAL15 A16 A17 A18 A19 A20 A21 A22 No Connect A23 RD 3/56 MK50H27 TAble 1 - PIN DESCRIPTION LEGEND: I Input only IO Input / Output OD Open Drain (no internal pull-up) Note: O 3S Output only 3-State Pin out for 52 pin PLCC is shown in brackets. SIGNAL NAME PIN(S) TYPE DESCRIPTION DAL<15:00> 2-9 40-47 [2-10 44-51] IO/3S The time multiplexed Data/Address bus. During the address portion of a memory transfer, DAL<15:00> contains the lower 16 bits of the memory address. During the data portion of a memory transfer, DAL<15:00> contains the read or write data, depending on the type of transfer. READ 10 [11] IO/3S READ indicates the type of operation that the bus controller is performing during a bus transaction. READ is driven by the MK50H27 only while it is the BUS MASTER. READ is valid during the entire bus transaction and is tristated at all other times. MK50H27 as a Bus Slave : READ = HIGH - Data is placed on the DAL lines by the chip. READ = LOW - Data is taken off the DAL lines by the chip. MK50H27 as a Bus Master : READ = HIGH - Data is taken off the DAL lines by the chip. READ = LOW - Data is placed on the DAL lines by the chip. INTR 11 [12] O/OD INTERRUPT is an attention interrupt line that indicates that one or more of the following CSR0 status flags is set: MISS, MERR, RINT, TINT or PINT. INTERRUPT is enabled by CSR0<09>, INEA=1. DALI 12 [13] O/3S DAL IN is an external bus transceiver control line. DALI is driven by the MK50H27 only while it is the BUS MASTER. DALI is asserted by the MK50H27 when it reads from the DAL lines during the data portion of a READ transfer. DALI is not asserted during a WRITE transfer. DALO 13 [14] O/3S DAL OUT is an external bus transceiver control line. DALO is driven by the MK50H27 only while it is the BUS MASTER. DALO is asserted by the MK50H27 when it drives the DAL lines during the address portion of a READ transfer or for the duration of a WRITE transfer. DAS 14 [15] IO/3S DATA STROBE defines the data portion of a bus transaction. By definition, data is stable and valid at the low to high transition of DAS. This signal is driven by the MK50H27 while it is the BUS MASTER. During the BUS SLAVE operation, this pin is used as an input. At all other times the signal is tristated. BMO BYTE BUSREL 15 [16] IO/3S I/O pins 15 and 16 are programmable through CSR4. If bit 06 of CSR4 is set to a one, pin 15 becomes input BUSREL and is used by the host to signal the MK50H27 to terminate a DMA burst after the current bus transfer has completed. If bit 06 is clear then pin 15 is an output and behaves as described below for pin 16. BM1 BUSAKO 16 [18] O/3S Pins 15 and 16 are programmable through bit 00 of CSR4 (BCON). If CSR4<00> BCON = 0, I/O PIN 15 = BMO (O/3S) I/O PIN 16 = BM1 (O/3S) BYTE MASK<1:0> Indicates the byte(s) on the DAL to be read or written during this bus transaction. MK50H27 drives these lines only as a Bus Master. MK50H27 ignores the BM lines when it is a Bus Slave. Byte selection is done as outlined in the following table. BM1 BM0 TYPE OF TRANSFER LOW LOW ENTIRE WORD LOW HIGH UPPER BYTE (DAL<15:08>) HIGH LOW LOWER BYTE (DAL<07:00>) HIGH HIGH NONE 4/56 MK50H27 Table 1: PIN DESCRIPTION (continued) SIGNAL NAME PIN(S) TYPE DESCRIPTION If CSR4<00> BCON = 1, I/O PIN 15 = BYTE (O/3S) I/O PIN 16 = BUSAKO (O) Byte selection is done using the BYTE line and DAL<00> latched during the address portion of the bus transaction. MK50H27 drives BYTE only as a Bus Master and ignores it when a Bus Slave. Byte selection is done as outlined in the following table. BYTE DAL<00> TYPE OF TRANSFER LOW LOW ENTIRE WORD LOW HIGH ILLEGAL CONDITION HIGH LOW LOWER BYTE HIGH HIGH UPPER BYTE BUSAKO is a bus request daisy chain output. If MK50H27 is not requesting the bus and it receives HLDA, BUSAKO will be driven low. If MK50H27 is requesting the bus when it receives HLDA, BUSAKO will remain high Note: All transfers are entire word unless the MK50H27 is configured for 8 bit operation. HOLD BUSRQ 17 [19] IO/OD Pin 17 is configured through bit 0 of CSR4. If CSR4<00> BCON = 0, I/O PIN 17 = HOLD HOLD request is asserted by MK50H27 when it requires a DMA cycle, if HLDA is inactive, regardless of the previous state of the HOLD pin. HOLD is held low for the entire ensuing bus transaction. If CSR4<00> BCON = 1, I/O PIN 17 = BUSRQ BUSRQ is asserted by MK50H27 when it requires a DMA cycle if the prior state of the BUSRQ pin was high and HLDA is inactive. BUSRQ is held low for the entire ensuing bus transaction. ALE AS 18 [20] O/3S The active level of ADDRESS STROBE is programmable through CSR4. The address portion of a bus transfer occurs while this signal is at its asserted level. This signal is driven by MK50H27 while it is the BUS MASTER. At all other times, the signal is tristated. If CSR4<01> ACON = 0, I/O PIN 18 = ALE ADDRESS LATCH ENABLE is used to demultiplex the DAL lines and define the address portion of the transfer. As ALE, the signal transitions from high to low during the address portion of the transfer and remains low during the data portion. If CSR4<01> ACON = 1, I/O PIN 18 = AS As AS, the signal pulses low during the address portion of the bus transfer. The low to high transition of AS can be used by a slave device to strobe the address into a register. AS is effectively the inversion of ALE. HLDA 19 [21] I HOLD ACKNOWLEDGE is the response to HOLD. When HLDA is low in response to MK50H27’s assertion of HOLD, the MK50H27 is the Bus Master. HLDA should be deasserted ONLY after HOLD has been released by the MK50H27. CS 20 [22] I CHIP SELECT indicates, when low, that the MK50H27 is the slave device for the data transfer. CS must be valid throughout the entire transaction. ADR 21 [23] I ADDRESS selects the Register Address Port or the Register Data Port. It must be valid throughout the data portion of the transfer and is only used by the chip when CS is low. ADR PORT LOW REGISTER DATA PORT HIGH REGISTER ADDRESS PORT READY 22 [24] IO/OD When the MK50H27 is a Bus Master, READY is an asynchronous acknowledgement from the bus memory that memory will accept data in a WRITE cycle or that memory has put data on the DAL lines in a READ cycle. 5/56 MK50H27 Table 1: PIN DESCRIPTION (continued) SIGNAL NAME PIN(S) TYPE DESCRIPTION As a Bus Slave, the MK50H27 asserts READY when it has put data on the DAL lines during a READ cycle or is about to take data from the DAL lines during a WRITE cycle. READY is a response to DAS and it will be released after DAS or CS is negated. RESET 23 [25] I RESET is the Bus signal that will cause MK50H27 to cease operation, clear its internal logic and enter an idle state with the Stop bit of CSR0 set. TCLK 25 [28] I TRANSMIT CLOCK. A 1x clock input for transmitter timing. TD changes on the falling edge of TCLK. The frequency of TCLK may not be greater than the frequency of SYSCL DTR RTS 26 [29] IO RCLK 27 [30] I RECEIVE CLOCK. A 1x clock input for receiver timing. RD is sampled on the rising edge of RCLK. The frequency of RCLK may not be greater than the frequency of SYSCLK. SYSCLK 28 [31] I SYSTEM CLOCK. System clock used for internal timing of the MK50H27. SYSCLK should be a square wave, of frequency up to 33 MHz. TD 29 [32] O TRANSMIT DATA. Transmit serial data output. DSR CTS 30 [33] IO DATA SET READY, CLEAR TO SEND. Modem Control Pin. Pin 30 is configurable through CSR5. This pin can be programmed to behave as input CTS or as programmable IO pin DSR. If configured as CTS, the MK50H27 will transmit all ones while CTS is high. RD 31 [34] I A<23:16> 32-39 [37-43] O/3S VSS-GND 1,24 [1,26] VCC 48 [52] DATA TERMINAL READY, REQUEST TO SEND. Modem control pin. Pin 26 is configurable through CSR5. This pin can be programmed to behave as output RTS or as programmable IO pin DTR. If configured as RTS, the MK50H27 will assert this pin if it has data to send and throughout the transmission of a signal unit. RECEIVE DATA. Received serial data input. Address bits <23:16> used in conjunction with DAL<15:00> to produce a 24 bit address. MK50H27 drives these lines only as a Bus Master. A23-A20 may be driven continuously as described in the CSR4<7> BAE bit. Ground Pins Power Supply Pin +5.0 VDC + 5% SECTION 3 OPERATIONAL DESCRIPTION The SGS-Thomson MK50H27 Multi-Logical Link Communications Controller device is a VLSI product intended for high performance data communication applications requiring SDLC link level control. The MK50H27 will perform all frame formatting, such as: frame delimiting with flags, FCS (CRC) generation and detection, and zero bit insertion and deletion for transparency. The MK50H27 also handles all supervisory (S) and unnumbered (U) frames (see Tables A & B). The MK50H27 also includes a buffer management mechanism that allows the user to transmit and/or receive multiple frames for each active channel or DLCI. Contained in the buffer management is an on-chip dual channel DMA: one channel for receive and one channel for transmit. 6/56 The MK50H27 can be used with any popular 16 or 8 bit microprocessor. A possible system configuration for the MK50H27 is shown in Figure 1. This document assumes that the processor has a byte addressable memory organization. The MK50H27 will move multiple blocks of receive and transmit data directly in and out of memory through the Host’s bus. The MK50H27 may be operated in full or half duplex mode. In half duplex mode the RTS and CTS modem control pins are provided. In full duplex mode, these pins become user programmable I/O pins. All signal pins on the MK50H27 are TTL compatible. This has the advantage of making the MK50H27 independent of the physical interface. As shown in Fig. 1, line drivers and receivers are used for electrical connection to the physical layer. MK50H27 Figure 1: Possible System Configuration for thr MK50H27 HOST PROCESSOR (68020, i960, Z8000, ETC) MEMORY (MULTIPLE DATA BLOCKS) 16-BIT DATA BUS INCLUDING 24-BIT ADDRESS AND BUS CONTROL TD TCLK RD RCLK DSR, CTS DTR, RTS MK50H27 LINE DRIVERS AND RECEIVERS ELECTRICAL I/O (SUCH AS RS-232C, RS-423, RS-422) DATA COMM. CONNECTOR (SUCH AS RS-449, RS-232C, V.35) 7/56 MK50H27 INTR DSR, CTS ADR DTR, RTS CS BM0 BM1 ALE, AS HOLD HLDA DALI DALO A <23:16> DAL <15:00> Figure 2: MK50H27 Simplified Block Diagram READY READ DAS FIRMWARE ROM CONTROL / STATUS REGISTERS 0 - 5 DMA CONTROLLER MICRO CONTROLLER SYSCLK INTERNAL BUS TRANSMITTER FIFO RECEIVER FIFO VCC VSS - GND RESET RCLK RECEIVER TRANSMITTER RD TD LOOPBACK TEST 8/56 TCLK TIMERS MK50H27 3.1 Functional Blocks Refer to the block diagram in Figure 2. The MK50H27 is primarily initialized and controlled through six 16-bit Control and Status Registers (CSR0 thru CSR5). The CSR’s are accessed through two bus addressable ports, the Register Address Port (RAP), and the Register Data Port (RDP). The MK50H27 may also generate an interrupt(s) to the Host. These interrupts are enabled and disabled through CSR0. The on-chip microcontroller is used to control the movement of parallel receive and transmit data, and to handle the Address field filtering. 3.1.4 Check Bit Sequence or Cyclic Redundancy Check The CK (CRC) on the transmitter or receiver may be either 16 bit or 32 bit, and is user selectable. For full duplex operation, both the receiver and transmitter have individual CK computation circuits. The characteristics of the CK are: Transmitted Polarity: Inverted Transmitted Order: High Order Bit First Pre-set Value: All 1’s Polynomial 16 bit: X16 + X12 + X5 + 1 3.1.1 Microcontroller The microcontroller controls all of the other blocks of the MK50H27. The microcontroller performs frame processing and protocol processing. All primitive processing and generation is also done here. The microcode ROM contains the control program of the microcontroller. Remainder 16 bit (if received correctly): High order bit-->0001 1101 0000 1111 Polynomial 32 bit: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 Remainder 32 bit (if received correctly): high order bit--> 1100 0111 0000 0100 1101 1101 0111 1011 3.1.2 Receiver Serial receive data comes into the Receiver (Figure 2). The Receiver is responsible for: 1. Leading and trailing flag detection. 2. Deletion of zeroes inserted for transparency. 3. Detection of idle and abort sequences. 4. Detection of good & bad CK (ChecK bit seq.) 5. Monitoring Receiver FIFO status. 6. Detection of Receiver Over-Run. 7. Odd byte detection. NOTE: If frames are received that have an odd number of bytes then the last byte of the frame is said to be an odd byte. 8. Detection of non-octet aligned frames. Such frames are treated as invalid. 3.1.3 Transmitter The Transmitter is responsible for: 1. Serialization of outgoing data. 2. Generating and appending the CK (CRC). 3. Framing outgoing frame with flags. 4. Zero bit insertion for transparency. 5. Transmitter Under-Run detection. 6. Transmission of odd byte. 7. RTS/CTS control. 3.1.5 Receive FIFO The Receive FIFO buffers the data received by the receiver. This performs two major functions. First, it resynchronizes the data from the receive clock to the system clock. Second, it allows the microcontroller time to finish whatever it may be doing before it has to process the received data. The receive FIFO holds the data from the receiver without interrupting the microcontroller for service until it contains enough data to reach the watermark level, or an end of frame is received. This watermark level can be programmed in CSR4 (FWM) to occur when the FIFO contains at least 18 or more bytes; 34 or more bytes; or 50 or more bytes. This programmability , along with the programmable burst length of the DMA controller, enables the user to define how often and for how long the MK50H27 must use the host bus. For more information, see CSR4. For example, if the watermark level is set at 34 bytes and the burst length is limited to 8 word transfers at a time, the MK50H27 will request control of the host bus as soon as 34 bytes are received and again after every 16 subsequent bytes. 3.1.6 Transmit FIFO The Transmit FIFO buffers the data to be transmitted by the MK50H27. This also performs two major functions. First, it resynchronizes the data from the system clock to the transmit clock. Second, it allows the microcontroller and DMA controller to burst read data from the host’s memory buffers; making both the MK50H27 and the host bus more efficient. 9/56 MK50H27 The transmit FIFO has a watermark scheme similar to the one described for the receive FIFO above, and uses the same FWM value selections in CSR4 for the watermark. Once filled to within FWM of being full (by DMA from TX buffer in shared memory), the transmit FIFO will not interrupt the microcontroller until it empties enough to fall below the watermark level. 3.1.7 DMA Controller The MK50H27 has an on-chip DMA Controller circuit. This allows it to access memory without requiring host software intervention. Whenever the MK50H27 requires access to the host memory it will negotiate for mastership of the bus. Upon gaining control of the bus the MK50H27 will begin transferring data to or from memory. The MK50H27 will perform memory transfers until either it has nothing more to transfer, it has reached its DMA burst limit (user programmable), or the BUSREL pin is driven low. In any case, it will complete all bus transfers before releasing bus mastership back to the host. If during a memory transfer, the memory does not respond within 256 SCLK cycles, the MK50H27 will release ownership of the bus immediately and the MERR bit will be set in CSR0. The DMA burst limit can be programmed by the user through CSR4. In 16 bit mode the limit can be set to 1 word, 8 words, or unlimited word transfers. In 8 bit mode,it can be set to 2 bytes, 16 bytes, or unlimited byte transfers. For high speed data lines (i.e. > 1 Mbps) a burst limit of 8 words or 16 bytes is suggested to allow maximum throughput. The byte ordering of the DMA transfers can be programmed to account for differences in processor architectures or host programming languages. Byte ordering can be programmed separately for data and control information. Data information is defined as all contents of data buffers; control information is defined as anything else in the shared memory space (i.e. initialization block, descriptors, etc). For more information see section 4.1.2.5 on control status register 4. 3.1.8 Bus Slave Circuitry The MK50H27 contains a bank of internal control/status registers (CSR0-5) which can be accessed by the host as a peripheral. The host can read or write to these registers like any other bus slave. The contents of these registers are listed in Section 4 and bus signal timing is described in Figures 9 and 10. 3.2 Buffer Management Overview Refer to Fig. 3. 10/56 3.2.1 Initalization Block Chip initialization information is located in a block of memory called the Initialization Block. The Initialization Block consists of 200 contiguous words of memory starting on a word boundary. This memory is assembled by the HOST, and is accessed by the MK50H27 during initialization. The Initialization Block is comprised of: A. Mode of Operation. B. Counter/Timer Preset Values. C. Protocol Parameters or Options D. Location and size of Receive and Transmit Descriptor Rings. E. Optional Transmit Window SIze Value F. Location of Status Buffer. G. Optional JT-Q703 Signal Unit Interval Timer Values H. Statistics and Error Counters. 3.2.2 The Circular Queue The basic organization of the buffer management is a circular queue of tasks in memory called descriptor rings. There are separate rings to describe the transmit and receive operations. Up to 128 buffers may be queued-up on a descriptor ring awaiting execution by the MK50H27. The descriptor ring has a descriptor assigned to each buffer. Each descriptor holds a pointer for the starting address of the buffer, and holds a value for the length of the buffer in bytes. Each descriptor also contains two control bits called OWNA and OWNB, which denote whether the MK50H27, the HOST, or an I/O ACCELERATION PROCESSOR ( if present ) ”owns” the buffer. For transmit, when the MK50H27 owns the buffer, the MK50H27 is allowed and commanded to transmit the buffer. When the MK50H27 does not own the buffer, it will not transmit that buffer. For receive, when the MK50H27 owns a buffer, it may place received data into that buffer. Conversely, when the MK50H27 does not own a receive buffer, it will not place received data into that buffer. The MK50H27 buffer management mechanism will handle frames which are longer than the length of an individual buffer. This is done by a chaining method which utilizes multiple buffers. The MK50H27 tests the next descriptor in the descriptor ring in a ”look ahead” manner. If the frame is too long for one buffer, the next buffer will be used after filling the first buffer; that is, ”chained”. The MK50H27 will then ”look ahead” to the next buffer, and chain that buffer if necessary, and so on.The operational parameters for the buffer management are defined by the user in the initialization block. The parameters defined include the basic mode of operation, protocol options, the number of entries for the transmitter MK50H27 and receiver descriptor rings, etc. The starting address for the Initialization block, IADR, is defined in the CSR2 and CSR3 registers inside the MK50H27. 3.2.3 Signal Unit Repertoire The frame format supported by the MK50H27 is shown in Table A. Each signal unit (SU) may consist of a programmable number of leading flag patterns (01111110), Backward Sequence Number, Backward Indicator Bit, Forward Sequence Number, Forward Indicator Bit, Lenght Indicator Field, followed by Signalling Information Octet, Service Information Field, or Status Field, depending on SU type, and then ended with a CK (CRC) of either 16 or 32 bits, and a trailing flag pattern. The number of leading flags transmitted is programmable through the Mode Register in the Initialization Block. Received signal units may have as few as one flag between adjacent signal units The symbols and definitions for the signal unit types handled by the MK50H27 are: NAME DEFINITION MSU Message Signal Unit LSSU Link Status Signal Unit FISU Fill In Signal Unit F Flag Sequence (01111110) FSN Forward Sequence Number BSN Backward Sequence Number FIB Forward Indicator Bit BIB Backward Indicator Bit LI Lenght Indicator X Reserved - programmed as zeroes PRI Priority Indication (JT-Q703 only) SIO Signalling Information Octe SIF Service Information Field SF Status Field CK Check bit Sequence (CRC) TABLE A - MK50H27 Signal Unit Repertoire 11/56 MK50H27 TABLE A - MK50H27 Signal Unit Repertoire Message Signal Unit (MSU) F CK 8 16/32 SIF SIO X LI FIB 8 2 6 1 8n,n>=2 FSN 7 BIB BSN F 1 7 8 Link Status Signal Unit (LSSU) F CK SF X LI FIB FSN BIB BSN 8 16/32 8/16 2 6 1 7 1 7 F 8 Values for SF: 0 - SIO, Out of alignment 3 - SIOS, Out-of-service 1 - SIN, Normal alignment 4 - SIPO, Processor outage 2 - SIE, Emergency 5 - SIB, Congestion (Busy) Fill-in Signal Unit (FISU) F CK X LI FIB FSN 8 16/32 2 6 1 7 BIB 1 BSN 7 Right-most fields are transmitted first 12/56 F 8 MK50H27 Figure 3: MK50H27 Memory Management Structure RECEIVE BUFFER CSR 2, CSR3 POINTER TO RECEIVER DESCRIPTOR RINGS BUFFER 0 INITIALIZAT ION BLOCK DESCRIPTOR 0 BUFFER STATUS BUFFER ADDRESS BUFFER SIZE BUFFER 1 BUFFER MSG COUNT DESCRIPTOR 1 INITIALIZAT ION BLOCK BUFFER M MODE TIMER VALUES DESCRIPTOR M PROTOCOL PARAMETERS RX DESCRIPTOR POINTER TRANSMIT DESCRIPTOR RINGS TX DESCRIPTOR POINTER STATUS DESCRIPTOR 0 BUFFER STATUS TRANSMIT BUFFER BUFFER 0 BUFFER ADDRESS BUFFER ADDRES S BUFFER SIZE STATISTIC S BUFFER MSG COUNT BUFFER 1 DESCRIPTOR 1 STATUS BUFFER BUFFER N DESCRIPTOR N 13/56 MK50H27 SECTION 4 PROGRAMMING SPECIFICATION This section defines the Control and Status Registers and the memory data structures required to program the MK50H27. 4.1 Control and Status Registers There are six Control and Status Registers (CSR’s) resident within the MK50H27. The CSR’s are accessed through two bus addressable ports, an address port (RAP), and a data port (RDP), thus requiring only two locations in the system memory or I/O map. 4.1.1 Accessingthe Control & Status Registers The CSR’s are read (or written) in a two step operation. The address of the CSR is written into the address port (RAP) during a bus slave transaction. During a subsequent bus slave transaction, the data being read from (or written into) the data port (RDP) is read from (or written into) the CSR selected in the RAP. Once written, the address in RAP remains unchanged until rewritten or upon a bus reset. A control I/O pin (ADR) is provided to distinguish the address port from the data port. ADR L H Port Register Data Port (RDP) Register Address Port (RAP) 4.1.1.1 Register Address Port (RAP) 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 0 0 0 0 0 0 0 B M 8 0 0 0 0 3 0 2 CSR <2:0> 0 1 0 0 H B Y T E BIT NAME 15:08 RESERVED 07 BM8 06:04 RESERVED 03:01 CS3<2:0> CSR address select bits. READ/WRITE. Selects the CSR to be accessed through the RDP. RAP is cleared by Bus RESET. CSR<2:0> CSR 0 CSR0 1 CSR1 2 CSR2 3 CSR3 4 CSR4 5 CSR5 00 HBYTE Determines which byte is addressed for 8 bit mode. If set, the high byte of the register referred to by CSR<2:0> is addressed, otherwise the low byte is addressed. This bit is only meaningful in 8 bit mode and must be written as zero if BM8=0. HBYTE is READ/WRITE and cleared on bus reset. 14/56 DESCRIPTION Must be written as zeroes When set, places chip into 8 bit mode. CSR’s, Init Block, and data transfers are all 8 bit transfers; this provides compatibility with 8 bitmicroprocessors. When clear, all transfers are 16 bit transfers. This bit must be set to the same value each time it is written, changing this bit during normal operation will achieve unexpected results. BM8 is READ/WRITE and cleared on Bus RESET. Must be written as zeroes MK50H27 4.1.1.2 Register Data Port (RDP) 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 CSR 0 6 0 5 0 4 0 3 0 2 0 1 0 0 DATA BIT NAME DESCRIPTION 15:00 CSR DATA Writing data to the RDP loads data into the CSR selected by RAP. Reading the data from RDP reads the data from the CSR selected in RAP. 4.1.2 Control and Status Register Definition 4.1.2.1 Control and Status Register 0 (CSR0) RAP<3:1> = 0 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 T D M D P O F F D T X D R X T X O N R X O N I N E A I N T R M E R R M I S S R O R T U R P I N T T I N T R I N T 0 BIT 15 NAME TDMD 14 POFF 13 DTX DESCRIPTION TRANSMIT DEMAND, when set, causes MK50H27 to access the Transmit Descriptor Ring without waiting for the transmit polltime interval to elapse. TDMD need not be set to transmit a MSU, it merely hastens MK50H27’s response to a Transmit Descriptor Ring entry insertion by the host. TDMD is Write With ONE ONLY and cleared by the microcode after it is used. It may read as a ”1” for a short time after it is written because the microcode may have been busy when TDMD was set. It is also cleared by Bus RESET. Writing a ”0” in this bit has no effect. POFF, when set, indicates that MK50H27 is operating in the Power Off phase of operation. All external activity is disabled and internal logic is reset. MK50H27 remains inactive except for primitive processing until a Power On primitive is issued. POFF IS READ ONLY and set by Bus RESET or a Power Off primitive. Writing to this bit has no effect. Transmitter ring disable prevents the MK50H27 from further access to the Transmitter Descriptor Ring and terminates transmitter polling. No transmissions are attempted after finishing transmission of any signal unit in transmission at the time of DTX being set. TXON acknowledges changes to DTX, see below. DTX is READ/WRITE. 15/56 MK50H27 4.1.2.1 Control and Status Register 0 (CSR0) BIT 12 NAME DRX 11 TXON 10 RXON 09 INEA 08 INTR 07 MERR 06 MISS 05 ROR 16/56 DESCRIPTION Disable the Receiver prevents the MK50H27 from further access to the Receiver Descriptor Ring. No received signal units are accepted after finishing reception of any signal unit in reception at the time of DRX being set. RXON acknowledges changes to DRX, see below. DRX is READ/WRITE. TRANSMITTER ON indicates that the transmit ring access is enabled. TXON is set as the Power On primitive is issued if the DTX bit is ”0” or afterward as DTX is cleared. TXON is cleared upon recognition of DTX being set, by sending a Power Off primitive in CSR1, or by a Bus RESET. If TXON is clear, the host may modify the Transmit Descriptor Ring entries regardless of the state of the OWNA bits. TXON is READ ONLY; writing to this bit has no effect. RECEIVER ON indicates that the receive ring access is enabled. RXON is set as the Power On primitive is issued if DRX=0, or afterward as DRX is cleared. RXON is cleared upon recognition of DRX being set, by sending a Power Off primitive in CSR1, or by a Bus RESET. RXON is READ ONLY; writing to this bit has no effect. INTERRUPT ENABLE allows the INTR I/O pin to be driven low when the Interrupt Flag is set. If INEA = 1 and INTR = 1 the INTR I/O pin will be low. If INEA = 0 the INTR I/O pin will be high, regardless of the state of the Interrupt Flag. INEA is READ/WRITE set by writing a ”1” into this bit and is cleared by writing a ”0” into this bit, by Bus RESET, or while in the Power Off phase. INEA may not be set while in the Power Off phase. INTERRUPT FLAG indicates that one or more of the following interrupt causing conditions has occurred: MISS, MERR, RINT, TINT, PINT. If INEA = 1 and INTR = 1 the INTR I/O pin will be low. INTR is READ ONLY, writing this bit has no effect. INTR is cleared as the specific interrupting condition bits are cleared. INTR is also cleared by Bus RESET or by issuing a Power Off primitive. MEMORY ERROR is set when the MK50H27 is the Bus Master and READY has not been asserted within 256 SYSCLKs (25.6 usec @ 10MHz) after asserting the address on theDAL lines. When a Memory Error is detected, the MK50H27 releases the bus, the receiver and transmitter are turned off, and an interrupt is generated if INEA = 1. MERR is READ/CLEAR ONLY and is set by the chip and cleared by writing a ”1” into the bit. Writing a ”0” has no effect. It is cleared by Bus RESET or by issuing a Power Off primitive. MISSED MSU is set when the receiver loses a MSU because it does not own a receive buffer indicating loss of data. When MISS is set, an interrupt will be generated if INEA = 1. MISS is READ/CLEAR ONLY and is set by MK50H27 and cleared by writing a ”1” into the bit. Writing a ”0” has no effect. It is also cleared by Bus RESET or by issuing a Power Off primitive. RECEIVER OVERRUN indicates that the Receiver FIFO was full When the receiver was ready to input data to the Receiver FIFO. The signal unit being received is lost but is recoverable according to the Link Level protocol. When ROR is set, an interrupt is generated if INEA = 1. ROR is READ/CLEAR ONLY and is set by MK50H27 and cleared by writing a ”1” into the bit. Writing a ”0” has no effect. It is also cleared by Bus RESET or by issuing a Power Off primitive. MK50H27 04 TUR 03 PINT 02 TINT 01 RINT 00 0 TRANSMITTER UNDERRUN indicates that the MK50H27 has aborted a signal unit since data was late from memory. This condition is reached when the transmitter and transmitter FIFO both become empty while transmitting a signal unit. When TUR is set, an interrupt is generated if INEA = 1. TUR is READ/CLEAR ONLY and is set by MK50H27 and cleared by writing a ”1” into the bit. Writing a ”0” has no effect. It is also cleared by RESET or by issuing a Power Off primitive. PRIMITIVE INTERRUPT is set after the chip updates the primitive register to issue a provider primitive. When PINT is set, an interrupt is generated if INEA =1. PINT is READ/CLEAR ONLY and is set by MK50H27 and cleared by writing a ”1” into the bit. Writing a ”0” has no effect. It is also cleared by RESET or by issuing a Power Off primitive. TRANSMITTER INTERRUPT is set after the chip updates an entry in the Transmit Descriptor Ring. When TINT is set, an interrupt is generated if INEA =1. TINT is READ/CLEAR ONLY and is set by MK50H27 and cleared by writing a ”1” into the bit. Writing a ”0” has no effect. It is also cleared by RESET or by issuing a PowerOff primitive. RECEIVER INTERRUPT is set after the MK50H27 updates an entry in the Receive Descriptor Ring. When RINT is set, an interrupt is generated if INEA =1. RINT is READ/CLEAR ONLY and is set by MK50H27 and cleared by writing a ”1” into the bit. Writing a ”0” has no effect. It is cleared by Bus RESET or by issuing a Power Off primitive. This bit is READ ONLY and will always read as a zero. 4.1.2.2 Control and Status Register 1 (CSR1) 1 5 1 4 U E R R U A V RAP <3:1> = 1 BIT NAME 15 UERR 14 UAV 13:08 UPRIM 0 1 1 3 1 2 1 1 1 0 UPRIM <5:0> 0 9 0 8 0 7 0 6 P L O S T P A V 0 5 0 4 0 3 0 2 0 1 0 0 PPRIM <5:0> DESCRIPTION USER PRIMITIVE ERROR is set by the MK50H27 when a primitive is issued by the user which is in conflict with the current status of the link. UERR is READ/CLEAR ONLY and is set by MK50H27 and cleared by writing a ”1” into the bit. Writing a ”0” in this bit has no effect. It is also cleared by Bus RESET. USER PRIMITIVE AVAILABLE is set by the user when a primitive is written into UPRIM. It is cleared by the MK50H27 after the primitive has been processed. This bit is also cleared by a Bus RESET. USER PRIMITIVE is written by the user, in conjunction with setting UAV, to control the MK50H27 link procedures. The following primitives are available: Power Off: causes the MK50H27 to enter the Power Off state. All DMA activity ceases, the transmitter transmits all ones, and all received data is ignored. Valid in all states except Power Off. Power On: valid only in the Power Off phase and must be issued after the Init primitive and prior to the Start primitive. Causes the MK50H27 to exit the Power Off phase and to enter the Out of Service phase and 17/56 MK50H27 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18/56 to continuouslytransmit SIOS signal units. Init: instructs the MK50H27 to read the initialization block from memory. Valid only in the Power Off mode. Trans: instructs the MK50H27 to enter the HDLC Transparent phase of operation. Data frames are transmitted and received out of the descriptor rings but no protocol processing is done. Address and Control fields are not prepended to the frames, but CK processing works normally. HDLC Transparent Mode may be exited only with a Power Off primitive or by a bus RESET. Valid only in the Power Off phase. Status Request: instructs the MK50H27 to write the current link status into the STATUS BUFFER. Valid in all states, but only after the Init primitive has been previously issued. Self-Test Request: instructs the MK50H27 to perform the built in internal self test. Valid only in the Power Off phase. See section 4.4.8 for the self test procedure. Stop: forces all DMA activity to cease. Causes the MK50H27 to enter the Out of Service phase and to continuously transmit SIOS signal units. Valid in all phases except the Power Off and Out of Service phase. Start: initial alignment begins and the descriptor rings are reset. Start should only be issued when in the Out of Service phase, after the initialization block has been read. Local Processor Outage: issued to the MK50H27 to indicate that level 3 or higher levels cannot accept signalling messages. All subsequent MSU’s are ignored by the MK50H27 & SIPO signal units are transmitted. Local Processor Recovered: indicates end of Local Processor Outage condition. The MK50H27 may resume transmitting FISUs and MSUs. Emergency: indicates that the emergency proving period is to be used for initial alignment. Emergency Ceases: Indicates that the normal proving period is to be used for initial alignment (this is the default proving period). Retrieve BSNT: causes the entire STATUS BUFFER to be updated including the last transmitted Backward Sequence Number (BSNT). When completed, PPRIM 18 will be issued. Retrieval request and FSNC: indicates that the FSNC has been written to the Status Buffer and requests the MK50H27 to update the retransmission buffer. The MK50H27 should then place the updated retransmission index into the Status Buffer. Congestion: causes the MK50H27 to enter a congestion state and send SIB signal units at T5 timer interval. It is recommended that the DRX bit in CSR0 also be set when issuing this primitive so that MSUs cannot be received during congestion. Clear Congestion: This primitive should be used only to clear the Congestion state caused by UPRIM 14. If DRX is set, it should be cleared just prior to issuing this primitive. If congestion state was entered due to a MISSed signal unit then the congestion state should be cleared by clearing MISS. Start Sending SIOS: If JSS7E=1, this primitive can be used to resume sending of SIOS signal units, stopped by issuance of UPRIM 17. Valid only in Out Of Service phase when JSS7E=1 (CSR2). Stop Sending SIOS: If JSS7E=1, this primitive can be used to stop the transmission of SIOS signal units while the MK50H27 is in the Out of Service phase. TTC specification JT-Q703 requires that transmission of SIOS stop some period of time after going Out Of Service; this primitive provides the mechanism for meeting that requiremnt. Transmis- MK50H27 07 PLOST 06 PAV 05:00 PPRIM 0 1 2 3 4 5 8 9 10 11 ‘ 12 13 16 17 18 19 20 21 sion of SIOS can be resumed by issuing UPRIM 16 described above. Valid only in Out Of Service phase when JSS7E=1 (CSR2). PROVIDER PRIMITIVE LOST is set by MK50H27 when a provider primitive cannot be issued because the PAV bit is still set from the previous provider primitive. PLOST is cleared when PAV is cleared and by a Bus RESET. Writing to this bit has no affect. PROVIDER PRIMITIVE AVAILABLE is set by the MK50H27 when a new provider primitive has been placed in PPRIM. PPRIM is READ/CLEAR ONLY and is set by the chip and cleared by writing a ”1” to the bit or by Bus RESET. Under normal operation the host should clear the PAV bit after PPRIM is read. PROVIDER PRIMITIVE is written by the MK50H27, in conjunction with setting the PAV bit, to inform the user of link control conditions. Valid Provider Primitives are as follows: Init Confirmation: indicates that the initialization has completed. In Service: indicates that alignment has completed successfully. In Service Yellow: indicates alignment completed succesfully with CCITT Yellow Book definitions for SINs & SIEs (SF = 9 & 10 respectively). This primitive will occur only if enabled by RYEL=1 in Protocol Options. Transmit Clock Watchdog Timer Expired: indicates that the watchdog timer for TCLK has expired due to no transition on TCLK for more than the number of SYSCLK cycles as selected by CSR4<15:14>. Receive Clock Watchdog Timer Expired: indicates that the watchdog timer for RCLK has expired due to no transition on RCLK for more than the number of SYSCLK cycles as selected by CSR4<13:12>. Received SU Timer timeout: indicates that no signal units have been received within the previous 32xTP time (where TP is the poll timer). This primitive is only issued if RSUTE=1 (CSR2<12>). Alignment Out of Service: indicates that a transfer to Out of Service phase has occured, due to an alignment failure. Alignment will fail if AERM is exceeded, timer T2 times out, or timer T3 times out. LSSU Out of Service: indicates that a transfer to the Out of Service phase has occured, due to a received LSSU. T1 Out of Service: indicates that a transfer to the Out of Service phase has occured, due to a timer T1 time out. Transmit Out of Service: indicates that a transfer to the Out of Service phase has occured, due to a transmit link failure. The transmit link will fail if timers T6 or T7 time out. Receive Out of Service: indicates that a transfer to the Out of Service phase has occured due to receive link failure. A receive link failure will occur when more than 2 out of 3 signal units have a FIB or BSN error. SUERM Out of Service: indicates that a transfer to the Out of Service phase has occured, due to SUERM being exceeded. Remote Processor Outage: indicates that a SIPO has been received indicating that a remote processor outage condition has occured. Remote Processor Outage Recovered: an FISU or an MSU has been received since remote processor outage condition has been reported. Received message BSNT: indicates that the MK50H27 has written the BSNT to the Status Buffer as requested by UPRIM 12. Retrieval complete: retrieval request and FSNC completed successfully. The pointer to the retransmission buffer is available in STATUS buffer. Remote Processor Busy: an SIB has been received indicating that the remote node has entered into congestion. Remote Processor Busy Recovered: the remote node has acknowledged 19/56 MK50H27 the receipt of an MSU after having entered congestion. This primitive indicates that the remote node congestion has abated. 1 5 1 4 C Y C L E E S E N 1 3 0 1 2 R S U T E 1 1 0 1 0 0 0 9 0 8 0 J S S 7 E 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 IADR<23:16> 4.1.2.3 Control and Status Register 2 (CSR2) RAP<3:1> = 2 BIT NAME DESCRIPTION 15 CYCLE Setting this bit selects a shorter DMA cycle (5 vs 6 SYSCLKs for bursting or 5 vs 7 SYSCLKs for single DMA). See Figures 7a and 8a for details. 14 ESEN Extended Scaler Enable. Setting this bit enables the use of the 16-bit timer pre-scaler at IADR+24 rather than the 8-bit Scaler at IADR+02. Using the 16-bit Scaler allows longer timer values at higher SYSCLK rates. Set ESEN=0 for backward compatibility with the MK50H27. 13 0 Reserved, must be written as zeroes. 12 RSUTE Received SU Timer Enable. Setting this bit enables a timer for detecting more than 32xTP time between received Signal Units. If RSUTE=1, PPRIM=5 will be issued upon expiry of the Received SU Timer. A typical use for RSUT is to detect breaking of the serial data connection. 11:09 0 Reserved, must be written as zeroes. 08 JSS7E Japanese SS7 Enable. Setting this bit enables TTC JT-Q703 compliance. When JSS7E=1 the MK50H27 will align using only SIEs, timers Tf, Ts, To, Ta, and Te will be activated appropriately, and the SUERM will act in accordance with JT-Q703 requiring interchanging the location of the T and D fields in the Initialization Block. If JSS7E=1 the MK50H27 will NOT comply with all CCITT/ITU, ANSI, or AT&T specifications. 07:00 IADR The high order 8 bits of the address of the first word (lowest address) in the Initialization Block. IADR must be written by the Host prior to issuing an INIT primitive. 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 IADR <15:00> 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 4.1.2.4 Control and Status Register 3 (CSR3) RAP<3:1> = 3 BIT NAME DESCRIPTION 15:00 IADR The low order 16 bits of the address of the first word (lowest address) in the Initialization Block. Must be written by the Host prior to issuing an INIT primitive. The Initialization block must begin on a word boundary. 20/56 MK50H27 4.1.2.5 Control and Status Register 4 (CSR4) 1 5 1 4 1 3 1 2 X W D 1 X W D 0 R W D 1 R W D 0 1 1 0 1 0 0 0 9 0 8 F W M 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 B A E B U S R B S W P C B U R S T 1 : 0 B S W P D A C O N B C O N CSR4 allows redefinition of the bus master interface. RAP<3:1> = 4 BIT 15:12 NAME XWD0/1, RWD0/1 DESCRIPTION These bits enable and determine the timer values for the Transmit and Receive Watchdog Timers. These timers are independently programmable and are reset by any transition on the TCLK and RCLK pins respectively. The Watchdog timers will expire after approximately Wn SYSCLK cycles (if not reset by transition on TCLK / RCLK pins) and Provider Primitive 3 or 4 will be issued. The following table shows the selections for Wn: XWD1/RWD1 XWD0/RWD0 Wn 0 0 Disabled 0 1 218 1 0 219 1 1 220 11:10 09:08 0 FWM Reserved, must be written as zero. These bits define the FIFO watermarks. FIFO watermarks prevent the MK50H27 from performing DMA transfers to/from the data buffers until the FIFOs contain a minimum amount of data or space for data. For receive data, data will only be transferred to the data buffers after the FIFO has at least N 16-bit words or an end of signal unit has been reached. Conversely, for transmit data, data will only be transferred from the data buffers when the transmit FIFO has room for at least N words of data. N is defined as follows: 07 BAE 06 BUSR 05 BSWPC FWM<1:0> N 11 1 word 10* 9 words 01 17 words 00 25 words * Suggested setting Bus Address Enable: if BAE is set then the A23-A20 pins are driven by the MK50H27 constantly providing the ability to use A23-A20 for memory bus selection. If clear, A23-A20 behave identically to A19A16. If this bit is set, pin 15 becomes input BUSREL. If this bit is clear then pin 15 is either BM0 or BYTE depending on bit 00. For more information see the description for pin 15 in this document. BUSR is READ/WRITE and cleared on bus Reset. This bit determines the byte ordering of all ”non-data” DMA transfers. 21/56 MK50H27 ”Non-data DMA transfers refers to any DMA transfers that access memory other than the data buffers themselves. This includes the Initialization Block, Descriptors, and Status Buffer. It has no effect on data DMA transfers. BSWPC allows the MK50H27 to operate with memory organizations that have bits 07:00 at even addresses and with bits 15:08 at odd addressses or vice versa. BSWPC is Read/Write and cleared by BUS RESET. With BSWPC = 1: Address Address XX1 0 . .. XX1 7 8 . . . 15 This memory organization is used with the 8086 family of microprocessors. With BSWPC = 0: Address Address XX0 04:03 BURST 8 ... 15 XX1 BSWPD 01 ACON 00 BCON 7 8 bit mode 16 bit mode 1 words 00 2 bytes 10* 16 bytes 8 words 01 unlimited unlimited * Suggested setting This bit determines the byte ordering of all data DMA transfers. Data transfers are those to or from a data buffer. BSWPD has no effect on non-data transfers. The effect of BSWPD on data transfers is the same as that of BSWPC on non-data transfers (see above). For most applications, including most 68000 based systems, this bit should be set. ALE CONTROL defines the assertive state of pin 18 when the MK50H27 is a Bus Master. ACON is READ/ WRITE and cleared by Bus RESET. ACON PIN18 NAME 0 ASSERTED HIGH ALE 1 ASSERTED LOW AS BYTE CONTROL redefines the Byte Mask and Hold I/O pins. BCON is READ/WRITE and cleared by Bus RESET. BCON 22/56 .. . This memory organization is used with the 68000 and the Z8000 microprocessors. This field determines the maximum number of data transfers performed each time control of the host bus is obtained. BURST is READ/WRITE and cleared on bus Reset. BURST <1:0> 02 0 PIN16 PIN15 PIN17 0 BM1 BM0 HOLD 1 BUSAKO BYTE BUSRQ MK50H27 4.1.2.6 Control and Status Register 5 (CSR5) CSR5 facilitates control and monitoring of modem controls. RAP<3:1> = 5 1 5 0 1 4 0 BIT 15:05 4 NAME 0 RTSEN 3 DTRD 2 DSRD 1 DTR 0 DSR 1 3 0 1 2 0 1 1 0 1 0 0 0 9 0 0 8 0 0 7 0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 X E D G E R T S E N D T R D D S R D D T R D S R DESCRIPTION Reserved, must be written as zeroes. RTS/CTS ENABLE is a READ/WRITE bit used to configure pins 26 and 30. If this bit is set, pin 26 becomes RTS and pin 30 becomes CTS. RTS is driven low whenever the MK50H27 has data to transmit and is kept low during transmission. RTS will be driven high after the closing flag of a signal unit is transmited if either no other frames are in the FIFO or if the minimum signal unit spacing is higher than 2 (see Mode Register). The MK50H27 will not begin transmission and TD will remain HIGH if CTS is high. If RTSEN = 0 then pins 26 and 30 become programmable I/O pins DTR and DSR. The direction and behavior of DSR and DTR are controlled by the following bits. DTR DIRECTION is a READ/WRITE bit used to control the direction of the DTR pin. If DTRD = 0, the DTR pin becomes an input pin and the DTR bit reflects the current value of the pin; if DTRD = 1, the DTR pin is an output pin controlled by the DTR bit below. DSR DIRECTION is a READ/WRITE bit used to control the direction of the DSR pin. If DSRD = 0, the DSR pin becomes an input pin and the DSR bit reflects the current value of the pin; if DSRD = 1, the DSR pin is an output pin controlled by the DSR bit below. DATA TERMINAL READY is used to control or observe the DTR I/O pin depending on the value of DTRD. If DTRD = 0, this bit becomes READ ONLY and always equals the current value of the DTR pin. If DTRD = 1, this bit becomes READ/WRITE and any value written to this bit appears on the DTR pin. DATA SET READY is used to control or observe the DSR I/O pin depending on the value of DSRD. If DSRD = 0, this bit becomes READ ONLY and always equals the current value of the DSR pin. If DSRD = 1 this bit becomes READ/WRITE and any value written to this bit appears on the DSR pin. 23/56 MK50H27 4.2 Initialization Block MK50H27 initialization includes the reading of the initialization block in memory to obtain the operating parameters. The Initialization Block is defined below. Upon receiving an Init primitive, portions of the Initialization block are read by the MK50H27. The remainder of the Initialization block will be read as needed by the MK50H27. Figure 4: Initialization Block BASE ADDRESS MODE IADR+00 COUNTER / TIMER PERIODS IADR+02 PROTOCOL PARAMETERS IADR+26 RLEN - RDRA <23:16> IADR+36 RDRA <15:00> IADR+38 TLEN - TDRA <23:16> IADR+40 TDRA <15:00> IADR+42 STATUS BUFFER ADDRESS HIGHER ADDR 24/56 STATISTICS IADR+44 IADR+50 THRU IADR+198 MK50H27 4.2.1 Mode Register The Mode Register allows alteration of the MK50H27’s operating parameters. 1 5 IADR + 00 BIT 15:11 NAME MFS<4:0> 1 4 1 3 1 2 MFS <4:0> MFS<4:0> 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 1 0 2 4 9 18 5 11 22 12 25 19 7 15 31 30 EXTCF 09 EXTAF 08 DACE 07 EXTC 06 EXTA 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 E X T C F E X T A F D A C E E X T C E X T A D R C K D T C K C K S 0 2 0 1 0 0 LBACK <2:0> DESCRIPTION Minimum Frame Spacing defines the minimum number of flag sequences transmitted between adjacent frames transmitted by the MK50H27. This only affects frames transmitted by the MK50H27 and does not restrict the spacing of the frames received by the MK50H27. When using RTS/CTS control this field defines the number of flags transmitted at the beginning of the frame after CTS is driven low (minus one for the trailing flag). See the following table for encoding of this field. NUMBER OF FLAGS 10 1 1 NUMBER OF FLAGS 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 MFS<4:0> 28 24 17 3 6 13 27 23 14 29 26 21 10 20 8 16 Extended Control Force. Must be reset to zero for both SS7 and HDLC transparent mode Extended Address Force. If set along with EXTA, the receiver will assume the address to be two otets long regardless of the first bit of the address. See EXTA below. Must be set to a 1 for SS7 operation. Must be reset to a zero for HDLC transparent mode. Disable Address and Control field Extraction. DACE should be written with ”0” for normal SS7 operation and with ”1” for HDLC Transparent mode. The MK50H27 however, has a feature to allow shifting of the alignment of the data in the MSU buffers. If DACE is set to ”1” for SS7 mode, the received LI will be placed in the first byte of the receive buffer, followed by the SIO in the second byte and so on. If DACE = 1, on transmit the LI must be placed in the first byte of the transmit buffer rather than in the SUL field of the Transmit Descriptor Entry (TMD2). Extended Control Field. Must be reset to zero for both SS7 and HDLC transparent mode. Extended address Field. Must be set to a 1 for SS7 operation. Must be reset to a zero for HDLC transparent mode. 25/56 MK50H27 05 DRCK 04 DTCK 03 CKS 02:00 LBACK Disable Receiver CK. When DRCK = 0, the receiver will extract and check the CK field at the end of each signal unit. When DRCK = 1, the receiver continues to extract the last 16 or 32 bits of each signal unit, depending on CKS, but no check is performed to determine whether the CK is correct. The CK is not stored into the Receive buffer. Disable Transmitter CK. When DTCK = 0, the transmitter will generate and append the CK to each signal unit. When DTCK = 1, the CK logic is disabled, and no CK is generated with transmitted signal units. Setting DTCK=1 is useful in loopback testing for checking the ability of the receiver to detect an incorrect CK. CK Select. When CKS = 1, the 16 bit CK is selected otherwise the 32 bit CK is used. Loopback Control puts the MK50H27 into one of several loopback configurations. LBACK DESCRIPTION 0 Normal operation. No loopback. 4 Simple loopback. Receive data and clock are driven internally by transmit data and clock. Transmit clock must be supplied externally 5 Clockless loopback. Receive data is driven internally by transmit data. Transmit and receive clocks are driven by SYSCLK divided by 8. 6 Silent loopback. Same as simple loopback with td pin forced to all ones. 7 Silent clockless loopback. Combination of Silent and Clockless loopbacks. Receive data is driven internally by transmit data, transmit and receive clocks are driven by SYSCLK divided by 8. The TD pin is forced to all ones. 4.2.2 Timers There are ten independent counter-timers defined in SS7. The upper 8 bits of IADR+02 are used as a scaler for T1 through T7, and TP. The scaler is driven by a clock which is 1/32 of SYSCLK. N1 is the maximum number of signal units allowed for retransmission (transmission window size) and N2 is the maximum number of bytes allowed for retransmission. The value for N1 is set to 128. The Host will write the period of N2, T1-T7, and TP into the Initialization Block. TIMER SCALER N2 T1 T2 26/56 DESCRIPTION TIMER PRESCALER. Timers T1-T7 and TP are scaled by this number. The prescaler is incremented once every 32 system clock pulses. When it reaches zero the timers are incremented and the prescaler is reset. This field is interpreted as the two’s complement of the prescaler period. The MK50H27 multiplies this value by 16 when it is read into the device. Note: a prescale value of one gives the smallest amount of scaling to the timers (512 clock pulses), zero gives the largest (131584 clock pulses). Octet window size. N2 gives the maximum number of MSU octets allowed for retransmission. N2 includes the opening and closing flags, BSN/BIB, FSN/FIB, LI, and the CK octets. This value is expressed as a positive integer. Bits <14:8> of IADR + 02 represent the most significant bits of N2. ALIGNED READY TIMER PERIOD. T1 determines the maximum time the MK50H27 will stay in the ALIGNED READY state before signalling link failure. Represented as two’s complement. NOT ALIGNED TIMER PERIOD. T2 determines the maximum time the MK50H27 will wait in the NOT ALIGNED state before signalling link failure. Represented as two’s complement. MK50H27 T3 T4n T4e T5 T6 T7 TP RESERVED/ 16-bit Scaler ALIGNED TIMEOUT TIMER PERIOD. T3 determines the maximum time the MK50H27 will wait in the ALIGNED state before signalling link failure. Represented as two’s complement. NORMAL PROVING PERIOD. T4n determines the length of the normal proving period as defined in CCITT Q.703. Represented as two’s complement. EMERGENCY PROVING PERIOD. T4e determines the length of the emergency proving period as defined in CCITT Q.703. Represented as two’s complement. BUSY TRANSMIT PERIOD. T5 determines the amount of time the MK50H27 will wait between transmissions of status indication ”B” while in congestion state. Represented as two’s complement. EXCESSIVE BUSY TIMER PERIOD. T6 determines the amount of time the MK50H27 will allow a remote site to remain in the congested state before signalling link failure. Represented as two’s complement. EXCESSIVE ACKNOWLEDGE TIMER PERIOD. T7 determines the maximum amount of time the MK50H27 will wait for an expected acknowledgement of an MSU before signalling link failure. Represented as two’s complement. TRANSMIT POLLING PERIOD. This scaled timer determines the length of time between transmit signal unit checks. Unless TDMD (see CSR0) is set or a signal unit is received on the link, no attempt to transmit a signal unit in the transmit descriptor ring is made until TP expires. At TP expiration all transmit signal units in the transmit descriptor ring are sent. Represented as two’s complement. Can be programmed as all zeroes for compatibliity with existing MK50H27 applications. However, if ESEN=1 (CSR2<14>), then this field is defined as a 16-bit scaler for all of the timers, and it will be used instead of the Scaler at IADR+02. This prescaler is incremented once every 32 system clock pulses. When it reaches zero the timers are incremented and the prescaler is reset. This field is interpreted as the two’s complement of the prescaler period. This 16-bit scaler is NOT multiplied by 16 when read into the MK50H27. Timers For Optional TTC JT-Q703 Compliance Tf FISU Sending Interval timer. This timer, located at IADR + 144 will determine the amount of time between transmission of FISUs when in TTC JT-Q703 compliant mode (CSR2<08> JSS7E=1). Represented as two’s complement. Ts SIOS Sending Interval timer. This timer, located at IADR + 146 will determine the amount of time between transmission of SIOS signal units when in TTC JT-Q703 compliant mode (CSR2<08> JSS7E=1). Represented as two’s complement. To SIO Sending Interval timer. This timer, located at IADR + 148 will determine the amount of time between transmission of SIOsignal units when in TTC JT-Q703 compliant mode (CSR2<08> JSS7E=1). Represented as two’s complement. Ta SIE Sending Interval timer. This timer, located at IADR + 150 will determine the amount of time between transmission of SIE signal units when in TTC JT-Q703 compliant mode (CSR2<08> JSS7E=1). Represented as two’s complement. Note: The Tf, Ts, To, & Ta timers are only active and valid when JSS7E=1 (CSR2<08>). 27/56 MK50H27 IADR + 02 0 14 87 Counter N2 0 SCALER 0 15 IADR + 04 COUNTER N2 0 15 TIMER T1 IADR + 06 0 15 IADR + 08 TIMER T2 0 15 IADR + 10 TIMER T3 0 15 TIMER T4n IADR + 12 0 15 TIMER T4e IADR + 14 0 15 TIMER T5 IADR + 16 0 15 TIMER T6 IADR + 18 0 15 IADR + 20 TIMER T7 0 15 IADR + 22 TIMER TP 15 IADR + 24 28/56 0 RESERVED / 16-Bit SCALER (if ESEN=1) MK50H27 4.2.3 Protocol Parameters 15 0 IADR + 26 PO 8 7 15 T IADR + 28 0 M 0 15 D IADR + 30 8 7 15 IADR + 32 IADR + 34 PARM PO Tin 0 0 Tie 14 0 m DESCRIPTION PROTOCOL OPTIONS. Defines the SS7 protocol options to be used. BIT NAME DEFINITION 00 DBUSY DBUSY = 1: Disables busy mechanisms on both transmit and receive. Missed MSU interrupts (CSR0<06>, MISS) are not affected by this bit. 01 XYEL XYEL= 0: Transmitted SINs and SIEs conform to CCITT Red/Blue Book definitions (SF = 1 and 2 respectively). XYEL= 1: Transmitted SINs and SIEs conform to CCITT Yellow Book definitions (SF = 9 & 10 respectively). 02 RYEL RYEL= 0: Only CCITT Red/Blue Book definitions for received SINs and SIEs are accepted. RYEL= 1: Either CCITT Yellow or Red/Blue Book definitions for received SINs and SIEs are accepted. 03 RMODE Defines the retransmission method to be used. RMODE = 0: specifies Basic Error Recovery (BEC). RMODE = 1: specifies Preventive Cyclic Redundancy(PCR). 04 BECDOUBLE Provides double transmission of all MSUs in BEC. All MSU’s including those sent during negative acknowledgement are transmitted twice. If RMODE= 0 then the following definitions apply: BECDOUBLE = 0: specifies normal BEC. BECDOUBLE = 1: specifies BEC with doubletransmission. NOTE: BECDOUBLE must be 0 if RMODE = 1. 05 ERMEN Enables the AERM and SUERM error rate monitors. ERMEN = 0: disables the AERM and SUERM. ERMEN = 1: enables the AERM and SUERM. 06 OCTEN Enables octet counting. OCTEN = 0: disables octet counting. OCTEN = 1: enables octet counting. 07 2/3EN Enables 2/3 errored FIB/BSN error monitoring. 2/3EN = 0: disables 2/3 error monitoring. 2/3EN = 1: enables 2/3 error monitoring. 08 ANSIT6/T7 Selects ANSI or ITU compliance for SS7 T6 & T7 timers ANSIT6/T7 =0: T6 & T7 timer operation complies with ITU Q.703 ANSIT6/T7 =1: T6 & T7 timer operation complies with ANSI T1.111.3 15-09 RESERVED Must be programmed with all zeroes. 29/56 MK50H27 T / TTC D M D / TTC T Tin Tie m SUERM THRESHOLD. Number of consecutive signal units received in error that will cause an error rate high indication. When operating in TTC compliant mode (CSR2 JSS7E=1), this field should contain the D value (typically 16) used for TTC JT-Q703 SUERM operation. PROVING ABORT LIMIT. Number of consecutive aborted proving periods that cause the MK50H27 to return to the OUT-OF-SERVICE state. SUERM ERROR RATE. The lowest acceptable number of signal units per signal unit error. When operating in TTC compliant mode (CSR2 JSS7E=1), this field should contain the T SUERM Threshold value (typically 285) used for TTC JT-Q703 SUERM operation. This field should be expressed as a two’s complement value. NORMAL AERM THRESHOLD. Number of signal unit errors that cause the abortion of a normal proving period. EMERGENCY AERM THRESHOLD. Number of signal unit errors that cause the abortion of an emergency proving period. Maximum frame length. Number of bytes allowed in the information portion of received MSUs before octect counting begins. NOTE: The operation of the SUERM (Signal Unit Error Rate Monitor) is different between CCITT / ITU compliant systems and TTC JT-Q703 compliant systems. Although both SUERM schemes operate based upon a leaky bucket principle, there are some major differences in their implementation. For CCITT/ITU Q.703 the SUERM count is incremented by 1 for each errored SU received until a threshold T (typically 64) is reached, at which time a link failure is declared.. For every D (typically 256) good SUs received the SUERM Count, Cs, is decremented by 1 (not to go less than 0). For TTC JT-Q703 the SUERM count is updated once every monitor time Te (typically 24 ms) regardless of the number of SUs received during the time Te. If the last SU received was errored, then the SUERM count is incremented by D (typically 16) when Te expires. If the last SU received was good, then the SUERM count is decremented by 1 (not to go less than 0) when Te expires. If the SUERM count should ever reach the threshold T (typically 285), then a link failure is declared. For the MK50H27 the value used for time Te is the same value as programmed for time Tf (typically 24 ms for both). Due to this difference in SUERM operation, the fields in the MK50H27 Initialization Block that are used for D and T are exchanged if JSS7E=1 selecting Japanese SS7 (TTC JT-Q703 compliance). 30/56 MK50H27 4.2.4 Receive Descriptor Ring Pointer 1 5 IADR + 36 1 4 0 1 3 1 2 RLEN 1 1 1 0 0 9 0 8 0 0 0 0 IADR + 38 BIT 15 14:12 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RDRA<23:16> RDRA<15:00> NAME 0 RLEN 11:08 07:00/15:00 0 7 0 DESCRIPTION Reserved, must be written as a zero. RECEIVE RING LENGTH is the number of entries in the Receive Descriptor Ring expressed as a power of two. 0 RDRA RLEN Number of Entries 0 1 1 2 2 4 3 8 4 16 5 32 6 64 7 128 Reserved, must be written as zeroes. RECEIVE DESCRIPTOR RING ADDRESS is the base address (lowest address) of the Receive Descriptor Ring. The Receive Descriptor Address must begin on a word boundary. 4.2.5 Transmit Descriptor Ring Pointer 1 5 IADR + 40 IADR + 42 0 1 4 1 3 TLEN 1 2 1 1 1 0 0 9 0 8 0 0 0 0 0 7 TDRA<15:00> 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TDRA<23:16> 0 31/56 MK50H27 4.2.5 Transmit Descriptor Ring Pointer (continued) BIT NAME DESCRIPTION 15 0 Reserved, must be written as a zero. 14:12 TLEN TRANSMIT RING LENGTH is the number of entries in the Transmit Ring expressed as a power of two. 11:08 07:00/15:00 0 TDRA TLEN Number of Entries 0 1 1 2 2 4 3 8 4 16 5 32 6 64 7 128 Reserved, must be written as a zero. TRANSMIT DESCRIPTOR RING ADDRESS is the base address (lowest address) of the Transmit Descriptor Ring. The Transmit Descriptor Ring Address must begin on a word boundary. 4.2.6 Status Buffer Address 1 5 IADR + 44 IADR + 46 BIT 15:08 NAME TWS 07:00/15:00 SBA 32/56 1 4 1 3 1 2 1 1 0 0 0 9 0 8 0 7 TWS <15:08> 0 6 0 5 0 4 0 3 0 2 0 1 0 0 SBA<23:16> SBA<15:00> 0 DESCRIPTION TRANSMIT WINDOW SIZE is used to determine the maximum number of MSUs that can be transmitted without acknowledgement. For compliance with Japanese TTC JT-Q703 this value should typically be 40. For compliance with CCITT/ITU Q.703 this value should be 127. For compatibility with the original MK50H27, this field may be programmed with all zeroes, causing the MK50H27 to use a default value of 127 as did the MK50H27. STATUS BUFFER ADDRESS points to the status buffer into which link status information is placed upon the issuance of the Status Request primitive by the HOST. The status buffer must begin on a word boundary. MK50H27 4.2.7 Reserved 1 5 IADR + 48 BIT 15:00 NAME 0 1 4 1 3 1 2 1 1 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RESERVED DESCRIPTION Reserved, must be written as zeroes. 4.2.8 Statistics A significant portion of the initialization buffer is reserved for statistical information collected by the MK50H27. When a statistic is updated, the MK50H27 will read the appropriate statistic, increment it, and then write it back out to memory. These statistics are intended for the use of the Host CPU for statistical analysis. The MK50H27 will only increment these counters; it is up to the user to clear and preset these counters. The statistics collected are: Memory Address IADR + 50 IADR + 52 IADR + 54 IADR + 56 IADR + IADR + IADR + IADR + IADR + IADR + IADR + IADR + IADR + IADR + IADR + 58 60 62 64 66 - 122 124 126 128 130 132 134 IADR + 136 - 198 Note: IADR+144 - 151 Error Counter SL Failure - number of link failures due to abnormal FIB/BSN received. SL Failure - number of link failures due to excessive delays of acknowledgementcaused by timer T7 time out. SL Failure - number of link failures due to excessive SUERM error rate. SL Failure - number of link failures due to excessive congestion caused by timer T6 time out. Number of alignment failures due to timers T2 or T3 timing out. Number of alignment failues due to AERM exceeded. Number of negative acknowledgements received. Number of Signal Units in error. Reserved. Must be programmed as zeroes. Number of SIB’s transmitted. Number of SIB’s received. Number of forced retransmissions caused by N1. Number of forced retransmissions caused by N2. Number of MSU’s retransmitted. Number of MSU octets retransmitted. This value includes the opening and closing flags, BSN/BIB, FSN/FIB, LI, and the CK octets. Reserved. Must be programmed as zeroes. Used for TTC JT-Q703 compliant timers Tf, Ts, To, and Ta if JSS7E=1. See page 27 for details. 33/56 MK50H27 4.3 Receive and Transmit Descriptor Rings Each descriptor ring in memory is a 4 word entry. The following is the format of the receive and transmit descriptors. 4.3.1 Receive Message Descriptor Entry 4.3.1.1 Receive Message Descriptor 0 (RMD0) 1 5 1 4 1 3 1 2 O W N A O W N B S L F E L F BIT 15 NAME OWNA 14 OWNB 13 SLF 12 ELF 11:08 11:10 0 PRIN 07:00 RBADR 34/56 1 1 1 0 0 9 0 8 PRIN 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RBADR<23:16> DESCRIPTION When this bit is a zero either the HOST or the I/O ACCELERATION PROCESSOR owns this descriptor. When this bit is a one the MK50H27 owns this descriptor. The chip clears the OWNA bit after filling the buffer pointed to by the descriptor entry provided a valid signal unit has been received. The Host sets the OWNA bit after emptying the buffer. Once the MK50H27, Host, or I/O acceleration processor has relinquished ownership of a buffer, it may not change any field in the four words that comprise the descriptor entry. This bit determines whether the Host or the Layer 3 I/O Processor owns the buffer when OWNA is a zero. The MK50H27 never uses this bit. This bit is provided to facilitate use of a Layer 3 I/O processor. Start of Long Signal Unit indicates that this is the first buffer used by MK50H27 for this signal unit. It is used for data chaining buffers. SLF is set by the MK50H27. NOTE: A ”Long Signal Unit” is any MSU which needs data chaining. End of Long Signal Unit indicates that this the last buffer used by MK50H27 for this signal unit. It is used for data chaining buffers. If both SLF and ELF were set, the signal unit would fit into one buffer and no data chaining would be required. ELF is set by the MK50H27. Reserved, must be written as zeroes for CCITT/ITU compliant operation. These bits indicate the content of the Priority Indication bits of the received frame when JSS7E=1 (TTC JT-Q703 compliant mode). The High Order 8 address bits of the buffer pointed to by this descriptor. This field is written by the Host and unchanged by MK50H27. MK50H27 4.3.1.2 Receive Message Descriptor 1 (RMD1) 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 RBADR<15:00> BIT 15:01 NAME RBADR 0 0 DESCRIPTION The low order 16 address bits of the receive buffer pointed to by this descriptor. RBADR is written by the Host CPU and unchanged by MK50H27. The receive buffers must be word aligned. 4.3.1.3 Receive Message Descriptor 2 (RMD2) 1 5 1 4 1 3 1 2 1 1 1 0 1 BIT 15:00 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 BCNT<15:00> NAME BCNT 0 0 0 DESCRIPTION Buffer Byte Count is the length of the buffer pointed to by this descriptor expressed in two’s complement. This field is written to by the Host and unchanged by MK50H27. The value of BCNT must be an even number. 4.3.1.4 Receive Message Descriptor 3 (RMD3) 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 MCNT<15:00> BIT 15:00 NAME MCNT DESCRIPTION Message Byte Count is the length, in bytes, of the received signal unit. MCNT is valid only when ELF is set to a one. MCNT is written by MK50H27 and read by the Host. If ELF is set to a zero the entire buffer has been utilized and the message byte count is given in BCNT above. The value of this field is expressed in two’s complement. 35/56 MK50H27 4.3.2 Transmit Message Descriptor Entry 4.3.2.1 Transmit Message Descriptor 0 (TMD0) BIT 15 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 O W N A O W N B S L F E L F PRIN 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TBADR<23:16> NAME OWNA DESCRIPTION When this bit is a zero either the HOST or the SLAVE PROCESSOR owns this descriptor. When this bit is a one the MK50H27 owns this descriptor. The host sets the OWNA bit after filling the buffer pointed to by the descriptor entry. The MK50H27 releases the descriptor after transmitting the buffer and receiving the proper acknowledgement from the receiver. After the MK50H27, Host, or I/O acceleration processor has relinquished ownership of a buffer, it may not change any field in the four words that comprise the descriptor entry. 14 OWNB This bit determines whether the Host or the Layer 3 I/O Processor owns the buffer when OWNA is a zero. The MK50H27 never uses this bit. This bit is provided to facilitate use of a Layer 3 I/O processor. 13 SLF Start of Long Signal Unit indicates that this is the first buffer used by the MK50H27 for this signal unit. It is used for data chaining buffers. SLF is set by the Host. When not chaining, SLF should be set to a one. NOTE: A ”Long Signal Unit” is any MSU which needs data chaining. 12 ELF End of Long Signal Unit indicates that this is the last buffer used by the MK50H27 for this signal unit. It is used for data chaining buffers. If both SLF and ELF were set the signal unit would fit into one buffer and no data chaining would be required. ELF is set by the Host. When not chaining, ELF should be set to a one. 11:08 0 Reserved, must be written as zeroes for CCITT/ITU operation. 11:10 PRIN These bits determine the content of the Priority Indication bits of the transmitted frame when JSS7E=1 (TTC JT-Q703 compliant mode). 07:00 TBADR The High Order 8 address bits of the buffer pointed to by this descriptor. This field is written by the Host and unchanged by MK50H27. 4.3.2.2 Transmit Message Descriptor 1 (TMD1) 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 TBADR<15:00> BIT 15:00 36/56 NAME TBADR 0 5 0 4 0 3 0 2 0 1 0 0 0 DESCRIPTION The Low Order 16 address bits of the buffer pointed to by this descriptor TBADR is written by the Host and unchanged by MK50H27. The least significant bit is zero since the descriptor must be word aligned. MK50H27 4.3.2.3 Transmit Message Descriptor 2 (TMD2) 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 SUL<15:00> BIT 15:00 NAME SUL DESCRIPTION Signal Unit Length. Only required when in the first descriptor of a signal unit (SLF = 1) and when DACE = 0. Contains the length of the SIF and the SIO fields of the signal unit, in octets, to be transmitted. The value of this field is expressed as a positive integer. 4.3.2.4 Transmit Message Descriptor 3 (TMD3) 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 MCNT<15:00> BIT 15:00 NAME MCNT DESCRIPTION Message byte count is the length, in octets, of the data contained in the corresponding buffer. The value of this field is expressed in two’s complement. 37/56 MK50H27 Figure 4a: MK50H27 Status Buffer 1 5 SBA + 00 B I B T SBA + 02 F I B T 1 4 1 3 1 2 1 1 1 0 0 9 BSNT FSNT/FSNC 0 8 0 7 0 6 0 5 0 4 0 3 B I B R BSNR F I B R FSNR SBA + 04 RFSN FSNX SBA + 06 TIDX RIDX SBA + 08 RTIDX PHASE SBA + 10 TX STATE RX STATE SBA + 12 FIRMWARE RELEASE NUMBER RESERVED SBA + 14 NUMBER OF OCTETS RETRANSMITTED SBA + 16-48 RESERVED 38/56 0 2 0 1 0 0 MK50H27 4.3.3 Status Buffer FIELD BIBT BSNT BIBR BSNR FIBT FSNT/FSNC FIBR FSNR RFSN FSNX TIDX RIDX RTIDX PHASE TX STATE RX STATE FIRMWARE RELEASE NUMBER NUMBER OF OCTETS RETRANSMITTED RESERVED DESCRIPTION The value of the last BIB transmitted. The value of the last BSN transmitted. 0 ≤ BSNT ≤ 127. The value of the last BIB received. The value of the last BSN received. 0 ≤ BSNR ≤ 127. The value of the last FIB transmitted. Under normal operation this is the value of the last FSN transmitted. If a UPRIM 13 is to be issued in CSR1 then the FSNC value to be read by the MK50H27 must be placed here by the host. 0 ≤ FSNT/FSNC ≤ 127. The value of the last FIB received. The value of the last FSN received. 0 ≤ FSNR ≤ 127. The value of the oldest unacknowledged FSNT in the retransmission buffer. 0 ≤ RFSN ≤ 127. The value of the next expected FSN to be received. 0 ≤ FSNX ≤ 127. Index to the descriptor of the current transmission buffer. Index to the descriptor of the current receive buffer. Index to the first descriptor of the retransmission buffer. Indicates the current phase of operation for the device. 0:Power Off. 2:Out of Service. 4: Initial alignment not aligned. 5:Initial alignment aligned. 6:Initial alignment proving. 7:Alignment not ready. 8:Alignment ready. 9:In Service. 10:Processor outage. 11:Transparent mode. 12:Memory Error. Indicates the current state of the transmitter. 0: The transmitter is waiting to transmit a Signal Unit. 1:A Signal Unit is currently being transmitted. 2:A Signal Unit transmission has completed. Indicates the current state of the receiver. 0:The receiver is expecting the beginning of a Signal Unit. 1:A MSU is being transferred to the receive buffer(s). 2:End of frame detected. 3:Receive data being ignored. 4:Buffer chaining requested. Indicates the release number of the firmware within the MK50H27. This value represents the lower two bytes of the total number of octets retransmitted. The number of octets retransmitted statistics counter represents the upper two bytes of the total number of octets retransmitted. This two byte status buffer value together with the two byte error counter value provide a 32 bit value for the total number of octets retransmitted. Must be programmed as ZEROES. 39/56 MK50H27 4.4 Detailed Programming Procedures 4.4.1 Initialization The following procedure should be followed to intialize the MK50H27: 1. Setup bus control information in CSR4. 2. Setup the Initialization Block and Desciptor Rings. 3. Load the address of the initialization block information into CSR’s 2 and 3. 4. Issue the INIT primitive through CSR1 instructing the MK50H27 to read the initialization block pointed to by CSR’s 2 and 3. 5. Wait for the INIT confirmation primitive from the MK50H27. 6. For SS7 operation, issue the PON primitive through CSR1, SIOS’s will now be continuously transmitted. For HDLC Transparent mode, issue the TRANS primitive through CSR1, flags will now be continously transmitted. 7. Enable interrupts in CSR0 if desired. 4.4.2 Alignment 1. For SS7 operation issue the START primitive through CSR1 to begin alignment. 2. Wait for the IN SERVICE provider primitive. 4.4.3 Sending Data Use the following procedure to send a MSU: 1. Wait for the OWNA bit of the current transmit descriptor to be cleared, if it is not already. 2. Fill the buffer associated with the current transmit descriptor with the data to be sent, or set the descriptor buffer address to any already filled buffer. 3. Repeat steps 1 and 2 for the next buffer if chaining is necessary, setting SLF, ELF and MCNT appropriately. 4. Set the OWNA bit for each descriptor used. 4.4.4 Receiving Data The following procedure should be followed when receiving a MSU: 1. Make sure the OWNA bit of the current receive descriptor is clear. 2. Read data out of the buffer associated with the current receive descriptor. 3. Set the OWNA bit of the current receive descriptor. 4. If the ELF bit of the current receive descriptor is clear, then go on to the next descriptor and repeat the above steps appending data from each buffer until a descriptor with the ELF bit set is reached. 4.4.5 Link Disconnection The following procedure should be followed to disconnect an established link: 1. For SS7 operation, issue the STOP primitive through CSR1. The MK50H27 will enter the Out of Service state and continuously transmit SIOS’s. 4.4.6 Disabling the MK50H27 The following procedure should be followed to disable the MK50H27: 1. Issue the POFF primitive through CSR1. This will disable the MK50H27 from receiving or transmitting. The TD pin will be held high while the MK50H27 is in the Power Off state. The POFF bit in CSR0 will be set and interrupts will be disabled. If a link is currently established, then data may be lost. 4.4.7 Re-enabling the MK50H27 The same procedure should be followed for re-enabling the MK50H27 as was used to initalize upon power up. If the Initialization Block and the hardware configuration have not changed, then steps 1,2,3, 4 and 5 of the intialization sequence may be omitted. 40/56 MK50H27 4.4.8 MK50H27 Internal Self Test The MK50H27 contains an easy to use internal self test designed to test, with a high fault coverage, all of the major blocks of the device except the DMA controller. It is suggested that a loopback test also be performed to more completely test the DMA controller. The following procedure should be followed to execute the internal self test: 1. Reset the device using the RESET pin. 2. Set bit 04 of CSR4. 3. Issue a Self Test Request through CSR1. 4. Poll CSR1, waiting for the PAV bit in CSR1 to be set by the MK50H27. 5. After the PAV bit is set, read CSR1. The success or failure of the test is indicated in the PPRIM field as follows: PPRIM RESULT 00 Passed self test. 17 Failed the reset test of the self test. 18 Failed the self test in the micro controller RAM. 19 Failed the self test in the ALU. 20 Failed the self test in the timers. 21 Failed the self test in the transmitter and/or receiver. 22 Failed the self test in the CSR’s and/or bus master. Otherwise Failed device. 6. If the PAV bit is not set within 75 msec (SYSCLK = 10MHZ), then the MK50H27 is unable to respond to the Self Test Request and will not complete successfully. If the self test passes, then it may be immediately reexecuted from step 3, otherwise re-execution should proceed from step 1. 41/56 MK50H27 SECTION 5 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Symbol Parameter TUB Temperature Under Bias Tstg Storage Temperature VG Voltage on any pin with respect to ground Ptot Power Dissipation Value Unit -25 to +100 °C -65 to +150 -0.5 to VCC+0.5 °C V 0.5 W Stresses above those listed under ”Absolute Maximum Rating” may cause permanent damage to the above device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS T A=0 °C to 70 °C, VCC = +5 V ±5 percent unless otherwise specified. Symbol Parameter Min. VIL VIH VOL @ IOL = 3.2 mA VOH @ IOH= -0.4 mA Max. Units -0.5 Typ. +0.8 V +2.0 VCC +0.5 V +0.5 V +10 mA +2.4 IIL @ VIN = 0.4 to VCC ICC @ TSCT = 100 ns V µA 50 CAPACITANCE f = 1MHz Symbol CIN C OUT C IO Parameter Min. Typ. Max. Units Capacitance on Input pins 10 pF Capacitance on Output Pins 10 pF Capacitance on I/O pins 20 pF AC TIMING SPECIFICATIONS T A = 0 °C to 70 °C, VCC = +5 V ±5 percent, unless otherwise specified. MK50H27 No Signal Symbol Parameter Test Condition -16 -25 -33 -16/25/33 Min. Min. Min. Max. Units 10000 ns 1 SYSCLK TSCT SYSCLK period 60 40 30 2 SYSCLK TSCL SYSCLK low time 24 16 12 3 SYSCLK TSCH SYSCLK high time 24 16 12 4 SYSCLK TSCR Rise time of SYSCLK 0 0 0 8 5 SYSCLK TSCF Fall time of SYSCLK 0 0 0 8 6 TCLK TTCT TCLK period 20 20 20 ns 7 TCLK TTCL TCLK low time 8 8 8 ns 8 TCLK TTCH TCLK high time 9 TCLK TTCR Rise time of TCLK 10 TCLK TTCF Fall time of TCLK 11 TD TTDP TD data propagation delay after the falling edge of TCLK 12 TD TTDH TD data hold time after the falling edge of TCLK 42/56 CL = 50 pF 8 8 8 0 0 0 0 0 0 CL = 50 pF 5 5 5 ns ns ns ns ns 8 ns 8 ns 13 ns ns MK50H27 AC TIMING SPECIFICATIONS CONTINUED - MK50H27 -25 T A = 0 °C to 70 °C, VCC = +5 V ±5 percent, unless otherwise specified. Parameter Notes MK50H27 -25 No Signal Symbol Min. 13 RCLK TRCT RCLK period 20 Typ. Max. Units ns 14 RCLK TRCH RCLK high time 8 ns 15 RCLK TRCL RCLK low time 8 16 RCLK TRCR Rise time of RCLK 0 8 ns 17 RCLK TRCF Fall time of RCLK 0 8 ns 18 RD TRDR RD data rise time 0 8 ns 19 RD TRDF RD data fall time 0 8 20 RD TRDH RD hold time after rising edge of RCLK 2 ns 21 RD TRDS RD setup time prior to rising edge of RCLK 8 ns ns ns 22 ALE/DAS TDOFF Bus Master driver disable Output Delay 0 20 ns 23 ALE/DAS TDON Bus Master driver enable after rising edge T1 SYSCLK Output Delay 0 20 ns 24 HLDA THHA Delay to falling edge of HLDA from falling edge of HOLD (Bus Master) 25 HLDA T HLAH HLDA input setup time 10 ns 26 HLDA THLAS Delay to rising edge HLDA from rising edge HOLD 10 ns 0 ns 27 A TXAS Address setup time Output Delay 30 ns 28 A TXAH Address hold time Output Delay 20 ns 29 DAL TAS Address setup time Output Delay 30 DAL TAH Address hold time Output Delay 31 DAL TRDAS Data setup time (Bus Master read) 15 32 DAL TRDAH Data hold time (Bus Master read) 10 33 DAL TWAH Address hold time (Bus Master write) Output Delay 15 ns 34 DAL TWDS Data setup time (Bus Master write) Output Delay 25 ns 35 DAL TWDH Data hold time (Bus Master write) Output Delay 25 ns 36 DAL TSRDS Data setup time (Bus Slave read) 25 ns 37 DAL TSRDH Data hold time (Bus slave read) 25 ns 38 DAL TSWDH Data hold time (Bus slave write) 10 39 DAL TSWDS Data setup time (Bus slave write) 10 40 ALE TALES ALE setup time Output Delay 30 ns 41 ALE TALHB ALE hold time (asserted to deasserted) (DMA Burst) Output Delay 15 ns 42 ALE TALHS ALE hold time (asserted to 3-State) (Single DMA cycle) Output Delay 20 ns 43 DAS TDASS DAS setup time from falling edge of T2 SYSCLK (Bus Master) Output Delay 25 ns 44 DAS TDASH DAS hold time from rising edge of SYSCLK (Bus Master) Output Delay 15 ns TBMDE Bus Master driver enable (from 3State to driven) (Bus Master) Output Delay 25 ns ns 45 DALI/DALO BM)/BM1 0 5 35 ns 20 ns ns ns ns ns 46 DALI TRIS DALI setup time (Bus Master read) Output Delay 15 47 DALI TRIH DALI hold time (Bus Master read) Output Delay 25 ns 48 DALI TBMDD Bus Master driver disable (from driven to 3-State) (Bus Master) Output Delay 20 ns 43/56 MK50H27 AC TIMING SPECIFICATIONS CONTINUED - MK50H27 -25 T A = 0 °C to 70 °C, VCC = +5 V ±5 percent, unless otherwise specified. Signal Symbol 49 DALO TROS DALO setup time (Bus Master read) Output Delay 50 DALO TROH DALO hold time (Bus Master read) Output Delay 52 CS TCSH CS hold time 10 ns 53 CS TCSS CS setup time 10 ns 54 ADR TSAH ADR hold time 10 ns 55 ADR TSAS ADR setup time 10 ns 56 DAS TSDAS DAS input setup time (Bus slave) 10 ns 57 DAS TSDSH DAS input hold time (Bus slave) 10 ns 58 READY TRDYS READY setup time (Bus slave) 59 READY TSRYH READY hold time after rising edge of DAS (Bus slave read) 60 READY TRSH READY setup time (Bus Master) 61 READY TSRS READY hold time (Bus Master) 10 ns 62 READ TREDS READ setup time (Bus slave) 10 ns 63 READ TREDH READ hold time (Bus slave) 10 ns 64 HOLD T HLDS HOLD setup time (Bus Master) Output Delay 15 ns 65 HOLD THLDH HOLD hold time (Bus Master) Output Delay 35 ns 44/56 Parameter Notes MK50H27 -25 No Min. Typ. Max. Units 30 ns 30 Output Delay ns 15 ns 15 ns 18 ns MK50H27 Figure 5a: TTL Output Load Diagram Figure 5b: Open Drain Output Load Diagram TEST POINT Vcc Vcc R1 = 1.2 K FROM OUTPUT UNDER TEST R1 = 1.4 K FROM OUTPUT UNDER TEST CR1 - CR4 = 1N914 or EQUIV CR 1 C CR 0.4 mA 2 L C CR 3 L C L = 50pF min @ 1 MHz CR 4 NOTE: This load is used on open NOTE: This load is used on all outputs except INTR, HOLD, READY. drain outputs INTR, HOLD, READY. Figure 6: MK50H27 Serial Link Timing Diagram 13 14 15 RCLK 16 21 17 20 19 RD 18 6 8 7 TCLK 10 9 11 12 TD TIMING MEASUREMENTS ARE MADE AT THE FOLLOWING VOLTAGES, UNLESS OTHERWISE SPECIFIED: ”1” ”0” OUTPUT 2.0 V O.8 V INPUT 2.0 V O.8 V FLOAT 10 % 90 % 45/56 MK50H27 Figure 7: MK50H27 BUS Master Timing (Read) (for CYCLE = 0, CSR2<15>) T0 T1 T2 T3 T4 T5 T6 SYSCLK 65 64 HOLD 24 26 25 HLDA 28 27 A 16-23 ADDRESS 40 23 41 ALE 43 23 42 44 DAS 22 60 61 READY 29 30 DAL0-15 ADDR 31 32 DATA IN 48 50 49 DALO 45 46 47 DALI READ 48 BM0,1 NOTES: 1. The shaded SYSCLK periods T0 and T5 will be removed when setting CSR2 bit 15, CYCLE =1 to select the shorter DMA cycle as shown in Figure 7a. 2. Output delay times are the maximum delay from the specifed edge to a valid output. 3. The Bus Master cycle time will increase from a minimum, in 1 SYSCLK increments until the slave device returns READY. 46/56 MK50H27 Figure 7a: MK50H27 Reduced Cycle BUS Master Timing (Read) (for CYCLE = 1, CSR2<15>) T1 T2 T3 T4 T5 SYSCLK 65 64 HOLD 24 26 25 HLDA 28 27 A 16-23 ADDRESS 40 23 41 ALE 42 43 23 44 DAS 22 60 61 READY 29 31 30 DAL0-15 ADDR 32 DATA IN 50 48 49 DALO 45 46 47 DALI READ 48 BM0,1 NOTES: 1. This reduced DMA Cycle Time is selected by setting CSR2 bit 15, CYCLE =1. 2. Output delay times are the maximum delay from the specifed edge to a valid output. 3. The Bus Master cycle time will increase from a minimum, in 1 SYSCLK increments until the slave device returns READY. 47/56 MK50H27 Figure 8: MK50H27 BUS Master Timing Diagram (Write) (for CYCLE = 0, CSR2<15>) T0 T1 T2 T3 T4 T5 T6 SYSCLK 65 64 HOLD 24 26 25 HLDA 28 27 A 16-23 ADDRESS 40 23 41 ALE 43 23 42 44 DAS 22 60 61 READY 29 DAL0-15 35 34 ADDR DATA 33 48 DALO 45 DALI READ 48 BM0,1 NOTES: 1. The shaded SYSCLK periods T0 and T5 will be removed when setting CSR2 bit 15, CYCLE =1 to select the shorter DMA cycle as shown in Figure 8a. 2. Output delay times are the maximum delay from the specifed edge to a valid output. 3. The Bus Master cycle time will increase from a minimum, in 1 SYSCLK increments until the slave device returns READY. 48/56 MK50H27 Figure 8a MK50H27 Reduced Cycle BUS Master Timing (Write) (for CYCLE = 1, CSR2<15>) T1 T2 T3 T4 T5 SYSCLK 65 64 HOLD 24 25 26 HLDA 28 27 A 16-23 ADDRESS 40 23 41 ALE 42 43 23 44 DAS 22 60 61 READY 29 DAL0-15 35 34 ADDR DATA 33 48 DALO 45 DALI READ 48 BM0,1 NOTES: 1. This Reduced DMA Cycle Time is selected by setting CSR2 bit 15, CYCLE = 1. Times T0 and T5 from the standard DMA Cycle are removed for this reduced timing. 2. Output delay times are the maximum delay from the specifed edge to a valid output. 3. The Bus Master cycle time will increase from a minimum, in 1 SYSCLK increments until the slave device returns READY. 49/56 MK50H27 Figure 8b: BUS Master BURST Timing (Reduced Cycle - Write) T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 SYSCLK 65 64 HOLD 24 26 25 HLDA 27 27 A 16-23 28 ADDRESS ADDRESS 40 23 40 41 41 ALE 43 23 43 44 42 44 DAS 60 60 61 22 61 READY 29 DAL0-15 ADDR 34 29 34 DATA ADDR 35 DATA 33 48 DALO 45 DALI READ 48 BM0,1 50/56 MK50H27 Figure 9: MK50H27 BUS Slave Timing Diagram (Read) SYSCLK 53 52 55 54 CS ADR 56 57 DAS 58 59 READY 62 63 READ (Read) 36 DAL 0-15 37 DATA OUT NOTES: 1. Input setup and hold times are in minimum values required to or from the particular edge specified in order to be recognized in that cycle. 2. Output delay times are from the specified edge to a valid output. 51/56 MK50H27 Figure 10: MK50H27 BUS Slave Timing Diagram (Write) SYSCLK 53 52 55 54 CS ADR 56 57 DAS 58 59 READY 62 63 39 38 READ (Write) DAL0-15 DATA IN NOTES: 1. Input setup and hold times are the minimum values required to or from the particular edge specified in order to be recognized in that cycle. 2. Output delay times are from the specified edge to a valid output. 52/56 MK50H27 ORDERING INFORMATION MK50H27 Q XX SPEED SORT 25 = 25MHz SYSCLK PACKAGE N = Plastic DIP (48 Pins) Q = Plastic J-Leaded Chip Carrier (52 Pins) PART# PROTOCOL 50H27 = SS7 Layer 2 protocol 53/56 MK50H27 DIP48 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. MAX. MIN. TYP. a1 0.63 0.025 b 0.45 0.018 b1 0.23 b2 0.31 E 0.009 1.27 D 15.2 MAX. 0.012 0.050 62.74 16.68 2.470 0.598 0.657 e 2.54 0.100 e3 58.42 2.300 F 54/56 inch 14.1 0.555 I 4.445 0.175 L 3.3 0.130 MK50H27 PLCC52 PACKAGE MECHANICAL DATA DIM. mm TYP. MAX. A 4.20 5.08 A1 0.51 A3 2.29 3.30 0.090 0.13 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 D 19.94 20.19 0.785 0.795 D1 19.05 19.20 0.750 0.756 D2 17.53 18.54 0.690 0.730 C D3 MIN. inch MIN. TYP. MAX. 0.165 0.20 0.020 0.25 0.01 15.24 0.60 E 19.94 20.19 0.785 0.795 E1 19.05 19.20 0.750 0.756 17.53 18.54 0.690 0.730 E2 E3 15.24 0.60 e 1.27 0.05 L 0.64 0.025 L1 1.53 0.060 55/56 MK50H27 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGSTHOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1997 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 56/56