TLC320AD58C Data Manual Sigma-Delta Stereo Analog-to-Digital Converter SLAS102 May 1995 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. 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Copyright 1995, Texas Instruments Incorporated Contents Section Title Page 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 1–1 1–1 1–2 1–2 1–2 2 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Power-Down and Reset Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Differential Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Sigma-Delta Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 High-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Master-Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 2–1 2–1 2–1 2–2 2–3 2–3 2–3 2–3 2–3 2–3 2–4 2–5 3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range . . . . . 3.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Digital Interface, TA = 25°C, AVDD = DVDD = 5 V . . . . . . . . . . . . . . . . . . . . 3.3.2 Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Channel Characteristics, TA = 25°C, AVDD = DVDD = 5 V, fs = 48 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 3–1 3–1 3–2 3–2 3–2 3–3 3–3 4 Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1 5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 Appendix A Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 iii List of Illustrations Figure Title Page 2–1. 2–2. 2–3. 2–4. Power-Down Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Analog Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Master Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Slave Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 2–2 2–5 2–6 4–1. 4–2. 4–3. 4–4. 4–5. 4–6. SCLK to Fsync and DOUT – Master Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCLK to Fsync, DOUT, and LRClk – Master Modes 4 and 6 . . . . . . . . . . . . . . . . . . . . . SCLK to Fsync, DOUT, and LRClk – Master Mode 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . SCLK to Fsync, DOUT, and LRClk – Master Mode 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . SCLK to LRClk and DOUT – Slave Mode 0, Fsync High . . . . . . . . . . . . . . . . . . . . . . . . SCLK to Fsync, LRClk, and DOUT – Slave Mode 2, Fsync Controlled . . . . . . . . . . . . 4–1 4–1 4–1 4–2 4–2 4–2 5–1. TLC320AD58C Configuration Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2 5–2. TLC320AD58C External Digital Timing and Control-Signal Generation Schematic . 5–3 5–3. TLC320AD58C External Analog Input Buffer Schematic . . . . . . . . . . . . . . . . . . . . . . . . 5–4 List of Tables Table Title Page 2–1. Master-Clock to Sample-Rate Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 iv 1 Introduction The TLC320AD58C provides high-resolution signal conversion from analog to digital using oversampling sigma-delta technology. This device consists of two synchronous conversion paths. Also included is a decimation filter after the modulator as shown in the functional block diagram. Other functions provide analog filtering and on-chip timing and control. A functional block diagram of the TLC320AD58C is included in Section 1.2. Each block is described in the detailed description section. 1.1 Features • • • • • • • • • • • 1.2 Single 5-V Power Supply Sample Rates up to 48 kHz 18-Bit Resolution Signal-to-Noise Ratio (EIAJ) of 97 dB Dynamic Range of 95 dB Total Signal-to-Noise+Distortion of 95 dB Internal Reference Voltage (Vref) Serial-Port Interface Differential Architecture Power Dissipation of 200 mW. Power-Down Mode for Low-Power Applications One-Micron Advanced LinEPIC1Z Process Functional Block Diagram INLP Sigma-Delta Modulator INLM REFO Decimation Filter High-Pass Filter DOUT Fsync VREF REFI Serial Interface INRP Sigma-Delta Modulator INRM Decimation Filter High-Pass Filter LRClk OSFR OSFL MCLK CMODE CONTROL MODE(0 – 2) SCLK LinEPIC1Z is a trademark of Texas Instruments Incorporated. 1–1 1.3 Terminal Assignments DW PACKAGE (TOP VIEW) INLP INLM REFI AVDD AVSS AnaPD TEST1 MODE2 OSFL DigPD TEST2 CMODE MODE0 LRClk 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 INRP INRM REFO LGND Vlogic NC MODE1 OSFR MCLK DVSS DVDD Fsync DOUT SCLK NC – No internal connection 1.4 Ordering Information PACKAGE 1.5 TA SMALL OUTLINE (DW) 0°C to 70°C TLC320AD58CDW Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AnaPD 6 I Analog power-down mode. The analog power-down mode disables the analog modulators. The single-bit modulator outputs become invalid, rendering the outputs of the digital filters invalid. When AnaPD is pulled high, normal operation of the device is resumed. AVDD AVSS 4 I Analog supply voltage 5 I Analog ground CMODE 12 I Clock mode. CMODE is used to select between two methods of determining the master clock frequency. When CMODE is high, the master clock input is 384× the conversion frequency. When CMODE is low, the master clock input is 256× the conversion frequency. DOUT 16 O Data output. DOUT is used to transmit the sigma-delta audio ADC output data to a DSP serial port or other compatible serial interface and is synchronized to SCLK. This output is low when DigPD is high. DVDD 18 I Digital supply voltage DVSS 19 I Digital ground DigPD 10 I Digital power-down mode. The digital power-down mode shuts down the digital filters and clock generators. All digital outputs are brought to unasserted states. When DigPD is pulled high, normal operation of the device is resumed. Fsync 17 I/O 1–2 Frame sync. Frame sync is used to designate the valid data from the ADC. 1.5 Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION INLM 2 I Inverting input to left analog input amplifier INLP 1 I Noninverting input to left analog input amplifier INRM 27 I Inverting input to right analog input amplifier INRP 28 I Noninverting input to right analog input amplifier LGND 25 I Logic power supply ground for analog modulator LRClk 14 I/O Left/right clock. LRClk signifies whether the serial data is associated with the left channel ADC (when LRClk is high) or the right channel ADC (when LRClk is low). LRClk is low when DigPD is low. MCLK 20 I Master clock. MCLK is used to derive all the key logic signals of the sigma-delta audio ADC. The nominal input frequency range is 18.432 MHz to 256 kHz. 13, 22, 8 I Serial modes. MODE(0–2) configure this device for many different modes of operation. The different configurations are: Master versus slave 16 bit versus 18 bit MSB first versus LSB first Slave: Fsync controlled versus Fsync high Each of these modes is described in the serial interface section along with timing diagrams. MODE MASTER/ MSB/LSB 0 1 2 SLAVE BITS FIRST 0 0 0 slave up to 18 MSB 0 0 1 slave 18 LSB 0 1 0 slave up to 18 MSB 0 1 1 master 16 MSB 1 0 0 master 18 MSB 1 0 1 master 18 LSB 1 1 0 master 16 MSB 1 1 1 master 16 LSB OSFL, OSFR 9, 21 O Over scale flag left/right. If the left/right channel digital output exceeds full scale output range for two consecutive conversions, this flag is set high for 4096 LRClk periods. OSFL and OSFR are low when DigPD is low. SCLK 15 I/O Shift clock. If SCLK is configured as an input, SCLK is used to clock serial data out of the sigma-delta audio ADC. If SCLK is configured as an output, SCLK stops clocking when DigPD is low. TEST1 7 I Test mode 1. TEST1 should be low for normal operation. TEST2 11 I Test mode 2. TEST2 should be low for normal operation. REFI 3 I Input voltage for modulator reference (normally connected to REFO, terminal 26). REFO 26 I Internal voltage reference Vlogic 24 I Logic power supply voltage (5 V) for analog modulator MODE(0–2) 1–3 1–4 2 Detailed Description The sigma-delta converter allows for simple antialias external filtering. Typically, a first order RC filter is sufficient. 2.1 2.1.1 Power-Down and Reset Functions Power Down The power-down state is comprised of a separate digital and analog power down. The power consumption of each is detailed in the electrical characteristics section. The digital power-down mode shuts down the digital filters and clock generators. All digital outputs are set to an unasserted level. When the digital power-down terminal is pulled high, normal operation of the device is initiated. In slave mode, the conversion process must synchronize to an input on the LRClk terminal as well as the SCLK terminal. Therefore, the conversion process is not initiated until the first rising edges of both SCLK and LRClk are detected after DigPD is pulled high. This synchronizes the conversion cycle; all conversions are performed at a fixed LRClk rate [MCLK/256 (CMODE low) or MCLK/384 (CMODE high)] after the initial synchronization. After the digital power-down terminal is brought high, the output of the digital filters remains invalid for 50 LRClk cycles [see Figures 2–1(a) and 2–1(b)]. In master mode, LRClk is an output; therefore, the conversion process initiates based on internal timing. The first valid data out occurs as shown in Figure 2–1(c). The analog power-down mode disables the analog modulators. The single-bit modulator outputs become invalid which renders the outputs of the digital filters invalid. When the analog power-down terminal is brought high, the modulators are brought back online; however, the outputs of the digital filters require 50 LRClk cycles for valid results. 2.1.2 Reset Function The conversion process is not initiated until the first rising edges of both SCLK and LRClk are detected after DigPD is pulled high. This synchronizes the conversion cycle; all conversions are performed at a fixed LRClk rate [MCLK/256 (CMODE low) or MCLK/384 (CMODE high)] after the initial synchronization. 2–1 tsu5 Slave-Mode Digital Power Down DigPD LRClk DOUT Data Valid (a) tsu6 Master-Mode Digital Power Down DigPD LRClk DOUT Data Valid (b) td1 Analog Power Down ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ AnaPD DOUT (c) Figure 2–1. Power-Down Timing Relationships 2.2 Differential Input The input is differential in order to provide common-mode noise rejection and increase the input dynamic range. Figure 2–2 shows the analog input signals used in a differential configuration to achieve a 6.4 VI(PP) differential swing with a 3.2 VI(PP) swing per input line. Both a differential and a single-ended configuration are shown in the application information section. TLC320AD58 4.1 V 2.5 V INLP, INRP 0.9 V 4.1 V 2.5 V INLM, INRM 0.9 V Figure 2–2. Differential Analog Input Configuration 2–2 2.3 Sigma-Delta Modulator The modulator is a fourth-order sigma-delta modulator with 64 times oversampling. The ADC provides high-resolution, low-noise performance from a one-bit converter using oversampling techniques. 2.4 Decimation Filter The decimation filter used after the sigma-delta modulator reduces the digital data rate to the sampling rate of LRClk. This is accomplished by decimating with a ratio of 1:64. The output of this filter is a 2s complement data word of up to 18 bits serially clocked out. If the input value exceeds the full range of the converter, the output of the decimator is held at the appropriate extreme until the input returns to the dynamic range of this device. 2.5 High-Pass Filter The high-pass filter removes dc from the input. 2.6 Master-Clock Circuit The master-clock circuit is used to generate and distribute necessary clocks throughout the device. MCLK is the external master clock input. CMODE is used to select the relationship of MCLK to the sample rate of LRClk. When CMODE is low, the sample rate of the data paths is set as LRClk = MCLK/256. When CMODE is high, the sample rate is set as LRClk = MCLK/384. With a fixed oversampling ratio of 64×, the effect of changing MCLK is shown in Table 2–1. When the TLC320AD58C is in master mode, SCLK is derived from MCLK in order to provide clocking of the serial communications between the sigma-delta audio ADC and a digital signal processor (DSP) or control logic. This is equivalent to a clock running at 64 × LRClk. When the TLC320AD58C is in slave mode, SCLK is externally derived. Table 2–1. Master-Clock to Sample-Rate Comparison (Modes 1, 3, 4, 5) 2.7 MCLK (MHz) CMODE 12.2880 Low 18.4320 High 11.2896 Low 16.9344 High 8.1920 Low 12.2880 High 0.2560 Low 0.3840 High SCLK (MHz) LRClk (kHz) 3 0720 3.0720 48 2 8224 2.8224 44 1 44.1 2 0480 2.0480 32 0 0640 0.0640 1 Test TEST1 and TEST2 are reserved for factory test and should be tied to digital ground (DVSS). 2.8 Serial Interface Although the serial data is shifted out in two seperate time packets that represent the left and right channels, the inputs are sampled and converted simultaneously. The serial interface protocol has master and slave modes each with different read out modes. The master mode is used to source the control signals for conversion synchronization, while the slave mode allows an external controller to provide conversion synchronization signals. The five master modes are shown in Figures 2–3(a) through 2–3(e), and the three slave modes are shown in Figures 2–4(a) through 2–4(c). For a 16-bit word, D15 is the most significant bit and D0 is the least significant bit. Unless otherwise specified, all values are in 2s complement format. 2–3 In master mode, SCLK is generated internally and is sourced as an output. The relationship of SCLK to LRClk is 64× (modes 1, 3, 4, 5) or 32× (modes 6, 7). In slave mode, SCLK is an input. SCLK timing must meet the timing specifications shown in the recommended operating conditions section. 2.8.1 Master Mode As the master, the TLC320AD58C generates LRClk, Fsync, and SCLK from MCLK. These signals are provided for synchronizing the serial port of a digital signal processor (DSP) or other control devices. Fsync is used to designate the valid data from the ADC, and this is accomplished in the master modes by one of two methods. The first is a single pulse on Fsync prior to valid data. This indicates the starting point for the data. The second method of frame synchronization is to hold Fsync high during the entire valid data cycle, which provides boundaries for the data. LRClk is generated internally from MCLK. The frequency of this signal is fixed at the sampling frequency fs [MCLK/256 (CMODE low) or MCLK/384 (CMODE high)]. During the high period of this signal, the left channel data is serially shifted to the output; during the low period, the right channel data is shifted to the output. The conversion cycle is synchronized with the rising edge of LRClk. Five modes are available when the device is configured as a master. Two modes are for 18-bit communications. These modes differ from each other in that the MSB is transferred first in one mode while the LSB is transferred first in the second mode [see Figures 2–3(b) and 2–3(c)]. When the LSB is transferred first, the data is right justified to the LRClk [see Figures 2–3(a) through 2–3(e)]. The three other master modes are 16-bit modes. Once again, two of the modes differ as MSB first versus LSB first. These two modes set SCLK = LRClk × 32. This is half the frequency used in the other transfer modes [see Figures 2–3(d) and 2–3(e)]. The third 16-bit mode provides the data MSB first with one clock delay after LRClk [see Figure 2–3(a)]. 2–4 Mode 011 (a) 16-BIT MASTER MODE (Fsync bound) SCLK Fsync DOUT 15 14 ... 1 0 15 ... 14 1 0 64 SCLKs LRClk Right Left Mode 100 (b) 18-BIT MASTER MODE SCLK Fsync 17 16 DOUT LRClk ... 1 0 17 16 ... 1 0 0 1 17 64 SCLKs Right Left (c) 18-BIT MASTER MODE Mode 101 SCLK Fsync ... 0 1 DOUT LRClk 16 17 ... 16 17 64 SCLKs Right Left Mode 110 (d) 16-BIT DSP CONTINUOUS MODE SCLK Fsync DOUT 15 14 ... 1 0 15 14 ... 1 0 ... 14 15 15 32 SCLKs LRClk Right Left Mode 111 (e) 16-BIT DSP CONTINUOUS MODE SCLK Fsync 0 DOUT 1 ... 14 15 0 1 0 32 SCLKs LRClk Left Right Figure 2–3. Serial Master Transfer Modes 2.8.2 Slave Mode As a slave, the TLC320AD58C receives LRClk, Fsync, and SCLK as inputs. The conversion cycle is synchronized to the rising edge of LRClk, and the data is synchronized to the falling edge of SCLK. SCLK must meet the setup requirements specified in the recommended operating conditions section. Synchronization of the slave modes is accomplished with the digital power-down control. In slave mode, Fsync is an input. Three modes are provided as shown in Figures 2–4(a) through 2–4(c). SCLK and LRClk are externally generated and sourced. The first rising edges of SCLK and LRClk after a power-down cycle initiate the conversion cycle. Refer to the master-mode section for signal functions. 2–5 Several modes are available when the TLC320AD58C is configured as a slave. Using the Mode0, Mode1, and Mode2 terminals, the TLC320AD58C can be set to shift out the MSB first or the LSB first [see Figures 2–4(a) and 2–4(b)]. The number of bits shifted out, however, can be controlled by the number of valid SCLK cycles provided within the left or right channel period. If only enough clocks are provided to shift out 16 data bits before LRClk changes state, then this is equivalent to a 16-bit mode. Modes 1 and 2 both require 64 SCLK periods per LRClk period. (a) 18-BIT SLAVE MODE (Fsync high) Mode 000 SCLK input Fsync DOUT input output LRClk input 17 16 ... 1 0 17 16 32 – 128 SCLKs Right Left ... 1 0 (b) 18-BIT SLAVE MODE (Fsync high) Mode 001 SCLK Fsync DOUT LRClk 0 1 ... 16 0 17 1 ... 64 SCLKs Right Left (c) 18-BIT SLAVE MODE (Fsync controlled) Mode 010 SCLK Fsync_1 DOUT_1 17 ... 0 17 17 ... 0 17 ... 0 Fsync_2 DOUT_2 LRClk Left 32 – 128 SCLKs Right Figure 2–4. Serial Slave Transfer Modes 2–6 ... 0 16 17 3 Specifications 3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)† Supply voltage range, AVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 6.5 V Supply voltage range, DVDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 6.5 V Analog input voltage range, INLP, INLM, INRP, INRM . . . . . . . . . . . . . . . – 0.3 V to 6.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Case temperature for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values for maximum ratings are with respect to AVSS. 2. Voltage values for maximum ratings are with respect to DVSS. 3.2 Recommended Operating Conditions MIN NOM MAX UNIT Analog supply voltage, AVDD (see Note 3) 4.75 5 5.25 V Digital supply voltage, DVDD 4.75 5 5.25 V Analog logic supply voltage, Vlogic 4.75 5 5.25 V Reference voltage, Vref 3.2 V Setup time, SCLK↑ to LRClk, slave mode, tsu1 30 ns Setup time, LRClk to SCLK↑, slave mode, tsu2 30 ns Setup time, SCLK↑ to Fsync, slave mode, tsu3 30 ns Setup time, Fsync to SCLK↑, slave mode, tsu4 30 ns Setup time, DigPD to LRClk↑, slave mode, tsu5 30 ns Setup time, DigPD to LRClk↑, master mode, tsu6 30 ns Load resistance at DOUT, RL Input dc offset range 10 – 50 kΩ 0 50 mV Operating free-air temperature, TA 0 NOTE 3: Voltages at analog inputs and outputs and AVDD are with respect to the AVSS terminal. 70 °C 3–1 3.3 Electrical Characteristics 3.3.1 Digital Interface, TA = 25°C, AVDD = DVDD = 5 V PARAMETER TEST CONDITIONS MIN TYP 2 4.6 MAX UNIT VIH VIL High-level input voltage VOH VOL High-level output voltage at DOUT IIH IIL High-level input current, any digital input 1 µA Low-level input current, any digital input 1 µA Ci Input capacitance 5 pF Co Output capacitance 5 pF 3.3.2 Low-level input voltage 0.2 IOH = 2 mA IOL = 2 mA Low-level output voltage at DOUT 2.4 V 0.8 4.6 0.2 V V 0.4 V Analog Interface 3.3.2.1 ADC Modulator, TA = 25°C, AVDD = DVDD = 5 V, fs = 48 kHz, Bandwidth = 24 kHz, CMODE = 0, MODE(0 – 2) = 000 PARAMETER TEST CONDITIONS MIN TYP Resolution DYNAMIC PERFORMANCE ANSI A-weighting filter Signal to noise (EIAJ) INLP = INRP = 2.5 V dc INLM = INRM = 2.5 V dc Dynamic range Signal to noise + distortion (THD + N) 1 dB down d f –1 from 6-V differential in ut input Total harmonic distortion (THD) MAX UNIT 18 Bits 96 100 dB 90 95 dB 93 dB 88 0.0015% Interchannel isolation 120 dB ± 0.6 dB DC ACCURACY Absolute gain error ± 0.2 dB 120 ± 5 mV ± 0.17 LSB/°C Interchannel gain mismatch Offset error (18-bit resolution) Offset drift 3.3.2.2 Inputs/Supplies, TA = 25°C, AVDD = DVDD = 5 V, fs = 48 kHz, Bandwidth = 24 kHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Input voltage range (differential) 6.2 (0 to peak) 3.1 Input impedance V 200 kΩ POWER SUPPLIES Power supply current Power-supply Power dissipation 3–2 IDD (analog), normal mode IDD (digital), normal mode 24 32 mA 26 32 mA IDD (analog), power down IDD (digital), power down 250 µA 150 µA 250 mW 3.3 Electrical Characteristics (Continued) 3.3.3 Channel Characteristics, TA = 25°C, AVDD = DVDD = 5 V, fs = 48 kHz PARAMETER TEST CONDITIONS Passband (– 3 dB) MIN 0.001 Passband ripple 30 Hz – 21.8 kHz Stopband attenuation 26.2 kHz – 3046 kHz MAX 24 ± 0.01 UNIT kHz dB 80 Group delay 3.4 TYP dB 25/fs s Switching Characteristics PARAMETER MIN TYP MAX 30 UNIT td1 td(MFSD) Delay time, AnaPD to DOUT valid ns Delay time, SCLK↓ to Fsync, master mode – 20 20 ns td(MDD) td(MIRD) Delay time, SCLK↓ to DOUT, master mode 0 50 ns Delay time, SCLK↓ to LRClk, master mode – 20 20 ns td(SDD1) td(SDD2) Delay time, LRClk to DOUT, slave mode 50 ns Delay time, SCLK↓ to DOUT, slave mode 50 ns 3–3 3–4 4 Parameter Measurement Information SCLK td(MFSD) Fsync td(MDD) DOUT MSB MSB – 1 ... LRClk Figure 4–1. SCLK to Fsync and DOUT – Master Mode 3 SCLK td(MFSD) Fsync td(MDD) DOUT MSB MSB – 1 ... td(MIRD) LRClk Figure 4–2. SCLK to Fsync, DOUT, and LRClk – Master Modes 4 and 6 SCLK td(MFSD) Fsync td(MDD) DOUT LSB LSB – 1 ... LRClk Figure 4–3. SCLK to Fsync, DOUT, and LRClk – Master Mode 5 4–1 SCLK td(MFSD) Fsync td(MDD) DOUT LSB ... LSB – 1 td(MIRD) LRClk Figure 4–4. SCLK to Fsync, DOUT, and LRClk – Master Mode 7 tsu1 tsu2 SCLK LRClk td(SDD2) td(SDD1) DOUT 17 ... 16 Figure 4–5. SCLK to LRClk and DOUT – Slave Mode 0, Fsync High tsu1 tsu3 tsu4 SCLK Fsync td(SDD2) DOUT 17 ... LRClk Figure 4–6. SCLK to Fsync, LRClk, and DOUT – Slave Mode 2, Fsync Controlled 4–2 1 5 Application Information 5–1 2 AVSS1 AVSS1 128 SN74HC14 LP 4700 pF AVSS1 LM 4700 pF AVSS1 RP 4700 pF 4700 pF 5–2 RM 5 EXFS EXLR 1 EXSK 3 7 DVDD2 TLC320AD58C 1 MCK 2Ω 2 1 0.1 µF OSC 3 4 47 µF DVSS2 DVDD2 SCLK DOUT 20 Fsync MCLK CMODE OSFL OSFR 14 10 kΩ DVSS1 DVDD1 2 kΩ 0.1 µF DATA SK 16 50 Ω DVDD1 17 9 21 2 kΩ 2 kΩ DVSS1 DVDD1 47 µF/25 V 0.1 µF DVSS1 AVDD1 47 µF/25 V 0.1 µF 0.1 µF AVSS1 50 Ω AVDD1 47 µF/25 V 50 Ω AVDD1 SCK 15 18 MODE0 DV DD 22 MODE1 8 19 MODE2 DVSS 4 11 TEST2 AVDD 7 TEST1 5 10 DigPD AVSS 24 6 AnaPD Vlogic 3 REFI 25 26 REFO LGND 10 kΩ LRCK LR 50 Ω 13 10 kΩ DigRET 2 INLM 28 INRP 27 INRM 12 10 kΩ 1 2 DIP SWITCH 3 4 LRClk 50 Ω DVSS2 10 kΩ 10 kΩ DVDD1 INLP 128/FSNC 220 µF AVSS1 Figure 5–1. TLC320AD58C Configuration Schematic AVSS1 EXSK SK DVDDL SN74HC163 128 3 SN74HC163 3 DVDDL SN74HC164 DIGRET 47 µF/25 V 1 D Q CK QX CL 2 9 8 A QA B QB CL QC CK QD QE QF QG QH 3 4 5 6 A 4 B DVSSL 5 C 6 D 7 DVDDL 10 ENP ENT 9 LOAD 1 CL 2 CK 4 14 QA 13 QB 12 QC QD 11 15 RCO DVSSL 5 DVDDL 6 7 10 9 1 2 A B C D ENP 14 QA 13 QB 12 QC QD 11 RCO 15 EXLR ENT LOAD CL CK 10 11 LR 12 13 DVDDL MCK PCLR 9 Q P D CK CL Q P D CK CL SN74HC74 Figure 5–2. TLC320AD58C External Digital Timing and Control-Signal Generation Schematic SN74HC74 DVDDL 5–3 1 2 5–4 Optional Optional 0.1 µF 0.1 µF TL32088 1 AVSS2 100 µF/25 V 2 3 47 µF/25 V REFL REFR1 AVSS INRP INLP INRM INLM OUTR 19 100 µF/50 V AVSS2 47 µF/25 V 5 kΩ 18 AINR BNC 10 kΩ 5 kΩ 4 AINL BNC 10 kΩ 50 kΩ 20 100 kΩ 5 OUTL REFR2 6 REFL FLTR1 FLTL1 FLTR2 FLTL2 AOUTRM 100 pF AVSS2 17 100 kΩ 50 kΩ 100 P 16 AVSS2 15 200 pF 7 14 200 pF 8 9 10 Check Pin AOUTLM AOUTRP AVDD AOUTLP 13 12 AVDD2 11 Check Pin 0.1 µF 100 µF/50 V 100 µF/50 V 100 µF/50 V LM LP 100 µF/50 V 100 µF/50 V RP Figure 5–3. TLC320AD58C External Analog Input Buffer Schematic RM Appendix A Mechanical Data DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PIN SHOWN PINS ** 0.050 (1,27) 16 20 24 28 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) 0.700 (17,78) DIM 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.293 (7,45) 0.010 (0,25) NOM Gage Plane 0.010 (0,25) 1 8 0°– 8° A 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) 0.004 (0,10) 4040000 / B 10/94 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). 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