STMICROELECTRONICS PSD813F1-A-90MI

PSD813F1-A
Flash In-System Programmable (ISP) Peripherals
For 8-bit MCUs
PRELIMINARY DATA
FEATURES SUMMARY
■ Single Supply Voltage:
Figure 1. Packages
– 5 V±10% for PSD813F1-A
– 3.3 V±10% for PSD813F1-AV
■
Up to 1Mbit of Primary Flash Memory (8 uniform
sectors)
■
256Kbit Secondary EEPROM (4 uniform
sectors)
■
Up to 16Kbit SRAM
■
Over 3,000 Gates of PLD: DPLD and CPLD
■
27 Reconfigurable I/O ports
■
Enhanced JTAG Serial Port
■
Programmable power management
■
High Endurance:
PQFP52 (T)
– 100,000 Erase/Write Cycles of Flash Memory
– 10,000 Erase/Write Cycles of EEPROM
– 1,000 Erase/Write Cycles of PLD
PLCC52 (K)
January 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/3
Revision A Flash PSD
PSD813F1-A
Flash In-System-Programmable Microcontroller Peripherals
Table of Contents
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
i
Introduction ...........................................................................................................................................................1
Key Features ........................................................................................................................................................2
PSD813F1 Block Diagram .............................................................................................................................4
General Information ..............................................................................................................................................5
PSD813F1 Family.................................................................................................................................................5
PSD813F1 Architectural Overview .......................................................................................................................6
5.1 Memory...................................................................................................................................................6
5.2 Page Register .........................................................................................................................................6
5.3 PLDs .......................................................................................................................................................6
5.4 I/O Ports..................................................................................................................................................7
5.5 Microcontroller Bus Interface ..................................................................................................................7
5.6 JTAG Port ...............................................................................................................................................7
5.7 In-System Programming .........................................................................................................................8
5.8 Power Management................................................................................................................................8
Development System............................................................................................................................................9
PSD813F1 Pin Descriptions ...............................................................................................................................10
PSD813F1 Register Description and Address Offset .........................................................................................14
PSD813F1 Functional Blocks .............................................................................................................................15
9.1 Memory Blocks .....................................................................................................................................15
9.1.1 Main Flash and Secondary EEPROM ........................................................................................15
9.1.2 SRAM .........................................................................................................................................29
9.1.3 Memory Select Signals...............................................................................................................29
9.1.4 Page Register.............................................................................................................................32
9.2 PLDs .....................................................................................................................................................33
9.2.1 Decode PLD (DPLD) ..................................................................................................................35
9.2.2 Complex PLD (CPLD) ................................................................................................................35
9.3 Microcontroller Bus Interface ................................................................................................................44
9.3.1 PSD813F Interface to a Multiplexed 8-bit Bus ...........................................................................44
9.3.2 PSD813F Interface to a Non-Multiplexed 8-bit Bus....................................................................44
9.3.3 Data Byte Enable Reference......................................................................................................47
9.3.4 Microcontroller Interface Examples ............................................................................................47
9.4 I/O Ports................................................................................................................................................52
9.4.1 General Port Architecture...........................................................................................................52
9.4.2 Port Operating Modes ................................................................................................................54
9.4.3 Port Configuration Registers (PCRs) .........................................................................................57
9.4.4 Port Data Registers ....................................................................................................................60
9.4.5 Ports A and B – Functionality and Structure ............................................................................61
9.4.6 Port C – Functionality and Structure ........................................................................................63
9.4.7 Port D – Functionality and Structure ........................................................................................63
9.5 Power Management..............................................................................................................................67
9.5.1 Automatic Power Down (APD) Unit and Power Down Mode .....................................................67
9.5.2 Other Power Saving Options......................................................................................................71
9.5.3 Reset and Power On Requirement ............................................................................................72
Revision A Flash PSD
PSD813F1-A
Flash In-System-Programmable Microcontroller Peripherals
Table of Contents
(cont.)
9.6 Programming In-Circuit Using the JTAG Interface ...............................................................................73
9.6.1 Standard JTAG Signals..............................................................................................................74
9.6.2 JTAG Extensions........................................................................................................................75
9.6.3 Security and Flash Memories and EEPROM Protection ............................................................75
Absolute Maximum Ratings.........................................................................................................................................76
AD/DC Parameters......................................................................................................................................................77
Example of PSD813F Typical Power Calculation at VCC = 5.0 V.......................................................................78
PSD813F1 DC Characteristics (5 V ± 10% Versions) ........................................................................................80
PSD813F1 AD/DC Parameters – CPLD Timing Parameters (5 V ± 10% versions) .........................................81
PSD813F1V DC Characteristics (3 V Versions) .................................................................................................91
PSD813F1V AC/DC Parameters – CPLD Timing Parameters (3 V versions) .................................................92
Timing Diagrams .......................................................................................................................................................100
Programming .............................................................................................................................................................107
PSD813F1 Pin Assignments .....................................................................................................................................108
PSD813F1 Package Information ...............................................................................................................................110
Selector Guide...........................................................................................................................................................113
Part Number Construction .........................................................................................................................................114
Ordering Information..................................................................................................................................................114
Product Revisions......................................................................................................................................................115
For additional information,
Call 800-832-6974
Fax: 510-657-8495
Web Site: http://www.psdst.com
E-mail: [email protected]
ii
PSD813F1-A Family
Preliminary
For additional information,
Call 800-832-6974
Fax: 510-657-8495
Web Site: http://www.psdst.com
E-mail: [email protected]
iii
Programmable Peripheral
Revision A Flash PSD
PSD813F1-A
Preliminary
1.0
Introduction
Flash In-System-Programmable
Microcontroller Peripherals
The PSD813F1 family of Programmable Microcontroller (MCU) Peripherals brings
In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a
simple and flexible solution for embedded designs. PSD813F1 devices combine many of
the peripheral functions found in MCU based applications:
• 1 Mbit of Flash memory
• A second EEPROM memory
• Over 3,000 gates of Flash programmable logic
• SRAM
• Reconfigurable I/O ports
• Programmable power management.
PSD813F1 devices integrate an optimized “microcontroller macrocell” logic architecture
called the Micro⇔CellTM. The Micro⇔Cell was created to address the unique requirements
of embedded system designs. It allows direct connection between the system address/data
bus and the internal PSD registers to simplify communication between the MCU and other
supporting devices.
1
PSD813F1-A
Preliminary
1.0
Introduction
The PSD813F1 family offers two methods to program PSD Flash memory while the PSD is
soldered to a circuit board.
(Cont.)
❏ In-System Programming (ISP) JTAG
An IEEE 1149.1 compliant JTAG interface is included on the PSD enabling the entire
device (Flash memory, EEPROM, the PLD, and all configuration) to be rapidly
programmed while soldered to the circuit board. This requires no MCU participation,
which means the PSD can be programmed anytime, even while completely blank.
The innovative JTAG interface to flash memories is an industry first, solving key
problems faced by designers and manufacturing houses, such as:
• First time programming – How do I get firmware into the flash the very first time?
JTAG is the answer, program the PSD while blank with no MCU involvement.
• Inventory build-up of pre-programmed devices – How do I maintain an accurate
count of pre-programmed flash memory and PLD devices based on customer
demand? How many and what version? JTAG is the answer, build your hardware
with blank PSDs soldered directly to the board and then custom program just before
they are shipped to customer. No more labels on chips and no more wasted
inventory.
• Expensive sockets – How do I eliminate the need for expensive and unreliable
sockets? JTAG is the answer. Solder the PSD directly to the circuit board. Program
first time and subsequent times with JTAG. No need to handle devices and bend the
fragile leads.
❏ In-Application Programming (IAP)
Two independent memory arrays (Flash and EEPROM) are included so the MCU can
execute code from one memory while erasing and programming the other. Robust
product firmware updates in the field are possible over any communication channel
(CAN, Ethernet, UART, J1850, etc) using this unique architecture. Designers are
relieved of these problems:
• Simultaneous read and write to flash memory – How can the MCU program the
same memory from which it is executing code? It cannot. The PSD allows the MCU
to operate the two memories concurrently, reading code from one while erasing and
programming the other during IAP.
• Complex memory mapping – I have only a 64K-byte address space to start with.
How can I map these two memories efficiently? A Programmable Decode PLD is the
answer. The concurrent PSD memories can be mapped anywhere in MCU address
space, segment by segment with extremely high address resolution. As an option,
the secondary flash memory can be swapped out of the system memory map when
IAP is complete. A built-in page register breaks the 64K-byte address limit.
• Separate program and data space – How can I write to flash or EEPROM memory
while it resides in “program” space during field firmware updates, my MCU won’t
allow it! The flash PSD provides means to “reclassify” flash or EEPROM memory as
“data” space during IAP, then back to “program” space when complete.
PSDsoft — ST’s software development tool — now has the ability to generate
ANSI-C compliant code for use with your target MCU. The code generated allows you to
manipulate the non-volatile memory (NVM) within the PSD. Code examples are also
provided for:
• Flash ISP via the UART of the host MCU
• Memory paging to execute code across several PSD memory pages
• Loading, reading, and manipulation of PSD Micro⇔Cells by the MCU
The PSD813F1 is available in a 52-pin PLCC package and a 64-pin plastic Thin Quad
Flatpack (TQFP) package.
2
Preliminary
2.0
Key Features
PSD813F1-A
❏ A simple interface to 8-bit microcontrollers that use either multiplexed or
non-multiplexed busses. The bus interface logic uses the control signals generated by
the microcontroller automatically when the address is decoded and a read or write is
performed. A partial list of the MCU families supported include:
•
•
•
•
Intel 8031, 80196, 80186, 80C251, and 80386EX
Motorola 68HC11, 68HC16, 68HC12, and 683XX
Philips 8031 and 8051XA
Zilog Z80 and Z8
❏ Internal 1 Mbit Flash memory. This is the main Flash memory. It is divided into eight
equal-sized blocks that can be accessed with user-specified addresses.
❏ Internal secondary 256 Kbit EEPROM memory. It is divided into four equal-sized blocks
that can be accessed with user-specified addresses. This secondary memory brings
the ability to execute code and update the main Flash concurrently.
❏ 16 Kbit scratchpad SRAM. The SRAM’s contents can be protected from a power failure
by connecting an external battery.
❏ Optional 64 byte One Time Programmable (OTP) memory that can be used for product
configuration and calibration.
❏ CPLD with 16 Output Micro⇔Cells (OMCs) and 24 Input Micro⇔Cells (IMCs). The
CPLD may be used to efficiently implement a variety of logic functions for internal
and external control. Examples include state machines, loadable shift registers, and
loadable counters.
❏ Decode PLD (DPLD) that decodes address for selection of internal memory blocks.
The DPLD can also be used to generate external chip selects.
❏ 27 individually configurable I/O port pins that can be used for the following functions:
• MCU I/Os
• PLD I/Os
• Latched MCU address output
• Special function I/Os.
• 16 of the I/O ports may be configured as open-drain outputs.
❏ Standby current as low as 50 µA for 5 V devices, 25 µA for 3 V devices.
❏ Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
With it, you can program a blank device or reprogram a device in the factory or the field.
❏ Internal page register that can be used to expand the microcontroller address space by
a factor of 256.
❏ Internal programmable Power Management Unit (PMU) that supports a low power mode
called Power Down Mode. The PMU can automatically detect a lack of microcontroller
activity and put the PSD813F1 into Power Down Mode.
❏ Erase/Write cycles:
• Flash memory – 100,000 minimum
• EEPROM – 10,000 minimum
• PLD – 1,000 minimum
• Data Retention: 15 year minimum at 90 degrees Celsius (for Main Flash, Boot, PLD
and Configuration bits).
3
4
AD0 – AD15
CNTL0,
CNTL1,
CNTL2
CLKIN
GLOBAL
CONFIG. &
SECURITY
ADIO
PORT
PROG.
MCU BUS
INTRF.
PLD
INPUT
BUS
CLKIN
73
CSIOP
CLKIN
16 KBIT BATTERY
BACKUP SRAM
256 KBIT SECONDARY
MEMORY (BOOT OR DATA)
4 SECTORS
EEPROM – F1
8 SECTORS
1 MBIT MAIN FLASH
MEMORY
PLD, CONFIGURATION
& FLASH MEMORY
LOADER
JTAG
SERIAL
CHANNEL
PORT A ,B & C
24 INPUT MICRO⇔CELLS
PORT A ,B & C
16 OUTPUT MICRO⇔CELLS
3 EXT CS TO PORT D
RUNTIME CONTROL
AND I/O REGISTERS
PERIP I/O MODE SELECTS
SRAM SELECT
SECTOR
SELECTS
FLASH ISP CPLD
(CPLD)
FLASH DECODE
PLD (DPLD)
SECTOR
SELECTS
EMBEDDED
ALGORITHM
MICRO⇔CELL FEEDBACK OR PORT INPUT
73
PAGE
REGISTER
ADDRESS/DATA/CONTROL BUS
PORT
D
PROG.
PORT
PORT
C
PROG.
PORT
PORT
B
PROG.
PORT
PORT
A
PROG.
PORT
POWER
MANGMT
UNIT
PD0 – PD2
PC0 – PC7
PB0 – PB7
PA0 – PA7
VSTDBY
(PC2)
PSD813F1-A
Preliminary
Figure 1. PSD813F1 Block Diagram
Preliminary
PSD813F1-A
3.0
General
Information
The PSD813F1 series architecture allows In-System Programming of all Memory, PLD
Logic and Device Configuration. The embedded Input and Output Micro⇔Cells enable
efficient implementation of user defined logic functions that require both software and
hardware interaction. The devices eliminate the need for discrete ‘glue’ logic, and allow the
development of entire systems using only a few highly integrated devices.
4.0
PSD813F1
Family
All PSD813F1 devices provide these features: 1 Mbit main Flash Memory, JTAG port,
CPLD, DPLD, power management, and 27 I/O pins. The PSD813F1 also adds 64 bytes of
OTP memory for any use (product serial number, calibration constants, etc.). Once written,
the OTP memory can never be altered.
The following table summarizes the PSD813F1:
Table 1. PSD813F1 Product Matrix
Part #
PSD813F1
Family
Device
I/O
Pins
No. of
Serial ISP
Micro⇔Cells JTAG/ISC
Input/Output
Port
Flash
Main Memory
Kbit
(8 Sectors)
Additional
Memory for
Boot and/or Data
(4 Sectors)
SRAM
Kbit
Turbo
Mode
Supply
Voltage
PSD813F1
PSD813F1
27
24/16
Yes
1024
256 Kbit EEPROM
16
Yes
5V
PSD813F1V
PSD813F1V
27
24/16
Yes
1024
256 Kbit EEPROM
16
Yes
3V
5
PSD813F1-A
5.0
PSD813F1
Architectural
Overview
Preliminary
PSD813F1 devices contain several major functional blocks. Figure 1 on page 3 shows the
architecture of the PSD813F1 device. The functions of each block are described briefly in
the following sections. Many of the blocks perform multiple functions and are user configurable.
5.1 Memory
The PSD813F1 contains the following memories:
• A 1 Mbit Flash
• A secondary 256 Kbit EEPROM memory
• A 16 Kbit SRAM.
Each of the memories is briefly discussed in the following paragraphs. A more detailed
discussion can be found in section 9.
The 1 Mbit Flash is the main memory of the PSD813F1. It is divided into eight equally-sized
sectors that are individually selectable.
The 256 Kbit EEPROM or Flash is divided into four equally-sized sectors. Each sector is
individually selectable.
The 16 Kbit SRAM is intended for use as a scratchpad memory or as an extension to the
microcontroller SRAM. If an external battery is connected to the PSD813F1’s Vstby pin,
data will be retained in the event of a power failure.
Each block of memory can be located in a different address space as defined by the user.
The access times for all memory types includes the address latching and DPLD decoding
time.
5.2 Page Register
The eight-bit Page Register expands the address range of the microcontroller by up to
256 times.The paged address can be used as part of the address space to access external
memory and peripherals or internal memory and I/O. The Page Register can also be used
to change the address mapping of blocks of Flash memory into different memory spaces for
in-circuit reprogramming.
5.3 PLDs
The device contains two PLD blocks, each optimized for a different function, as shown in
Table 2. The functional partitioning of the PLDs reduces power consumption, optimizes
cost/performance, and eases design entry.
The Decode PLD (DPLD) is used to decode addresses and generate chip selects for the
PSD813F1 internal memory and registers. The CPLD can implement user-defined logic
functions. The DPLD has combinatorial outputs. The CPLD has 16 Output Micro⇔Cells
and 3 combinatorial outputs. The PSD813F1 also has 24 Input Micro⇔Cells that can be
configured as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus
and are differentiated by their output destinations, number of Product Terms, and
Micro⇔Cells.
The PLDs consume minimal power by using Zero-Power design techniques. The speed
and power consumption of the PLD is controlled by the Turbo Bit (ZPSD only) in the
PMMR0 register and other bits in the PMMR2 registers. These registers are set by the
microcontroller at runtime. There is a slight penalty to PLD propagation time when invoking
the ZPSD features.
Table 2. PLD I/O Table
Name
6
Abbreviation
Inputs
Outputs
Product Terms
Decode PLD
DPLD
73
17
42
Complex PLD
CPLD
73
19
140
Preliminary
PSD813F1
Architectural
Overview
(cont.)
PSD813F1-A
5.4 I/O Ports
The PSD813F1 has 27 I/O pins divided among four ports (Port A, B, C, and D). Each
I/O pin can be individually configured for different functions. Ports A, B, C and D can be
configured as standard MCU I/O ports, PLD I/O, or latched address outputs for
microcontrollers using multiplexed address/data busses.
The JTAG pins can be enabled on Port C for In-System Programming (ISP).
Ports A and B can also be configured as a data port for a non-multiplexed bus or
multiplexed Address/Data buses for certain types of 16-bit microcontrollers.
5.5 Microcontroller Bus Interface
The PSD813F1 easily interfaces with most 8-bit microcontrollers that have either
multiplexed or non-multiplexed address/data busses. The device is configured to respond to
the microcontroller’s control signals, which are also used as inputs to the PLDs. Where
there is a requirement to use a 16-bit data bus to interface to a 16-bit microcontroller, two
PSDs must be used. Section 9.3.5 contains microcontroller interface examples.
5.6 JTAG Port
In-System Programming can be performed through the JTAG pins on Port C. This serial
interface allows complete programming of the entire PSD813F1 device. A blank device can
be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can
be multiplexed with other functions on Port C. Table 3 indicates the JTAG signals pin
assignments.
Table 3. JTAG Signals on Port C
Port C Pins
JTAG Signal
PC0
TMS
PC1
TCK
PC3
TSTAT
PC4
TERR
PC5
TDI
PC6
TDO
7
PSD813F1-A
PSD813F1
Architectural
Overview
(cont.)
Preliminary
5.7 In-System Programming
Using the JTAG signals on Port C, the entire PSD813F1 device can be programmed or
erased without the use of the microcontroller. The main Flash memory can also be
programmed in-system by the microcontroller executing the programming algorithms out
of the EEPROM or SRAM. The EEPROM can be programmed the same way by executing
out of the main Flash memory. The PLD logic or other PSD813F1 configuration can be
programmed through the JTAG port or a device programmer. Table 4 indicates which
programming methods can program different functional blocks of the PSD813F1.
Table 4. Methods of Programming Different Functional Blocks of the PSD813F1
Functional Block
JTAG
Programming
Device
Programmer
In-System Parallel
Programming
Main Flash memory
Yes
Yes
Yes
EEPROM memory
Yes
Yes
Yes
PLD Array (DPLD and CPLD)
Yes
Yes
No
PSD Configuration
Yes
Yes
No
Optional OTP Row
No
Yes
Yes
5.8 Power Management Unit
The Power Management Unit (PMU) in the PSD813F1 gives the user control of the
power consumption on selected functional blocks based on system requirements. The PMU
includes an Automatic Power Down unit (APD) that will turn off device functions due to
microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce power
consumption.
The PSD813F1 also has some bits that are configured at run-time by the MCU to reduce
power consumption of the CPLD. The turbo bit in the PMMR0 register can be turned off and
the CPLD will latch its outputs and go to sleep until the next transition on its inputs.
Additionally, bits in the PMMR2 register can be set by the MCU to block signals from
entering the CPLD to reduce power consumption. See section 9.5.
8
Preliminary
6.0
Development
System
PSD813F1-A
The PSD813F1 is supported by PSDsoft a Windows-based (95, 98, NT) software
development tool. A PSD design is quickly and easily produced in a point and click
environment. The designer does not need to enter Hardware Definition Language (HDL)
equations (unless desired) to define PSD pin functions and memory map information. The
general design flow is shown in Figure 2 below. PSDsoft is available from our web site
(www.st.com/psm) or other distribution channels.
PSDsoft directly supports two low cost device programmers from ST, PSDpro
and FlashLINK (JTAG). Both of these programmers may be purchased through your local
rep/distributor, or directly from our web site using a credit card. The PSD813F1 is also
supported by third party device programmers, see web site for current list.
Figure 2. PSDsoft Development Tool
Choose MCU and PSD
Automatically Configures MCU
bus interface and other PSD
attributes.
Define PSD Pin and
Node functions
Point and click definition of
PSD pin functions, internal nodes,
and MCU system memory map.
Define General Purpose
Logic in CPLD
C Code Generation
Point and click definition of
combinatorial and registered logic
in CPLD. Access to HDL is
available if needed.
Generate C Code
Specific to PSD
Functions
Merge MCU Firmware
with PSD Configuration
A composite object file is created
containing MCU firmware and
PSD configuration.
MCU Firmware
Hex or S-Record
format
User's choice of
Microcontroller
Compiler/Linker
*.OBJ FILE
ST
PSD Programmer
PSDPro or
FlashLink (JTAG)
*.OBJ file
available
for 3rd party
programmers
(Conventional or JTAG-ISP)
9
PSD813F1-A
7.0
Table 5.
PSD813F1
Pin
Descriptions
10
Preliminary
The following table describes the pin names and pin functions of the PSD813F1. Pins that
have multiple names and/or functions are defined using PSD Configuration.
Pin Name
Pin* Type
Description
ADIO0-7
30-37
I/O
This is the lower Address/Data port. Connect your MCU
address or address/data bus according to the following rules:
1. If your MCU has a multiplexed address/data bus where
the data is multiplexed with the lower address bits,
connect AD[0:7] to this port.
2. If your MCU does not have a multiplexed address/data
bus, or you are using an 80C251 in page mode, connect
A[0:7] to this port.
3. If you are using an 80C51XA in burst mode, connect
A4/D0 through A11/D7 to this port.
ALE or AS latches the address. The PSD drives data out only
if the read signal is active and one of the PSD functional
blocks was selected. The addresses on this port are passed
to the PLDs.
ADIO8-15
39-46
I/O
This is the upper Address/Data port. Connect your MCU
address or address/data bus according to the following rules:
1. If your MCU has a multiplexed address/data bus where
the data is multiplexed with the lower address bits,
connect A[8:15] to this port.
2. If your MCU does not have a multiplexed address/data
bus, connect A[8:15] to this port.
3. If you are using an 80C251 in page mode, connect
AD[8:15] to this port.
4. If you are using an 80C51XA in burst mode, connect
A12/D8 through A19/D15 to this port.
ALE or AS latches the address. The PSD drives data out only
if the read signal is active and one of the PSD functional
blocks was selected. The addresses on this port are passed
to the PLDs.
CNTL0
47
I
The following control signals can be connected to this port,
based on your MCU:
1. WR — active-low write input.
2. R_W — active-high read/active low write input.
This port is connected to the PLDs. Therefore, these signals
can be used in decode and other logic equations.
CNTL1
50
I
The following control signals can be connected to this port,
based on your MCU:
1. RD — active-low read input.
2. E — E clock input.
3. DS — active-low data strobe input.
4. PSEN — connect PSEN to this port when it is being used
as an active-low read signal. For example, when the
80C251 outputs more than 16 address bits, PSEN is
actually the read signal.
This port is connected to the PLDs. Therefore, these
signals can be used in decode and other logic equations.
Preliminary
Table 5.
PSD813F1
Pin
Descriptions
PSD813F1-A
Pin Name Pin* Type
Description
CNTL2
49
I
This port can be used to input the PSEN (Program Select
Enable) signal from any MCU that uses this signal for code
exclusively. If your MCU does not output a Program Select
Enable signal, this port can be used as a generic input. This
port is connected to the PLDs.
Reset
48
I
Active low reset input. Resets I/O Ports, PLD Micro⇔Cells
and some of the configuration registers. Must be active at
power up.
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
29
28
27
25
24
23
22
21
I/O
These pins make up Port A. These port pins are configurable
and can have the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro⇔Cell (McellAB0-7) outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 6).
5. Address inputs. For example, PA0-3 could be used for
A[0:3] when using an 80C51XA in burst mode.
6. As the data bus inputs D[0:7] for non-multiplexed
address/data bus MCUs.
7. D0/A16-D3/A19 in M37702M2 mode.
8. Peripheral I/O mode.
Note: PA0-3 can only output CMOS signals with an option
for high slew rate. However, PA4-7 can be configured as
CMOS or Open Drain Outputs.
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7
6
5
4
3
2
52
51
I/O
These pins make up Port B. These port pins are configurable
and can have the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro⇔Cell (McellAB0-7 or McellBC0-7) outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 6).
Note: PB0-3 can only output CMOS signals with an option
for high slew rate. However, PB4-7 can be configured as
CMOS or Open Drain Outputs.
PC0
20
I/O
PC0 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro⇔Cell (McellBC0) output.
3. Input to the PLDs.
4. TMS Input** for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC1
19
I/O
PC1 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro⇔Cell (McellBC1) output.
3. Input to the PLDs.
4. TCK Input** for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
(cont.)
11
PSD813F1-A
Table 5.
PSD813F1
Pin
Descriptions
Preliminary
Pin Name Pin*
Type
Description
PC2
18
I/O
PC2 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro⇔Cell (McellBC2) output.
3. Input to the PLDs.
4. Vstby — SRAM standby voltage input for SRAM battery
backup.
This pin can be configured as a CMOS or Open Drain output.
PC3
17
I/O
PC3 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro⇔Cell (McellBC3) output.
3. Input to the PLDs.
4. TSTAT output** for the JTAG interface.
5. Rdy/Bsy output for in-system parallel programming.
This pin can be configured as a CMOS or Open Drain output.
PC4
14
I/O
PC4 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro⇔Cell (McellBC4) output.
3. Input to the PLDs.
4. TERR output** for the JTAG interface.
5. Vbaton — battery backup indicator output. Goes high
when power is being drawn from an external battery.
This pin can be configured as a CMOS or Open Drain output.
PC5
13
I/O
PC5 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro⇔Cell (McellBC5) output.
3. Input to the PLDs.
4. TDI input** for the JTAG interface.
This pin can be configured as a CMOS or Open Drain output.
PC6
12
I/O
PC6 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro⇔Cell (McellBC6) output.
3. Input to the PLDs.
4. TDO output** for the JTAG interface.
This pin can be configured as a CMOS or Open Drain output.
(cont.)
12
Preliminary
Table 5.
PSD813F1
Pin
Descriptions
PSD813F1-A
Pin Name
Pin*
Type
Description
PC7
11
I/O
PC7 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro⇔Cell (McellBC7) output.
3. Input to the PLDs.
4. DBE — active-low Data Byte Enable input from 68HC912
type MCUs.
This pin can be configured as a CMOS or Open Drain output.
PD0
10
I/O
PD0 pin of Port D. This port pin can be configured to have
the following functions:
1. ALE/AS input latches address output from the MCU.
2. MCU I/O — write or read from a standard output or input
port.
3. Input to the PLDs.
4. CPLD output (external chip select).
PD1
9
I/O
PD1 pin of Port D. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. Input to the PLDs.
3. CPLD output (external chip select).
4. CLKIN — clock input to the CPLD Micro⇔Cells, the
automatic power-down unit’s power-down counter, and
the CPLD AND array.
PD2
8
I/O
VCC
GND
15, 38
1,16,26
PD2 pin of Port D. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. Input to the PLDs.
3. CPLD output (external chip select).
4. CSI — chip select input. When low, the MCU can access
the PSD memory and I/O. When high, the PSD memory
blocks are disabled to conserve power.
Power pins
Ground pins
(cont.)
**The pin numbers in this table are for the PLCC package only. See the package information section for pin
numbers on other package types.
**These functions can be multiplexed with other functions.
Table 6. I/O Port Latched Address Output Assignments*
Microcontroller
Port A
Port A (3:0) Port A (7:4)
Port B
Port B (3:0)
Port B (7:4)
8051XA (8-bit)
80C251 (page mode)
N/A
N/A
Address [7:4]
N/A
Address [11:8] N/A
Address [11:8] Address [15:12]
All other 8-bit
multiplexed
8-bit non-multiplexed
bus
Address [3:0]
Address [7:4]
Address [3:0]
Address [7:4]
N/A
N/A
Address [3:0]
Address [7:4]
N/A = Not Applicable
** Refer to the I/O Port Section on how to enable the Latched Address Output function.
13
PSD813F1-A
8.0
PSD813F1
Register
Description
and Address
Offset
Preliminary
Table 7 shows the offset addresses to the PSD813F1 registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD813F1 registers. Table 7 provides brief descriptions of the registers in CSIOP
space. For a more detailed description, refer to section 9.
Table 7. Register Address Offset
Register Name Port A Port B Port C Port D Other*
Data In
00
01
10
11
Control
02
03
Data Out
04
05
12
13
Direction
06
07
14
15
Drive Select
08
09
16
17
Input Micro⇔Cell
0A
0B
18
Enable Out
0C
0D
1A
Output
Micro⇔Cells AB
20
20
Output
Micro⇔Cells BC
Mask
Micro⇔Cells AB
Mask
Micro⇔Cells BC
21
22
21
22
23
23
Flash Protection
C0
PSD/EE
Protection
C2
JTAG Enable
C7
PMMR0
B0
PMMR2
B4
Page
E0
VM
E2
*Other registers that are not part of the I/O ports.
14
1B
Description
Reads Port pin as input,
MCU I/O input mode
Selects mode between
MCU I/O or Address Out
Stores data for output
to Port pins, MCU I/O
output mode
Configures Port pin as
input or output
Configures Port pins as
either CMOS or Open
Drain on some pins, while
selecting high slew rate
on other pins.
Reads Input Micro⇔Cells
Reads the status of the
output enable to the I/O
Port driver
Read – reads output of
Micro⇔Cells AB
Write – loads Micro⇔cell
Flip-Flops
Read – reads output of
Micro⇔Cells BC
Write – loads Micro⇔cell
Flip-Flops
Blocks writing to the
Output Micro⇔Cells AB
Blocks writing to the
Output Micro⇔Cells BC
Read only – Flash Sector
Protection
Read only – PSD Security
and EEPROM Sector
Protection
Enables JTAG Port
Power Management
Register 0
Power Management
Register 2
Page Register
Places PSD memory
areas in Program and/or
Data space on an
individual basis.
Preliminary
9.0
The
PSD813F1
Functional
Blocks
PSD813F1-A
As shown in Figure 1, the PSD813F1 consists of six major types of functional blocks:
❏
❏
❏
❏
❏
❏
Memory Blocks
PLD Blocks
Bus Interface
I/O Ports
Power Management Unit
JTAG Interface
The functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable.
9.1 Memory Blocks
The PSD813F1 has the following memory blocks:
• The main Flash memory
• Secondary EEPROM memory
• SRAM.
The memory select signals for these blocks originate from the Decode PLD (DPLD) and
are user-defined in PSDsoft.
Table 8 summarizes the PSD813F1 memory blocks.
Table 8. Memory Blocks
Device
Main Flash
EEPROM
SRAM
PSD813F1
128KB
32KB
2KB
9.1.1 Main Flash and Secondary EEPROM
The 1 Mbit main Flash memory block is divided evenly into eight 16 Kbyte sectors. The
EEPROM memory is divided into four sectors of eight Kbytes each. Each sector of either
memory can be separately protected from program and erase operations.
Flash memory may be erased on a sector-by-sector basis and programmed byte-by-byte.
Flash sector erasure may be suspended while data is read from other sectors of memory
and then resumed after reading.
EEPROM may be programmed byte-by-byte or sector-by-sector, and erasing is automatic
and transparent. The integrity of the data can be secured with the help of Software Data
Protection (SDP). Any write operation to the EEPROM is inhibited during the first five
milliseconds following power-up.
During a program or erase of Flash, or during a write of the EEPROM, the status can be
output on the Rdy/Bsy pin of Port C3. This pin is set up using PSDsoft Configuration.
15
PSD813F1-A
The
PSD813F1
Functional
Blocks
(cont.)
Preliminary
9.1.1.1 Memory Block Selects
The decode PLD in the PSD813F1 generates the chip selects for all the internal memory
blocks (refer to the PLD section). Each of the eight Flash memory sectors have a
Flash Select signal (FS0-FS7) which can contain up to three product terms. Each of the
four EEPROM memory sectors have a Select signal (EES0-3 or CSBOOT0-3) which can
contain up to three product terms. Having three product terms for each sector select signal
allows a given sector to be mapped in different areas of system memory. When using a
microcontroller with separate Program and Data space, these flexible select signals allow
dynamic re-mapping of sectors from one space to the other.
9.1.1.2 The Ready/Busy Pin (PC3)
Pin PC3 can be used to output the Ready/Busy status of the PSD813F1. The output on
the pin will be a ‘0’ (Busy) when Flash or EEPROM memory blocks are being written to, or
when the Flash memory block is being erased. The output will be a ‘1’ (Ready) when no
write or erase operation is in progress.
9.1.1.3 Memory Operation
The main Flash and EEPROM memory are addressed through the microcontroller interface
on the PSD813F1 device. The microcontroller can access these memories in one of two
ways:
❏ The microcontroller can execute a typical bus write or read operation just as it would
if accessing a RAM or ROM device using standard bus cycles.
❏ The microcontroller can execute a specific instruction that consists of several write
and read operations. This involves writing specific data patterns to special addresses
within the Flash or EEPROM to invoke an embedded algorithm. These instructions are
summarized in Table 9.
Typically, Flash memory can be read by the microcontroller using read operations, just as it
would read a ROM device. However, Flash memory can only be erased and programmed
with specific instructions. For example, the microcontroller cannot write a single byte directly
to Flash memory as one would write a byte to RAM. To program a byte into Flash memory,
the microcontroller must execute a program instruction sequence, then test the status
of the programming event. This status test is achieved by a read operation or polling the
Rdy/Busy pin (PC3).
The Flash memory can also be read by using special instructions to retrieve particular Flash
device information (sector protect status and ID).
The EEPROM is a bit different. Data can be written to EEPROM memory using write
operations, like writing to a RAM device, but the status of each write event must be checked
by the microcontroller. A write event can be one to 64 contiguous bytes. The status test is
very similar to that used for Flash memory (read operation or Rdy/Busy). Optionally, the
EEPROM memory may be put into a Software Data Protect (SDP) mode where it requires
instructions, rather than operations, to alter its contents. SDP mode makes writing to
EEPROM much like writing to Flash memory.
16
Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1-A
9.1.1.3.1 Instructions
An instruction is defined as a sequence of specific operations. Each received byte is
sequentially decoded by the PSD and not executed as a standard write operation. The
instruction is executed when the correct number of bytes are properly received and the time
between two consecutive bytes is shorter than the time-out value. Some instructions are
structured to include read operations after the initial write operations.
The sequencing of any instruction must be followed exactly. Any invalid combination of
instruction bytes or time-out between two consecutive bytes while addressing Flash
memory will reset the device logic into a read array mode (Flash memory reads like a ROM
device). An invalid combination or time-out while addressing the EEPROM block will cause
the offending byte to be interpreted as a single operation.
The PSD813F1 supports these instructions (see Table 9):
Flash memory:
❏ Erase memory by chip or sector
❏ Suspend or resume sector erase
❏ Program a byte
❏ Reset to read array mode
❏ Read Flash Identifier value
❏ Read sector protection status
EEPROM:
❏ Write data to OTP Row
❏ Read data from OTP Row
❏ Power down memory
❏ Enable Software Data Protect (SDP)
❏ Disable SDP
❏ Return from read OTP Row read mode or power down mode.
These instructions are detailed in Table 9. For efficient decoding of the instructions, the first
two bytes of an instruction are the coded cycles and are followed by a command byte or
confirmation byte. The coded cycles consist of writing the data AAh to address X555h
during the first cycle and data 55h to address XAAAh during the second cycle. Address
lines A15-A12 are don’t cares during the instruction write cycles. However, the appropriate
sector select signal (FSi or EESi) must be selected.
17
PSD813F1-A
The
PSD813F1
Functional
Blocks
(cont.)
Preliminary
Table 9. Instructions
Instruction
Read
Flash
Identifier
(Note 3, 5)
Read OTP Row
(Note 4)
Read Sector
Protection
Status
(Notes 3, 5)
EEPROM
Sector
Select
(EESi)
Flash
Sector
Select
(FSi)
(Note 2)
Cycle 1 Cycle 2 Cycle 3
Cycle 4
Cycle5
0
1
AAh
55h
90h
@X555h @XAAAh @X555h
Read
identifier
with
(A6,A1,A0
at 0,0,1)
1
0
AAh
55h
90h
@X555h @XAAAh @X555h
Read
byte 1
AAh
55h
90h
@X555h @XAAAh @X555h
Read
identifier
with
(A6,A1,A0
at 0,1,0)
AAh
55h
A0h
@X555h @XAAAh @X555h
Data
@ address
AAh
55h
80h
@X555h @XAAAh @X555h
AAh
@X555h
55h
@XAAAh
30h
@ Sector
address
AAh
55h
80h
@X555h @XAAAh @X555h
AAh
@X555h
55h
@XAAAh
10h
@X555h
Read
byte 2
0
1
0
1
0
1
Erase the
whole Flash
(Note 5)
0
1
Suspend Sector
Erase
(Note 5)
0
1
B0h
@ any
address
Resume
Sector Erase
(Note 5)
0
1
30h
@ any
address
EEPROM Power
Down (Note 4)
1
0
AAh
55h
30h
@X555h @XAAAh @X555h
1
0
AAh
55h
A0h
@X555h @XAAAh @X555h
Write
byte 1
Write
byte 2
SDP Disable
(Note 4)
1
0
AAh
55h
80h
@X555h @XAAAh @X555h
AAh
@X555h
55h
@XAAAh
Write in OTP
Row (Notes 4, 6)
1
0
AAh
55h
B0h
@X555h @XAAAh @X555h
Write
byte 1
Write
byte 2
Return (from OTP
Read or EEPROM
Power-Down)
(Note 4)
1
0
F0h @
any
address
Reset
(Notes 3, 5)
0
1
AAh
55h
@X555h @XAAAh
Reset
(short instruction)
(Note 5)
0
1
F0h
@ any
address
Program a
Flash Byte
(Note 5)
Erase one
Flash Sector
(Note 5)
SDP Enable/
EEPROM Write
(Note 4)
Cycle 6
Cycle 7
Read
byte N
30h
@ Sector
address(1)
Write
byte N
20h
@X555h
Write
byte N
F0h
@ any
address
NOTES: 1. Additional sectors to be erased must be entered within 80 µs. A Sector Address is any address within
the Sector.
2. Flash and EEPROM Sector Selects are active high. Addresses A15-A12 are don’t cares in Instruction
Bus Cycles.
3. The Reset instruction is required to return to the normal read array mode if DQ5 goes high or after
reading the Flash Identifier or Protection status.
4. The MCU cannot invoke these instructions while executing code from EEPROM. The MCU must be
operating from some other memory when these instructions are performed.
5. The MCU cannot invoke these instructions while executing code from the same Flash memory for
which the instruction is intended. The MCU must operate from some other memory when these
instructions are executed.
6. Writing to OTP Row is allowed only when SDP mode is disabled.
18
Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1-A
9.1.1.4 Power Down Instruction and Power Up Condition
9.1.1.4.1 EEPROM Power Down Instruction
The EEPROM can enter power down mode with the help of the EEPROM power down
instruction (see Table 9). Once the EEPROM power down instruction is decoded, the
EEPROM memory cannot be accessed unless a Return instruction (also in Table 9) is
decoded. Alternately, this power down mode will automatically occur when the APD circuit
is triggered (see section 9.5.1). Therefore, this instruction is not required if the APD circuit is
used.
9.1.1.4.2 Power-Up Condition
The PSD813F1 internal logic is reset upon power-up to the read array mode. Any write
operation to the EEPROM is inhibited during the first 5 msec following power-up. The FSi
and EESi select signals, along with the write strobe signal, must be in the false state during
power-up for maximum security of the data contents and to remove the possibility of a byte
being written on the first edge of a write strobe signal. Any write cycle initiation is locked
when VCC is below VLKO.
9.1.1.5 Read
Under typical conditions, the microcontroller may read the Flash or EEPROM memory
using read operations just as it would a ROM or RAM device. Alternately, the microcontoller
may use read operations to obtain status information about a program or erase operation in
progress. Lastly, the microcontroller may use instructions to read special data from these
memories. The following sections describe these read functions.
9.1.1.5.1 Read the Contents of Memory
Main Flash is placed in the read array mode after power-up, chip reset, or a Reset Flash
instruction (see Table 9). The microcontroller can read the memory contents of main
Flash or EEPROM by using read operations any time the read operation is not part of an
instruction sequence.
9.1.1.5.2 Read the Main Flash Memory Identifier
The main Flash memory identifier is read with an instruction composed of 4 operations:
3 specific write operations and a read operation (see Table 9). During the read operation,
address bits A6, A1, and A0 must be 0,0,1, respectively, and the appropriate sector select
signal (FSi) must be active. The Flash ID is E3h for the PSD813F1. The MCU can read the
ID only when it is executing from the EEPROM.
9.1.1.5.3 Read the Main Flash Memory Sector Protection Status
The main Flash memory sector protection status is read with an instruction composed of 4
operations: 3 specific write operations and a read operation (see Table 9). During the read
operation, address bits A6, A1, and A0 must be 0,1,0, respectively, while the chip select FSi
designates the Flash sector whose protection has to be verified. The read operation will
produce 01h if the Flash sector is protected, or 00h if the sector is not protected.
The sector protection status for all NVM blocks (main Flash or EEPROM) can be read by
the microcontroller accessing the Flash Protection and PSD/EE Protection registers in PSD
I/O space. See section 9.1.1.9.1 for register definitions.
19
PSD813F1-A
The
PSD813F1
Functional
Blocks
(cont.)
Preliminary
9.1.1.5.4 Read the OTP Row
There are 64 bytes of One-Time-Programmable (OTP) memory that reside in EEPROM.
These 64 bytes are in addition to the 32 Kbytes of EEPROM memory. A read of the
OTP row is done with an instruction composed of at least 4 operations: 3 specific write
operations and one to 64 read operations (see Table 9). During the read operation(s),
address bit A6 must be zero, while address bits A5-A0 define the OTP Row byte to be read
while any EEPROM sector select signal (EESi) is active. After reading the last byte, an
EEPROM Return instruction must be executed (see Table 9).
9.1.1.5.5 Read the Erase/Program Status Bits
The PSD813F1 provides several status bits to be used by the microcontroller to confirm
the completion of an erase or programming instruction of Flash memory. Bits are also
available to show the status of writes to EEPROM. These status bits minimize the time that
the microcontroller spends performing these tasks and are defined in Table 10. The status
bits can be read as many times as needed.
Table 10. Status Bit
FSi/
CSBOOTi
EESi
Flash
VIH
VIL
Data Toggle Error
Polling Flag
Flag
EEPROM
VIL
VIH
Data Toggle
Polling Flag
DQ7
DQ6
DQ5
X
DQ4
DQ3
DQ2
DQ1
DQ0
X
Erase
Timeout
X
X
X
X
X
X
X
X
NOTES: 1. X = Not guaranteed value, can be read either 1 or 0.
2. DQ7-DQ0 represent the Data Bus bits, D7-D0.
3. FSi and EESi are active high.
For Flash memory, the microcontroller can perform a read operation to obtain these status
bits while an erase or program instruction is being executed by the embedded algorithm.
See section 9.1.1.7 for details.
For EEPROM not in SDP mode, the microcontroller can perform a read operation to obtain
these status bits just after a data write operation. The microcontroller may write one to 64
bytes before reading the status bits. See section 9.1.1.6 for details.
For EEPROM in SDP mode, the microcontroller will perform a read operation to obtain
these status bits while an SDP write instruction is being executed by the embedded
algorithm. See section 9.1.1.1.3 for details.
20
Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1-A
9.1.1.5.6 Data Polling Flag DQ7
When Erasing or Programming the Flash memory (or when Writing into the EEPROM
memory), bit DQ7 outputs the complement of the bit being entered for Programming/Writing
on DQ7. Once the Program instruction or the Write operation is completed, the true logic
value is read on DQ7 (in a Read operation). Flash memory specific features:
❏ Data Polling is effective after the fourth Write pulse (for programming) or after the
❏
❏
❏
sixth Write pulse (for Erase). It must be performed at the address being programmed
or at an address within the Flash sector being erased.
During an Erase instruction, DQ7 outputs a ‘0’. After completion of the instruction,
DQ7 will output the last bit programmed (it is a ‘1’ after erasing).
If the byte to be programmed is in a protected Flash sector, the instruction is
ignored.
If all the Flash sectors to be erased are protected, DQ7 will be set to ‘0’ for about
100 µs, and then return to the previous addressed byte. No erasure will be performed.
9.1.1.5.7 Toggle Flag DQ6
The PSD813F1 offers another way for determining when the EEPROM write or the Flash
memory Program instruction is completed. During the internal Write operation and when
either the FSi or EESi is true, the DQ6 will toggle from ‘0’ to ‘1’ and ‘1’ to ‘0’ on subsequent
attempts to read any byte of the memory.
When the internal cycle is complete, the toggling will stop and the data read on the
Data Bus D0-7 is the addressed memory byte. The device is now accessible for a new
Read or Write operation. The operation is finished when two successive reads yield the
same output data. Flash memory specific features:
❏ The Toggle bit is effective after the fourth Write pulse (for programming) or after the
❏
❏
sixth Write pulse (for Erase).
If the byte to be programmed belongs to a protected Flash sector, the instruction is
ignored.
If all the Flash sectors selected for erasure are protected, DQ6 will toggle to ‘0’ for
about 100 µs and then return to the previous addressed byte.
9.1.1.5.8 Error Flag DQ5
During a correct Program or Erase, the Error bit will set to ‘0’. This bit is set to ‘1’ when
there is a failure during Flash byte programming, Sector erase, or Bulk Erase.
In the case of Flash programming, the Error Bit indicates the attempt to program a Flash
bit(s) from the programmed state (0) to the erased state (1), which is not a valid operation.
The Error bit may also indicate a timeout condition while attempting to program a byte.
In case of an error in Flash sector erase or byte program, the Flash sector in which the
error occurred or to which the programmed byte belongs must no longer be used.
Other Flash sectors may still be used. The Error bit resets after the Reset instruction.
9.1.1.5.9 Erase Time-out Flag DQ3 (Flash Memory only)
The Erase Timer bit reflects the time-out period allowed between two consecutive Sector
Erase instructions. The Erase timer bit is set to ‘0’ after a Sector Erase instruction for a time
period of 100 µs + 20% unless an additional Sector Erase instruction is decoded. After this
time period or when the additional Sector Erase instruction is decoded, DQ3 is set to ‘1’.
21
PSD813F1-A
The
PSD813F1
Functional
Blocks
(cont.)
Preliminary
9.1.1.6 Writing to the EEPROM
Data may be written a byte at a time to the EEPROM using simple write operations, much
like writing to an SRAM. Unlike SRAM though, the completion of each byte write must be
checked before the next byte is written. To speed up this process, the PSD813F1 offers a
Page write feature to allow writing of several bytes before checking status.
To prevent inadvertent writes to EEPROM, the PSD813F1 offers a Software Data Protect
(SDP) mode. Once enabled, SDP forces the MCU to “unlock” the EEPROM before altering
its contents, much like Flash memory programming.
9.1.1.6.1 Write a Byte to EEPROM
A write operation is initiated when an EEPROM select signal (EESi) is true and the write
strobe signal (wr) into the PSD813F1 is true. If the PSD813F1 detects no additional writes
within 120 µsec, an internal storage operation is initiated. Internal storage to EEPROM
memory technology typically takes a few milliseconds to complete.
The status of the write operation is obtained by the MCU reading the Data Polling or Toggle
bits (as detailed in section 9.1.1.5), or the Ready/Busy output pin (section 9.1.1.2).
Keep in mind that the MCU does not need to erase a location in EEPROM before writing it.
Erasure is performed automatically as an internal process.
9.1.1.6.2 Write a Page to EEPROM
Writing data to EEPROM using page mode is more efficient than writing one byte at a
time. The PSD813F1 EEPROM has a 64 byte volatile buffer that the MCU may fill before an
internal EEPROM storage operation is initiated. Page mode timing approaches a 64:1
advantage over the time it takes to write individual bytes.
To invoke page mode, the MCU must write to EEPROM locations within a single page, with
no more than 120 µsec between individual byte writes. A single page means that address
lines A14 to A6 must remain constant. The MCU may write to the 64 locations on a page in
any order, which is determined by address lines A5 to A0. As soon as 120 µsec have
expired after the last page write, the internal EEPROM storage process begins and the
MCU checks programming status. Status is checked the same way it is for byte writes,
described above.
Note: be aware that if the upper address bits (A14 to A6) change during page write
operations, loss of data may occur. Ensure that all bytes for a given page have
been successfully stored in the EEPROM before proceeding to the next page. Correct
management of MCU interrupts during EEPROM page write operations is essential.
9.1.1.6.3 EEPROM Software Data Protect (SDP)
The SDP feature is useful for protecting the contents of EEPROM from inadvertent write
cycles that may occur during uncontrolled MCU bus conditions. These may happen if the
application software gets lost or when VCC is not within normal operating range.
Instructions from the MCU are used to enable and disable SDP mode (see Table 9). Once
enabled, the MCU must write an instruction sequence to EEPROM before writing data
(much like writing to Flash memory). SDP mode can be used for both byte and page writes
to EEPROM. The device will remain in SDP mode until the MCU issues a valid SDP disable
instruction.
PSD813F1 devices are shipped with SDP mode disabled. However, within PSDsoft, SDP
mode may be enabled as part of programming the device with a device programmer
(PSDpro).
22
Preliminary
The
PSD813F1
Functional
Blocks
PSD813F1-A
9.1.1.6.3 EEPROM Software Data Protect (SDP) (cont.)
To enable SDP mode at run time, the MCU must write three specific data bytes at three
specific memory locations, as shown in Figure 3. Any further writes to EEPROM when SDP
is set will require this same sequence, followed by the byte(s) to write. The first SDP enable
sequence can be followed directly by the byte(s) to be written.
(cont.)
To disable SDP mode, the MCU must write specific bytes to six specific locations, as shown
in Figure 4.
The MCU must not be executing code from EEPROM when these instructions are invoked.
The MCU must be operating from some other memory when enabling or disabling SDP
mode.
The state of SDP mode is not changed by power on/off sequences (nonvolatile). When
either the SDP enable or SDP disable instructions are issued from the MCU, the MCU must
use the Toggle bit (status bit DQ6) or the Ready/Busy output pin to check programming
status. The Ready/Busy output is driven low from the first write of AAh @ 555h until the
completion of the internal storage sequence. Data Polling (status bit DQ7) is not supported
when issuing the SDP enable or SDP disable commands.
Note: Using the SDP sequence (enabling, disabling, or writing data) is initiated when
specific bytes are written to addresses on specific “pages” of EEPROM memory, with no
more than 120 µsec between writes. The addresses 555h and AAAh are located on
different pages of EEPROM. This is how the PSD813F1 distinguishes these instruction
sequences from ordinary writes to EEPROM, which are expected to be within a single
EEPROM page.
Figure 3. EEPROM SDP Enable Flowcharts
SDP
not Set
SDP
Set
WRITE AAh to
Address 555h
Page Write
Instruction
WRITE AAh to
Address 555h
WRITE 55h to
Address AAAh
WRITE 55h to
Address AAAh
Page Write
Instruction
WRITE A0h to
Address 555h
WRITE A0h to
Address 555h
WRITE
is enabled
SDP is set
WRITE Data to
be Written in
any Address
SDP ENABLE ALGORITHM
Write Data
+
SDP Set
after tWC
(Write Cycle Time)
Write
in Memory
23
PSD813F1-A
The
PSD813F1
Functional
Blocks
Preliminary
Figure 4. Software Data Protection Disable Flow Chart
WRITE AAh to
Address 555h
(cont.)
WRITE 55h to
Address AAAh
WRITE 80h to
Address 555h
Page Write
Instruction
WRITE AAh to
Address 555h
WRITE 55h to
Address AAAh
WRITE 20h to
Address 555h
Unprotected State
after
tWC (Write Cycle time)
9.1.1.6.4 Write OTP Row
Writing to the OTP row (64 bytes) can only be done once per byte, and is enabled by an
instruction. This instruction is composed of three specific Write operations of data bytes at
three specific memory locations followed by the data to be stored in the OTP row (refer to
Table 9). During the write operations, address bit A6 must be zero, while address bits A5-A0
define the OTP Row byte to be written while any EEPROM Sector Select signal (EESi) is
active. Writing the OTP Row is allowed only when SDP mode is not enabled.
9.1.1.7 Programming Flash Memory
Flash memory must be erased prior to being programmed. The MCU may erase Flash
memory all at once or by-sector, but not byte-by-byte. A byte of Flash memory erases to all
logic ones (FF hex), and its bits are programmed to logic zeros. Although erasing Flash
memory occurs on a sector basis, programming Flash memory occurs on a byte basis.
The PSD813F1 main Flash and optional boot Flash require the MCU to send an instruction
to program a byte or perform an erase function (see Table 9). This differs from EEPROM,
which can be programmed with simple MCU bus write operations (unless EEPROM SDP
mode is enabled).
Once the MCU issues a Flash memory program or erase instruction, it must check for the
status of completion. The embedded algorithms that are invoked inside the PSD813F1
support several means to provide status to the MCU. Status may be checked using any of
three methods: Data Polling, Data Toggle, or the Ready/Busy output pin.
24
Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1-A
9.1.1.7.1 Data Polling
Polling on DQ7 is a method of checking whether a Program or Erase instruction is in
progress or has completed. Figure 5 shows the Data Polling algorithm.
When the MCU issues a programming instruction, the embedded algorithm within the
PSD813F1 begins. The MCU then reads the location of the byte to be programmed in Flash
to check status. Data bit DQ7 of this location becomes the compliment of data bit 7of the
original data byte to be programmed. The MCU continues to poll this location, comparing
DQ7 and monitoring the Error bit on DQ5. When the DQ7 matches data bit 7 of the original
data, and the Error bit at DQ5 remains ‘0’, then the embedded algorithm is complete.
If the Error bit at DQ5 is ‘1’, the MCU should test DQ7 again since DQ7 may have changed
simultaneously with DQ5 (see Figure 5).
The Error bit at DQ5 will be set if either an internal timeout occurred while the embedded
algorithm attempted to program the byte or if the MCU attempted to program a ‘1’ to a bit
that was not erased (not erased is logic ‘0’).
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed to compare the byte that was written to Flash with
the byte that was intended to be written.
When using the Data Polling method after an erase instruction, Figure 5 still applies.
However, DQ7 will be ‘0’ until the erase operation is complete. A ‘1’ on DQ5 will indicate
a timeout failure of the erase operation, a ‘0’ indicates no error. The MCU can read any
location within the sector being erased to get DQ7 and DQ5.
PSDsoft will generate ANSI C code functions which implement these Data Polling
algorithms.
Figure 5. Data Polling Flow Chart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA7
YES
NO
NO
DQ5
=1
YES
READ DQ7
DQ7
=
DATA
YES
NO
FAIL
PASS
25
PSD813F1-A
Preliminary
The
PSD813F1
Functional
Blocks
9.1.1.7.2 Data Toggle
Checking the Data Toggle bit on DQ6 is a method of determining whether a Program or
Erase instruction is in progress or has completed. Figure 6 shows the Data Toggle
algorithm.
(cont.)
When the MCU issues a programming instruction, the embedded algorithm within the
PSD813F1 begins. The MCU then reads the location of the byte to be programmed in
Flash to check status. Data bit DQ6 of this location will toggle each time the MCU reads
this location until the embedded algorithm is complete. The MCU continues to read this
location, checking DQ6 and monitoring the Error bit on DQ5. When DQ6 stops toggling
(two consecutive reads yield the same value), and the Error bit on DQ5 remains ‘0’, then
the embedded algorithm is complete. If the Error bit on DQ5 is ‘1’, the MCU should test
DQ6 again, since DQ6 may have changed simultaneously with DQ5 (see Figure 6).
The Error bit at DQ5 will be set if either an internal timeout occurred while the embedded
algorithm attempted to program the byte, or if the MCU attempted to program a ‘1’ to a bit
that was not erased (not erased is logic ‘0’).
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed to compare the byte that was written to Flash with
the byte that was intended to be written.
When using the Data Toggle method after an erase instructin, Figure 6 still applies. DQ6 will
toggle until the erase operation is complete. A ‘1’ on DQ5 will indicate a timeout failure of
the erase operation, a ‘0’ indicates no error. The MCU can read any location within the
sector being erased to get DQ6 and DQ5.
PSDsoft will generate ANSI C code functions which implement these Data Toggling
algorithms.
Figure 6. Data Toggle Flow Chart
START
READ
DQ5 & DQ6
DQ6
=
TOGGLE
NO
YES
NO
DQ5
=1
YES
READ DQ6
DQ6
=
TOGGLE
NO
YES
FAIL
26
PASS
Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1-A
9.1.1.8 Erasing Flash Memory
9.1.1.8.1. Flash Bulk Erase Instruction
The Flash Bulk Erase instruction uses six write operations followed by a Read operation of
the status register, as described in Table 9. If any byte of the Bulk Erase instruction is wrong,
the Bulk Erase instruction aborts and the device is reset to the Read Flash memory status.
During a Bulk Erase, the memory status may be checked by reading status bits DQ5, DQ6,
and DQ7, as detailed in section 9.1.1.7. The Error bit (DQ5) returns a ‘1’ if there has been
an Erase Failure (maximum number of erase cycles have been executed).
It is not necessary to program the array with 00h because the PSD813F1 will automatically
do this before erasing to 0FFh.
During execution of the Bulk Erase instruction, the Flash memory will not accept any
instructions.
9.1.1.8.2 Flash Sector Erase Instruction
The Sector Erase instruction uses six write operations, as described in Table 9. Additional
Flash Sector Erase confirm commands and Flash sector addresses can be written
subsequently to erase other Flash sectors in parallel, without further coded cycles, if the
additional instruction is transmitted in a shorter time than the timeout period of about
100 µs. The input of a new Sector Erase instruction will restart the time-out period.
The status of the internal timer can be monitored through the level of DQ3 (Erase time-out
bit). If DQ3 is ‘0’, the Sector Erase instruction has been received and the timeout is
counting. If DQ3 is ‘1’, the timeout has expired and the PSD813F1 is busy erasing the Flash
sector(s). Before and during Erase timeout, any instruction other than Erase suspend and
Erase Resume will abort the instruction and reset the device to Read Array mode. It is not
necessary to program the Flash sector with 00h as the PSD813F1 will do this automatically
before erasing (byte=FFh).
During a Sector Erase, the memory status may be checked by reading status bits DQ5,
DQ6, and DQ7, as detailed in section 9.1.1.7.
During execution of the erase instruction, the Flash block logic accepts only Reset and
Erase Suspend instructions. Erasure of one Flash sector may be suspended, in order to
read data from another Flash sector, and then resumed.
9.1.1.8.3 Flash Erase Suspend Instruction
When a Flash Sector Erase operation is in progress, the Erase Suspend instruction will
suspend the operation by writing 0B0h to any address when an appropriate Chip Select
(FSi) is true. (See Table 9). This allows reading of data from another Flash sector after the
Erase operation has been suspended. Erase suspend is accepted only during the Flash
Sector Erase instruction execution and defaults to read array mode. An Erase Suspend
instruction executed during an Erase timeout will, in addition to suspending the erase,
terminate the time out.
The Toggle Bit DQ6 stops toggling when the PSD813F1 internal logic is suspended. The
toggle Bit status must be monitored at an address within the Flash sector being erased. The
Toggle Bit will stop toggling between 0.1 µs and 15 µs after the Erase Suspend instruction
has been executed. The PSD813F1 will then automatically be set to Read Flash Block
Memory Array mode.
If an Erase Suspend instruction was executed, the following rules apply:
• Attempting to read from a Flash sector that was being erased will output invalid data.
• Reading from a Flash sector that was not being erased is valid.
• The Flash memory cannot be programmed, and will only respond to Erase Resume
and Reset instructions (read is an operation and is OK).
• If a Reset instruction is received, data in the Flash sector that was being erased will
be invalid.
27
PSD813F1-A
Preliminary
The
PSD813F1
Functional
Blocks
9.1.1.8.4 Flash Erase Resume Instruction
If an Erase Suspend instruction was previously executed, the erase operation may be
resumed by this instruction. The Erase Resume instruction consists of writing 030h to any
address while an appropriate Chip Select (FSi) is true. (See Table 9.)
(cont.)
9.1.1.9 Flash and EEPROM Memory Specific Features
9.1.1.9.1 Flash and EEPROM Sector Protect
Each Flash and EEPROM sector can be separately protected against Program and Erase
functions. Sector Protection provides additional data security because it disables all
program or erase operations. This mode can be activated through the JTAG Port or a
Device Programmer.
Sector protection can be selected for each sector using the PSDsoft Configuration program.
This will automatically protect selected sectors when the device is programmed through
the JTAG Port or a Device Programmer. Flash and EEPROM sectors can be
unprotected to allow updating of their contents using the JTAG Port or a Device
Programmer. The microcontroller can read (but cannot change) the sector protection bits.
Any attempt to program or erase a protected Flash or EEPROM sector will be ignored by
the device. The Verify operation will result in a read of the protected data. This allows a
guarantee of the retention of the Protection status.
The sector protection status can be read by the MCU through the Flash protection and
PSD/EE protection registers (CSIOP). See Table 11.
Table 11. Sector Protection/Security Bit Definition
Flash Protection Register
Bit 7
Sec7_Prot
Bit 6
Bit 5
Bit 4
Sec6_Prot Sec5_Prot Sec4_Prot
Bit Definitions:
Sec<i>_Prot
Sec<i>_Prot
Bit 3
Bit 2
Bit 1
Bit 0
Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
1 = Flash <i> is write protected.
0 = Flash <i> is not write protected.
PSD/EE Protection Register
*:
Bit 7
Bit 6
Bit 5
Bit 4
Security_
Bit
*
*
*
Bit 3
Bit 2
Bit 1
Bit 0
Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Not used.
Bit Definitions:
Sec<i>_Prot
Sec<i>_Prot
Security_Bit
1 = EEPROM Boot Sector <i> is write protected.
0 = EEPROM Boot Sector <i> is not write protected.
0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.
9.1.1.9.2 Reset Instruction
The Reset instruction resets the internal memory logic state machine in a few milliseconds.
Reset is an instruction of either one write operation or three write operations (refer to
Table 9).
28
Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1-A
9.1.2 SRAM
The SRAM is a 16 Kbit (2K x 8) memory. The SRAM is enabled when RS0— the SRAM
chip select output from the DPLD— is high. RS0 can contain up to two product terms,
allowing flexible memory mapping.
The SRAM can be backed up using an external battery. The external battery should be
connected to the Vstby pin (PC2). If you have an external battery connected to the
PSD813F1, the contents of the SRAM will be retained in the event of a power loss. The
contents of the SRAM will be retained so long as the battery voltage remains at 2V or
greater. If the supply voltage falls below the battery voltage, an internal power switchover to
the battery occurs.
Pin PC4 can be configured as an output that indicates when power is being drawn from the
external battery. This Vbaton signal will be high with the supply voltage falls below the
battery voltage and the battery on PC2 is supplying power to the internal SRAM.
The chip select signal (RS0) for the SRAM, Vstby, and Vbaton are all configured using
PSDsoft Configuration.
9.1.3 Memory Select Signals
The main Flash (FSi), EEPROM (EESi), and SRAM (RS0) memory select signals are all
outputs of the DPLD. They are setup by entering equations for them in PSDsoft. The
following rules apply to the equations for the internal chip select signals:
1. Flash memory and EEPROM memory sector select signals must not be larger than the
physical sector size.
2. Any main Flash memory sector must not be mapped in the same memory space as
another Flash sector.
3. An EEPROM memory sector must not be mapped in the same memory
space as another EEPROM sector.
4. SRAM, I/O, and Peripheral I/O spaces must not overlap.
5. An EEPROM memory sector may overlap a main Flash memory sector.
In case of overlap, priority will be given to the EEPROM.
6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority
will be given to the SRAM, I/O, or Peripheral I/O.
Example
FS0 is valid when the address is in the range of 8000h to BFFFh, EES0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0
will always access the SRAM. Any address in the range of EES0 greater than 87FFh (and
less than 9FFFh) will automatically address EEPROM memory segment 0. Any address
greater than 9FFFh will access the Flash memory segment 0. You can see that half of the
Flash memory segment 0 and one-fourth of EEPROM segment 0 can not be accessed in
this example. Also note that an equation that defined FS1 to anywhere in the range of
8000h to BFFFh would not be valid.
Figure 7 shows the priority levels for all memory components. Any component on a higher
level can overlap and has priority over any component on a lower level. Components on the
same level must not overlap. Level one has the highest priority and level 3 has the lowest.
29
PSD813F1-A
The
PSD813F1
Functional
Blocks
(cont.)
Preliminary
Figure 7. Priority Level of Memory and I/O Components
Highest Priority
Level 1
SRAM, I /O, or
Peripheral I /O
Level 2
EEPROM Memory
Level 3
Flash Memory
Lowest Priority
9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces
The 8031 and compatible family of microcontrollers, which includes the 80C51, 80C151,
80C251, 80C51XA, and the C500 family, have separate address spaces for code memory
(selected using PSEN) and data memory (selected using RD). Any of the memories within
the PSD813F1 can reside in either space or both spaces. This is controlled through manipulation of the VM register that resides in the PSD’s CSIOP space.
The VM register is set using PSDsoft to have an initial value. It can subsequently be
changed by the microcontroller so that memory mapping can be changed on-the-fly.
For example, I may wish to have SRAM and Flash in Data Space at boot, and EEPROM in
Program Space at boot, and later swap EEPROM and Flash. This is easily done with
the VM register by using PSDsoft to configure it for boot up and having the microcontroller
change it when desired.
Table 13 describes the VM Register.
Table 13. VM Register
Bit 7
Bit 6* Bit 5* Bit 4
Bit 3
PIO_EN
FL_Data EE_Data
Bit 1
Bit 0
EE_Code SRAM_Code
0 = disable
PIO mode
*
*
0 = RD
can’t
access
Flash
0 = RD
can’t
access
EEPROM
0 = PSEN
can’t
access
Flash
0 = PSEN
can’t
access
EEPROM
0 = PSEN
can’t
access
SRAM
1= enable
PIO mode
*
*
1 = RD
access
Flash
1 = RD
access
EEPROM
1 = PSEN 1 = PSEN
access
access
Flash
EEPROM
1 = PSEN
access
SRAM
NOTE: Bits 6-5 are not used.
30
Bit 2
FL_Code
Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1-A
9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces
9.1.3.2.1 Separate Space Modes
Code memory space is separated from data memory space. For example, the PSEN
signal is used to access the program code from the Flash Memory, while the RD signal is
used to access data from the EEPROM, SRAM and I/O Ports. This configuration requires
the VM register to be set to 0Ch.
9.1.3.2.2 . Combined Space Modes
The program and data memory spaces are combined into one space that allows the main
Flash Memory, EEPROM, and SRAM to be accessed by either PSEN or RD. For example,
to configure the main Flash memory in combined space mode, bits 2 and 4 of the VM
register are set to “1”.
9.1.3.3 80C31 Memory Map Example
See Application Notes 57 and 64 for examples.
Figure 8. 8031 Memory Modes – Separate Space Mode
DPLD
FLASH
RS0
EEPROM
SRAM
EES0-3
FS0-7
CS
CS
OE
CS
OE
OE
PSEN
RD
Figure 9. 80C31 Memory Mode – Combined Space Mode
DPLD
RD
RS0
FLASH
EEPROM
SRAM
EES0-3
FS0-7
CS
CS
OE
CS
OE
OE
VM REG BIT 3
VM REG BIT 4
PSEN
VM REG BIT 1
VM REG BIT 2
RD
VM REG BIT 0
31
PSD813F1-A
The
PSD813F1
Functional
Blocks
(cont.)
Preliminary
9.1.4 Page Register
The eight bit Page Register increases the addressing capability of the microcontroller by a
factor of up to 256. The contents of the register can also be read by the microcontroller. The
outputs of the Page Register (PGR0-PGR7) are inputs to the DPLD decoder and can be
included in the Flash Memory, EEPROM, and SRAM chip select equations.
If memory paging is not needed, or if not all 8 page register bits are needed for memory
paging, then these bits may be used in the CPLD for general logic. See Application
Note 57.
Figure 10 shows the Page Register. The eight flip flops in the register are connected to the
internal data bus D0-D7. The microcontroller can write to or read from the Page Register.
The Page Register can be accessed at address location CSIOP + E0h.
Figure 10. Page Register
RESET
D0
D0 - D7
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
PGR0
INTERNAL
SELECTS
AND LOGIC
PGR1
PGR2
PGR3
PGR4
PGR5
FLASH
DPLD
AND
FLASH
CPLD
PGR6
PGR7
R/W
PAGE
REGISTER
32
FLASH
PLD
Preliminary
PSD813F1-A
The
PSD813F1
Functional
Blocks
9.2 PLDs
(cont.)
The PSD813F1 contains two PLDs: the Decode PLD (DPLD), and the Complex PLD
(CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in
sections 9.2.1 and 9.2.2. Figure 11 shows the configuration of the PLDs.
The PLDs bring programmable logic functionality to the PSD813F1. After specifying the
logic for the PLDs using the PSDabel tool in PSDsoft, the logic is programmed into the
device and available upon power-up.
The DPLD performs address decoding for internal and external components, such as
memory, registers, and I/O port selects.
The CPLD can be used for logic functions, such as loadable counters and shift registers,
state machines, and encoding and decoding logic. These logic functions can be constructed
using the 16 Output Micro⇔Cells (OMCs), 24 Input Micro⇔Cells (IMCs), and the AND
array. The CPLD can also be used to generate external chip selects.
The AND array is used to form product terms. These product terms are specified using
PSDabel. An Input Bus consisting of 73 signals is connected to the PLDs. The signals are
shown in Table 15.
Table 15. DPLD and CPLD Inputs
Input Source
Input Name
Number
of Signals
MCU Address Bus
A[15:0]*
16
MCU Control Signals
CNTL[2:0]
3
Reset
RST
1
Power Down
PDN
1
Port A Input Micro⇔Cells
PA[7-0]
8
Port B Input Micro⇔Cells
PB[7-0]
8
Port C Input Micro⇔Cells
PC[7-0]
8
Port D Inputs
PD[2:0]
3
Page Register
PGR(7:0)
8
Micro⇔Cell AB Feedback
MCELLAB.FB[7:0]
8
Micro⇔Cell BC Feedback
MCELLBC.FB[7:0]
8
EEPROM Programming Status Bit
Rdy/Bsy
1
NOTE: The address inputs are A[19:4] in 80C51XA mode.
The Turbo Bit in PSD813F1
The PLDs in the PSD813F1 can minimize power consumption by switching off when inputs
remain unchanged for an extended time of about 70 ns. Setting the Turbo mode bit to off
(Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs
are changing. Turbo-off mode increases propagation delays while reducing power
consumption. Refer to the Power Management Unit section on how to set the Turbo Bit.
Additionally, five bits are available in the PMMR2 register to block MCU control signals from
entering the PLDs. This reduces power consumption and can be used only when these
MCU control signals are not used in PLD logic equations.
33
PAGE
REGISTER
8
73
FLASH MEMORY SELECTS
4
EEPROM SELECTS
1
SRAM SELECT
1
CSIOP SELECT
2
PERIPHERAL SELECTS
PLD INPUT BUS
1
16
JTAG SELECT
DIRECT MICRO ⇔CELL ACCESS FROM MCU DATA BUS
OUTPUT MICRO⇔CELL FEEDBACK
CPLD
16 OUTPUT
MICRO⇔CELL
PT
ALLOC.
73
24 INPUT MICRO⇔CELL
(PORT A,B,C)
MICRO⇔CELL
ALLOC.
I/O PORTS
DECODE PLD
PSD813F1-A
Figure 11. PLD Block Diagram
34
8
DATA
BUS
MCELLAB
TO PORT A OR B
8
MCELLBC
TO PORT B OR C
8
3
EXTERNAL CHIP SELECTS
TO PORT D
DIRECT MICRO⇔CELL INPUT TO MCU DATA BUS
24
INPUT MICRO⇔CELL & INPUT PORTS
3
PORT D INPUTS
Preliminary
Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1-A
Each of the two PLDs has unique characteristics suited for its applications They are
described in the following sections.
9.2.1 Decode PLD (DPLD)
The DPLD, shown in Figure 12, is used for decoding the address for internal and external
components. The DPLD can generate the following decode signals:
• 8 sector selects for the main Flash memory (three product terms each)
• 4 sector selects for the EEPROM memory
(three product terms each)
• 1 internal SRAM select signal (two product terms)
• 1 internal CSIOP (PSD configuration register) select signal
• 1 JTAG select signal (enables JTAG on Port C)
• 2 internal peripheral select signals (peripheral I/O mode).
9.2.2 Complex PLD (CPLD)
The CPLD can be used to implement system logic functions, such as loadable counters
and shift registers, system mailboxes, handshaking protocols, state machines, and random
logic. The CPLD can also be used to generate 3 external chip selects, routed to Port D.
Although external chip selects can be produced by any Output Micro⇔Cell, these three
external chip selects on Port D do not consume any Output Micro⇔Cells.
As shown in Figure 11, the CPLD has the following blocks:
• 24 Input Micro⇔Cells (IMCs)
• 16 Output Micro⇔Cells (OMCs)
• Micro⇔Cell Allocator
• Product Term Allocator
• AND array capable of generating up to 137 product terms
• Four I/O ports.
Each of the blocks are described in the subsections that follow.
The Input and Output Micro⇔Cells are connected to the PSD813F1 internal data bus and
can be directly accessed by the microcontroller. This enables the MCU software to load
data into the Output Micro⇔Cells or read data from both the Input and Output Micro⇔Cells.
This feature allows efficient implementation of system logic and eliminates the need to
connect the data bus to the AND logic array as required in most standard PLD macrocell
architectures.
35
3
EES1
3
EES2
3
EES3
3
EEPROM
SELECTS
PSD813F1-A
I /O PORTS (PORT A,B,C)
EES0
Figure 12. DPLD Logic Array
36
(INPUTS)
3
FS0
(24)
3
MCELLAB.FB [7:0] (FEEDBACKS)
(8)
MCELLBC.FB [7:0] (FEEDBACKS)
(8)
PGR0 - PGR7
(8)
3
3
8 FLASH MEMORY
SECTOR SELECTS
3
A[15:0] *
(16)
3
PD[2:0] (ALE,CLKIN,CSI)
(3)
PDN (APD OUTPUT)
(1)
CNTRL[2:0] (READ/WRITE CONTROL SIGNALS)
(3)
RESET
(1)
RD_BSY
(1)
3
3
2
FS7
RS0
CSIOP
SRAM SELECT
I/O DECODER
SELECT
PSEL0
PSEL1
PERIPHERAL I/O MODE
SELECT
JTAGSEL
Preliminary
*NOTE: The address inputs are A[19:4] in 80C51XA mode.
PLD INPUT BUS
PLD INPUT BUS
Q
CK
PT INPUT LATCH GATE/CLOCK
CL
D/T/JK FF
SELECT
D/T
MICRO ⇔CELL FEEDBACK
I/O PORT INPUT
MCU LOAD
MCU DATA IN
PR DI LD
PT OUTPUT ENABLE (OE)
PT CLEAR
CLOCK
SELECT
GLOBAL
CLOCK
PT
CLOCK
POLARITY
SELECT
UP TO 10
PRODUCT TERMS
PRODUCT TERM
ALLOCATOR
PT PRESET
COMB.
/REG
SELECT
MUX
CPLD MICRO⇔CELLS
MUX
MICRO ⇔CELL
TO
I/O PORT
ALLOC.
FGPLD
OUTPUT
MICRO ⇔CELL
OUT TO
MCU
DATA
LOAD
CONTROL
MCU ADDRESS / DATA BUS
D
Q
Q
DIR
REG.
D
INPUT
SELECT
MUX
ALE/AS
G
Q D
Q D
INPUT MICRO⇔CELLS
WR
PDR
FGPLD OUTPUT
WR
DATA
LATCHED
ADDRESS OUT
I/O PORTS
TO OTHER I/O PORTS
MUX
MUX
PRODUCT TERMS
FROM OTHER
MICRO ⇔ CELLS
I/O PIN
Preliminary
PSD813F1-A
Figure 13. The Micro⇔Cell and I/O Port
37
AND ARRAY
PSD813F1-A
The
PSD813F1
Functional
Blocks
(cont.)
Preliminary
9.2.2.1 Output Micro⇔Cell
Eight of the Output Micro⇔Cells are connected to Ports A and B pins and are named as
McellAB0-7. The other eight Micro⇔Cells are connected to Ports B and C pins and are
named as McellBC0-7. If an McellAB output is not assigned to a specific pin in PSDabel,
the Micro⇔Cell Allocator will assign it to either Port A or B. The same is true for a McellBC
output on Port B or C. Table 16 shows the Micro⇔Cells and Port assignment.
Table 16. Output Micro⇔Cell Port and Data Bit Assignments
Output
Micro⇔Cell
Port
Assignment
Native
Product
Terms
Maximum
Borrowed
Product
Terms
McellAB0
Port A0, B0
3
6
D0
McellAB1
Port A1, B1
3
6
D1
McellAB2
Port A2, B2
3
6
D2
McellAB3
Port A3, B3
3
6
D3
McellAB4
Port A4, B4
3
6
D4
McellAB5
Port A5, B5
3
6
D5
McellAB6
Port A6, B6
3
6
D6
McellAB7
Port A7, B7
3
6
D7
McellBC0
Port B0, C0
4
5
D0
McellBC1
Port B1, C1
4
5
D1
McellBC2
Port B2, C2
4
5
D2
McellBC3
Port B3, C3
4
5
D3
McellBC4
Port B4, C4
4
6
D4
McellBC5
Port B5, C5
4
6
D5
McellBC6
Port B6, C6
4
6
D6
McellBC7
Port B7, C7
4
6
D7
Data Bit for
Loading or
Reading
The Output Micro⇔Cell (OMC) architecture is shown in Figure 14. As shown in the figure,
there are native product terms available from the AND array, and borrowed product terms
available (if unused) from other OMCs. The polarity of the product term is controlled by the
XOR gate. The OMC can implement either sequential logic, using the flip-flop element, or
combinatorial logic. The multiplexer selects between the sequential or combinatorial logic
outputs. The multiplexer output can drive a Port pin and has a feedback path to the AND
array inputs.
The flip-flop in the OMC can be configured as a D, T, JK, or SR type in the PSDabel
program. The flip-flop’s clock, preset, and clear inputs may be driven from a product term
of the AND array. Alternatively, the external CLKIN signal can be used for the clock input to
the flip-flop. The flip-flop is clocked on the rising edge of the clock input. The preset and
clear are active-high inputs. Each clear input can use up to two product terms.
38
Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1-A
9.2.2.2 The Product Term Allocator
The CPLD has a Product Term Allocator. The PSDabel compiler uses the Allocator to
borrow and place product terms from one Micro⇔Cell to another. The following list
summarizes how product terms are allocated:
• McellAB0-7 all have three native product terms and may borrow up to six more
• McellBC0-3 all have four native product terms and may borrow up to five more
• McellBC4-7 all have four native product terms and may borrow up to six more.
Each Micro⇔Cell may only borrow product terms from certain other Micro⇔Cells. Product
terms already in use by one Micro⇔Cell will not be available for a different Micro⇔Cell.
If an equation requires more product terms than what is available to it, then “external”
product terms will be required, which will consume other OMCs. If external product terms
are used, extra delay will be added for the equation that required the extra product terms.
This is called product term expansion. PSDsoft will perform this expansion as needed.
9.2.2.3 Loading and Reading the Output Micro⇔Cells (OMCs)
The OMCs occupy a memory location in the MCU address space, as defined by the
CSIOP (refer to the I/O section). The flip-flops in each of the 16 OMCs can be loaded from
the data bus by a microcontroller. Loading the OMCs with data from the MCU takes priority
over internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be
overridden by the MCU. The ability to load the flip-flops and read them back is useful in
such applications as loadable counters and shift registers, mailboxes, and handshaking
protocols.
Data can be loaded to the OMCs on the trailing edge of the WR signal (edge loading) or
during the time that the WR signal is active (level loading). The method of loading is
specified in PSDsoft Configuration.
9.2.2.4 The OMC Mask Register
There is one Mask Register for each of the two groups of eight OMCs. The Mask Registers
can be used to block the loading of data to individual OMCs. The default value for the Mask
Registers is 00h, which allows loading of the OMCs. When a given bit in a Mask Register is
set to a ‘1’, the MCU will be blocked from writing to the associated OMC. For example,
suppose McellAB0-3 are being used for a state machine. You would not want a MCU write
to McellAB to overwrite the state machine registers. Therefore, you would want to load the
Mask Register for McellAB (Mask Micro⇔Cell AB) with the value 0Fh.
9.2.2.5 The Output Enable of the OMC
The OMC can be connected to an I/O port pin as a PLD output. The output enable of each
Port pin driver is controlled by a single product term from the AND array, ORed with the
Direction Register output. The pin is enabled upon power up if no output enable equation is
defined and if the pin is declared as a PLD output in PSDsoft.
If the OMC output is declared as an internal node and not as a Port pin output in the
PSDabel file, then the Port pin can be used for other I/O functions. The internal node
feedback can be routed as an input to the AND array.
39
40
CLKIN
PRESET(.PR)
ENABLE (.OE)
PORT INPUT
FEEDBACK (.FB)
MUX
CLEAR (.RE)
POLARITY
SELECT
WR
Q
MUX
PROGRAMMABLE
FF (D / T/JK /SR)
CLR
IN
LD
DIN PR
COMB/REG
SELECT
DIRECTION
REGISTER
D [ 7:0]
MICRO⇔CELL
ALLOCATOR
INTERNAL DATA BUS
INPUT
MICRO⇔CELL
PORT
DRIVER
I/O PIN
(cont.)
PT CLK
PT
PT
PT
PT
ALLOCATOR
RD
The
PSD813F1
Functional
Blocks
MICRO⇔CELL CS
MASK
REG.
PSD813F1-A
Preliminary
Figure 14. CPLD Output Micro⇔Cell
AND ARRAY
PLD INPUT BUS
Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1-A
9.2.2.6 Input Micro⇔Cells (IMCs)
The CPLD has 24 IMCs, one for each pin on Ports A, B, and C. The architecture of the IMC
is shown in Figure 15. The IMCs are individually configurable, and can be used as a latch,
register, or to pass incoming Port signals prior to driving them onto the PLD input bus. The
outputs of the IMCs can be read by the microcontroller through the internal data bus.
The enable for the latch and clock for the register are driven by a multiplexer whose inputs
are a product term from the CPLD AND array or the MCU address strobe (ALE/AS). Each
product term output is used to latch or clock four IMCs. Port inputs 3-0 can be controlled by
one product term and 7-4 by another.
Configurations for the IMCs are specified by equations written in PSDabel (see Application
Note 55). Outputs of the IMCs can be read by the MCU via the IMC buffer. See the I/O Port
section on how to read the IMCs.
IMCs can use the address strobe to latch address bits higher than A15. Any latched
addresses are routed to the PLDs as inputs.
IMCs are particularly useful with handshaking communication applications where two
processors pass data back and forth through a common mailbox. Figure 16 shows a typical
configuration where the Master MCU writes to the Port A Data Out Register. This, in turn, can
be read by the Slave MCU via the activation of the “Slave-Read” output enable product term.
The Slave can also write to the Port A IMCs and the Master can then read the IMCs directly.
Note that the “Slave-Read” and “Slave-Wr” signals are product terms that are derived from
the Slave MCU inputs RD, WR, and Slave_CS.
41
D [ 7: 0]
DIRECTION
REGISTER
ENABLE ( .OE )
AND ARRAY
PLD INPUT BUS
PT
PSD813F1-A
Figure 15. Input Micro⇔Cell
INPUT MICRO⇔CELL _ RD
The
PSD813F1
Functional
Blocks
(cont.)
42
INTERNAL DATA BUS
OUTPUT
MICRO⇔CELLS BC
AND
MICRO⇔CELL AB
I/O PIN
PT
PORT
DRIVER
MUX
Q
D
PT
MUX
ALE/AS
D FF
FEEDBACK
Q
D
G
INPUT MICRO⇔CELL
Preliminary
LATCH
WR
SLAVE– READ
PORT A
DATA OUT
REGISTER
MCU -RD
MASTER
MCU
D [ 7:0]
CPLD
D
Q
MCU - WR
MCU -WR
SLAVE– WR
D [ 7:0]
PORT A
INPUT
MICRO ⇔ CELL
Q
MCU - RD
D
PORT A
SLAVE
MCU
Preliminary
RD
Figure 16. Handshaking Communication Using Input Micro⇔Cells
SLAVE– CS
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1
PSD813F1-A
43
PSD813F1-A
The
PSD813F1
Functional
Blocks
(cont.)
Preliminary
9.3 Microcontroller Bus Interface
The “no-glue logic” PSD813F1 Microcontroller Bus Interface can be directly connected to
most popular microcontrollers and their control signals. Key 8-bit microcontrollers with their
bus types and control signals are shown in Table 17. The interface type is specified using
the PSDsoft Configuration.
Table 17. Microcontrollers and their Control Signals
MCU
Data
Bus
Width
CNTL0
CNTL1
CNTL2
PC7
PD0**
ADIO0
8031
8
WR
RD
PSEN
ALE
A0
*
80C51XA
8
WR
RD
PSEN
ALE
A4
A3-A0
80C251
8
WR
PSEN
*
ALE
A0
80C251
8
WR
RD
PSEN
ALE
A0
80198
8
WR
RD
ALE
A0
68HC11
8
R/W
E
AS
A0
68HC912
8
R/W
E
DBE
AS
A0
*
*
*
*
*
*
*
*
*
*
*
*
Z80
8
WR
RD
A0
D3-D0
D7-D4
8
R/W
DS
AS
A0
68330
8
R/W
DS
AS
A0
*
*
*
*
M37702M2
8
R/W
E
*
*
*
*
*
Z8
*
*
*
*
*
*
*
*
*
*
*
*
*
ALE
A0
D3-D0
D7-D4
PA3-PA0 PA7-PA3
**Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PC7, PD0, PA3-0) can be
**configured for other I/O functions.
**ALE/AS input is optional for microcontrollers with a non-multiplexed bus
9.3.1. PSD813F1 Interface to a Multiplexed 8-Bit Bus
Figure 17 shows an example of a system using a microcontroller with an 8-bit multiplexed
bus and a PSD813F1. The ADIO port on the PSD813F1 is connected directly to the
microcontroller address/data bus. ALE latches the address lines internally. Latched
addresses can be brought out to Port A or B. The PSD813F1 drives the ADIO data bus only
when one of its internal resources is accessed and the RD input is active. Should the
system address bus exceed sixteen bits, Ports A, B, C, or D may be used as additional
address inputs.
9.3.2. PSD813F1 Interface to a Non-Multiplexed 8-Bit Bus
Figure 18 shows an example of a system using a microcontroller with an 8-bit
non-multiplexed bus and a PSD813F1. The address bus is connected to the ADIO Port,
and the data bus is connected to Port A. Port A is in tri-state mode when the PSD813F1 is
not accessed by the microcontroller. Should the system address bus exceed sixteen bits,
Ports B, C, or D may be used for additional address inputs.
44
A[ 15:8]
ADIO
PORT
PORT
A
PORT
B
WR
WR (CNTRL0)
RD
RD (CNTRL1)
BHE (CNTRL2)
BHE
RST
ALE
ALE (PD0)
PORT D
PORT
C
A [ 7: 0]
(OPTIONAL)
A [ 15: 8]
(OPTIONAL)
Preliminary
AD [ 7:0]
Figure 17. An Example of a Typical 8-Bit Multiplexed Bus Interface
MICROCONTROLLER
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1
RESET
PSD813F1-A
45
D [ 7:0]
A [ 15:0]
PORT
B
WR
WR (CNTRL0)
RD
RD (CNTRL1)
BHE (CNTRL2)
BHE
RST
ALE
ALE (PD0)
PORT D
RESET
PORT
C
A[ 23:16]
(OPTIONAL)
PSD813F1-A
ADIO
PORT
PORT
A
Figure 18. An Example of a Typical 8-Bit Non-Multiplexed Bus Interface
D [ 7:0]
MICROCONTROLLER
The
PSD813F1
Functional
Blocks
(cont.)
46
PSD813F1
Preliminary
Preliminary
The
PSD813F1
Functional
Blocks
PSD813F1-A
9.3.3 Data Byte Enable Reference
Microcontrollers have different data byte orientations. The following table shows how the
PSD813F1 interprets byte/word operations in different bus write configurations. Even-byte
refers to locations with address A0 equal to zero and odd byte as locations with A0 equal
to one.
(cont.)
Table 18. Eight-Bit Data Bus
BHE
A0
D7-D0
X
0
Even Byte
X
1
Odd Byte
9.3.4 Microcontroller Interface Examples
Figures 19 through 23 show examples of the basic connections between the PSD813F1
and some popular microcontrollers. The PSD813F1 Control input pins are labeled as to the
microcontroller function for which they are configured. The MCU interface is specified using
the PSDsoft Configuration.
9.3.4.1 80C31
Figure 19 shows the interface to the 80C31, which has an 8-bit multiplexed address/data
bus. The lower address byte is multiplexed with the data bus. The microcontroller control
signals PSEN, RD, and WR may be used for accessing the internal memory components
and I/O Ports. The ALE input (pin PD0) latches the address.
9.3.4.2 80C251
The Intel 80C251 microcontroller features a user-configurable bus interface with four
possible bus configurations, as shown in Table 19.
Configuration 1 is 80C31 compatible, and the bus interface to the PSD813F1 is identical to
that shown in Figure 19. Configurations 2 and 3 have the same bus connection as shown in
Figure 20. There is only one read input (PSEN) connected to the Cntl1 pin on the
PSD813F1. The A16 connection to the PA0 pin allows for a larger address input to the
PSD813F1. Configuration 4 is shown in Figure 21. The RD signal is connected to Cntl1 and
the PSEN signal is connected to the CNTL2.
The 80C251 has two major operating modes: Page Mode and Non-Page Mode. In
Non-Page Mode, the data is multiplexed with the lower address byte, and ALE is active in
every bus cycle. In Page Mode, data D[7:0] is multiplexed with address A[15:8]. In a bus
cycle where there is a Page hit, the ALE signal is not active and only addresses A[7:0]
are changing. The PSD813F1 supports both modes. In Page Mode, the PSD bus timing
is identical to Non-Page Mode except the address hold time and setup time with respect
to ALE is not required. The PSD access time is measured from address A[7:0] valid to
data in valid.
47
PSD813F1-A
The
PSD813F1
Functional
Blocks
Preliminary
Table 19. 80C251 Configurations
Configuration
Connecting to
PSD813F1
Pins
Page Mode
1
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Non-Page Mode, 80C31 compatible
A [7:0] multiplex with D [7:0}
2
WR
PSEN only
CNTL0
CNTL1
Non-Page Mode
A [7:0] multiplex with D [7:0}
3
WR
PSEN only
CNTL0
CNTL1
Page Mode
A [15:8] multiplex with D [7:0}
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Page Mode
A [15:8] multiplex with D [7:0}
(cont.)
4
80C251
Read/Write
Pins
9.3.4.3 80C51XA
The Philips 80C51XA microcontroller family supports an 8- or 16-bit multiplexed bus that
can have burst cycles. Address bits A[3:0] are not multiplexed, while A[19:4] are multiplexed
with data bits D[15:0] in 16-bit mode. In 8-bit mode, A[11:4] are multiplexed with data bits
D[7:0].
The 80C51XA can be configured to operate in eight-bit data mode. (shown in Figure 22).
The 80C51XA improves bus throughput and performance by executing Burst cycles for
code fetches. In Burst Mode, address A19-4 are latched internally by the PSD813F1, while
the 80C51XA changes the A3-0 lines to fetch up to 16 bytes of code. The PSD access
time is then measured from address A3-A0 valid to data in valid. The PSD bus timing
requirement in Burst Mode is identical to the normal bus cycle, except the address setup
and hold time with respect to ALE does not apply.
9.3.4.4 68HC11
Figure 23 shows an interface to a 68HC11 where the PSD813F1 is configured in 8-bit
multiplexed mode with E and R/W settings. The DPLD can generate the READ and WR
signals for external devices.
48
Preliminary
PSD813F1-A
Figure 19. Interfacing the PSD813F1 with an 80C31
AD [ 7:0]
PSD813F
80C31
31
19
18
9
RESET
12
13
14
15
EA/VP
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
X1
X2
RESET
INT0
INT1
T0
T1
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
AD[ 7:0 ]
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
RD
WR
PSEN
ALE/P
TXD
RXD
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
30
31
32
33
34
35
36
37
39
38
37
36
35
34
33
32
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
21
22
23
24
25
26
27
28
A8
A9
A10
A11
A12
A13
A14
A15
39
40
41
42
43
44
45
46
17
RD
WR
47
16
29
PSEN
ALE
30
50
49
11
10
10
9
8
RESET
48
RESET
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
CNTL0 (WR)
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
CNTL1(RD)
CNTL2 (PSEN)
PD0-ALE
PD1
PD2
29
28
27
25
24
23
22
21
7
6
5
4
3
2
52
51
20
19
18
17
14
13
12
11
RESET
Figure 20. Interfacing the PSD813F1 to the 80C251, with One Read Input
PSD813F
80C251SB
A17
2
3
4
5
6
7
8
9
21
20
11
13
14
15
16
17
RESET
10
35
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
X1
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
X2
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
RST
EA
ALE
PSEN
WR
RD/A16
A0
A1
A2
A3
A4
A5
A6
A7
30
31
32
33
34
35
36
37
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
39
40
41
42
43
44
45
46
43
42
41
40
39
38
37
36
A0
A1
A2
A3
A4
A5
A6
A7
24
25
26
27
28
29
30
31
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
33
ALE
47
32
RD
50
18
WR
19
A16
49
10
9
8
RESET
RESET
48
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0 ( WR)
CNTL1( RD)
CNTL 2(PSEN)
PD0- ALE
PD1
PD2
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
29 A16
28
27
25
24
23
22
21
*
A17
*
7
6
5
4
3
2
52
51
20
19
18
17
14
13
12
11
RESET
**Connection is optional.
**Non-page mode: AD[7:0] - ADIO[7:0].
49
PSD813F1-A
Preliminary
Figure 21. Interfacing the PSD813F1 to the 80C251, with Read and PSEN Inputs
80C251SB
2
3
4
5
6
7
8
9
21
20
11
13
14
15
16
17
RESET
10
35
PSD813F
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
X1
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
X2
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
RST
ALE
PSEN
WR
RD/A16
EA
43
42
41
40
39
38
37
36
A0
A1
A2
A3
A4
A5
A6
A7
24
25
26
27
28
29
30
31
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
A0
A1
A2
A3
A4
A5
A6
A7
30
31
32
33
34
35
36
37
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
39
40
41
42
43
44
45
46
33
ALE
47
32
RD
50
18
WR
19
PSEN
49
10
9
8
RESET
RESET
48
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
CNTL0 ( WR)
CNTL1( RD)
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
CNTL 2(PSEN)
PD0- ALE
PD1
PD2
29
28
27
25
24
23
22
21
7
6
5
4
3
2
52
51
20
19
18
17
14
13
12
11
RESET
Figure 22. Interfacing the PSD813F1 to the 80C51XA, 8-Bit Data Bus
PSD813F
80C51XA
21
20
11
13
6
7
9
8
16
RESET
10
14
15
XTAL1
XTAL2
RXD0
TXD0
RXD1
TXD1
T2EX
T2
T0
RST
INT0
INT1
A0/WRH
A1
A2
A3
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12D8
A13D9
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
2
3
4
5
43
42
41
40
39
38
37
36
24
25
26
27
28
29
30
31
A0
A1
A2
A3
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12
A13
A14
A15
A16
A17
A18
A19
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
30
31
32
33
34
35
36
37
A12
A13
A14
A15
A16
A17
A18
A19
39
ADIO8
40
ADIO9
41
ADIO10
42
ADIO11
43
AD1012
44
AD1013
45
ADIO14
46
ADIO15
47
50
35
17
EA/WAIT
BUSW
PSEN
RD
WRL
ALE
32
PSEN
49
19
RD
WR
ALE
10
8
9
18
33
48
RESET
50
ADIO0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
CNTL0 (WR)
CNTL1(RD)
CNTL 2 (PSEN)
PD0-ALE
PD1
PD2
RESET
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
29
28
27
25
24
23
22
21
7
6
5
4
3
2
52
51
20
19
18
17
14
13
12
11
A0
A1
A2
A3
Preliminary
PSD813F1-A
Figure 23. Interfacing the PSD813F1 with a 68HC11
AD[7:0]
AD[7:0]
PSD813F
31
30
29
28
27
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
30
31
32
33
34
35
36
37
42
41
40
39
38
37
36
35
A8
A9
A10
A11
A12
A13
A14
A15
39
40
41
42
43
44
45
46
68HC11
8
7
RESET
17
19
18
2
34
33
32
43
44
45
46
47
48
49
50
52
51
XT
EX
RESET
IRQ
XIRQ
MODB
PA0
PA1
PA2
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
VRH
VRL
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
MODA
E
AS
R/W
9
10
11
12
13
14
15
16
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
20
21
22
23
24
25
47
50
49
10
9
8
48
ADIO0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
ADIO8
ADIO9
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
CNTL0 (R _W)
CNTL1(E)
CNTL 2
PD0 – AS
PD1
PD2
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
29
28
27
25
24
23
22
21
7
6
5
4
3
2
52
51
20
19
18
17
14
13
12
11
RESET
3
5
E
4
AS
6
R/W
RESET
51
PSD813F1-A
The
PSD813F1
Functional
Blocks
(cont.)
Preliminary
9.4 I/O Ports
There are four programmable I/O ports: Ports A, B, C, and D. Each of the ports is eight bits
except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing
multiple functions per port. The ports are configured using PSDsoft Configuration or by the
microcontroller writing to on-chip registers in the CSIOP address space.
The topics discussed in this section are:
• General Port Architecture
• Port Operating Modes
• Port Configuration Registers
• Port Data Registers
• Individual Port Functionality.
9.4.1 General Port Architecture
The general architecture of the I/O Port is shown in Figure 24. Individual Port architectures
are shown in Figures 26 through 29. In general, once the purpose for a port pin has been
defined, that pin will no longer be available for other purposes. Exceptions will be noted.
As shown in Figure 24, the ports contain an output multiplexer whose selects are driven
by the configuration bits in the Control Registers (Ports A and B only) and PSDsoft
Configuration. Inputs to the multiplexer include the following:
❏ Output data from the Data Out Register
❏ Latched address outputs
❏ CPLD Micro⇔Cell output
❏ External Chip Select from CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be
read. The PDB is connected to the Internal Data Bus for feedback and can be read by the
microcontroller. The Data Out and Micro⇔Cell outputs, Direction and Control Registers,
and port pin input are all connected to the PDB.
The Port pin’s tri-state output driver enable is controlled by a two input OR gate whose
inputs come from the CPLD AND array enable product term and the Direction Register. If
the enable product term of any of the array outputs are not defined and that port pin is not
defined as a CPLD output in the PSDabel file, then the Direction Register has sole control
of the buffer that drives the port pin.
The contents of these registers can be altered by the microcontroller. The PDB feedback
path allows the microcontroller to check the contents of the registers.
Ports A, B, and C have embedded Input Micro⇔Cells (IMCs). The IMCs can be configured
as latches, registers, or direct inputs to the PLDs. The latches and registers are clocked by
the address strobe (AS/ALE) or a product term from the PLD AND array. The outputs from
the IMCs drive the PLD input bus and can be read by the microcontroller. Refer to the IMC
subsection of the PLD section.
52
D
Q
DATA OUT
WR
ADDRESS
ALE
ADDRESS
PORT PIN
OUTPUT
MUX
G
MICRO ⇔ CELL OUTPUTS
EXT CS
INTERNAL DATA BUS
READ MUX
P
OUTPUT
SELECT
D
DATA IN
B
Preliminary
Q
Figure 24. General I/O Port Architecture
D
The
PSD813F1
Functional
Blocks
(cont.)
DATA OUT
REG.
CONTROL REG.
D
Q
ENABLE OUT
WR
DIR REG.
D
Q
WR
ENABLE PRODUCT TERM (.OE)
INPUT
MICRO ⇔ CELL
53
PSD813F1-A
CPLD - INPUT
PSD813F1-A
The
PSD813F1
Functional
Blocks
(cont.)
Preliminary
9.4.2 Port Operating Modes
The I/O Ports have several modes of operation. Some modes can be defined using
PSDabel, some by the microcontroller writing to the Control Registers in CSIOP space, and
some by both. The modes that can only be defined using PSDsoft must be programmed
into the device and cannot be changed unless the device is reprogrammed. The modes
that can be changed by the microcontroller can be done so dynamically at run-time. The
PLD I/O, Data Port, Address Input, and Peripheral I/O modes are the only modes that
must be defined before programming the device. All other modes can be changed by the
microcontroller at run-time. See Application Note 55 for more detail.
Table 20 summarizes which modes are available on each port. Table 23 shows how and
where the different modes are configured. Each of the port operating modes are described
in the following subsections.
Table 20. Port Operating Modes
Port Mode
Port A
Port C
Port D
MCU I/O
Yes
Yes
Yes
Yes
PLD I/O
McellAB Outputs
McellBC Outputs
Additional Ext. CS Outputs
PLD Inputs
Yes
No
No
Yes
Yes
Yes
No
Yes
No
Yes
No
Yes
No
No
Yes
Yes
Address Out
Yes (A7 – 0)
Yes (A7 – 0)
or A15 – 8)
No
No
Address In
Yes
Yes
Yes
Yes
Data Port
Yes (D7 – 0)
No
No
No
Peripheral I/O
Yes
No
No
No
JTAG ISP
No
No
Yes*
No
*Can be multiplexed with other I/O functions.
54
Port B
Preliminary
The
PSD813F1
Functional
Blocks
PSD813F1-A
Table 21. Port Operating Mode Settings
Defined In
PSDabel
Mode
Control Direction
VM
Defined In
Register Register Register
PSDconfiguration Setting
Setting
Setting
(cont.)
JTAG
Enable
NA*
0
1 = output,
0 = input
(Note 1)
NA
NA
NA
NA
(Note 1)
NA
NA
Specify bus type
NA
NA
NA
NA
Declare
pins only
NA
1
1 (Note 1)
NA
NA
Address In
(Port A,B,C,D)
Logic equation
for Input
Micro⇔Cells
NA
NA
NA
NA
NA
Peripheral I/O
(Port A)
Logic equations
(PSEL0 & 1)
NA
NA
NA
PIO bit = 1
NA
JTAG ISP
(Note 2)
JTAGSEL
JTAG Configuration
NA
NA
NA
JTAG_
Enable
MCU I/O
Declare
pins only
PLD I/O
Logic
equations
Data Port
(Port A)
NA
Address Out
(Port A,B)
*NA = Not Applicable
NOTE: 1. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the
individual output enable product term (.oe) from the CPLD AND array.
2. Any of these three methods will enable JTAG pins on Port C.
9.4.2.1 MCU I/O Mode
In the MCU I/O Mode, the microcontroller uses the PSD813F1 ports to expand its own
I/O ports. By setting up the CSIOP space, the ports on the PSD813F1 are mapped into the
microcontroller address space. The addresses of the ports are listed in Table 7.
A port pin can be put into MCU I/O mode by writing a ‘0’ to the corresponding bit in the
Control Register. The MCU I/O direction may be changed by writing to the corresponding
bit in the Direction Register, or by the output enable product term. See the subsection on
the Direction Register in the “Port Registers” section. When the pin is configured as an
output, the content of the Data Out Register drives the pin. When configured as an input,
the microcontroller can read the port input through the Data In buffer. See Figure 25.
Ports C and D do not have Control Registers, and are in MCU I/O mode by default. They
can be used for PLD I/O if equation are written for them in PSDabel.
9.4.2.2 PLD I/O Mode
The PLD I/O Mode uses a port as an input to the CPLD’s Input Micro⇔Cells, and/or as an
output from the CPLD’s Output Micro⇔Cells. The output can be tri-stated with a control
signal. This output enable control signal can be defined by a product term from the PLD, or
by setting the corresponding bit in the Direction Register to ‘0’. The corresponding bit in the
Direction Register must not be set to ‘1’ if the pin is defined as a PLD input pin in PSDabel.
The PLD I/O Mode is specified in PSDabel by declaring the port pins, and then writing an
equation assigning the PLD I/O to a port.
55
PSD813F1-A
The
PSD813F1
Functional
Blocks
(cont.)
Preliminary
9.4.2.3 Address Out Mode
For microcontrollers with a multiplexed address/data bus, Address Out Mode can be used
to drive latched addresses onto the port pins. These port pins can, in turn, drive external
devices. Either the output enable or the corresponding bits of both the Direction Register
and Control Register must be set to a ‘1’ for pins to use Address Out Mode. This must be
done by the MCU at run-time. See Table 22 for the address output pin assignments on
Ports A and B for various MCUs.
For non-multiplexed 8 bit bus mode, address lines A[7:0] are available to Port B in Address
Out Mode.
Note: do not drive address lines with Address Out Mode to an external memory device if it
is intended for the MCU to boot from the external device. The MCU must first boot from
PSD memory so the Direction and Control register bits can be set.
Table 22. I/O Port Latched Address Output Assignments
Microcontroller
Port A (3:0)
Port A (7:4)
Port B (3:0)
8051XA (8-Bit)
N/A*
Address (7:4)
Address (11:8)
N/A
80C251
(Page Mode)
N/A
N/A
Address (11:8)
Address (15:12)
All Other
8-Bit Multiplexed
Address (3:0)
Address (7:4)
Address (3:0)
Address (7:4)
N/A
Address [3:0]
Address [7:4]
8-Bit
N/A
Non-Multiplexed Bus
Port B (7:4)
N/A = Not Applicable.
9.4.2.4 Address In Mode
For microcontrollers that have more than 16 address lines, the higher addresses can be
connected to Port A, B, C, and D. The address input can be latched in the Input Micro⇔Cell
by the address strobe (ALE/AS). Any input that is included in the DPLD equations for the
PLD’s Flash, EEPROM, or SRAM is considered to be an address input.
9.4.2.5 Data Port Mode
Port A can be used as a data bus port for a microcontroller with a non-multiplexed
address/data bus. The Data Port is connected to the data bus of the microcontroller. The
general I/O functions are disabled in Port A if the port is configured as a Data Port.
9.4.2.6 Peripheral I/O Mode
Peripheral I/O Mode can be used to interface with external peripherals. In this mode, all of
Port A serves as a tri-stateable, bi-directional data buffer for the microcontroller. Peripheral
I/O Mode is enabled by setting Bit 7 of the VM Register to a ‘1’. Figure 25 shows how Port A
acts as a bi-directional buffer for the microcontroller data bus if Peripheral I/O Mode is
enabled. An equation for PSEL0 and/or PSEL1 must be written in PSDabel. The buffer is
tri-stated when PSEL 0 or 1 is not active.
9.4.2.7 JTAG ISP
Port C is JTAG compliant, and can be used for In-System Programming (ISP). You can
multiplex JTAG operations with other functions on Port C because ISP is not performed
during normal system operation. For more information on the JTAG Port, refer to
section 9.6.
56
Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1-A
Figure 25. Peripheral I/O Mode
RD
PSEL0
PSEL
PSEL1
D0 - D7
DATA BUS
VM REGISTER BIT 7
PA0 - PA7
WR
9.4.3 Port Configuration Registers (PCRs)
Each port has a set of PCRs used for configuration. The contents of the registers can be
accessed by the microcontroller through normal read/write bus cycles at the addresses
given in Table 7. The addresses in Table 7 are the offsets in hex from the base of the
CSIOP register.
The pins of a port are individually configurable and each bit in the register controls its
respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three PCRs,
shown in Table 23, are used for setting the port configurations. The default power-up state
for each register in Table 23 is 00h.
Table 23. Port Configuration Registers
Register Name
Port
MCU Access
Control
A,B
Write/Read
Direction
A,B,C,D
Write/Read
Drive Select*
A,B,C,D
Write/Read
*NOTE:
See Table 27 for Drive Register bit definition.
57
PSD813F1-A
Preliminary
The
PSD813F1
Functional
Blocks
9.4.3.1 Control Register
Any bit set to ‘0’ in the Control Register sets the corresponding Port pin to MCU I/O Mode,
and a ‘1’ sets it to Address Out Mode. The default mode is MCU I/O. Only Ports A and B
have an associated Control Register.
(cont.)
9.4.3.2 Direction Register
The Direction Register, in conjunction with the output enable (except for Port D), controls
the direction of data flow in the I/O Ports. Any bit set to ‘1’ in the Direction Register will
cause the corresponding pin to be an output, and any bit set to ‘0’ will cause it to be an
input. The default mode for all port pins is input.
Figures 26 and 28 show the Port Architecture diagrams for Ports A/B and C, respectively.
The direction of data flow for Ports A, B, and C are controlled not only by the direction
register, but also by the output enable product term from the PLD AND array. If the output
enable product term is not active, the Direction Register has sole control of a given pin’s
direction.
An example of a configuration for a port with the three least significant bits set to output and
the remainder set to input is shown in Table 26. Since Port D only contains three pins, the
Direction Register for Port D has only the three least significant bits active.
Table 24. Port Pin Direction Control,
Output Enable P.T. Not Defined
Direction Register Bit
Port Pin Mode
0
1
Input
Output
Table 25. Port Pin Direction Control, Output Enable P.T. Defined
Direction Register Bit
Output Enable P.T.
Port Pin Mode
0
0
1
1
0
1
0
1
Input
Output
Output
Output
Table 26. Port Direction Assignment Example
58
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
1
1
Preliminary
PSD813F1-A
The
PSD813F1
Functional
Blocks
9.4.3.3 Drive Select Register
The Drive Select Register configures the pin driver as Open Drain or CMOS for some port
pins, and controls the slew rate for the other port pins. An external pull-up resistor should be
used for pins configured as Open Drain.
(cont.)
A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is
set to a ‘1’. The default pin drive is CMOS.
Aside: the slew rate is a measurement of the rise and fall times of an output. A higher slew
rate means a faster output response and may create more electrical noise. A pin operates
in a high slew rate when the corresponding bit in the Drive Register is set to ‘1’. The default
rate is slow slew.
Table 27 shows the Drive Register for Ports A, B, C, and D. It summarizes which pins can
be configured as Open Drain outputs and which pins the slew rate can be set for.
Table 27. Drive Register Pin Assignment
Drive
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port A
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port B
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port C
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port D
NA
NA
NA
NA
NA
Slew
Rate
Slew
Rate
Slew
Rate
NOTE: NA = Not Applicable.
59
PSD813F1-A
The
PSD813F1
Functional
Blocks
(cont.)
Preliminary
9.4.4 Port Data Registers
The Port Data Registers, shown in Table 28, are used by the microcontroller to write data
to or read data from the ports. Table 28 shows the register name, the ports having each
register type, and microcontroller access for each register type. The registers are described
below.
9.4.4.1 Data In
Port pins are connected directly to the Data In buffer. In MCU I/O input mode, the pin input
is read through the Data In buffer.
9.4.4.2 Data Out Register
Stores output data written by the MCU in the MCU I/O output mode. The contents of the
Register are driven out to the pins if the Direction Register or the output enable product
term is set to “1”. The contents of the register can also be read back by the microcontroller.
9.4.4.3 Output Micro⇔Cells (OMCs)
The CPLD OMCs occupy a location in the microcontroller’s address space. The
microcontroller can read the output of the OMCs. If the Mask Micro⇔Cell Register bits are
not set, writing to the Micro⇔Cell loads data to the Micro⇔Cell flip flops. Refer to the PLD
section for more details.
9.4.4.4 Mask Micro⇔Cell Register
Each Mask Register bit corresponds to an OMC flip flop. When the Mask Register bit
is set to a “1”, loading data into the OMC flip flop is blocked. The default value is “0” or
unblocked.
9.4.4.5 Input Micro⇔Cells (IMCs)
The IMCs can be used to latch or store external inputs. The outputs of the IMCs
are routed to the PLD input bus, and can be read by the microcontroller. Refer to the PLD
section for a detailed description.
9.4.4.6 Enable Out
The Enable Out register can be read by the microcontroller. It contains the output enable
values for a given port. A “1” indicates the driver is in output mode. A “0” indicates the driver
is in tri-state and the pin is in input mode.
Table 28. Port Data Registers
Register Name
60
Port
MCU Access
Data In
A,B,C,D
Read – input on pin
Data Out
A,B,C,D
Write/Read
Output Micro⇔Cell
A,B,C
Read – outputs of Micro⇔Cells
Write – loading Micro⇔Cells Flip-Flop
Mask Micro⇔Cell
A,B,C
Write/Read – prevents loading into a given
Micro⇔Cell
Input Micro⇔Cell
A,B,C
Read – outputs of the Input Micro⇔Cells
Enable Out
A,B,C
Read – the output enable control of the port driver
Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1-A
9.4.5 Ports A and B – Functionality and Structure
Ports A and B have similar functionality and structure, as shown in Figure 26. The two ports
can be configured to perform one or more of the following functions:
❏ MCU I/O Mode
❏ CPLD Output – Micro⇔Cells McellAB[7:0] can be connected to Port A or Port B.
McellBC[7:0] can be connected to Port B or Port C.
❏
❏
❏
❏
CPLD Input
– Via the input Micro⇔Cells.
Latched Address output – Provide latched address output per Table 30.
Address In – Additional high address inputs using the Input Micro⇔Cells.
Open Drain/Slew Rate – pins PA[3:0] and PB[3:0] can be configured to fast slew rate,
pins PA[7:4] and PB[7:4] can be configured to Open Drain
Mode.
❏ Data Port – Port A to D[7:0] for 8 bit non-multiplexed bus
❏ Multiplexed Address/Data port for certain types of microcontroller interfaces.
❏ Peripheral Mode – Port A only
61
D
Q
DATA OUT
WR
ADDRESS
ALE
ADDRESS
A[ 7:0] OR A[15:8]
G
PORT
A OR B PIN
OUTPUT
MUX
MICRO ⇔ CELL OUTPUTS
INTERNAL DATA BUS
READ MUX
P
OUTPUT
SELECT
D
PSD813F1-A
Q
Figure 26. Ports A and B Structure
D
The
PSD813F1
Functional
Blocks
(cont.)
62
DATA OUT
REG.
DATA IN
B
CONTROL REG.
D
Q
ENABLE OUT
WR
DIR REG.
D
Q
WR
ENABLE PRODUCT TERM (.OE)
INPUT
MICRO ⇔ CELL
Preliminary
CPLD - INPUT
Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1-A
9.4.6 Port C – Functionality and Structure
Port C can be configured to perform one or more of the following functions (see Figure 28):
❏
❏
❏
❏
❏
MCU I/O Mode
CPLD Output – McellBC[7:0] outputs can be connected to Port B or Port C.
CPLD Input – via the Input Micro⇔Cells
Address In – Additional high address inputs using the Input Micro⇔Cells.
In-System Programming – JTAG port can be enabled for programming/erase of the
PSD813F1 device. (See Section 9.6 for more information on JTAG programming.)
❏ Open Drain – Port C pins can be configured in Open Drain Mode
❏ Battery Backup features – PC2 can be configured as a Battery Input (Vstby) pin.
PC4 can be configured as a Battery On Indicator output
pin, indicating when Vcc is less than Vbat.
Port C does not support Address Out mode, and therefore no Control Register is required.
Pin PC7 may be configured as the DBE input in certain microcontroller interfaces.
9.4.7 Port D – Functionality and Structure
Port D has three I/O pins. See Figure 29. This port does not support Address Out mode,
and therefore no Control Register is required. Port D can be configured to perform one or
more of the following functions:
❏
❏
❏
❏
MCU I/O Mode
CPLD Output – (external chip select)
CPLD Input – direct input to CPLD, no Input Micro⇔Cells
Slew rate – pins can be set up for fast slew rate
Port D pins can be configured in PSDsoft as input pins for other dedicated functions:
❏ PD0 – ALE, as address strobe input
❏ PD1 – CLKIN, as clock input to the Micro⇔Cells Flip Flops and APD counter
❏ PD2 – CSI, as active low chip select input. A high input will disable the
Flash/EEPROM/SRAM and CSIOP.
9.4.7.1 External Chip Select
The CPLD also provides three chip select outputs on Port D pins that can be used to
select external devices. Each chip select (ECS0-2) consists of one product term that can be
configured active high or low. The output enable of the pin is controlled by either the output
enable product term or the Direction Register. (See Figure 29.)
63
64
D
Q
DIR REG.
B
D
P
READ MUX
DATA IN
SPECIAL FUNCTION*
DATA OUT
*ISP or battery back-up.
SPECIAL FUNCTION*
INPUT
MICRO ⇔ CELL
ENABLE OUT
OUTPUT
SELECT
OUTPUT
MUX
CONFIGURATION
BIT
PORT C PIN
(cont.)
CPLD -INPUT
ENABLE PRODUCT TERM (.OE)
WR
MCELLBC [ 7:0 ]
WR
Q
The
PSD813F1
Functional
Blocks
D
DATA OUT
REG.
PSD813F1-A
Preliminary
Figure 27. Port C Structure
INTERNAL DATA BUS
WR
PORT D PIN
OUTPUT
MUX
Preliminary
Q
Figure 28. Port D Structure
DATA OUT
D
The
PSD813F1
Functional
Blocks
(cont.)
DATA OUT
REG.
ECS [ 2:0 ]
INTERNAL DATA BUS
READ MUX
OUTPUT
SELECT
P
D
DATA IN
B
ENABLE PRODUCT
TERM (.OE)
DIR REG.
D
WR
Q
65
PSD813F1-A
CPLD-INPUT
CPLD AND ARRAY
PLD INPUT BUS
PD0 PIN
ECS0
POLARITY
BIT
ENABLE (.OE)
PT1
DIRECTION
REGISTER
PSD813F1-A
DIRECTION
REGISTER
Figure 29. Port D External Chip Selects
PT0
The
PSD813F1
Functional
Blocks
(cont.)
66
ENABLE (.OE)
PD1 PIN
ECS1
POLARITY
BIT
ENABLE (.OE)
PT2
DIRECTION
REGISTER
ECS2
Preliminary
POLARITY
BIT
PD2 PIN
Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1-A
9.5 Power Management
The PSD813F1 offers configurable power saving options. These options may be used
individually or in combinations, as follows:
❏ All memory types in a PSD (Flash, EEPROM, and SRAM) are built with Zero-Power
technology. In addition to using special silicon design methodology, Zero-Power
technology puts the memories into standby mode when address/data inputs are not
changing (zero DC current). As soon as a transition occurs on an input, the affected
memory “wakes up”, changes and latches its outputs, then goes back to standby. The
designer does not have to do anything special to achieve memory standby mode when
no inputs are changing—it happens automatically.
The PLD sections can also achieve standby mode when its inputs are not changing,
see PMMR registers below.
❏ Like the Zero-Power feature, the Automatic Power Down (APD) logic allows the PSD to
reduce to standby current automatically. The APD will block MCU address/data signals
from reaching the memories and PLDs. This feature is available on all PSD813F1
devices. The APD unit is described in more detail in section 9.5.1.
Built in logic will monitor the address strobe of the MCU for activity. If there is no activity
for a certain time period (MCU is asleep), the APD logic initiates Power Down Mode
(if enabled). Once in Power Down Mode, all address/data signals are blocked from
reaching PSD memories and PLDs, and the memories are deselected internally. This
allows the memories and PLDs to remain in standby mode even if the address/data
lines are changing state externally (noise, other devices on the MCU bus, etc.). Keep
in mind that any unblocked PLD input signals that are changing states keeps the PLD
out of standby mode, but not the memories.
❏ The PSD Chip Select Input (CSI) on all families can be used to disable the internal
memories, placing them in standby mode even if inputs are changing. This feature
does not block any internal signals or disable the PLDs. This is a good alternative to
using the APD logic, especially if your MCU has a chip select output. There is a slight
penalty in memory access time when the CSI signal makes its initial transition from
deselected to selected.
❏ The PMMR registers can be written by the MCU at run-time to manage power.
PSD813F1 supports “blocking bits” in these registers that are set to block
designated signals from reaching both PLDs. Current consumption of the PLDs is
directly related to the composite frequency of the changes on their inputs (see Figures
34 and 34a). Significant power savings can be achieved by blocking signals that are
not used in DPLD or CPLD logic equations.
The PSD813F1 has a Turbo Bit in the PMMR0 register. This bit can be set to disable
the Turbo Mode feature (default is Turbo Mode on). While Turbo Mode is disabled, the
PLDs can achieve standby current when no PLD inputs are changing (zero DC current).
Even when inputs do change, significant power can be saved at lower frequencies
(AC current), compared to when Turbo Mode is enabled. When the Turbo Mode is
enabled, there is a significant DC current component and the AC component is higher.
9.5.1 Automatic Power Down (APD) Unit and Power Down Mode
The APD Unit, shown in Figure 30, puts the PSD into Power Down Mode by monitoring
the activity of the address strobe (ALE/AS). If the APD unit is enabled, as soon as activity
on the address strobe stops, a four bit counter starts counting. If the address strobe
remains inactive for fifteen clock periods of the CLKIN signal, the Power Down (PDN) signal
becomes active, and the PSD will enter into Power Down Mode, discussed next.
67
PSD813F1-A
The
PSD813F1
Functional
Blocks
(cont.)
Preliminary
9.5.1 Automatic Power Down (APD) Unit and Power Down Mode (cont.)
Power Down Mode
By default, if you enable the PSD APD unit, Power Down Mode is automatically enabled.
The device will enter Power Down Mode if the address strobe (ALE/AS) remains inactive for
fifteen CLKIN (pin PD1) clock periods.
The following should be kept in mind when the PSD is in Power Down Mode:
• If the address strobe starts pulsing again, the PSD will return to normal operation.
•
•
•
•
The PSD will also return to normal operation if either the CSI input returns low or the
Reset input returns high.
The MCU address/data bus is blocked from all memories and PLDs.
Various signals can be blocked (prior to Power Down Mode) from entering the PLDs
by setting the appropriate bits in the PMMR registers. The blocked signals include
MCU control signals and the common clock (CLKIN). Note that blocking CLKIN from
the PLDs will not block CLKIN from the APD unit.
All PSD memories enter Standby Mode and are drawing standby current. However,
the PLDs and I/O ports do not go into Standby Mode because you don’t want to have
to wait for the logic and I/O to “wake-up” before their outputs can change. See table 29
for Power Down Mode effects on PSD ports.
Typical standby current is 50 µA for 5 V devices, and 25 µA for 3 V devices. These
standby current values assume that there are no transitions on any PLD input.
Table 29. Power Down Mode’s Effect on
Ports
Port Function
Pin Level
MCU I/O
PLD Out
Address Out
Data Port
Peripheral I/O
No Change
No Change
Undefined
Three-State
Three-State
Table 30. PSD813F1 Timing and Standby Current During Power
Down Mode
Mode
Power Down
PLD
Propagation
Delay
Memory
Access
Time
Access
Recovery Time
to Normal
Access
5V VCC,
Typical
Standby
Current
Normal tpd
(Note 1)
No Access
tLVDV
50 µA
(Note 2)
NOTES: 1. Power Down does not affect the operation of the PLD. The PLD operation in this
mode is based only on the Turbo Bit.
2. Typical current consumption assuming no PLD inputs are changing state and
the PLD Turbo bit is off.
HC11 (or compatible) Users Note
The HC11 turns off its E clock when it sleeps. Therefore, if you are using an HC11
(or compatible) in your design, and you wish to use the Power Down, you must not
connect the E clock to the CLKIN input (PD1). You should instead connect an
independent clock signal to the CLKIN input. The clock frequency must be less than
15 times the frequency of AS. The reason for this is that if the frequency is greater than
15 times the frequency of AS, the PSD813F1 will keep going into Power Down Mode.
68
Preliminary
The
PSD813F1
Functional
Blocks
PSD813F1-A
Figure 30. APD Logic Block
APD EN
PMMR0 BIT 1=1
(cont.)
TRANSITION
DETECTION
DISABLE BUS
INTERFACE
ALE
PD
CLR
RESET
CSI
EEPROM SELECT
APD
COUNTER
FLASH SELECT
EDGE
DETECT
PD
PLD
CLKIN
SRAM SELECT
POWER DOWN
(PDN) SELECT
DISABLE
FLASH/EEPROM/SRAM
Figure 31. Enable Power Down Flow Chart
RESET
Enable APD
Set PMMR0 Bit 1 = 1
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 2 through 6.
No
ALE/AS idle
for 15 CLKIN
clocks?
Yes
PSD in Power
Down Mode
69
PSD813F1-A
The
PSD813F1
Functional
Blocks
(cont.)
Preliminary
Table 31. Power Management Mode Registers (PMMR0, PMMR2)**
PMMR0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
*
PLD
Mcell clk
PLD
Array clk
PLD
Turbo
*
APD
Enable
*
1 = off
1 = off
1 = off
1 = on
***Bits 0, 2, 6, and 7 are not used, and should be set to 0.
***The PMMR0, and PMMR2 register bits are cleared to zero following power up.
***Subsequent reset pulses will not clear the registers.
Bit 1 0
1
Bit 3 0
1
Bit 4 0
=
=
=
=
=
Automatic Power Down (APD) is disabled.
Automatic Power Down (APD) is enabled.
PLD Turbo is on.
PLD Turbo is off, saving power.
CLKIN input to the PLD AND array is connected.
Every CLKIN change will power up the PLD when Turbo bit is off.
1 = CLKIN input to PLD AND array is disconnected, saving power.
Bit 5 0 = CLKIN input to the PLD Micro⇔Cells is connected.
1 = CLKIN input to PLD Micro⇔Cells is disconnected, saving power.
PMMR2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
PLD
array
DBE
PLD
array
ALE
PLD
array
CNTL2
PLD
array
CNTL1
PLD
array
CNTL0
*
*
1 = off
1 = off
1 = off
1 = off
1 = off
*Unused bits should be set to 0.
Bit 2 0 = Cntl0 input to the PLD AND array is connected.
1 = Cntl0 input to PLD AND array is disconnected, saving power.
Bit 3 0 = Cntl1 input to the PLD AND array is connected.
1 = Cntl1 input to PLD AND array is disconnected, saving power.
Bit 4 0 = Cntl2 input to the PLD AND array is connected.
1 = Cntl2 input to PLD AND array is disconnected, saving power.
Bit 5 0 = ALE input to the PLD AND array is connected.
1 = ALE input to PLD AND array is disconnected, saving power.
Bit 6 0 = DBE input to the PLD AND array is connected.
1 = DBE input to PLD AND array is disconnected, saving power.
70
Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1-A
Table 32. APD Counter Operation
APD
Enable Bit
ALE
PD Polarity
ALE Level
APD Counter
0
1
1
1
X
X
1
0
X
Pulsing
1
0
Not Counting
Not Counting
Counting (Generates PDN after 15 Clocks)
Counting (Generates PDN after 15 Clocks)
9.5.2 Other Power Saving Options
The PSD813F1 offers other reduced power saving options that are independent of the
Power Down Mode. Except for the SRAM Standby and CSI input features, they are enabled
by setting bits in the PMMR0 and PMMR2 registers.
9.5.2.1 Zero Power PLD
The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in the PMMR0. By
setting the bit to “1”, the Turbo mode is disabled and the PLDs consume Zero Power
current when the inputs are not switching for an extended time of 70 ns. The propagation
delay time will be increased by 10 ns after the Turbo bit is set to “1” (turned off) when the
inputs change at a composite frequency of less than 15 MHz. When the Turbo bit is set to a
“0” (turned on), the PLDs run at full power and speed. The Turbo bit affects the PLD’s D.C.
power, AC power, and propagation delay.
Note: Blocking MCU control signals with PMMR2 bits can further reduce PLD AC power
consumption.
9.5.2.2 SRAM Standby Mode (Battery Backup)
The PSD813F1 supports a battery backup operation that retains the contents of the SRAM
in the event of a power loss. The SRAM has a Vstby pin (PC2) that can be connected to an
external battery. When VCC becomes lower than Vstby then the PSD will automatically
connect to Vstby as a power source to the SRAM. The SRAM Standby Current (Istby) is
typically 0.5 µA. The SRAM data retention voltage is 2 V minimum. The battery-on indicator
(Vbaton) can be routed to PC4. This signal indicates when the VCC has dropped below the
Vstby voltage.
9.5.2.3 The CSI Input
Pin PD2 of Port D can be configured in PSDsoft as the CSI input. When low, the signal
selects and enables the internal Flash, EEPROM, SRAM, and I/O for read or write
operations involving the PSD813F1. A high on the CSI pin will disable the Flash memory,
EEPROM, and SRAM, and reduce the PSD power consumption. However, the PLD and I/O
pins remain operational when CSI is high. Note: there may be a timing penalty when using
the CSI pin depending on the speed grade of the PSD that you are using. See the timing
parameter t SLQV in the AC/DC specs.
9.5.2.4 Input Clock
The PSD813F1 provides the option to turn off the CLKIN input to the PLD to save AC power
consumption. The CLKIN is an input to the PLD AND array and the Output Micro⇔Cells.
During Power Down Mode, or, if the CLKIN input is not being used as part of the PLD logic
equation, the clock should be disabled to save AC power. The CLKIN will be disconnected
from the PLD AND array or the Micro⇔Cells by setting bits 4 or 5 to a “1” in PMMR0.
9.5.2.5 Input Control Signals
The PSD813F1 provides the option to turn off the input control signals (CNTL0-2, ALE, and
DBE) to the PLD to save AC power consumption. These control signals are inputs to the
PLD AND array. During Power Down Mode, or, if any of them are not being used as part of
the PLD logic equation, these control signals should be disabled to save AC power. They
will be disconnected from the PLD AND array by setting bits 2, 3, 4, 5, and 6 to a “1” in the
PMMR2.
71
PSD813F1-A
The
PSD813F1
Functional
Blocks
(cont.)
Preliminary
9.5.3 Reset and Power On Requirement
Power On Reset
Upon power up the PSD813F1 requires a reset pulse of tNLNH-PO (minimum 1ms) after
VCC is steady. During this time period the device loads internal configurations, clears some
of the registers and sets the Flash or EEPROM into operating mode. After the rising edge of
reset, the PSD813F1 remains in the reset state for an additional tOPR (minimum 120 ns)
nanoseconds before the first memory access is allowed.
The PSD813F1 Flash or EEPROM memory is reset to the read array mode upon power up.
The FSi and EESi select signals along with the write strobe signal must be in the false state
during power-up reset for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of a write strobe signal. The PSD
automatically prevents write strobes from reaching the EEPROM memory array for about
5 ms (tEEHWL). Any Flash memory write cycle initiation is prevented automatically when
VCC is below VLKO.
Warm Reset
Once the device is up and running, the device can be reset with a much shorter pulse of
tNLNH (minimum 150 ns). The same tOPR time is needed before the device is operational
after warm reset. Figure 32 shows the timing of the power on and warm reset.
Figure 32. Power On and Warm Reset Timing
OPERATING LEVEL
t NLNH
t NLNH – PO
VCC
RESET
t OPR
POWER ON RESET
WARM
RESET
t OPR
I/O Pin, Register and PLD Status at Reset
Table 33 shows the I/O pin, register and PLD status during power on reset, warm reset and
power down mode. PLD outputs are always valid during warm reset, and they are valid in
power on reset once the internal PSD configuration bits are loaded. This loading of PSD is
completed typically long before the VCC ramps up to operating level. Once the PLD is
active, the state of the outputs are determined by the PSDabel equations.
72
Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1-A
Table 33. Status During Power On Reset, Warm Reset and Power Down Mode
Port Configuration
Power On Reset
Warm Reset
MCU I/O
Input Mode
PLD Output
Valid after internal
PSD configuration
bits are loaded
Address Out
Tri-stated
Tri-stated
Not defined
Data Port
Tri-stated
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
Tri-stated
Register
Input Mode
Power Down Mode
Valid
Power On Reset
Warm Reset
Unchanged
Depend on inputs to
PLD (address are
blocked in PD mode)
Power Down Mode
PMMR0, 2
Cleared to “0”
Unchanged
Unchanged
Micro⇔Cells Flip
Flop status
Cleared to “0” by
internal power on
reset
Depend on .re and
.pr equations
Depend on .re and
.pr equations
VM Register*
Initialized based on
the selection in
PSDsoft
Configuration Menu.
Initialized based on
the selection in
PSDsoft
Configuration Menu
Unchanged
All other registers
Cleared to “0”
Cleared to “0”
Unchanged
*SR_cod and Periph Mode bits in the VM Register are always cleared to zero on power on or warm reset.
9.6 Programming In-Circuit using the JTAG Interface
The JTAG interface on the PSD813F1 can be enabled on Port C (see Table 34). All memory
(Flash and EEPROM), PLD logic, and PSD configuration bits may be programmed through
the JTAG interface. A blank part can be mounted on a printed circuit board and
programmed using JTAG.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and
erase operations.
By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port C
are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
See Application Note 54 for more details on JTAG In-System-Programming.
Table 34. JTAG Port Signals
Port C Pin
JTAG Signals
Description
PC0
TMS
Mode Select
PC1
TCK
Clock
PC3
TSTAT
Status
PC4
TERR
Error Flag
PC5
TDI
Serial Data In
PC6
TDO
Serial Data Out
73
PSD813F1-A
The
PSD813F1
Functional
Blocks
(cont.)
Preliminary
9.6.1 Standard JTAG Signals
The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three
different conditions that are logically ORed. When enabled, TDI, TDO, TCK, and TMS are
inputs, waiting for a serial command from an external JTAG controller device (such as
FlashLink or Automated Test Equipment). When the enabling command is received from the
external JTAG controller, TDO becomes an output and the JTAG channel is fully functional
inside the PSD. The same command that enables the JTAG channel may optionally enable
the two additional JTAG pins, TSTAT and TERR.
The following symbolic logic equation specifies the conditions enabling the four basic
JTAG pins (TMS, TCK, TDI, and TDO) on their respective Port C pins. For purposes of
discussion, the logic label JTAG_ON will be used. When JTAG_ON is true, the four pins are
enabled for JTAG. When JTAG_ON is false, the four pins can be used for general PSD I/O.
JTAG_ON =
PSDsoft_enabled +
/* An NVM configuration bit inside the PSD is set by the designer
in the PSDsoft Configuration utility. This dedicates the pins for
JTAG at all times (compliant with IEEE 1149.1) */
Microcontroller_enabled +
/* The microcontroller can set a bit at run-time by writing to the
PSD register, JTAG Enable. This register is located at address
CSIOP + offset C7h. Setting the JTAG_ENABLE bit in this
register will enable the pins for JTAG use. This bit is cleared
by a PSD reset or the microcontroller. See Table 35 for bit
definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT) inside the PSD can be used to
enable the JTAG pins. This PT has the reserved name
JTAGSEL. Once defined as a node in PSDabel, the designer
can write an equation for JTAGSEL. This method is used when
the Port C JTAG pins are multiplexed with other I/O signals.
It is recommended to logically tie the node JTAGSEL to the
JEN\ signal on the Flashlink cable when multiplexing JTAG
signals. See Application Note 54 for details.
Table 35. JTAG Enable Register
JTAG Enable
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
*
*
*
*
*
*
JTAG_ENABLE
*Bits 1-7 are not used and should set to 0.
Bit definitions:
JTAG_ENABLE 1 = JTAG Port is Enabled.
0 = JTAG Port is Disabled.
74
Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
PSD813F1-A
9.6.1 Standard JTAG Signals (cont.)
The PSD813F1 supports JTAG In-System-Configuration (ISC) commands, but not
Boundary Scan. A definition of these JTAG-ISC commands and sequences are defined in a
supplemental document available from ST. ST’s PSDsoft software tool and FlashLink JTAG
programming cable implement these JTAG-ISC commands. This document is needed only
as a reference for designers who use a FlashLink to program their PSD813F1.
9.6.2 JTAG Extensions
TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE”
command received over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They are
used to speed programming and erase functions by indicating status on PSD pins instead
of having to scan the status out serially using the standard JTAG channel. See Application
Note 54.
TERR will indicate if an error has occurred when erasing a sector or programming a byte in
Flash memory. This signal will go low (active) when an error condition occurs, and stay
low until an “ISC_CLEAR” command is executed or a chip reset pulse is received after an
“ISC-DISABLE” command. TERR does not apply to EEPROM.
TSTAT behaves the same as the Rdy/Bsy signal described in section 9.1.1.2. TSTAT will be
high when the PSD813F1 device is in read array mode (Flash memory and EEPROM
contents can be read). TSTAT will be low when Flash memory programming or erase cycles
are in progress, and also when data is being written to EEPROM.
TSTAT and TERR can be configured as open-drain type signals during an “ISC_ENABLE”
command. This facilitates a wired-OR connection of TSTAT signals from several PSD813F1
devices and a wired-OR connection of TERR signals from those same devices. This is
useful when several PSD813F1 devices are “chained” together in a JTAG environment.
9.6.3 Security and Flash Memories and EEPROM Protection
When the security bit is set, the device cannot be read on a device programmer or through
the JTAG Port. When using the JTAG Port, only a full chip erase command is allowed.
All other program/erase/verify commands are blocked. Full chip erase returns the part to a
non-secured blank state. The Security Bit can be set in PSDsoft Configuration.
All Flash Memory and EEPROM sectors can individually be sector protected against
erasures. The sector protect bits can be set in PSDsoft Configuration.
75
PSD813F1-A
Absolute
Maximum
Ratings
Preliminary
Symbol
Min
Max
Unit
– 65
+ 125
°C
0
+ 70
°C
Industrial
– 40
+ 85
°C
Voltage on any Pin
With Respect to GND
– 0.6
+7
V
VPP
Device Programmer
Supply Voltage
With Respect to GND
– 0.6
+ 14
V
VCC
Supply Voltage
With Respect to GND
– 0.6
+7
V
TSTG
Parameter
Condition
Storage Temperature
PLDCC
Operating Temperature
Commercial
>2000
ESD Protection
V
NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not recommended. Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect device reliability.
Operating
Range
Range
Commercial
Industrial
Commercial
Industrial
Recommended
Operating
Conditions
76
Temperature
VCC Tolerance
0° C to +70°C
+ 5 V ± 10%
–40° C to +85°C
+ 5 V ± 10%
0° C to +70°C
3 V to 3.6 V
–40° C to +85°C
3 V to 3.6 V
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VCC
Supply Voltage
All Speeds
4.5
5
5.5
V
VCC
Supply Voltage
V-Versions
All Speeds
3.0
3.6
V
Preliminary
The following tables describe the AD/DC parameters of the PSD813F1 family:
❏ DC Electrical Specification
❏ AC Timing Specification
• PLD Timing
•
– Combinatorial Timing
– Synchronous Clock Mode
– Asynchronous Clock Mode
– Input Micro⇔Cell Timing
Microcontroller Timing
– Read Timing
– Write Timing
– Peripheral Mode Timing
– Power Down and Reset Timing
Following are issues concerning the parameters presented:
❏ In the DC specification the supply current is given for different modes of operation.
Before calculating the total power consumption, determine the percentage of time that
the PSD813F1 is in each mode. Also, the supply power is considerably different if the
Turbo bit is "OFF".
❏ The AC power component gives the PLD, EPROM, and SRAM mA/MHz specification.
Figures 33 and 33a show the PLD mA/MHz as a function of the number of Product
Terms (PT) used.
❏ In the PLD timing parameters, add the required delay when Turbo bit is "OFF".
Figure 33. PLD ICC /FrequencyConsumption (VCC = 5 V ± 10%)
110
VCC = 5V
100
)
00%
90
BO
(1
ON
TUR
80
70
FF
)
ON
BO
R
U
T
BO
O
60
50
(25%
TU
R
ICC – (mA)
AC/DC
Parameters
PSD813F1-A
40
30
F
20
O
RB
OF
PT 100%
PT 25%
TU
10
0
0
5
10
15
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
77
PSD813F1-A
AC/DC
Parameters
Preliminary
Figure 33a. PLD ICC /Frequency Consumption (PSD813FV Versions, VCC = 3 V)
60
(cont.)
VCC = 3V
50
TU
40
O
FF
30
5%)
(2
O ON
B
R
U
T
RB
O
ICC – (mA)
)
100%
ON (
RBO
TU
20
10
PT 100%
PT 25%
F
O
RB
TU
OF
0
0
5
10
15
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
Example of PSD813F Typical Power Calculation at VCC = 5.0 V
Conditions
Highest Composite PLD input frequency
(Freq PLD)
MCU ALE frequency (Freq ALE)
% Flash Access
% SRAM access
% I/O access
=
=
=
=
=
8 MHz
4 MHz
80%
15%
5% (no additional power above base)
Operational Modes
% Normal
% Power Down Mode
=
=
10%
90%
Number of product terms used
(from fitter report)
% of total product terms
=
=
45 PT
45/182 = 24.7%
Turbo Mode
=
ON
Calculation (typical numbers used)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE
+ %SRAM x 1.5 mA/MHz x Freq ALE
+ % PLD x 2 mA/MHz x Freq PLD
+ #PT x 400 µA/PT
= 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz
+ 0.15 x 1.5 mA/MHz x 4 MHz
+2 mA/MHz x 8 MHz
+ 45 x 0.4 mA/PT)
= 45 µA + 0.1 x (8 + 0.9 + 16 + 18 mA)
= 45 µA + 0.1 x 42.9
= 45 µA + 4.29 mA
= 4.34 mA
This is the operating power with no EEPROM writes or Flash erases. Calculation is
based on IOUT = 0 mA.
78
Preliminary
AC/DC
Parameters
(cont.)
PSD813F1-A
Example of PSD813F1 Typical Power Calculation at VCC = 5.0 V
Conditions
Highest Composite PLD input frequency
(Freq PLD)
=
8 MHz
MCU ALE frequency (Freq ALE)
=
4 MHz
% Flash Access
% SRAM access
% I/O access
=
=
=
80%
15%
5% (no additional power above base)
Operational Modes
% Normal
% Power Down Mode
=
=
10%
90%
Number of product terms used
(from fitter report)
% of total product terms
=
=
45 PT
45/182 = 24.7%
Turbo Mode
=
Off
Calculation (typical numbers used)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE
+ %SRAM x 1.5 mA/MHz x Freq ALE
+ % PLD x (from graph using Freq PLD))
= 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz
+ 0.15 x 1.5 mA/MHz x 4 MHz
+ 24 mA)
= 45 µA + 0.1 x (8 + 0.9 + 24)
= 45 µA + 0.1 x 32.9
= 45 µA + 3.29 mA
= 3.34 mA
This is the operating power with no EEPROM writes or Flash erases. Calculation is
based on IOUT = 0 mA.
79
PSD813F1-A
Preliminary
PSD813F1 DC Characteristics
Symbol
(5 V ± 10% Versions)
Parameter
Conditions
Min
Max
Unit
5
5.5
V
VCC
Supply Voltage
All Speeds
VIH
High Level Input Voltage
4.5 V < VCC < 5.5 V
2
VCC +.5
V
VIL
Low Level Input Voltage
4.5 V < VCC < 5.5 V
–.5
0.8
V
VIH1
Reset High Level Input Voltage
(Note 1)
.8 VCC
VCC +.5
V
VIL1
Reset Low Level Input Voltage
(Note 1)
–.5
.2 VCC –.1
V
VHYS
Reset Pin Hysteresis
0.3
VLKO
VCC Min for Flash Erase and Program
2.5
VOL
Output Low Voltage
VOH
Output High Voltage Except VSTBY On
V
IOL = 8 mA, VCC = 4.5 V
0.25
0.45
V
IOH = –20 µA, VCC = 4.5 V
4.4
4.49
V
IOH = –2 mA, VCC = 4.5 V
2.4
3.9
V
SRAM Standby Voltage
ISBY
SRAM Standby Current (VSTBY Pin)
VCC = 0 V
IIDLE
Idle Current (VSTBY Pin)
VCC > VSBY
VDF
SRAM Data Retention Voltage
Only on VSTBY
ISB
Standby Supply Current for Power
Down Mode
CSI > VCC –0.3 V
(Notes 2 and 3)
ILI
Input Leakage Current
VSS < VIN < VCC
ILO
Output Leakage Current
0.45 < VIN < VCC
IOH1 = 1 µA
VSBY – 0.8
V
2.0
0.5
–0.1
VCC
V
1
µA
0.1
µA
2
V
50
200
µA
–1
±.1
1
µA
–10
±5
10
µA
ZPLD_TURBO = OFF,
f = 0 MHz (Note 5)
0
ZPLD_TURBO = ON,
f = 0 MHz
400
700
µA/PT
During Flash or EEPROM,
Write/Erase Only
15
30
mA
Read Only, f = 0 MHz
0
0
mA
f = 0 MHz
0
0
mA
FLASH or EEPROM AC Adder
2.5
3.5
mA/MHz
SRAM AC Adder
1.5
3.0
mA/MHz
ZPLD Only
Operating Supply
Current
Flash or
EEPROM
SRAM
ZPLD AC Adder
80
V
0.1
VSBY
NOTE: 1.
2.
3.
4.
5.
4.2
0.01
Output High Voltage VSTBY On
ICC (AC)
(Note 5)
V
IOL = 20 µA, VCC = 4.5 V
VOH1
ICC (DC)
(Note 5)
4.5
Typ
mA
Fig. 33
(Note 4)
Reset input has hysteresis. VIL1 is valid at or below .2VCC –.1. VIH1 is valid at or above .8VCC.
CSI deselected or internal Power Down mode is active.
PLD is in non-turbo mode and none of the inputs are switching
Refer to Figure 32 for PLD current calculation.
I OUT = 0 mA
Preliminary
PSD813F1 AC/DC
Parameters –
CPLD Timing
Parameters
(5 V ± 10% Versions)
CPLD Combinatorial Timing (5 V ± 10%)
-90
Symbol
Parameter
Conditions
Min
-12
Max
Min
-15
Max
Min
Max
Fast
PT
Aloc
TURBO
OFF*
Slew
(Note 1)
Unit
t PD
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
25
30
32
Add 2 Add 10 Sub 2
ns
t EA
CPLD Input to CPLD
Output Enable
26
30
32
Add 10 Sub 2
ns
t ER
CPLD Input to CPLD
Output Disable
26
30
32
Add 10 Sub 2
ns
t ARP
CPLD Register Clear or
Preset Delay
26
30
33
Add 10 Sub 2
ns
t ARPW
CPLD Register Clear or
Preset Pulse Width
Add 10
ns
t ARD
CPLD Array Delay
20
Any
Micro⇔Cell
24
16
29
18
22
Add 2
ns
NOTE: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
*ZPSD versions only.
PSD813F1-A
81
PSD813F1-A
PSD813F1 AC/DC
Parameters –
CPLD Timing
Parameters
(5 V ± 10% Versions)
82
CPLD Micro⇔Cell Synchronous Clock Mode Timing (5 V ± 10% Versions)
-90
Symbol
f MAX
Parameter
Conditions
Min
-12
Max
Min
-15
Max
Min
Max
Fast
PT
Aloc
TURBO
OFF*
Slew
(Note 1)
Unit
Maximum Frequency
External Feedback
1/(tS + t CO )
30.30
26.3
23.8
MHz
Maximum Frequency
Internal Feedback
( fCNT )
1/(tS + t CO –10)
43.48
35.7
31.25
MHz
Maximum Frequency
Pipelined Data
1/(tC H + t CL )
50.00
41.67
33.3
MHz
tS
Input Setup Time
15
18
20
tH
Input Hold Time
0
0
0
ns
t CH
Clock High Time
Clock Input
10
12
15
ns
t CL
Clock Low Time
Clock Input
10
12
15
ns
t CO
Clock to Output Delay
Clock Input
18
20
22
t ARD
CPLD Array Delay
Any Micro⇔Cell
16
18
22
t MIN
Minimum Clock Period
tC H + t CL (Note 2)
20
24
30
Add 2 Add 10
ns
Sub 2
Add 2
ns
ns
ns
NOTES: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
2. CLKIN t CLCL = t CH + t CL.
*ZPSD versions only.
Preliminary
Preliminary
PSD813F1 AC/DC
Parameters –
CPLD Timing
Parameters
(5 V ± 10% Versions)
CPLD Micro⇔Cell Asynchronous Clock Mode Timing (5 V ± 10% Versions)
-90
Symbol
f MAXA
Parameter
Conditions
Min
-12
Max
Min
-15
Max
Min
Max
PT
Aloc
TURBO
OFF*
Slew
Rate
Unit
Maximum Frequency
External Feedback
1/(tS A + t CO A )
26.32
23.25
20.4
MHz
Maximum Frequency
Internal Feedback
( fCNTA)
1/(tS A + t CO A –10)
35.71
30.30
25.64
MHz
Maximum Frequency
Pipelined Data
1/(tC H A+ t CLA)
41.67
35.71
33.3
MHz
t SA
Input Setup Time
8
10
12
t HA
Input Hold Time
12
14
14
t CHA
Clock Input High Time
12
14
15
Add 10
ns
t CLA
Clock Input Low Time
12
14
15
Add 10
ns
t COA
Clock to Output Delay
Add 10 Sub 2
ns
t ARDA
CPLD Array Delay
Any Micro⇔Cell
t MINA
Minimum Clock Period
1/ fC NTA
28
Add 2 Add 10
ns
30
33
37
16
18
22
33
39
ns
Add 2
ns
ns
*ZPSD versions only.
PSD813F1-A
83
PSD813F1-A
PSD813F1 AC/DC
Parameters –
CPLD Timing
Parameters
(5 V ± 10% Versions)
84
Input Micro⇔Cell Timing (5 V ± 10% Versions)
-90
Symbol
Parameter
Conditions
Min
-12
Max
Min
15
Max
Min
Max
PT
Aloc
TURBO
OFF*
Unit
t IS
Input Setup Time
(Note 1)
0
0
0
t IH
Input Hold Time
(Note 1)
20
22
26
t INH
NIB Input High Time
(Note 1)
12
15
18
ns
t IN L
NIB Input Low Time
(Note 1)
12
15
18
ns
t INO
NIB Input to Combinatorial Delay
(Note 1)
46
50
ns
Add 10
59
Add 2
Add 10
ns
ns
NOTE: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX.
*ZPSD versions only.
Preliminary
Preliminary
Microcontroller
Interface –
AC/DC
Parameters
(5V ± 10% Versions)
PSD813F1-A
AC Symbols for PLD Timing.
Example:
t AVLX – Time from Address Valid to ALE Invalid.
Signal Letters
A
C
D
E
G
I
L
N
P
Q
R
S
T
W
B
M
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Address Input
CEout Output
Input Data
E Input
Internal WDOG_ON signal
Interrupt Input
ALE Input
Reset Input or Output
Port Signal Output
Output Data
WR, UDS, LDS, DS, IORD, PSEN Inputs
Chip Select Input
R/W Input
Internal PDN Signal
Vstby Output
Output Micro⇔Cell
Signal Behavior
t
L
H
V
X
Z
PW
–
–
–
–
–
–
–
Time
Logic Level Low or ALE
Logic Level High
Valid
No Longer a Valid Logic Level
Float
Pulse Width
85
PSD813F1-A
Preliminary
Microcontroller Interface – PSD813F1 AC/DC Parameters
(5V ± 10% Versions)
Read Timing (5 V ± 10% Versions)
-90
Symbol
Parameter
t LVLX
ALE or AS Pulse Width
t AVLX
Address Setup Time
t LXAX
Address Hold Time
t AVQV
Address Valid to Data Valid
t SLQV
CS Valid to Data Valid
Conditions
Min
-12
Max
Min
-15
Max
Min
Max
Turbo
Off
Unit
20
22
28
ns
(Note 3)
6
8
10
ns
(Note 3)
8
9
11
ns
(Notes 3 and 6)
90
120
150
Add 10
ns
100
135
150
ns
RD to Data Valid 8-Bit Bus
(Note 5)
32
35
40
ns
RD or PSEN to Data Valid
8-Bit Bus, 8031, 80251
(Note 2)
38
42
45
ns
t RHQX
RD Data Hold Time
(Note 1)
0
0
0
ns
t RLRH
RD Pulse Width
(Note 1)
32
35
38
ns
t RHQZ
RD to Data High-Z
(Note 1)
t EHEL
E Pulse Width
32
36
38
ns
t THEH
R/W Setup Time to Enable
10
13
18
ns
t ELTL
R/W Hold Time After Enable
0
0
0
ns
t AVPV
Address Input Valid to
Address Output Delay
t RLQV
NOTES: 1.
2.
3.
4.
5.
6.
86
(Note 4)
25
25
29
33
28
RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
RD and PSEN have the same timing.
Any input used to select an internal PSD813F function.
In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
RD timing has the same timing as DS, LDS, and UDS signals.
In Turbo Off mode, add 10ns to t AVQV.
32
ns
ns
Preliminary
PSD813F1-A
Microcontroller Interface – PSD813F1 AC/DC Parameters
(5V ± 10% Versions)
Write, Erase and Program Timing (5 V ± 10% Versions)
-90
Symbol
Parameter
t LVLX
ALE or AS Pulse Width
t AVLX
Address Setup Time
t LXAX
Conditions
Min
-12
Max
Min
-15
Max
Min
Max
Unit
20
22
28
(Note 1)
6
8
10
ns
Address Hold Time
(Note 1)
8
9
11
ns
t AVWL
Address Valid to Leading
Edge of WR
(Notes 1 and 3)
15
18
20
ns
t SLWL
CS Valid to Leading Edge of WR
(Note 3)
15
18
20
ns
t DVWH
WR Data Setup Time
(Note 3)
35
40
45
ns
t WHDX
WR Data Hold Time
(Note 3)
5
5
5
ns
t WLWH
WR Pulse Width
(Note 3)
35
40
45
ns
(Note 3)
8
9
10
ns
0
0
0
ns
t WHAX1 Trailing Edge of WR to Address
Invalid
t WHAX2
Trailing Edge of WR to DPLD
Address Input Invalid
(Notes 3 and 6)
t WHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
30
35
38
ns
t WLMV
WR Valid to Port Output Valid Using
Micro⇔Cell Register Preset/Clear
(Notes 3 and 4)
55
60
65
ns
t DVMV
Data Valid to Port Output Valid
Using Micro⇔Cell Register
Preset/Clear
(Notes 3 and 5)
55
60
65
ns
t AVPV
Address Input Valid to Address
Output Delay
(Note 2)
25
28
30
ns
NOTES: 1.
2.
3.
4.
5.
6.
Any input used to select an internal PSD813F function.
In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
Assuming data is stable before active write signal.
Assuming write is active before data becomes valid.
Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.
87
PSD813F1-A
Preliminary
Microcontroller Interface – PSD813F1 AC/DC Parameters
(5V ± 10% Versions)
Port A Peripheral Data Mode Read Timing (5 V ± 10%)
-90
Symbol
Parameter
t AVQV (PA)
Address Valid to Data
Valid
t SLQV (PA)
CSI Valid to Data Valid
Conditions
Min
Max
Min
-15
Max
Min
Max
Turbo
Off
Unit
40
45
45
Add 10
ns
35
40
45
Add 10
ns
32
35
40
ns
RD to Data Valid 8031
Mode
38
42
45
ns
t DVQV (PA)
Data In to Data Out Valid
30
35
38
ns
t QXRH (PA)
RD Data Hold Time
t RLRH (PA)
RD Pulse Width
(Note 1)
t RHQZ (PA)
RD to Data High-Z
(Note 1)
RD to Data Valid
t RLQV (PA)
(Note 3)
-12
(Notes 1 and 4)
0
0
0
ns
32
35
38
ns
25
28
30
ns
Port A Peripheral Data Mode Write Timing (5 V ± 10%)
-90
Symbol
Parameter
Conditions
Min
-12
Max
Min
-15
Max
Min
Max
Unit
t WLQV (PA)
WR to Data Propagation Delay
(Note 2)
35
38
40
ns
t DVQV (PA)
Data to Port A Data Propagation
Delay
(Note 5)
30
35
38
ns
t WHQZ (PA)
WR Invalid to Port A Tri-state
(Note 2)
25
30
33
ns
NOTES: 1.
2.
3.
4.
5.
88
RD timing has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode) signals.
WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
Any input used to select Port A Data Peripheral Mode.
Data is already stable on Port A.
Data stable on ADIO pins to data on Port A.
Preliminary
PSD813F1-A
Microcontroller Interface – PSD813F1 AC/DC Parameters
(5V ± 10% Versions)
Power Down Timing (5 V ± 10%)
-90
Symbol
Parameter
t LVDV
ALE Access Time from
Power Down
t CLWH
Maximum Delay from
APD Enable to Internal
PDN Valid Signal
Conditions
Min
-12
Max
Min
90
Using CLKIN Input
-15
Max
Min
120
Max
Unit
150
ns
15 * t CLCL (Note 1)
µs
NOTE: 1. t CLCL is the CLKIN clock period.
Vstbyon Timing (5 V ± 10%)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t BVBH
Vstby Detection to Vstbyon Output High
20
µs
t BXBL
Vstby Off Detection to Vstbyon
Output Low
20
µs
Reset Timing (5 V ± 10%)
Symbol
Parameter
t NLNH
Warm RESET Active Low Time (Note 1)
t OPR
RESET High to Operational Device
t NLNH-PO
Power On Reset Active Low Time
(Note 2)
Conditions
Min
Typ
Max
150
ns
120
1
Unit
ns
ms
NOTE: 1. RESET will not reset Flash or EEPROM programming/erase cycles.
2. tNLNH-PO is 10 ms for devices manufactured before rev. A.
89
PSD813F1-A
Preliminary
Microcontroller Interface – PSD813F1 AC/DC Parameters
(5V ± 10% Versions)
Flash Program, Write and Erase Times (5 V ± 10%)
Symbol
Parameter
Min
Typ
Flash Program
3
Flash Bulk Erase (Not Preprogrammed)
10
t WHQV3
Sector Erase (Preprogrammed)
1
t WHQV2
Sector Erase (Not Preprogrammed)
2.2
t WHQV1
Byte Program
14
Program/Erase Cycles (Per Sector)
Sector Erase Time-Out
t Q7VQV
DQ7 Valid to Output (DQ7-0) Valid
(Data Polling) (Note 2)
Unit
8.5
Flash Bulk Erase (Preprogrammed) (Note 1)
t WHWLO
Max
sec
30
sec
sec
30
sec
sec
1200
100,000
µs
cycles
100
µs
30
ns
Max
Unit
NOTES: 1. Programmed to all zeros before erase.
2. The Polling Status DQ7 is valid t Q7VQV ns, before the data byte DQ0-7 is valid for reading.
EEPROM Write Times (5 V ± 10%)
Symbol
Parameter
Min
t EEHWL
Write Protect After Power Up
t BLC
EEPROM Byte Load Cycle Timing (Note 1)
t WCB
EEPROM Byte Write Cycle Time
t WCP
EEPROM Page Write Cycle Time (Note 2)
Typ
5
msec
0.2
Program/Erase Cycles (Per Sector)
120
µsec
4
10
msec
6
30
msec
10,000
cycles
NOTES: 1. If the maximum time has elapsed between successive writes to an EEPROM page, the transfer of this data to EEPROM cells will
begin. Also, bytes cannot be written (loaded) to a page any faster than the indicated minimum type.
2. These specifications are for writing a page to EEPROM cells.
ISC Timing (5 V ± 10%)
-90
Symbol
t ISCCF
t ISCCH
t ISCCL
t ISCCF-P
t ISCCH-P
t ISCCL-P
t ISCPSU
t ISCPH
t ISCPCO
t ISCPZV
t ISCPVZ
Parameter
TCK Clock Frequency (except for PLD)
TCK Clock High Time
TCK Clock Low Time
TCK Clock Frequency (for PLD only)
TCK Clock High Time (for PLD only)
TCK Clock Low Time (for PLD only)
ISC Port Set Up Time
ISC Port Hold Up Time
ISC Port Clock to Output
ISC Port High-Impedance to
Valid Output
ISC Port Valid Output to High-Impedance
Conditions Min Max
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 2)
NOTES: 1. For “non-PLD” programming, erase or in ISC by-pass mode.
2. For program or erase PLD only.
90
-12
Min
18
-15
Max
Min
Unit
14
23
24
25
MHz
ns
ns
MHz
ns
ns
ns
ns
ns
23
24
25
ns
23
24
25
ns
26
26
16
Max
29
29
2
240
240
8
5
31
31
2
240
240
10
5
2
240
240
10
5
Preliminary
PSD813F1-A
PSD813F1V DC Characteristics
Symbol
(3.0 V to 3.6 V Versions)
Parameter
Conditions
Min
Typ
Max
Unit
3.0
3.6
V
VCC
Supply Voltage
All Speeds
VIH
High Level Input Voltage
3.0 V < VCC < 3.6 V
.7 VCC
VCC +.5
V
VIL
Low Level Input Voltage
3.0 V < VCC < 3.6 V
–.5
0.8
V
VIH1
Reset High Level Input Voltage
(Note 1)
.8 VCC
VCC +.5
V
VIL1
Reset Low Level Input Voltage
(Note 1)
–.5
.2 VCC –.1
V
VHYS
Reset Pin Hysteresis
0.3
VLKO
VCC Min for Flash Erase and Program
1.5
VOL
Output Low Voltage
VOH
Output High Voltage Except VSTBY On
0.1
V
IOL = 4 mA, VCC = 3.0 V
0.15
0.45
V
IOH = –20 µA, VCC = 3.0 V
2.9
2.99
V
IOH = –1 mA, VCC = 3.0 V
2.7
2.8
V
VSBY
SRAM Standby Voltage
ISBY
SRAM Standby Current
VCC = 0 V
IIDLE
Idle Current (VSTBY Pin)
VCC > VSBY
VDF
SRAM Data Retention Voltage
Only on VSTBY
ISB
Standby Supply Current
for Power Down Mode
CSI >VCC –0.3 V (Note 2)
ILI
Input Leakage Current
VSS < VIN < VCC
ILO
Output Leakage Current
0.45 < VIN > VCC
Operating
Supply Current
FLASH or EEPROM
SRAM
V
0.01
Output High Voltage VSTBY On
ICC (DC)
(Note 3)
2.2
IOL = 20 µA, VCC = 3.0 V
VOH1
ZPLD Only
V
IOH1 = 1 µA
VSBY – 0.8
V
2.0
0.5
–0.1
VCC
V
1
µA
0.1
µA
2
V
25
100
µA
–1
±.1
1
µA
–10
±5
10
µA
ZPLD_TURBO = OFF,
f = 0 MHz (Note 3)
0
ZPLD_TURBO = ON,
f = 0 MHz
200
400
µA/PT
During FLASH or
EEPROM Write/Erase Only
10
25
mA
Read Only, f = 0 MHz
0
0
mA
f = 0 MHz
0
0
mA
mA
ZPLD AC Adder
ICC (AC)
(Note 3)
Figure 34a
FLASH or
EEPROM
AC Adder
1.5
2.0
mA/MHz
SRAM AC Adder
0.8
1.5
mA/MHz
NOTES: 1. Reset input has hysteresis. VIL1 is valid at or below .2VCC –.1. VIH1 is valid at or above .8VCC.
2. CSI deselected or internal PD is active.
3. I OUT = 0 mA
91
PSD813F1-A
Preliminary
PSD813F1V AC/DC Parameters – CPLD Timing Parameters
(3.0 V to 3.6 V Versions)
CPLD Combinatorial Timing (3.0 V to 3.6 V Versions)
-15
Symbol
Parameter
Conditions
Min
-20
Max
Min
Max
PT
Aloc
TURBO
OFF*
Slew
Rate
(Note 1)
Unit
t PD
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
48
55
Add 4 Add 20 Sub 6
ns
t EA
CPLD Input to CPLD Output
Enable
43
50
Add 20 Sub 6
ns
t ER
CPLD Input to CPLD Output
Disable
43
50
Add 20 Sub 6
ns
t ARP
CPLD Register Clear or
Preset Delay
48
55
Add 20 Sub 6
ns
t ARPW
CPLD Register Clear or
Preset Pulse Width
Add 20
ns
t ARD
CPLD Array Delay
30
35
Any Micro⇔Cell
29
33
Add 4
ns
NOTE: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
*ZPSD versions only.
CPLD Micro⇔Cell Synchronous Clock Mode Timing (3.0 V to 3.6 V Versions)
-15
Symbol
Parameter
Maximum Frequency
External Feedback
f MAX
Maximum Frequency
Internal Feedback ( fCNT )
Maximum Frequency
Pipelined Data
Conditions
Min
-20
Max
Min
Max
PT
Aloc
TURBO
OFF*
Slew
Rate
(Note 1)
Unit
1/(tS + t CO )
17.8
14.7
MHz
1/(tS + t CO –10)
19.6
17.2
MHz
1/(tC H + t CL )
33.3
31.2
MHz
tS
Input Setup Time
27
35
tH
Input Hold Time
0
0
ns
t CH
Clock High Time
Clock Input
15
16
ns
t CL
Clock Low Time
Clock Input
15
16
ns
t CO
Clock to Output Delay
Clock Input
35
39
t ARD
CPLD Array Delay
Any Micro⇔Cell
29
33
t MIN
Minimum Clock Period
tC H + t CL (Note 2)
29
NOTES: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
2. CLKIN tCLCL = tCH + tCL.
*ZPSD versions only.
92
32
Add 4 Add 20
ns
Sub 6
Add 4
ns
ns
ns
Preliminary
PSD813F1-A
PSD813F1V AC/DC Parameters – CPLD Timing Parameters
(3.0 V to 3.6 V Versions)
CPLD Micro⇔Cell Asynchronous Clock Mode Timing (3.0 V to 3.6 V Versions)
-15
Symbol
Parameter
Maximum Frequency
External Feedback
f MAXA
Maximum Frequency
Internal Feedback ( fCNTA)
Maximum Frequency
Pipelined Data
Conditions
Min
-20
Max
Min
Max
PT
Aloc
TURBO
OFF*
Slew
Rate
Unit
1/(tS A + t CO A )
19.2
16.9
MHz
1/(tS A + t CO A –10)
23.8
20.4
MHz
1/(tC H A+ t CLA)
27
24.4
MHz
t SA
Input Setup Time
12
13
t HA
Input Hold Time
15
17
t CHA
Clock High Time
22
25
Add 20
ns
t CLA
Clock Low Time
15
16
Add 20
ns
t COA
Clock to Output Delay
Add 20 Sub 6
ns
t ARD
CPLD Array Delay
t MINA
Minimum Clock Period
Any Micro⇔Cell
1/ fC NTA
Add 4 Add 20
ns
40
46
29
33
42
ns
Add 4
ns
49
ns
*ZPSD Versions Only.
Input Micro⇔Cell Timing (3.0 V to 3.6 V Versions)
-15
Symbol
Parameter
Conditions
Min
-20
Max
Min
Max
PT
Aloc
TURBO
OFF*
Unit
t IS
Input Setup Time
(Note 1)
0
0
t IH
Input Hold Time
(Note 1)
25
30
t INH
NIB Input High Time
(Note 1)
13
15
ns
t IN L
NIB Input Low Time
(Note 1)
13
15
ns
t INO
NIB Input to Combinatorial
Delay
(Note 1)
62
ns
Add 20
70
Add 4
Add 20
ns
ns
NOTE: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX.
*ZPSD Versions Only.
93
PSD813F1-A
Microcontroller
Interface –
PSD813F1V
AC/DC
Parameters
(3.0 V to 3.6 V
Versions)
Preliminary
AC Symbols for PLD Timing.
Example:
t AVLX – Time from Address Valid to ALE Invalid.
Signal Letters
A
C
D
E
G
I
L
N
P
Q
R
S
T
W
B
M
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Address Input
CEout Output
Input Data
E Input
Internal WDOG_ON signal
Interrupt Input
ALE Input
Reset Input or Output
Port Signal Output
Output Data
WR, UDS, LDS, DS, IORD, PSEN Inputs
Chip Select Input
R/W Input
Internal PDN Signal
Vstby Output
Output Micro⇔Cell
Signal Behavior
t
L
H
V
X
Z
PW
94
–
–
–
–
–
–
–
Time
Logic Level Low or ALE
Logic Level High
Valid
No Longer a Valid Logic Level
Float
Pulse Width
Preliminary
PSD813F1-A
Microcontroller Interface – PSD813F1V AC/DC Parameters
(3.0 V to 3.6 V Versions)
Read Timing (3.0 V to 3.6 V Versions)
-15
Symbol
Parameter
Conditions
Min
-20
Max
Min
Max
Turbo
Off
Unit
t LVLX
ALE or AS Pulse Width
t AVLX
Address Setup Time
t LXAX
Address Hold Time
t AVQV
Address Valid to Data Valid (Notes 3 and 6)
150
200
t SLQV
CS Valid to Data Valid
150
200
ns
t RLQV
t RHQX
t RLRH
26
30
ns
(Note 3)
10
12
ns
(Note 3)
12
14
ns
Add 20
ns
RD to Data Valid 8-Bit Bus
(Note 5)
35
40
ns
RD or PSEN to Data Valid 8-Bit Bus,
8031, 80251
(Note 2)
50
55
ns
RD Data Hold Time
(Note 1)
0
0
ns
RD Pulse Width (also DS, LDS, UDS)
40
45
ns
RD or PSEN Pulse Width (8031, 80251)
55
60
ns
t RHQZ
RD to Data High-Z
t EHEL
E Pulse Width
45
52
ns
t THEH
R/W Setup Time to Enable
18
20
ns
t ELTL
R/W Hold Time After Enable
0
0
ns
t AVPV
Address Input Valid to
Address Output Delay
NOTES: 1.
2.
3.
4.
5.
6.
(Note 1)
(Note 4)
40
45
35
40
ns
ns
RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
RD and PSEN have the same timing for 8031.
Any input used to select an internal PSD813F function.
In multiplexed mode latched address generated from ADIO delay to address output on any Port.
RD timing has the same timing as DS, LDS, and UDS signals.
In Turbo Off mode, add 20ns to t AVQV.
95
PSD813F1-A
Preliminary
Microcontroller Interface – PSD813F1V AC/DC Parameters
(3.0 V to 3.6 V Versions)
Write, Erase and Program Timing (3.0 V to 3.6 V Versions)
-15
Symbol
Parameter
t LVLX
ALE or AS Pulse Width
t AVLX
Address Setup Time
t LXAX
Conditions
Min
-20
Max
Min
Max
Unit
26
30
(Note 1)
10
12
ns
Address Hold Time
(Note 1)
12
14
ns
t AVWL
Address Valid to Leading
Edge of WR
(Notes 1 and 3)
20
25
ns
t SLWL
CS Valid to Leading Edge of WR
(Note 3)
20
25
ns
t DVWH
WR Data Setup Time
(Note 3)
45
50
ns
t WHDX
WR Data Hold Time
(Note 3)
8
10
ns
t WLWH
WR Pulse Width
(Note 3)
48
53
ns
t WHAX1
Trailing Edge of WR to Address Invalid
(Note 3)
12
17
ns
t WHAX2
Trailing Edge of WR to DPLD Address
Input Invalid
(Notes 3 and 6)
0
0
ns
t WHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
45
50
ns
t WLMV
WR Valid to Port Output Valid Using
Micro⇔Cell Register Preset/Clear
(Notes 3 and 4)
90
100
ns
t DVMV
Data Valid to Port Output Valid
Using Micro⇔Cell Register Preset/Clear
(Notes 3 and 5)
90
100
ns
t AVPV
Address Input Valid to Address
Output Delay
(Note 2)
48
55
ns
NOTES: 1.
2.
3.
4.
5.
6.
96
Any input used to select an internal PSD813F function.
In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
Assuming data is stable before active write signal.
Assuming write is active before data becomes valid.
Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.
Preliminary
PSD813F1-A
Microcontroller Interface – PSD813F1V AC/DC Parameters
(3.0 V to 3.6 V Versions)
Port A Peripheral Data Mode Read Timing (3.0 V to 3.6 V Versions)
-15
-20
Max
Turbo
Off
Unit
55
60
Add 20
ns
45
50
Add 20
ns
40
45
ns
RD to Data Valid 8031 Mode
45
50
ns
t DVQV (PA)
Data In to Data Out Valid
60
65
ns
t QXRH (PA)
RD Data Hold Time
t RLRH (PA)
RD Pulse Width
(Note 1)
t RHQZ (PA)
RD to Data High-Z
(Note 1)
Symbol
Parameter
t AVQV (PA)
Address Valid to Data Valid
t SLQV (PA)
CSI Valid to Data Valid
t RLQV (PA)
RD to Data Valid
Conditions
Min
(Note 3)
(Notes 1 and 4)
Max
Min
0
0
ns
36
46
ns
40
45
ns
Port A Peripheral Data Mode Write Timing (3.0 V to 3.6 V Versions)
-15
Symbol
Parameter
Conditions
Min
-20
Max
Min
Max
Unit
t WLQV (PA)
WR to Data Propagation Delay
(Note 2)
45
55
ns
t DVQV (PA)
Data to Port A Data Propagation
Delay
(Note 5)
40
45
ns
t WHQZ (PA)
WR Invalid to Port A Tri-state
(Note 2)
33
35
ns
NOTES: 1.
2.
3.
4.
5.
RD timing has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode) signals.
WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
Any input used to select Port A Data Peripheral Mode.
Data is already stable on Port A.
Data stable on ADIO pins to data on Port A.
97
PSD813F1-A
Preliminary
Microcontroller Interface – PSD813F1V AC/DC Parameters
(3.0 V to 3.6 V Versions)
Power Down Timing (3.0 V to 3.6 V Versions)
-15
Symbol
Parameter
t LVDV
ALE Access Time from
Power Down
t CLWH
Maximum Delay from APD Enable
to Internal PDN Valid Signal
Conditions
Min
-20
Max
Min
Max
Unit
200
ns
150
Using CLKIN Input
15 * t CLCL (Note 1)
µs
NOTE: 1. tCLCL is the CLKIN clock period.
Vstbyon Timing (3.0 V to 3.6 V Versions)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t BVBH
Vstby Detection to Vstbyon Output
High
2.0
µs
t BXBL
Vstby Off Detection to Vstbyon
Output Low
2.0
µs
Reset Timing (3.0 V to 3.6 V Versions)
Symbol
Parameter
t NLNH
Warm RESET Active Low Time (Note 1)
t OPR
RESET High to Operational Device
t NLNH-PO
Power On Reset Active Low Time
(Note 2)
Conditions
NOTE: 1. RESET will not reset Flash or EEPROM programming/erase cycles.
2. tNLNH-PO is 10 ms for devices manufactured before the rev. A.
98
Min
Typ
Max
300
ns
300
1
Unit
ns
ms
Preliminary
PSD813F1-A
Microcontroller Interface – PSD813F1V AC/DC Parameters
(3.0 V to 3.6 V Versions)
Flash Program, Write and Erase Times (3.0 V to 3.6 V Versions)
Symbol
Parameter
Min
Typ
Flash Program
3
Flash Bulk Erase (Not Preprogrammed)
10
t WHQV3
Sector Erase (Preprogrammed)
1
t WHQV2
Sector Erase (Not Preprogrammed)
2.2
t WHQV1
Byte Program
14
Program/Erase Cycles (Per Sector)
Sector Erase Time-Out
t Q7VQV
DQ7 Valid to Output (DQ7-0) Valid
(Data Polling) (Note 2)
Unit
8.5
Flash Bulk Erase (Preprogrammed) (Note 1)
t WHWLO
Max
sec
30
sec
sec
30
sec
sec
1200
100,000
µs
cycles
100
µs
30
ns
Max
Unit
NOTES: 1. Programmed to all zeros before erase.
2. The Polling Status DQ7 is valid t Q7VQV ns before the data byte DQ0-7 is valid for reading.
EEPROM Write Times (3.0 V to 3.6 V Versions)
Symbol
Parameter
t EEHWL
Write Protect After Power Up
t BLC
EEPROM Byte Load Cycle Timing (Note 1)
t WCB
EEPROM Byte Write Cycle Time
t WCP
EEPROM Page Write Cycle Time (Note 2)
Min
Typ
5
msec
0.2
Program/Erase Cycles (Per Sector)
120
µsec
4
10
msec
6
30
msec
10,000
cycles
NOTES: 1. If the maximum time has elapsed between successive writes to an EEPROM page, the transfer of this data to EEPROM cells will
begin. Also, bytes cannot be written (loaded) to a page any faster than the indicated minimum type.
2. These specifications are for writing a page to EEPROM cells.
ISC Timing (3.0 V to 3.6 V Versions)
-15
Symbol
Parameter
Conditions
Min
-20
Max
Min
10
Max
Unit
9
MHz
t ISCCF
TCK Clock Frequency (except for PLD)
(Note 1)
t ISCCH
TCK Clock High Time
(Note 1)
45
51
ns
t ISCCL
TCK Clock Low Time
(Note 1)
45
51
ns
t ISCCF-P
TCK Clock Frequency (for PLD only)
(Note 2)
t ISCCH-P
TCK Clock High Time (for PLD only)
(Note 2)
240
240
ns
t ISCCL-P
TCK Clock Low Time (for PLD only)
(Note 2)
240
240
ns
t ISCPSU
ISC Port Set Up Time
13
15
ns
t ISCPH
ISC Port Hold Up Time
10
10
ns
t ISCPCO
ISC Port Clock to Output
36
40
ns
t ISCPZV
ISC Port High-Impedance to Valid Output
36
40
ns
t ISCPVZ
ISC Port Valid Output to High-Impedance
36
40
ns
2
2
MHz
NOTES: 1. For “non-PLD” programming, erase or in ISC by-pass mode.
2. For program or erase PLD only.
99
PSD813F1-A
Preliminary
Figure 34. Read Timing
tAVLX
tLXAX *
ALE/AS
tLVLX
A/D
MULTIPLEXED
BUS
ADDRESS
VALID
DATA
VALID
tAVQV
ADDRESS
NON-MULTIPLEXED
BUS
ADDRESS
VALID
DATA
NON-MULTIPLEXED
BUS
DATA
VALID
tSLQV
CSI
tRLQV
tRHQX
tRLRH
RD
(PSEN, DS)
tRHQZ
tEHEL
E
tTHEH
R/W
tAVPV
ADDRESS OUT
*tAVLX and tLXAX are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.
100
tELTL
Preliminary
PSD813F1-A
Figure 35. Write Timing
tAVLX
t LXAX
ALE/AS
t LVLX
A/D
MULTIPLEXED
BUS
DATA
VALID
ADDRESS
VALID
tAVWL
ADDRESS
NON-MULTIPLEXED
BUS
ADDRESS
VALID
DATA
NON-MULTIPLEXED
BUS
DATA
VALID
tSLWL
CSI
tDVWH
t WLWH
WR
(DS)
t WHDX
t WHAX
t EHEL
E
t THEH
t ELTL
R/ W
t WLMV
tAVPV
t WHPV
ADDRESS OUT
STANDARD
MCU I/O OUT
101
PSD813F1-A
Preliminary
Figure 36. Peripheral I/O Read Timing
ALE/AS
A/D BUS
ADDRESS
DATA VALID
tAVQV (PA)
tSLQV (PA)
CSI
tRLQV (PA)
tQXRH (PA)
tRHQZ (PA)
tRLRH (PA)
RD
tDVQV (PA)
DATA ON PORT A
Figure 37. Peripheral I/O Write Timing
ALE/AS
A / D BUS
ADDRESS
DATA OUT
tWLQV
tWHQZ (PA)
(PA)
WR
tDVQV (PA)
PORT A
DATA OUT
102
Preliminary
PSD813F1-A
Figure 38. Combinatorial Timing – PLD
CPLD INPUT
t PD
CPLD
OUTPUT
Figure 39. Synchronous Clock Mode Timing – PLD
tCH
tCL
CLKIN
tS
tH
INPUT
tCO
REGISTERED
OUTPUT
103
PSD813F1-A
Preliminary
Figure 40. Asynchronous Clock Mode Timing (Product-Term Clock)
tCHA
tCLA
CLOCK
tSA
tHA
INPUT
tCOA
REGISTERED
OUTPUT
Figure 41. Input Micro⇔Cell Timing (Product-Term Clock)
t INH
t INL
PT CLOCK
t IS
t IH
INPUT
OUTPUT
t INO
104
Preliminary
PSD813F1-A
Figure 42. Input to Output Disable/Enable
INPUT
tER
tEA
INPUT TO
OUTPUT
ENABLE/DISABLE
Figure 43. Asynchronous Reset/Preset
tARPW
RESET/PRESET
INPUT
tARP
REGISTER
OUTPUT
Figure 44. ISC Timing
t ISCCH
TCK
t ISCCL
t ISCPSU
t ISCPH
TDI/TMS
t ISCPZV
t ISCPCO
ISC OUTPUTS/TDO
t ISCPVZ
ISC OUTPUTS/TDO
105
PSD813F1-A
Preliminary
Figure 45. Reset Timing
OPERATING LEVEL
t NLNH
t NLNH–PO
VCC
RESET
t OPR
WARM
RESET
POWER ON RESET
Figure 46. Key to Switching Waveforms
WAVEFORMS
106
INPUTS
OUTPUTS
STEADY INPUT
STEADY OUTPUT
MAY CHANGE FROM
HI TO LO
WILL BE CHANGING
FROM HI TO LO
MAY CHANGE FROM
LO TO HI
WILL BE CHANGING
LO TO HI
DON'T CARE
CHANGING, STATE
UNKNOWN
OUTPUTS ONLY
CENTER LINE IS
TRI-STATE
t OPR
Preliminary
Pin Capacitance
PSD813F1-A
TA = 25 °C, f = 1 MHz
Symbol
Parameter 1
Conditions Typical 2 Max Unit
CIN
Capacitance (for input pins only)
VIN = 0 V
4
6
pF
COUT
Capacitance (for input/output pins)
VOUT = 0 V
8
12
pF
CVPP
Capacitance (for CNTL2/VPP)
VPP = 0 V
18
25
pF
NOTES: 1. These parameters are only sampled and are not 100% tested.
2. Typical values are for TA = 25°C and nominal supply voltages.
Figure 47.
AC Testing
Input/Output
Waveform
3.0V
TEST POINT
1.5V
0V
Figure 48.
AC Testing
Load Circuit
2.01 V
195 Ω
DEVICE
UNDER TEST
Programming
CL = 30 pF
(INCLUDING
SCOPE AND JIG
CAPACITANCE)
Upon delivery from ST, the PSD813F device has all bits in the PLDs and memories in the
“1” or high state. The configuration bits are in the “0” or low state. The code, configuration,
and PLDs logic are loaded through the procedure of programming.
Information for programming the device is available directly from ST. Please contact your
local sales representative. (See the last page.)
107
PSD813F1-A
PSD813F1-A
Pin
Assignments
108
Preliminary
52-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J)
Pin No.
Pin Assignments
Pin No.
Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
GND
PB5
PB4
PB3
PB2
PB1
PB0
PD2
PD1
PD0
PC7
PC6
PC5
PC4
VCC
GND
PC3
PC2 (VSTBY)
PC1
PC0
PA7
PA6
PA5
PA4
PA3
GND
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
PA2
PA1
PA0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
VCC
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
CNTL0
RESET
CNTL2
CNTL1
PB7
PB6
Preliminary
PSD813F1-A
Pin
Assignments
(cont.)
PSD813F1-A
52-Pin Plastic Quad Flatpack (PQFP) (Package Type M)
Pin No.
Pin Assignments
Pin No.
Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
PD2
PD1
PD0
PC7
PC6
PC5
PC4
VCC
GND
PC3
PC2
PC1
PC0
PA7
PA6
PA5
PA4
PA3
GND
PA2
PA1
PA0
AD0
AD1
AD2
AD3
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
AD4
AD5
AD6
AD7
VCC
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
CNTL0
RESET
CNTL2
CNTL1
PB7
PB6
GND
PB5
PB4
PB3
PB2
PB1
PB0
109
PSD813F1-A
RESET
2
CNTL0
3
CNTL2
PB5
4
CNTL1
PB4
5
PB7
PB3
6
PB6
PB2
7
GND
PB1
Figure 49. Drawing J7 – 52-Pin Plastic Leaded Chip Carrier (PLDCC)
(Package Type J)
PB0
PSD813F1-A
Package
Information
Preliminary
52 51 50 49 48 47
1
PD2
8
46
AD15
PD1
9
45
AD14
PD0
10
44
AD13
PC7
11
43
AD12
PC6
12
42
AD11
PC5
13
41
AD10
PC4
VCC
14
40
AD9
15
39
AD8
GND
16
38
VCC
PC3
17
37
AD7
PC2 (VSTBY)
18
36
AD6
PC1
19
35
AD5
PC0
20
34
AD4
AD3
AD2
AD1
AD0
PA0
PA1
PA2
GND
PA3
PA4
PA5
PA6
PA7
21 22 23 24 25 26 27 28 29 30 31 32 33
CNTL0
RESET
CNTL2
CNTL1
PB7
PB6
GND
PB5
PB4
PB3
PB2
PB0
PB1
Figure 50. Drawing M3 – 52-Pin Plastic Quad Flatpack (PQFP)
(Package Type M)
52 51 50 49 48 47 46 45 44 43 42 41 40
PD2
1
39
PD1
2
38
AD14
PD0
3
37
AD13
PC7
4
36
AD12
PC6
5
35
AD11
PC5
6
34
AD10
PC4
7
33
AD9
VCC
8
32
AD8
GND
9
31
VCC
PC3
10
30
AD7
PC2
11
29
AD6
PC1
12
28
AD5
PC0
13
27
AD4
AD3
AD2
AD1
AD0
PA0
PA1
PA2
PA3
GND
PA4
PA5
PA7
PA6
14 15 16 17 18 19 20 21 22 23 24 25 26
110
AD15
Preliminary
PSD813F1-A
Figure 49A.
Drawing J7 – 52-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J)
D
D1
3 2 1 52 51
E1
E
.025
.045 R
View A
C
B1
A2
e1
B
D3
D2
A1
View A
E3
E2
A
Family: Plastic Leaded Chip Carrier
Millimeters
Symbol
Min
Max
A
4.19
A1
Inches
Min
Max
4.57
0.165
0.180
2.54
2.79
0.100
0.110
A2
B
3.66
0.33
3.86
0.53
0.144
0.013
0.152
0.021
B1
0.66
0.81
0.026
0.032
C
0.246
0.261
0.0097
0.0103
D
19.94
20.19
0.785
0.795
D1
19.05
19.15
0.750
0.754
D2
17.53
18.54
0.690
0.730
D3
15.24
Notes
Reference
0.600
Notes
Reference
E
19.94
20.19
0.785
0.795
E1
19.05
19.15
0.750
0.754
E2
17.53
18.54
0.690
0.730
E3
15.24
Reference
0.600
Reference
e1
1.27
Reference
0.050
Reference
N
52
52
020197R1
111
PSD813F1-A
Preliminary
Figure 50A.
Drawing M3 – 52-Pin Plastic Quad Flatpack (PQFP) (Package Type M)
D
D1
D3
52
1
2
3
Index
Mark
E3
E1
E
Standoff: 0.05 mm Min.
C
A2
A
α
L
B
e1
Lead Coplanarity: 0.1mm Max.
Family: Plastic Quad Flatpack (PQFP)
Millimeters
Symbol
Min
Max
α
0°
A
Inches
Min
Max
7°
0°
7°
–
2.35
–
0.093
A2
1.95
2.10
0.077
0.083
B
0.22
0.38
0.009
0.015
C
Notes
Reference
0.23
0.009
D
12.95
13.45
0.510
0.530
D1
9.90
10.10
0.390
0.398
D3
7.80
Notes
Reference
0.307
Reference
E
12.95
13.45
0.510
0.530
E1
9.90
10.10
0.390
0.398
E3
7.80
Reference
0.307
Reference
e1
0.65
Reference
0.026
Reference
L
N
0.73
1.03
52
0.029
0.041
52
060198R0
112
Preliminary
Selector Guide
Selector Guide – PSD813F1-A
Part #
PSD
@
5V
MCU
PSD
@
3V
PLDs/Decoders
I/O
Memory
Other
Data Path
PLD Inputs
Interface
Input Micro⇔Cells
Output
Micro⇔Cells
Ports Flash Program Store
JTAG
OTP EPROM Boot
Parallel ISP
EEPROM/EEPROM Boot
ISP Flash
2nd Flash Boot
ISP CPLD
PLD Outputs
SRAM
Periph. Mode
(w/BB)
Page
Security
Reg.
PMU
APD
PSD813F1
PSD813F1V
8
PLUS1
73 24 16
19
8-Bit 27
1024Kb
PSD813F2
PSD813F2V
8
PLUS1
73 24 16
19
8-Bit 27
PSD813F3
PSD813F3V
8
PLUS1
73 24 16
19
8-Bit 27
PSD813F4
PSD813F4V
8
PLUS1
73 24 16
19
8-Bit 27
1024Kb
PSD813F5
PSD813F5V
8
PLUS1
73 24 16
19
8-Bit 27
1024Kb
256Kb
16Kb
X
X
X
X
X
X X
X
1024Kb
256Kb 16Kb
X
X
X
X
X
X X
X
1024Kb
16Kb
X
X
X
X
X
X X
X
X
X
X
X
X
X X
X
X
X
X
X
X
X X
X
256Kb
Legend:
ZPSD
ZPSDV
STD
STD-M
PLUS
w/BB
APD
=
=
=
=
=
=
=
Zero Power version available at 4.5 V to 5.5 V VCC (Example: ZPSD311-15J).
Zero Power version available at 2.7 V to 5.5 V VCC (Example: ZPSD311V-25J). 2.7 V to 3.6 V VCC on PSD8XXF family.
Standard MCU interfaces supported (Multiplexed and Non-Multiplexed).
Standard MCU interfaces supported (Multiplexed only).
New Intel 80C251 and Philips 80C51XA supported plus all standard MCUs.
Battery backed-up SRAM.
Automatic Power Down.
PSD813F1-A
113
PSD813F1-A
Part Number
Construction
Preliminary
PSD 413A2 V
-A -20 J
I
Temperature (Blank = Commercial,
I = Industrial, M = Military)
Package Type
Speed (-70 = 70ns, -90 = 90ns, -15 = 150ns
-20 = 200ns, -25 = 250ns)
Revision (Blank = No Revision)
Supply Voltage (Blank = 5V, V = 3 Volt)
Base Part Number - see Selector Guide
PSD (ST Programmable System Device) Fam.
Ordering
Information
114
Part Number
Speed
(ns)
Package Type
Operating
Temperature
Range
PSD813F1-A-90J
PSD813F1-A-90JI
PSD813F1-A-90M
PSD813F1-A-90MI
90
90
90
90
52 Pin PLDCC
52 Pin PLDCC
52 Pin PQFP
52 Pin PQFP
Comm’l
Industrial
Comm’l
Industrial
PSD813F1-A-12JI
PSD813F1-A-12MI
120
120
52 Pin PLDCC
52 Pin PQFP
Industrial
Industrial
PSD813F1-A-V-15J
PSD813F1-A-V-15M
150
150
52 Pin PLDCC
52 Pin PQFP
Comm’l
Comm’l
PSD813F1-A-V-20JI
PSD813F1-A-V-20MI
200
200
52 Pin PLDCC
52 Pin PQFP
Industrial
Industrial
PSD813F1-A
REVISION HISTORY
Table 1. Document Revision History
Date
Rev.
Aug-2000
1.0
Document written in the WSI format
04-Jan-2002
1.1
Front page, and back two pages, in ST format, added to the PDF file
References to Waferscale, WSI, EasyFLASH and PSDsoft 2000
updated to ST, ST, Flash+PSD and PSDsoft Express
2/3
Description of Revision
PSD813F1-A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2002 STMicroelectronics - All Rights Reserved
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