STMICROELECTRONICS PSD835G2V-90UI

PSD835G2V
Flash PSD, 3 V supply, for 8-bit MCUs
4 Mbit + 256 Kbit dual Flash memories and 64 Kbit SRAM
Features
■
Flash in-system programmable (ISP)
peripheral for 8-bit MCUs
■
Dual bank Flash memories
– 4 Mbits of Primary Flash memory (8
uniform sectors, 64 Kbyte)
– 256 Kbits of secondary Flash memory with
4 sectors
– Concurrent operation: READ from one
memory while erasing and writing the other
TQFP80 (U)
■
Page register
– Internal page register that can be used to
expand the microcontroller address space
by a factor of 256
■
64 Kbit of battery-backed SRAM
■
52 reconfigurable I/O ports
■
Enhanced JTAG serial port
■
Programmable power management
■
PLD with macrocells
– Over 3000 gates of PLD: CPLD and DPLD
– CPLD with 16 output macrocells (OMCs)
and 24 input macrocells (IMCs)
– DPLD - user defined internal chip select
decoding
■
High endurance:
– 100 000 Erase/WRITE cycles of Flash
memory
– 1,000 Erase/WRITE cycles of PLD
– 15 year data retention
■
3 V to 3.6 V single supply voltage
52 individually configurable I/O port pins
They can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os.
– I/O ports may be configured as open-drain
outputs.
■
Standby current as low as 25 µA
■
Memory speed
– 90 ns Flash memory and SRAM access
time for VCC = 3.0 V to 3.6 V
– 120 ns Flash memory and SRAM access
time for VCC = 3.0 V to 3.6 V
■
ECOPACK® packages
■
■
In-system programming (ISP) with JTAG
– Built-in JTAG compliant serial port allows
full-chip In-System Programmability
– Efficient manufacturing allow easy product
testing and programming
– Use low cost FlashLINK cable with PC
April 2007
Rev 2
1/118
www.st.com
1
Contents
PSD835G2V
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1
1.2
1.3
2
In-system programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.1
First time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.2
Inventory build-up of pre-programmed devices . . . . . . . . . . . . . . . . . . . 11
1.1.3
Expensive sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.1
Simultaneous read and write to Flash memory . . . . . . . . . . . . . . . . . . . 12
1.2.2
Complex memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.3
Separate Program and Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PSDsoft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PSD architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2
Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5
MCU Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6
JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.7
In-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.8
In-application re-programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.9
Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3
Development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4
PSD register description and address offset . . . . . . . . . . . . . . . . . . . . 23
5
Register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6
Detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/118
6.1
Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2
Primary Flash memory and Secondary Flash memory description . . . . . 30
6.3
Memory Block Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4
Upper and Lower Block IN MAIN FLASH SECTOR . . . . . . . . . . . . . . . . . 30
PSD835G2V
7
8
Contents
6.5
Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.6
Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1
Power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.3
Read Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.4
Read Primary Flash Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.5
Read Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.6
Read the Erase/Program Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.7
Data polling flag (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.8
Toggle flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.9
Error flag (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.10
Erase time-out flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.1
Data polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.2
Data toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.2.1
9
10
Unlock bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1
Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.2
Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.3
Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.4
Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.1
Flash memory sector protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.2
Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.3
Reset (RESET) signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
11
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12
Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.1
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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PSD835G2V
12.2
Memory select configuration for MCUs with separate
program and data spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.3
Configuration modes for MCUs with separate program and data spaces 46
12.3.1
Separate space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
12.3.2
Combined Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13
Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
14
Memory ID registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
15
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
15.1
The Turbo Bit in PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
15.2
Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
15.3
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
15.4
Output macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
15.5
Product term allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
15.5.1
16
17
4/118
Loading and reading the output macrocells (OMC) . . . . . . . . . . . . . . . . 56
15.6
The OMC mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
15.7
The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
15.8
Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
15.9
External chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
16.1
PSD interface to a multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . . . . . 62
16.2
PSD interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . 63
16.3
MCU bus interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
16.4
80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
16.5
80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
16.6
80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
16.7
68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
17.1
General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
17.2
Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
17.3
MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
PSD835G2V
Contents
17.4
PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
17.5
Address out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
17.6
Address In mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
17.7
Data Port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
17.8
Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
17.9
JTAG in-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
17.10 Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
17.11 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
17.12 Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
17.13 Drive Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
17.14 Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
17.15 Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
17.16 Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
17.17 Output macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
17.18 OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
17.19 Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
17.20 Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
17.21 Ports A,B and C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . 80
17.22 Port D – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
17.23 Port E – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
17.24 Port F – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
17.25 Port G – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
18
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
18.1
Automatic Power-down (APD) unit and Power-down mode . . . . . . . . . . . 85
18.1.1
18.2
Other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
18.3
PLD power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
18.3.1
19
Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SRAM Standby mode (battery backup) . . . . . . . . . . . . . . . . . . . . . . . . . 87
18.4
PSD Chip Select input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
18.5
Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
18.6
Input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Reset timing and device status at reset . . . . . . . . . . . . . . . . . . . . . . . . 89
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Contents
20
PSD835G2V
19.1
Power-up reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
19.2
Warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
19.3
I/O pin, Register and PLD status at reset . . . . . . . . . . . . . . . . . . . . . . . . . 89
19.4
Reset of Flash memory Erase and Program cycles . . . . . . . . . . . . . . . . . 89
Programming in-circuit using the JTAG/ISP interface . . . . . . . . . . . . . 91
20.1
Standard JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
20.2
JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
20.3
Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
21
AC/DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
22
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
23
AC and DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
24
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
25
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Appendix A Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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PSD835G2V
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Pin description (for the TQFP80 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PLD I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
JTAG signals on Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Methods of programming different functional blocks of the PSD . . . . . . . . . . . . . . . . . . . . 21
Register address offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Data-In Registers – Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Data-Out Registers – Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Direction Registers – Ports A, B, C, D, E, F, G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Control Registers – Ports E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Drive Registers – Ports A, B, D, E, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Drive Registers – Ports C, F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Enable-Out Registers – Ports A, B, C, F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Input Macrocells – Ports A, B, C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Output Macrocells A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Output Macrocells B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mask Macrocells A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mask Macrocells B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flash Memory Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flash Boot Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
JTAG Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PMMR0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PMMR2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Memory_ID0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Memory_ID1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Memory block size and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DPLD and CPLD Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Output macrocell port and data bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
MCUs and their control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
80C251 configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Interfacing the PSD with the 80C251, with one read input . . . . . . . . . . . . . . . . . . . . . . . . . 67
Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Port operating mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I/O port latched address output assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Port pin direction control, Output Enable P.T. not defined . . . . . . . . . . . . . . . . . . . . . . . . . 78
Port pin direction control, Output Enable P.T. defined . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Port direction assignment example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Drive Register pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Power-down mode’s effect on ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
PSD timing and Standby current during Power-down mode. . . . . . . . . . . . . . . . . . . . . . . . 86
APD counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Status during power-up reset, warm reset and power-down mode . . . . . . . . . . . . . . . . . . 90
JTAG port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7/118
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
8/118
PSD835G2V
Example of PSD typical power calculation at VCC = 3.0 V (with Turbo mode on) . . . . . . . 94
Example of PSD typical power calculation at VCC = 3.0 V (with Turbo mode Off) . . . . . . . 95
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
AC signal letters for PLD timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
AC signal behavior symbols for PLD timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
CPLD combinatorial timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
CPLD Macrocell Synchronous clock mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
CPLD Macrocell Asynchronous clock mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Input macrocell timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Read timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Port F peripheral data mode read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Port F peripheral data mode write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Program, Write and Erase times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Power-down timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Reset (RESET) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
VSTBYON timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
TQFP80 - 80 lead Plastic Quad Flatpack, package mechanical data. . . . . . . . . . . . . . . . 114
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
PSD835G2V TQFP80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
PSD835G2V
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
TQFP80 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PSD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PSDsoft development tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Example for Flash Sector Chip Select FS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Selecting the upper or lower block in a Primary Flash memory sector . . . . . . . . . . . . . . . . 31
Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Priority level of memory and I/O components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8031 memory modules – separate space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8031 memory modules – combined space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
PLD diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DPLD logic array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Macrocell and I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
CPLD output macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Input macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Handshaking communication using input macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
An example of a typical 8-bit multiplexed bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
An example of a typical 8-bit non-multiplexed bus interface. . . . . . . . . . . . . . . . . . . . . . . . 64
Interfacing the PSD with an 80C31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Interfacing the PSD with the 80C251, with RD and PSEN Inputs . . . . . . . . . . . . . . . . . . . 68
Interfacing the PSD with the 80C51X, 8-bit data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Interfacing the PSD with a 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
General I/O port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Port A, B and C structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Port D structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Port E, F, G structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
APD unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Enable power-down flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Power-up and warm reset (RESET) timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
PLD ICC /frequency consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Switching waveforms – key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Input to Output Disable / Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Combinatorial Timing – PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Synchronous Clock mode timing – PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Asynchronous Reset / Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Asynchronous Clock mode timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Input macrocell timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Read timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Peripheral I/O Read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Peripheral I/O Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
9/118
List of figures
Figure 49.
10/118
PSD835G2V
TQFP80 - 80 lead Plastic Quad Flatpack, package outline . . . . . . . . . . . . . . . . . . . . . . . 113
PSD835G2V
1
Description
Description
The PSD family of memory systems for microcontrollers (MCUs) brings In-SystemProgrammability (ISP) to Flash memory and programmable logic. The result is a simple and
flexible solution for embedded designs. PSD devices combine many of the peripheral
functions found in MCU based applications.
The CPLD in the PSD devices features an optimized macrocell logic architecture. The PSD
macrocell was created to address the unique requirements of embedded system designs. It
allows direct connection between the system address/data bus, and the internal PSD
registers, to simplify communication between the MCU and other supporting devices.
The PSD family offers two methods to program the PSD Flash memory while the PSD is
soldered to the circuit board: In-System Programming (ISP) via JTAG, and In-Application
Programming (IAP).
1.1
In-system programming (ISP) via JTAG
An IEEE 1149.1 compliant JTAG In-System Programming (ISP) interface is included on the
PSD enabling the entire device (Flash memories, PLD, configuration) to be rapidly
programmed while soldered to the circuit board. This requires no MCU participation, which
means the PSD can be programmed anytime, even when completely blank.
The innovative JTAG interface to Flash memories is an industry first, solving key problems
faced by designers and manufacturing houses, such as:
1.1.1
First time programming
How do I get firmware into the Flash memory the very first time? JTAG is the answer.
Program the blank PSD with no MCU involvement.
1.1.2
Inventory build-up of pre-programmed devices
How do I maintain an accurate count of pre-programmed Flash memory and PLD devices
based on customer demand? How many and what version? JTAG is the answer. Build your
hardware with blank PSDs soldered directly to the board and then custom program just
before they are shipped to the customer. No more labels on chips, and no more wasted
inventory.
1.1.3
Expensive sockets
How do I eliminate the need for expensive and unreliable sockets? JTAG is the answer.
Solder the PSD directly to the circuit board. Program first time and subsequent times with
JTAG. No need to handle devices and bend the fragile leads.
1.2
In-application programming (IAP)
Two independent Flash memory arrays are included so that the MCU can execute code from
one while erasing and programming the other. Robust product firmware updates in the field
are possible over any communications channel (CAN, Ethernet, UART, J1850, etc.) using
this unique architecture. Designers are relieved of these problems:
11/118
Description
1.2.1
PSD835G2V
Simultaneous read and write to Flash memory
How can the MCU program the same memory from which it is executing code? It cannot.
The PSD allows the MCU to operate the two Flash memory blocks concurrently, reading
code from one while erasing and programming the other during IAP.
1.2.2
Complex memory mapping
How can I map these two memories efficiently? A programmable Decode PLD (DPLD) is
embedded in the PSD. The concurrent PSD memories can be mapped anywhere in MCU
address space, segment by segment with extremely high address resolution. As an option,
the secondary Flash memory can be swapped out of the system memory map when IAP is
complete. A built-in page register breaks the MCU address limit.
1.2.3
Separate Program and Data space
How can I write to Flash memory while it resides in Program space during field firmware
updates? My 80C51 will not allow it. The PSD provides means to reclassify Flash memory
as Data space during IAP, then back to Program space when complete.
1.3
PSDsoft
PSDsoft, a software development tool from ST, guides you through the design process stepby-step making it possible to complete an embedded MCU design capable of ISP/IAP in just
hours. Select your MCU and PSDsoft takes you through the remainder of the design with
point and click entry, covering PSD selection, pin definitions, programmable logic inputs and
outputs, MCU memory map definition, ANSI-C code generation for your MCU, and merging
your MCU firmware with the PSD design. When complete, two different device programmers
are supported directly from PSDsoft: FlashLINK (JTAG) and PSDpro.
12/118
PSD835G2V
Description
61 PB0
62 PB1
63 PB2
64 PB3
65 PB4
66 PB5
67 PB6
68 PB7
69 VCC
70 GND
71 PE0
72 PE1
73 PE2
74 PE3
75 PE4
76 PE5
77 PE6
78 PE7
79 PD0
TQFP80 connections
80 PD1
Figure 1.
PD2 1
60 CNTL1
PD3 2
59 CNTL0
AD0 3
58 PA7
AD1 4
57 PA6
AD2 5
56 PA5
AD3 6
55 PA4
AD4 7
54 PA3
GND 8
53 PA2
VCC 9
AD5 10
52 PA1
AD6 11
50 GND
AD7 12
49 GND
AD8 13
48 PC7
AD9 14
47 PC6
AD10 15
46 PC5
AD11 16
45 PC4
AD12 17
44 PC3
AD13 18
43 PC2
AD14 19
42 PC1
AD15 20
41 PC0
CNTL2 40
RESET 39
PF7 38
PF6 37
PF5 36
PF4 35
PF3 34
PF2 33
PF1 32
PF0 31
GND 30
VCC 29
PG7 28
PG6 27
PG5 26
PG4 25
PG3 24
PG2 23
PG1 22
PG0 21
51 PA0
AI04943
13/118
Description
Table 1.
Pin name
ADIO0-7
ADIO8-15
CNTL0
CNTL1
PSD835G2V
Pin description (for the TQFP80 package)
Pin
3-7-10-12
13-20
59
60
Type
Description
I/O
This is the lower Address/Data port. Connect your MCU address or address/data
bus according to the following rules:
If your MCU has a multiplexed address/data bus where the data is multiplexed
with the lower address bits, connect AD0-AD7 to this port.
If your MCU does not have a multiplexed address/data bus, connect A0-A7 to this
port.
If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to
this port.
ALE or AS latches the address. The PSD drives data out only if the read signal is
active and one of the PSD functional blocks was selected. The addresses on this
port are passed to the PLDs.
I/O
This is the upper Address/Data port. Connect your MCU address or address/data
bus according to the following rules:
If your MCU has a multiplexed address/data bus where the data is multiplexed
with the lower address bits, connect A8-A15 to this port.
If your MCU does not have a multiplexed address/data bus, connect A8-A15 to
this port.
If you are using an 80C251 in page mode, connect AD8-AD15 to this port.
If you are using an 80C51XA in burst mode, connect A12-A19 to this port.
ALE or AS latches the address. The PSD drives data out only if the read signal is
active and one of the PSD functional blocks was selected. The addresses on this
port are passed to the PLDs.
I
The following control signals can be connected to this port, based on your MCU:
WR – active Low Write Strobe input.
R_W – active High read/active Low write input.
This port is connected to the PLDs. Therefore, these signals can be used in
decode and other logic equations.
I
The following control signals can be connected to this port, based on your MCU:
RD – active Low Read Strobe input.
E – E clock input.
DS – active Low Data Strobe input.
PSEN – connect PSEN to this port when it is being used as an active Low read
signal. For example, when the 80C251 outputs more than 16 address bits, PSEN
is actually the read signal.
This port is connected to the PLDs. Therefore, these signals can be used in
decode and other logic equations.
CNTL2
40
I
This port can be used to input the PSEN (Program Select Enable) signal from
any MCU that uses this signal for code exclusively. If your MCU does not output a
Program Select Enable signal, this port can be used as a generic input. This port
is connected to the PLDs as input.
Reset
39
I
Active Low input. Resets I/O Ports, PLD macrocells and some of the
Configuration Registers and JTAG registers. Must be Low at Power-up. Reset
also aborts the Flash programming/erase cycle that is in progress.
14/118
PSD835G2V
Table 1.
Description
Pin description (for the TQFP80 package) (continued)
Pin name
Pin
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
58
57
56
55
54
53
52
51
These pins make up Port A. These port pins are configurable and can have the
following functions:
I/O
CMOS MCU I/O – write to or read from a standard output or input port.
or Open CPLD macrocell (McellA0-7) outputs.
Drain Inputs to the PLDs.
Latched, transparent or registered PLD input.
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
68
67
66
65
64
63
62
61
I/O
CMOS
or Open
Drain
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
48
47
46
45
44
43
42
41
These pins make up Port C. These port pins are configurable and can have the
I/O
following functions:
CMOS
MCU I/O – write to or read from a standard output or input port.
or Open
Drain External Chip Select (ECS0-7) output.
Latched, transparent or registered PLD input.
79
PD0 pin of Port D. This port pin can be configured to have the following functions:
I/O
ALE/AS input latches addresses on ADIO0-ADIO15 pins.
CMOS
AS input latches addresses on ADIO0-ADIO15 pins on the rising edge.
or Open
Drain Input to the PLDs.
Transparent PLD input.
80
PD1 pin of Port D. This port pin can be configured to have the following functions:
I/O
MCU I/O – write to or read from a standard output or input port.
CMOS
or Open Input to the PLDs.
Drain CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down
counter, and the CPLD AND Array.
1
I/O
CMOS
or Open
Drain
2
I/O
PD3 pin of Port D. This port pin can be configured to have the following functions:
CMOS
MCU I/O – write to or read from a standard output or input port.
or Open
Drain Input to the PLDs.
PD0
PD1
PD2
PD3
Type
Description
These pins make up Port B. These port pins are configurable and can have the
following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellB0-7) output.
Inputs to the PLDs.
Latched, transparent or registered PLD input.
PD2 pin of Port D. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
Input to the PLDs.
PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory
and I/O. When High, the PSD memory blocks are disabled to conserve power.
The trailing edge of CSI can be used to get the PSD out of power-down mode.
15/118
Description
Table 1.
Pin name
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PF0-PF7
16/118
PSD835G2V
Pin description (for the TQFP80 package) (continued)
Pin
Type
Description
71
I/O
CMOS
or Open
Drain
PE0 pin of Port E. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
Latched address output.
TMS input for JTAG/ISP interface.
72
I/O
CMOS
or Open
Drain
PE1 pin of Port E. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
Latched address output.
TCK input for JTAG/ISP interface (Schmidt Trigger).
73
I/O
CMOS
or Open
Drain
PE2 pin of Port E. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
Latched address output.
TDI input for JTAG/ISP interface.
74
I/O
CMOS
or Open
Drain
PE3 pin of Port E. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
Latched address output.
TDO input for JTAG/ISP interface.
75
PE4 pin of Port E. This port pin can be configured to have the following functions:
I/O
MCU I/O – write to or read from a standard output or input port.
CMOS
Latched address output.
or Open
Drain TSTAT input for the ISP interface.
Ready/Busy for in-circuit Parallel Programming.
76
I/O
CMOS
or Open
Drain
PE5 pin of Port E. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
Latched address output.
TERR active Low input for ISP interface.
77
I/O
CMOS
or Open
Drain
PE6 pin of Port E. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
Latched address output.
VSTBY SRAM standby voltage input for battery backup SRAM.
78
PE7 pin of Port E. This port pin can be configured to have the following functions:
I/O
MCU I/O – write to or read from a standard output or input port.
CMOS
Latched
address output.
or Open
battery
backup indicator output. Goes High when power is drawn from an
V
BATON
Drain
external battery.
31-38
PF0 through PF7 pins of Port F. This port pins can be configured to have the
following functions:
I/O
MCU I/O – write to or read from a standard output or input port.
CMOS
Input to the PLDs.
or Open
Drain Latched address outputs.
As address A0-A3 inputs in 80C51XA mode.
As data bus port (D07) in non-multiplexed bus configuration.
PSD835G2V
Table 1.
Pin name
Description
Pin description (for the TQFP80 package) (continued)
Pin
Type
Description
PG0-PG7
8, 30, 49,
50, 70
I/O
CMOS
or Open
Drain
VCC
9, 29, 69
Supply Voltage
GND
8, 30, 49,
50, 70
Ground pins
PG0 through PG7 pins of Port G. This port pins can be configured to have the
following functions:
MCU I/O – write to or read from a standard output or input port.
Latched address outputs.
17/118
18/118
PG0 – PG7
PF0 –PF7
CLKIN
(PD1)
PORT G
PROG.
PORT
PORT F
PROG.
PORT
ADIO
PORT
PROG.
MCU BUS
INTRF.
CLKIN
82
CSIOP
GLOBAL
CONFIG. &
SECURITY
CLKIN
64 KBIT BATTERY
BACKUP SRAM
256 KBIT SECONDARY
FLASH MEMORY
(BOOT OR DATA)
4 SECTORS
8 SECTORS
4 MBIT PRIMARY
FLASH MEMORY
PLD, CONFIGURATION
& FLASH MEMORY
LOADER
PORT F
JTAG
SERIAL
CHANNEL
PORT A ,B & C
24 INPUT MACROCELLS
PORT A & B
16 OUTPUT MACROCELLS
8 EXT CS TO PORT C OR F
RUNTIME CONTROL
AND I/O REGISTERS
PERIP I/O MODE SELECTS
SRAM SELECT
SECTOR
SELECTS
FLASH ISP CPLD
(CPLD)
FLASH DECODE
PLD (DPLD)
SECTOR
SELECTS
EMBEDDED
ALGORITHM
MACROCELL FEEDBACK OR PORT INPUT
82
PAGE
REGISTER
PORT
E
PROG.
PORT
PORT
D
PROG.
PORT
PORT
C
PROG.
PORT
PORT
B
PROG.
PORT
PORT
A
PROG.
PORT
POWER
MANGMT
UNIT
PE0 – PE7
PD0 – PD2
PC0 – PC7
PB0 – PB7
PA0 – PA7
VSTDBY
(PE6 )
Figure 2.
AD0 – AD15
CNTL0,
CNTL1,
CNTL2
PLD
INPUT
BUS
ADDRESS/DATA/CONTROL BUS
Description
PSD835G2V
PSD block diagram
AI05793b
PSD835G2V
2
PSD architectural overview
PSD architectural overview
PSD devices contain several major functional blocks. Figure 2. on page 18 shows the
architecture of the PSD device family. The functions of each block are described briefly in
the following sections. Many of the blocks perform multiple functions and are user
configurable.
2.1
Memory
Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed
discussion can be found in Memory blocks on page 29.
The 4Mbit (512K x 8) Flash memory is the primary memory of the PSD. It is divided into 8
equally-sized sectors that are individually selectable.
The 256Kbit (32K x8) secondary Flash memory is divided into 4 equally-sized sectors. Each
sector is individually selectable.
The 64 Kbit SRAM is intended for use as a scratch-pad memory or as an extension to the
MCU SRAM. If an external battery is connected to Voltage Standby (VSTBY, PC2), data is
retained in the event of power failure.
Each sector of memory can be located in a different address space as defined by the user.
The access times for all memory types includes the address latching and DPLD decoding
time.
2.2
Page Register
The 8-bit Page Register expands the address range of the MCU by up to 256 times. The
paged address can be used as part of the address space to access external memory and
peripherals, or internal memory and I/O. The Page Register can also be used to change the
address mapping of sectors of the Flash memories into different memory spaces for IAP.
2.3
PLDs
The device contains two PLDs, the Decode PLD (DPLD) and the Complex PLD (CPLD), as
shown in Table 2, each optimized for a different function. The functional partitioning of the
PLDs reduces power consumption, optimizes cost/performance, and eases design entry.
The DPLD is used to decode addresses and to generate Sector Select signals for the PSD
internal memory and registers. The CPLD can implement user-defined logic functions. The
DPLD has combinatorial outputs. The CPLD has 16 Output Macrocells (OMC) and 8
combinatorial outputs. The PSD also has 24 Input Macrocells (IMC) that can be configured
as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus and are
differentiated by their output destinations, number of product terms, and macrocells.
The PLDs consume minimal power by using Power-Management design techniques. The
speed and power consumption of the PLD is controlled by the Turbo bit in PMMR0 and other
bits in the PMMR2. These registers are set by the MCU at run-time. There is a slight penalty
to PLD propagation time when invoking the power management features.
19/118
PSD architectural overview
2.4
PSD835G2V
I/O Ports
The PSD has 52 I/O pins distributed over the seven ports (Port A, B, C, D, E, F and G). Each
I/O pin can be individually configured for different functions. Ports can be configured as
standard MCU I/O ports, PLD I/O, or latched address outputs for MCUs using multiplexed
address/data buses.
The JTAG pins can be enabled on Port E for In-System Programming (ISP). Ports F and G
can also be configured as data ports for a non-multiplexed bus.
Ports A and B can also be configured as a data port for a non-multiplexed bus.
2.5
MCU Bus Interface
PSD interfaces easily with most 8-bit MCUs that have either multiplexed or non-multiplexed
address/data buses. The device is configured to respond to the MCU’s control signals,
which are also used as inputs to the PLDs. For examples, please see MCU bus interface
examples on page 63.
Table 2.
PLD I/O
Name
Inputs
Outputs
Product Terms
Decode PLD (DPLD)
82
17
43
Complex PLD (CPLD)
82
24
150
Table 3.
JTAG signals on Port E
Port E Pins
2.6
JTAG Signal
PE0
TMS
PE1
TCK
PE2
TDI
PE3
TDO
PE4
TSTAT
PE5
TERR
JTAG Port
In-System Programming (ISP) can be performed through the JTAG signals on Port E. This
serial interface allows complete programming of the entire PSD device. A blank device can
be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can
be multiplexed with other functions on Port E. Table 3. on page 20 indicates the JTAG pin
assignments.
2.7
In-system programming (ISP)
Using the JTAG signals on Port E, the entire PSD device (memory, logic, configuration) can
be programmed or erased without the use of the MCU.
20/118
PSD835G2V
2.8
PSD architectural overview
In-application re-programming (IAP)
The primary Flash memory can also be programmed in-system by the MCU executing the
programming algorithms out of the secondary memory, or SRAM. Since this is a sizable
separate block, the application can also continue to operate. The secondary memory can be
programmed the same way by executing out of the primary Flash memory. The PLD or other
PSD Configuration blocks can be programmed through the JTAG port or a device
programmer. Table 4 indicates which programming methods can program different
functional blocks of the PSD.
2.9
Power management unit (PMU)
The Power Management Unit (PMU) gives the user control of the power consumption on
selected functional blocks based on system requirements. The PMU includes an Automatic
Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD Unit
has a Power-down mode that helps reduce power consumption.
The PSD also has some bits that are configured at run-time by the MCU to reduce power
consumption of the CPLD. The Turbo bit in PMMR0 can be reset to 0 and the CPLD latches
its outputs and goes to sleep until the next transition on its inputs.
Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD
to reduce power consumption. Please see Power management on page 84 for more details.
Table 4.
Methods of programming different functional blocks of the PSD
Functional Block
JTAG/ISP
Device Programmer
IAP
Primary Flash Memory
Yes
Yes
Yes
Secondary Flash Memory
Yes
Yes
Yes
PLD Array (DPLD and CPLD)
Yes
Yes
No
PSD Configuration
Yes
Yes
No
21/118
Development system
3
PSD835G2V
Development system
The PSD family is supported by PSDsoft, a Windows-based (95, 98, NT) software
development tool. A PSD design is quickly and easily produced in a point-and-click
environment. The designer does not need to enter Hardware Description Language (HDL)
equations, unless desired, to define PSD pin functions and memory map information. The
general design flow is shown in Figure 3. PSDsoft is available from our web site (the
address is given on the back page of this data sheet) or other distribution channels.
PSDsoft directly supports two low cost device programmers form ST: PSDpro and
FlashLINK (JTAG). Both of these programmers may be purchased through your local
distributor/representative, or directly from our web site using a credit card. The PSD is also
supported by third party device programmers. See our web site for the current list.
Figure 3.
PSDsoft development tool
Choose MCU and PSD
Automatically Configures MCU
bus interface and other PSD
attributes.
Define PSD Pin and
Node Functions
Point-and-click definition of PSD
pin functions, internal nodes and
MCU system memory map
Define General Purpose
Logic in CPLD
C Code Generation
Point-and-click definition of
combinatorial and registered
logic in CPLD. Access to HDL is
available if needed.
GENERATE C CODE
SPECIFIC TO PSD
FUNCTIONS
Merge MCU Firmware
with PSD Configuration
A composite object file is created
containing MCU firmware and
PSD configuration
MCU FIRMWARE
HEX OR S-RECORD
FORMAT
USER'S CHOICE OF
MICROCONTROLLER
COMPILER/LINKER
*.OBJ FILE
ST PSD Programmer
PSDPro, or
FlashLINK (JTAG)
*.OBJ
FILE AVAILABLE
FOR 3rd PARTY
PROGRAMMERS
(CONVENTIONAL or
JTAG/ISP)
AI04918b
22/118
PSD835G2V
4
PSD register description and address offset
PSD register description and address offset
Table 5 shows the offset addresses to the PSD registers relative to the CSIOP base
address. The CSIOP space is the 256 Bytes of address that is allocated by the user to the
internal PSD registers. Table 5 provides brief descriptions of the registers in CSIOP space.
The following section gives a more detailed description.
Table 5.
Register address offset
Register name Port A Port B Port C Port D Port E Port F Port G Other(1)
Data In
00
01
10
11
Control
Description
30
40
41
Reads Port pin as input, MCU
I/O input mode
32
42
43
Selects mode between MCU
I/O or Address Out
Data Out
04
05
14
15
34
44
45
Stores data for output to Port
pins, MCU I/O output mode
Direction
06
07
14
15
36
46
47
Configures Port pin as input or
output
49
Configures Port pins as either
CMOS or Open Drain on some
pins, while selecting high slew
rate on other pins.
Drive Select
08
09
Input Macrocell
0A
0B
Enable Out
0C
0D
Output
Macrocells A
Mask
Macrocells B
19
38
48
1A
1C
1B
Reads Input Macrocells
Reads the status of the output
enable to the I/O Port driver
4C
Read – reads output of
macrocells A
Write – loads macrocell flipflops
20
Output
Macrocells B
Mask
Macrocells A
18
Read – reads output of
macrocells B
Write – loads macrocell flipflops
21
Blocks writing to the Output
Macrocells A
22
Blocks writing to the Output
Macrocells B
23
Primary Flash
Protection
C0
Read only – Primary Flash
Sector Protection
Secondary
Flash memory
Protection
C2
Read only – PSD Security and
Secondary Flash memory
Sector Protection
JTAG Enable
C7
Enables JTAG Port
PMMR0
B0
Power Management Register 0
PMMR2
B4
Power Management Register 2
23/118
PSD register description and address offset
Table 5.
PSD835G2V
Register address offset (continued)
Register name Port A Port B Port C Port D Port E Port F Port G Other(1)
Description
Page
E0
Page Register
VM
E2
Places PSD memory areas in
Program and/or Data space on
an individual basis.
Memory_ID0
F0
Read only – Primary Flash
memory and SRAM size
Memory_ID1
F1
Read only – Secondary Flash
memory type and size
1. Other registers that are not part of the I/O ports.
24/118
PSD835G2V
5
Register bit definition
Register bit definition
All the registers of the PSD are included here, for reference. Detailed descriptions of these
registers can be found in the following sections.
Table 6.
Data-In Registers – Ports A, B, C, D, E, F, G(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
1. Bit Definitions (Read-only registers):
Read Port pin status when Port is in MCU I/O input mode.
Table 7.
Data-Out Registers – Ports A, B, C, D, E, F, G(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
1. Bit Definitions:
Latched data for output to Port pin when pin is configured in MCU I/O output mode.
Table 8.
Direction Registers – Ports A, B, C, D, E, F, G(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
1. Bit Definitions:
Port pin 0 = Port pin is configured in Input mode (default).
Port pin 1 = Port pin is configured in Output mode.
Table 9.
Control Registers – Ports E, F, G(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
1. Bit Definitions:
Port pin 0 = Port pin is configured in MCU I/O mode (default).
Port pin 1 = Port pin is configured in Latched Address Out mode.
Table 10.
Drive Registers – Ports A, B, D, E, G(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
1. Bit Definitions:
Port pin 0 = Port pin is configured for CMOS Output driver (default).
Port pin 1 = Port pin is configured for Open Drain output driver.
Table 11.
Drive Registers – Ports C, F(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
1. Bit Definitions:
Port pin 0 = Port pin is configured for CMOS Output driver (default).
Port pin 1 = Port pin is configured in Slew Rate mode.
25/118
Register bit definition
Table 12.
PSD835G2V
Enable-Out Registers – Ports A, B, C, F(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
1. Bit Definitions (Read-only registers):
Port pin 0 = Port pin is in tri-state driver (default).
Port pin 1 = Port pin is enabled.
Table 13.
Input Macrocells – Ports A, B, C(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IMcell 7
IMcell 6
IMcell 5
IMcell 4
IMcell 3
IMcell 2
IMcell 1
IMcell 0
1. Bit Definitions (Read-only registers):
Read Input Macrocell (IMC7-IMC0) status on Ports A, B and C.
Table 14.
Output Macrocells A Register(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcella 7
Mcella 6
Mcella 5
Mcella 4
Mcella 3
Mcella 2
Mcella 1
Mcella 0
1. Bit Definitions:
Write Register: Load MCellA7-MCellA0 with 0 or 1.
Read Register: Read MCellA7-MCellA0 output status.
Table 15.
Output Macrocells B Register(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcellb 7
Mcellb 6
Mcellb 5
Mcellb 4
Mcellb 3
Mcellb 2
Mcellb 1
Mcellb 0
1. Bit Definitions:
Write Register: Load MCellB7-MCellB0 with 0 or 1.
Read Register: Read MCellB7-MCellB0 output status.
Table 16.
Mask Macrocells A Register(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcella 7
Mcella 6
Mcella 5
Mcella 4
Mcella 3
Mcella 2
Mcella 1
Mcella 0
1. Bit Definitions:
McellA_Prot 0 = Allow MCellA flip-flop to be loaded by MCU (default).
McellA_Prot 1 = Prevent MCellA flip-flop from being loaded by MCU.
Table 17.
Mask Macrocells B Register(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcellb 7
Mcellb 6
Mcellb 5
Mcellb 4
Mcellb 3
Mcellb 2
Mcellb 1
Mcellb 0
Bit 1
Bit 0
1. Bit Definitions:
McellB_Prot 0 = Allow MCellB flip-flop to be loaded by MCU (default).
McellB_Prot 1 = Prevent MCellB flip-flop from being loaded by MCU.
Table 18.
Bit 7
Flash Memory Protection Register(1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
1. Bit Definitions (Read-only register):
Sec_Prot 1 = Primary Flash memory Sector is write protected.
Sec_Prot 0 = Primary Flash memory Sector is not write protected.
26/118
PSD835G2V
Register bit definition
Table 19.
Bit 7
Flash Boot Protection Register(1)
Bit 6
Security_Bit not used
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
not used
Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
1. Bit Definitions:
Sec_Prot 1 = Secondary Flash memory Sector is write protected.
Sec_Prot 0 = Secondary Flash memory Sector is not write protected.
Security_Bit 0 = Security Bit in device has not been set.
Security_Bit 1 = Security Bit in device has been set.
Table 20.
JTAG Enable Register(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
not used
not used
not used
not used
not used
not used
JTAGEnable
1. Bit Definitions:
JTAG_Enable 1 = JTAG Port is enabled.
JTAG_Enable 0 = JTAG Port is disabled.
Table 21.
Page Register(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PGR 7
PGR 6
PGR 5
PGR 4
PGR 3
PGR 2
PGR 1
PGR 0
Bit 2
Bit 1
Bit 0
not used
(set to 0)
APD
Enable
not used
(set to 0)
1. Bit Definitions:
Configure Page input to PLD. Default is PGR7-PGR0=00.
Table 22.
PMMR0 Register(1) (2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
not used
(set to 0)
not used
(set to 0)
PLD
PLD
PLD
MCells CLK Array CLK Turbo
1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset) pulses do not
clear the registers.
2. Bit Definitions:
APD Enable0 = Automatic Power-down (APD) is disabled.
1 = Automatic Power-down (APD) is enabled.
PLD Turbo0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
PLD Array CLK0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD
when Turbo bit is off.
1 = CLKIN to the PLD AND array is disconnected, saving power.
PLD MCells CLK0 = CLKIN to the PLD Macrocells is connected.
1 = CLKIN to the PLD Macrocells is disconnected, saving power.
Table 23.
PMMR2 Register(1)
Bit 7
Bit 6
Bit 5
not used
(set to 0)
PLD Array PLD Array
WRH
ALE
Bit 4
Bit 3
Bit 2
Bit 1
PLD Array PLD Array PLD Array not used
CNTL2
CNTL1
CNTL0
(set to 0)
Bit 0
PLD Array
Addr
1. Bit Definitions:
PLD Array Addr0 = Address A7-A0 are connected to the PLD array.
1 = Address A7-A0 are blocked from the PLD array, saving power.
(Note: in XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4)
PLD Array CNTL20 = CNTL2 input to the PLD AND array is connected.
1 = CNTL2 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL10 = CNTL1 input to the PLD AND array is connected.
1 = CNTL1 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL00 = CNTL0 input to the PLD AND array is connected.
1 = CNTL0 input to the PLD AND array is disconnected, saving power.
PLD Array ALE0 = ALE input to the PLD AND array is connected.
1 = ALE input to the PLD AND array is disconnected, saving power.
PLD Array WRH0 = WRH/DBE input to the PLD AND array is connected.
1 = WRH/DBE input to the PLD AND array is disconnected, saving power.
27/118
Register bit definition
Table 24.
PSD835G2V
VM Register(1) (2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Peripheral
mode
not used
(set to 0)
not used
(set to 0)
FL_data
Boot_data
FL_code
Boot_code
SR_code
1. On reset, Bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft. Bit0 and Bit7 are
always cleared on reset. Bit0-Bit4 are active only when the device is configured for the 8031 and
compatible MCU families.
2. Bit Definitions:
SR_code0 = PSEN cannot access SRAM.
1 = PSEN can access SRAM.
Boot_code0 = PSEN cannot access Secondary NVM.
1 = PSEN can access Secondary NVM.
FL_code0 = PSEN cannot access Primary Flash memory.
1 = PSEN can access Primary Flash memory.
Boot_data0 = RD cannot access Secondary NVM.
1 = RD can access Secondary NVM.
FL_data0 = RD cannot access Primary Flash memory.
1 = RD can access Primary Flash memory.
Peripheral mode0 = Peripheral mode of Port F is disabled.
1 = Peripheral mode of Port F is enabled.
Table 25.
Memory_ID0 Register(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
S_size 3
S_size 2
S_size 1
S_size 0
F_size 3
F_size 2
F_size 1
F_size 0
1. Bit Definitions:
F_size[3:0]4h = Primary Flash memory size is 4 Mbit
5h = Primary Flash memory size is 8Mbit
S_size[3:0]0h = There is no SRAM
1h = SRAM size is 16 Kbit
3h = SRAM size is 64 Kbit
Table 26.
Memory_ID1 Register(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to 0)
not used
(set to 0)
B_type 1
B_type 0
B_size 3
B_size 2
B_size 1
B_size 0
1. Bit Definitions:
B_size[3:0]0h = There is no Secondary NVM
2h = Secondary NVM size is 256 Kbit
B_type[1:0]0h = Secondary NVM is Flash memory
1h = Secondary NVM is EEPROM
28/118
PSD835G2V
6
Detailed operation
Detailed operation
As shown in Figure 2. on page 18, the PSD consists of six major types of functional blocks:
●
Memory Blocks
●
PLD Blocks
●
MCU Bus Interface
●
I/O Ports
●
Power Management Unit (PMU)
●
JTAG/ISP Interface
The functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable.
6.1
Memory blocks
The PSD has the following memory blocks:
–
Primary Flash memory
–
Secondary Flash memory
–
SRAM
The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are
user-defined in PSDsoft.
Table 27.
Memory block size and organization
Primary Flash memory
Sector
number
Secondary Flash memory
SRAM
Sector size Sector Select Sector size Sector Select SRAM size SRAM Select
(bytes)
signal
(bytes)
signal
(bytes)
signal
0
64K
FS0
8K
CSBOOT0
1
64K
FS1
8K
CSBOOT1
2
64K
FS2
8K
CSBOOT2
3
64K
FS3
8K
CSBOOT3
4
64K
FS4
5
64K
FS5
6
64K
FS6
7
64K
FS7
Total
512K
8 Sectors
32K
4 Sectors
16K
RS0
16K
29/118
Detailed operation
6.2
PSD835G2V
Primary Flash memory and Secondary Flash memory
description
The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash
memory is divided into four equal sectors of eight KBytes each. Each sector of either
memory block can be separately protected from Program and Erase cycles.
Flash memory may be erased on a sector-by-sector basis and programmed Word-by-Word.
Flash sector erasure may be suspended while data is read from other sectors of the block
and then resumed after reading.
During a Program or Erase cycle in Flash memory, the status can be output on Ready/Busy
(PE4). This pin is set up using PSDsoft.
6.3
Memory Block Select signals
The DPLD generates the Select signals for all the internal memory blocks (see PLDs on
page 49). Each of the eight sectors of the primary Flash memory has a Select signal (FS0FS7) which can contain up to three product terms. Each of the four sectors of the secondary
Flash memory has a Select signal (CSBOOT0-CSBOOT3) which can contain up to three
product terms. Having three product terms for each Select signal allows a given sector to be
mapped in different areas of system memory. When using an MCU with separate Program
and Data space, these flexible Select signals allow dynamic re-mapping of sectors from one
memory space to the other before and after IAP.
6.4
Upper and Lower Block IN MAIN FLASH SECTOR
The PSD835G2’s main Flash memory has eight 64-KByte sectors. The 64-KByte sector size
may cause some difficulty in code mapping for an 8-bit MCU with only 64-KByte address
space. To resolve this mapping issue, the PSD835G2 provides additional logic (see Figure
5. on page 31) for the user to split the 8 sectors such that each sector has a lower and upper
32-KByte block, and the two blocks can reside in different pages but in the same address
range.
If your design works with 64KB sectors, you don’t need to configure this logic. If the design
requires 32KB blocks in each sector, you need to define a “FA15” PLD equation in PSDsoft
as the A15 address input to the main Flash module. FA15 consists of 3 product terms and
will control whether the MCU is accessing the lower or upper 32KB in the selected sector.
Figure 4 shows an example for Flash sector chip select FS0. A typical equation is FA15 =
pgr4 of the Page Register. When pgr4 is 0 (page 00), the lower 32KB is selected. When pgr4
is switched to 1 by the user, the upper 32KB is selected. PSDsoft will automatically generate
the PLD equations shown, based on your point and click selections.
If no FA15 equation is defined in PSDsoft, the A15 that comes from the MCU address bus
will be routed as input to the primary Flash memory instead of FA15. The FA15 equation has
no impact on the Sector Erase operation.
Note:
30/118
FA15 affects all eight sectors of the primary Flash memory simultaneously. You cannot
direct FA15 to a particular Flash sector only.
PSD835G2V
Detailed operation
Figure 4.
Example for Flash Sector Chip Select FS0
page = [pgr7... pgr0]; “Page Register output
“Sector Chip Select Equation
FS0 = ((0000h <= address <= 7FFFh) & page = 00h) #
“select first 32KB block
((0000h <= address <= 7FFFh) & page = 10h);
“select second 32KB block
FA15 = pgr4;
“as address A15 input to the primary Flash memory
ai07652
Figure 5.
Selecting the upper or lower block in a Primary Flash memory sector
FLASH MEMORY CHIP SELECT PINS FS0-FS7
DPLD
ARRAY
FA15
MUX
ADDR A15
PRIMARY
FLASH
MEMORY
SECTOR
A15
NVM CONTROL BIT(1)
A14-A0
ai07653
6.5
Ready/Busy (PE4)
This signal can be used to output the Ready/Busy status of the PSD. The output on
Ready/Busy (PE4) is a 0 (Busy) when Flash memory blocks are being written to, or when
the Flash memory block is being erased. The output is a 1 (Ready) when no Write or Erase
cycle is in progress.
6.6
Memory operation
The primary Flash memory and secondary Flash memory are addressed through the MCU
Bus Interface. The MCU can access these memories in one of two ways:
●
The MCU can execute a typical bus Write or Read operation just as it would if
accessing a RAM or ROM device using standard bus cycles.
●
The MCU can execute a specific instruction that consists of several Write and Read
operations. This involves writing specific data patterns to special addresses within the
Flash memory to invoke an embedded algorithm. These instructions are summarized in
Table 28. on page 32.
Typically, the MCU can read Flash memory using Read operations, just as it would read a
ROM device. However, Flash memory can only be altered using specific Erase and Program
instructions. For example, the MCU cannot write a single byte directly to Flash memory as it
would write a byte to RAM. To program a byte into Flash memory, the MCU must execute a
Program instruction, then test the status of the Program cycle. This status test is achieved
by a Read operation or polling Ready/Busy (PE4).
Flash memory can also be read by using special instructions to retrieve particular Flash
device information (sector protect status and ID).
31/118
Detailed operation
Table 28.
PSD835G2V
Instructions(1) (2) (3)
Instruction
FS0-FS7 or
CSBOOT0CSBOOT3(4)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6 Cycle 7
Read(5)
1
“Read” RA
@ RD
Read Primary
Flash ID(6)(7)
1
AAh@ 555h 55h@ AAAh 90h@ 555h
Read Sector
Protection(6)(8)(7)
1
Read identifier
AAh@ 555h 55h@ AAAh 90h@ 555h 00h or 01h
@X02h
Program a Flash
Byte(7)
1
AAh@ 555h 55h@ AAAh
Flash Sector
Erase(9)
1
AAh@ 555h 55h@ AAAh 80h@ 555h AAh@ 555h
55h@
AAAh
30h@ SA
Flash Bulk Erase
1
AAh@ 555h 55h@ AAAh 80h@ 555h AAh@ 555h
55h@
AAAh
10h@
555h
Suspend Sector
Erase(10)
1
B0h@
XXXh
Resume Sector
Erase(11)
1
30h@
XXXh
Reset(6)
1
F0h@ any
address
Unlock Bypass
1
AAh@ 555h 55h@ AAAh 20h@ 555h
Unlock Bypass
Program(12)
1
A0h@
XXXh
PD@ PA
Unlock Bypass
Reset(13)
1
90h@
XXXh
00h@ XXXh
A0h@
555h
Read identifier
@X01h
PD@ PA
30h(9)@
next SA
1. All bus cycles are write bus cycles, except the ones with the “Read” label.
2. All values are in hexadecimal: X = Don’t Care. RA = Address of the memory location to be read, RD = Data read from
location RA during the Read cycle, PA = Address of the memory location to be programmed. Addresses are latched on the
falling edge of Write Strobe (WR, CNTL0). PA is an even address for PSD in word programming mode.
PD = Data to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select pins (FS0-FS7 or CSBOOT0-CSBOOT3) of the
sector or whole memory to be erased, or verified, must be Active (High).
3. Only address bits A11-A0 are used in instruction decoding. A15-A12 (or A16-A12) are don’t care.
4. Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) signals are active High, and are defined in PSDsoft.
5. No Unlock or instruction cycles are required when the device is in the Read mode
6. The Reset instruction is required to return to the Read mode after reading the Flash ID, or after reading the Sector
Protection Status, or if the Error Flag (DQ5/DQ13) bit goes High.
7. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the
instruction is intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the
Sector Protection Status of the primary Flash memory.
8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active,
and (A1,A0)=(1,0)
9. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80 µs.
10. The system may perform Read and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection
Status when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase
cycle.
11. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
12. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
13. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock
Bypass mode.
32/118
PSD835G2V
7
Instructions
Instructions
An instruction consists of a sequence of specific operations. Each received Byte is
sequentially decoded by the PSD and not executed as a standard Write operation. The
instruction is executed when the correct number of Bytes is properly received and the time
between two consecutive Bytes is shorter than the time-out period. Some instructions are
structured to include Read operations after the initial Write operations.
The instruction must be followed exactly. Any invalid combination of instruction Bytes or
time-out between two consecutive bytes while addressing Flash memory resets the device
logic into Read mode (Flash memory is read like a ROM device).
The PSD supports the instructions summarized in Table 28. on page 32:
Flash memory:
●
Erase memory by chip or sector
●
Suspend or resume sector erase
●
Program a Byte
●
Reset to Read mode
●
Read primary Flash Identifier value
●
Read Sector Protection Status
●
Bypass
These instructions are detailed in Table 28. For efficient decoding of the instructions, the first
two Bytes of an instruction are the coded cycles and are followed by an instruction Byte or a
confirmation Byte. The coded cycles consist in writing the data AAh to address X555h
during the first cycle and data 55h to address XAAAh during the second cycle unless the
Bypass Instruction feature is used). Address signals A15-A12 are Don’t Care during the
instruction Write cycles. However, the appropriate Sector Select (FS0-FS7 or CSBOOT0CSBOOT3) must be selected.
The primary and secondary Flash memories have the same instruction set (except for Read
Primary Flash Identifier). The Sector Select signals determine which Flash memory is to
receive and execute the instruction. The primary Flash memory is selected if any one of
Sector Select (FS0-FS7) is High, and the secondary Flash memory is selected if any one of
Sector Select (CSBOOT0-CSBOOT3) is High.
7.1
Power-up mode
The PSD internal logic is reset upon Power-up to the Read mode. Sector Select (FS0-FS7
and CSBOOT0-CSBOOT3) must be held Low, and Write Strobe (WR, CNTL0) High, during
Power-up for maximum security of the data contents and to remove the possibility of a byte
being written on the first edge of Write Strobe (WR, CNTL0). Any Write cycle initiation is
locked when VCC is below VLKO.
33/118
Instructions
7.2
PSD835G2V
READ
Under typical conditions, the MCU may read the primary Flash memory or the secondary
Flash memory using Read operations just as it would a ROM or RAM device. Alternately, the
MCU may use Read operations to obtain status information about a Program or Erase cycle
that is currently in progress. Lastly, the MCU may use instructions to read special data from
these memory blocks. The following sections describe these Read functions.
7.3
Read Memory Contents
Primary Flash memory and secondary Flash memory are placed in the Read mode after
Power-up, chip reset, or a Reset Flash instruction (see Table 28). The MCU can read the
memory contents of the primary Flash memory or the secondary Flash memory by using
Read operations any time the Read operation is not part of an instruction.
7.4
Read Primary Flash Identifier
The primary Flash memory identifier is read with an instruction composed of 4 operations: 3
specific Write operations and a Read operation (see Table 28). The identifier for the device
is E8h.
7.5
Read Memory Sector Protection Status
The primary Flash memory Sector Protection Status is read with an instruction composed of
4 operations: 3 specific Write operations and a Read operation (see Table 28). The Read
operation produces 01h if the Flash memory sector is protected, or 00h if the sector is not
protected.
The sector protection status for all NVM blocks (primary Flash memory or secondary Flash
memory) can also be read by the MCU accessing the Flash Protection and Flash Boot
Protection registers in PSD I/O space. See Flash memory sector protect on page 43, for
register definitions.
7.6
Read the Erase/Program Status Bits
The PSD provides several status bits to be used by the MCU to confirm the completion of an
Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU
spends performing these tasks and are defined in Table 29. The status bits can be read as
many times as needed.
For Flash memory, the MCU can perform a Read operation to obtain these status bits while
an Erase or Program instruction is being executed by the embedded algorithm. See
Programming Flash memory on page 37, for details.
34/118
PSD835G2V
Instructions
Table 29.
Functional
Block
Flash
memory
Status bit(1) (2)
FS0-FS7/CSBOOT0CSBOOT3(3)
VIH
DQ7
DQ6
DQ5
Data
Toggle Error
Polling Flag
Flag
DQ4
X
DQ3
DQ2 DQ1 DQ0
Erase
X
Time-out
X
X
1. X = Not guaranteed value, can be read either 1 or 0.
2. DQ7-DQ0 represent the Data Bus bits, D7-D0.
3. FS0-FS7 and CSBOOT0-CSBOOT3 are active High.
7.7
Data polling flag (DQ7)
When erasing or programming in Flash memory, the Data Polling Flag (DQ7) bit outputs the
complement of the bit being entered for programming/writing on the DQ7 bit. Once the
Program instruction or the Write operation is completed, the true logic value is read on the
Data Polling Flag (DQ7) bit (in a Read operation).
7.8
●
Data Polling is effective after the fourth Write pulse (for a Program instruction) or after
the sixth Write pulse (for an Erase instruction). It must be performed at the address
being programmed or at an address within the Flash memory sector being erased.
●
During an Erase cycle, the Data Polling Flag (DQ7) bit outputs a 0. After completion of
the cycle, the Data Polling Flag (DQ7) bit outputs the last bit programmed (it is a 1 after
erasing).
●
If the Byte to be programmed is in a protected Flash memory sector, the instruction is
ignored.
●
If all the Flash memory sectors to be erased are protected, the Data Polling Flag (DQ7)
bit is reset to 0 for about 100 µs, and then returns to the previous addressed byte. No
erasure is performed.
Toggle flag (DQ6)
The PSD offers another way for determining when the Flash memory Program cycle is
completed. During the internal Write operation and when either the FS0-FS7 or CSBOOT0CSBOOT3 is true, the Toggle Flag (DQ6) bit toggles from 0 to 1 and 1 to 0 on subsequent
attempts to read any Byte of the memory.
When the internal cycle is complete, the toggling stops and the data read on the Data Bus
D0-D7 is the addressed memory Byte. The device is now accessible for a new Read or
Write operation. The cycle is finished when two successive Reads yield the same output
data.
●
The Toggle Flag (DQ6) bit is effective after the fourth Write pulse (for a Program
instruction) or after the sixth Write pulse (for an Erase instruction).
●
If the Byte to be programmed belongs to a protected Flash memory sector, the
instruction is ignored.
●
If all the Flash memory sectors selected for erasure are protected, the Toggle Flag
(DQ6) bit toggles to 0 for about 100 µs and then returns to the previous addressed
Byte.
35/118
Instructions
7.9
PSD835G2V
Error flag (DQ5)
During a normal Program or Erase cycle, the Error Flag (DQ5) bit is set to 0. This bit is set to
1 when there is a failure during Flash memory Byte Program, Sector Erase, or Bulk Erase
cycle.
In the case of Flash memory programming, the Error Flag (DQ5) bit indicates the attempt to
program a Flash memory bit from the programmed state, 0, to the erased state, 1, which is
not valid. The Error Flag (DQ5) bit may also indicate a Time-out condition while attempting
to program a Byte.
In case of an error in a Flash memory Sector Erase or Byte Program cycle, the Flash
memory sector in which the error occurred or to which the programmed Byte belongs must
no longer be used. Other Flash memory sectors may still be used. The Error Flag (DQ5) bit
is reset after a Reset Flash instruction.
7.10
Erase time-out flag (DQ3)
The Erase Time-out Flag (DQ3) bit reflects the time-out period allowed between two
consecutive Sector Erase instructions. The Erase Time-out Flag (DQ3) bit is reset to 0 after
a Sector Erase cycle for a time period of 100 µs + 20% unless an additional Sector Erase
instruction is decoded. After this time period, or when the additional Sector Erase instruction
is decoded, the Erase Time-out Flag (DQ3) bit is set to 1.
36/118
PSD835G2V
8
Programming Flash memory
Programming Flash memory
Flash memory must be erased prior to being programmed. The MCU may erase Flash
memory all at once or by-sector. A Flash memory sector is erased to all 1s (FFh), and is
programmed by setting selected bits to 0. Although Flash memory is erased by-sector, it is
programmed Word-by-Word.
The primary and secondary Flash memories require the MCU to send an instruction to
program a Word or to erase sectors (see Table 28. on page 32).
Once the MCU issues a Flash memory Program or Erase instruction, it must check the
status bits for completion. The embedded algorithms that are invoked inside the PSD
support several means to provide status to the MCU. Status may be checked using any of
three methods: Data Polling, Data Toggle, or the Ready/Busy (PE4) output pin.
8.1
Data polling
Polling on the Data Polling Flag (DQ7) bit is a method of checking whether a Program or
Erase cycle is in progress or has completed. Figure 6 shows the Data Polling algorithm.
When the MCU issues a Program instruction, the embedded algorithm within the PSD
begins. The MCU then reads the location of the Word to be programmed in Flash memory to
check status. The Data Polling Flag (DQ7) bit of this location becomes the complement of
b7 of the original data byte to be programmed. The MCU continues to poll this location,
comparing the Data Polling Flag (DQ7) bit and monitoring the Error Flag (DQ5) bit. When
the Data Polling Flag (DQ7) bit matches b7 of the original data, and the Error Flag (DQ5) bit
remains 0, the embedded algorithm is complete. If the Error Flag (DQ5) bit is 1, the MCU
should test the Data Polling Flag (DQ7) bit again since the Data Polling Flag (DQ7) bit may
have changed simultaneously with the Error Flag (DQ5) bit (see Figure 6).
The Error Flag (DQ5) bit is set if either an internal time-out occurred while the embedded
algorithm attempted to program the Byte or if the MCU attempted to program a 1 to a bit that
was not erased (not erased is logic 0).
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed, to compare the Byte that was written to the Flash
memory with the Byte that was intended to be written.
When using the Data Polling method after an Erase cycle, Figure 6 still applies. However,
the Data Polling Flag (DQ7) bit is 0 until the Erase cycle is complete. A 1 on the Error Flag
(DQ5) bit indicates a time-out condition on the Erase cycle; a 0 indicates no error. The MCU
can read any location within the sector being erased to get the Data Polling Flag (DQ7) bit
and the Error Flag (DQ5) bit.
PSDsoft generates ANSI C code functions which implement these Data Polling algorithms.
37/118
Programming Flash memory
Figure 6.
PSD835G2V
Data polling flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
NO
DQ5
=1
YES
READ DQ7
DQ7
=
DATA
YES
NO
FAIL
PASS
AI01369B
38/118
PSD835G2V
8.2
Programming Flash memory
Data toggle
Checking the Toggle Flag (DQ6) bit is a method of determining whether a Program or Erase
cycle is in progress or has completed. Figure 7 shows the Data Toggle algorithm.
When the MCU issues a Program instruction, the embedded algorithm within the PSD
begins. The MCU then reads the location of the byte to be programmed in Flash memory to
check status. The Toggle Flag (DQ6) bit of this location toggles each time the MCU reads
this location until the embedded algorithm is complete. The MCU continues to read this
location, checking the Toggle Flag (DQ6) bit and monitoring the Error Flag (DQ5) bit. When
the Toggle Flag (DQ6) bit stops toggling (two consecutive reads yield the same value), and
the Error Flag (DQ5) bit remains 0, the embedded algorithm is complete. If the Error Flag
(DQ5) bit is 1, the MCU should test the Toggle Flag (DQ6) bit again, since the Toggle Flag
(DQ6) bit may have changed simultaneously with the Error Flag (DQ5) bit (see Figure 7).
The Error Flag (DQ5) bit is set if either an internal time-out occurred while the embedded
algorithm attempted to program the byte, or if the MCU attempted to program a 1 to a bit that
was not erased (not erased is logic 0).
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed, to compare the Byte that was written to Flash
memory with the Byte that was intended to be written.
When using the Data Toggle method after an Erase cycle, Figure 7 still applies. the Toggle
Flag (DQ6) bit toggles until the Erase cycle is complete. A 1 on the Error Flag (DQ5) bit
indicates a time-out condition on the Erase cycle; a 0 indicates no error. The MCU can read
any location within the sector being erased to get the Toggle Flag (DQ6) bit and the Error
Flag (DQ5) bit.
PSDsoft generates ANSI C code functions which implement these Data Toggling algorithms.
8.2.1
Unlock bypass
The Unlock Bypass instructions allow the system to program bytes to the Flash memories
faster than using the standard Program instruction. The Unlock Bypass mode is entered by
first initiating two Unlock cycles. This is followed by a third Write cycle containing the Unlock
Bypass code, 20h (as shown in Table 28. on page 32).
The Flash memory then enters the Unlock Bypass mode. A two-cycle Unlock Bypass
Program instruction is all that is required to program in this mode. The first cycle in this
instruction contains the Unlock Bypass Program code, A0h. The second cycle contains the
program address and data. Additional data is programmed in the same manner. These
instructions dispense with the initial two Unlock cycles required in the standard Program
instruction, resulting in faster total Flash memory programming.
During the Unlock Bypass mode, only the Unlock Bypass Program and Unlock Bypass
Reset Flash instructions are valid.
To exit the Unlock Bypass mode, the system must issue the two-cycle Unlock Bypass Reset
Flash instruction. The first cycle must contain the data 90h; the second cycle, the data 00h.
Addresses are Don’t Care for both cycles. The Flash memory then returns to Read mode.
39/118
Programming Flash memory
Figure 7.
PSD835G2V
Data toggle flowchart
START
READ
DQ5 & DQ6
DQ6
=
TOGGLE
NO
YES
NO
DQ5
=1
YES
READ DQ6
DQ6
=
TOGGLE
NO
YES
FAIL
PASS
AI01370B
40/118
PSD835G2V
9
Erasing Flash memory
9.1
Flash Bulk Erase
Erasing Flash memory
The Flash Bulk Erase instruction uses six Write operations followed by a Read operation of
the status register, as described in Table 28. on page 32. If any byte of the Bulk Erase
instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the Read
Flash memory status.
During a Bulk Erase, the memory status may be checked by reading the Error Flag (DQ5)
bit, the Toggle Flag (DQ6) bit, and the Data Polling Flag (DQ7) bit, as detailed in
Programming Flash memory on page 37. The Error Flag (DQ5) bit returns a 1 if there has
been an Erase Failure (maximum number of Erase cycles has been executed).
It is not necessary to program the memory with 00h because the PSD automatically does
this before erasing to 0FFh.
During execution of the Bulk Erase instruction, the Flash memory does not accept any
instructions.
9.2
Flash Sector Erase
The Sector Erase instruction uses six Write operations, as described in Table 28. on page
32. Additional Flash Sector Erase codes and Flash memory sector addresses can be written
subsequently to erase other Flash memory sectors in parallel, without further coded cycles,
if the additional bytes are transmitted in a shorter time than the time-out period of about 100
µs. The input of a new Sector Erase code restarts the time-out period.
The status of the internal timer can be monitored through the level of the Erase Time-out
Flag (DQ3) bit. If the Erase Time-out Flag (DQ3) bit is 0, the Sector Erase instruction has
been received and the time-out period is counting. If the Erase Time-out Flag (DQ3) bit is 1,
the time-out period has expired and the PSD is busy erasing the Flash memory sector(s).
Before and during Erase time-out, any instruction other than Suspend Sector Erase and
Resume Sector Erase instructions abort the cycle that is currently in progress, and reset the
device to Read mode. It is not necessary to program the Flash memory sector with 00h as
the PSD does this automatically before erasing (Byte=FFh).
During a Sector Erase, the memory status may be checked by reading the Error Flag (DQ5)
bit, the Toggle Flag (DQ6) bit, and the Data Polling Flag (DQ7) bit, as detailed in
Programming Flash memory on page 37.
During execution of the Erase cycle, the Flash memory accepts only Reset and Suspend
Sector Erase instructions. Erasure of one Flash memory sector may be suspended, in order
to read data from another Flash memory sector, and then resumed.
41/118
Erasing Flash memory
9.3
PSD835G2V
Suspend Sector Erase
When a Sector Erase cycle is in progress, the Suspend Sector Erase instruction can be
used to suspend the cycle by writing 0B0h to any even address when an appropriate Sector
Select (FS0-FS7 or CSBOOT0-CSBOOT3) is High. (See Table 28. on page 32). This allows
reading of data from another Flash memory sector after the Erase cycle has been
suspended. Suspend Sector Erase is accepted only during an Erase cycle and defaults to
Read mode. A Suspend Sector Erase instruction executed during an Erase time-out period,
in addition to suspending the Erase cycle, terminates the time out period.
The Toggle Flag (DQ6) bit stops toggling when the PSD internal logic is suspended. The
status of this bit must be monitored at an address within the Flash memory sector being
erased. The Toggle Flag (DQ6) bit stops toggling between 0.1 µs and 15 µs after the
Suspend Sector Erase instruction has been executed. The PSD is then automatically set to
Read mode.
If an Suspend Sector Erase instruction was executed, the following rules apply:
9.4
●
Attempting to read from a Flash memory sector that was being erased outputs invalid
data.
●
Reading from a Flash sector that was not being erased is valid.
●
The Flash memory cannot be programmed, and only responds to Resume Sector
Erase and Reset Flash instructions (Read is an operation and is allowed).
●
If a Reset Flash instruction is received, data in the Flash memory sector that was being
erased is invalid.
Resume Sector Erase
If a Suspend Sector Erase instruction was previously executed, the erase cycle may be
resumed with this instruction. The Resume Sector Erase instruction consists in writing 030h
to any even address while an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3)
is High. (See Table 28. on page 32.)
42/118
PSD835G2V
Specific features
10
Specific features
10.1
Flash memory sector protect
Each primary and secondary Flash memory sector can be separately protected against
Program and Erase cycles. Sector Protection provides additional data security because it
disables all Program or Erase cycles. This mode can be activated through the JTAG/ISP
Port or a Device Programmer.
Sector protection can be selected for each sector using the PSDsoft program. This
automatically protects selected sectors when the device is programmed through the JTAG
Port or a Device Programmer. Flash memory sectors can be unprotected to allow updating
of their contents using the JTAG Port or a Device Programmer. The MCU can read (but
cannot change) the sector protection bits.
Any attempt to program or erase a protected Flash memory sector is ignored by the device.
The Verify operation results in a read of the protected data. The retention of the Protection
status is thus ensured.
The sector protection status can be read by the MCU through the primary and secondary
Flash memory protection registers (in the CSIOP block). See Table 18. on page 26 and
Table 19. on page 27.
10.2
Reset Flash
The Reset Flash instruction consists of one Write cycle (see Table 28. on page 32). It can
also be optionally preceded by the standard two write decoding cycles (writing AAh to AAAh
and 55h to 554h).
It must be executed after:
●
Reading the Flash Protection Status or Flash ID using the Flash instruction.
●
An Error condition has occurred (and the device has set the Error Flag (DQ5) bit to 1)
during a Flash memory Program or Erase cycle.
The Reset Flash instruction puts the Flash memory back into normal Read mode
immediately. If an Error condition has occurred (and the device has set the Error Flag (DQ5)
bit to 1) the Flash memory is put back into normal Read mode within 25 µs of the Reset
Flash instruction having been issued. The Reset Flash instruction is ignored when it is
issued during a Program or Bulk Erase cycle of the Flash memory. The Reset Flash
instruction aborts any on-going Sector Erase cycle, and returns the Flash memory to the
normal Read mode within 25µs.
10.3
Reset (RESET) signal
A pulse on Reset (RESET) aborts any cycle that is in progress, and resets the Flash
memory to the Read mode. When the reset occurs during a Program or Erase cycle, the
Flash memory takes up to 25µs to return to the Read mode. It is recommended that the
Reset (RESET) pulse (except for Power-Up Reset, described in Power-up reset on page 89)
be at least 25µs so that the Flash memory is always ready for the MCU to fetch the
bootstrap instructions after the Reset cycle is complete.
43/118
SRAM
11
PSD835G2V
SRAM
The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select
(RS0) can contain up to three product terms, allowing flexible memory mapping.
The SRAM can be backed up using an external battery. The external battery should be
connected to Voltage Stand-by (VSTBY, PE6). If you have an external battery connected to
the PSD, the contents of the SRAM are retained in the event of a power loss. The contents
of the SRAM are retained so long as the battery voltage remains at 2 V or greater. If the
supply voltage falls below the battery voltage, an internal power switch-over to the battery
occurs.
PE7 can be configured as an output that indicates when power is being drawn from the
external battery. Battery-on Indicator (VBATON, PE7) is High when the supply voltage falls
below the battery voltage and the battery on Voltage Stand-by (VSTBY, PE6) is supplying
power to the internal SRAM.
SRAM Select (RS0), Voltage Stand-by (VSTBY, PC2) and Battery-on Indicator (VBATON,
PC4) are all configured using PSDsoft Express Configuration.
The SRAM Select (RS0), VBATON and VSTBY are all configured using PSDsoft.
44/118
PSD835G2V
12
Sector Select and SRAM Select
Sector Select and SRAM Select
Sector Select (FS0-FS7 for primary Flash memory, CSBOOT0-CSBOOT3 for secondary
Flash memory) and SRAM Select (RS0) are all outputs of the DPLD. They are setup using
PSDsoft. The following rules apply to the equations for these signals:
12.1
1.
Primary Flash memory and secondary Flash memory Sector Select signals must not
be larger than the physical sector size.
2.
Any primary Flash memory sector must not be mapped in the same memory space as
another primary Flash memory sector.
3.
A secondary Flash memory sector must not be mapped in the same memory space as
another secondary Flash memory sector.
4.
SRAM and I/O spaces must not overlap.
5.
A secondary Flash memory sector may overlap a primary Flash memory sector. In
case of overlap, priority is given to the secondary Flash memory sector.
6.
SRAM and I/O spaces may overlap any other memory sector. Priority is given to the
SRAM and I/O.
Example
FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0
always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh
(and less than 9FFFh) automatically addresses secondary Flash memory segment 0. Any
address greater than 9FFFh accesses the primary Flash memory segment 0. You can see
that half of the primary Flash memory segment 0 and one-fourth of secondary Flash
memory segment 0 cannot be accessed in this example. Also note that an equation that
defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid.
Figure 8 shows the priority levels for all memory components. Any component on a higher
level can overlap and has priority over any component on a lower level. Components on the
same level must not overlap. Level one has the highest priority and level 3 has the lowest.
12.2
Memory select configuration for MCUs with separate
program and data spaces
The 80C51 and compatible family of MCUs have separate address spaces for Program
memory (selected using Program Select Enable (PSEN, CNTL2)) and Data memory
(selected using Read Strobe (RD, CNTL1)). Any of the memories within the PSD can reside
in either space or both spaces. This is controlled through manipulation of the VM register
that resides in the CSIOP space.
The VM register is set using PSDsoft to have an initial value. It can subsequently be
changed by the MCU so that memory mapping can be changed on-the-fly.
For example, you may wish to have SRAM and primary Flash memory in the Data space at
Boot-up, and secondary Flash memory in the Program space at Boot-up, and later swap the
primary and secondary Flash memories. This is easily done with the VM register by using
PSDsoft to configure it for Boot-up and having the MCU change it when desired.
Table 24. on page 28 describes the VM Register.
45/118
Sector Select and SRAM Select
Figure 8.
PSD835G2V
Priority level of memory and I/O components
Highest Priority
Level 1
SRAM, I /O, or
Peripheral I /O
Level 2
Secondary
Non-Volatile Memory
Level 3
Primary Flash Memory
Lowest Priority
AI02867D
12.3
Configuration modes for MCUs with separate program and
data spaces
12.3.1
Separate space modes
Program space is separated from Data space. For example, Program Select Enable (PSEN,
CNTL2) is used to access the program code from the primary Flash memory, while Read
Strobe (RD, CNTL1) is used to access data from the secondary Flash memory, SRAM and
I/O Port blocks. This configuration requires the VM register to be set to 0Ch (see Figure 9).
12.3.2
Combined Space Modes
The Program and Data spaces are combined into one memory space that allows the
primary Flash memory, secondary Flash memory, and SRAM to be accessed by either
Program Select Enable (PSEN, CNTL2) or Read Strobe (RD, CNTL1). For example, to
configure the primary Flash memory in Combined space, bits b2 and b4 of the VM register
are set to 1 (see Figure 10).
Figure 9.
8031 memory modules – separate space
DPLD
RS0
Primary
Flash
Memory
Secondary
Flash
Memory
SRAM
CSBOOT0-3
FS0-FS7
CS
CS
OE
CS
OE
OE
PSEN
RD
AI02869C
46/118
PSD835G2V
Sector Select and SRAM Select
Figure 10. 8031 memory modules – combined space
DPLD
RD
RS0
Primary
Flash
Memory
Secondary
Flash
Memory
SRAM
CSBOOT0-3
FS0-FS7
CS
CS
OE
CS
OE
OE
VM REG BIT 3
VM REG BIT 4
PSEN
VM REG BIT 1
VM REG BIT 2
RD
VM REG BIT 0
AI02870C
47/118
Page Register
13
PSD835G2V
Page Register
The 8-bit Page Register increases the addressing capability of the MCU by a factor of up to
256. The contents of the register can also be read by the MCU. The outputs of the Page
Register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the Sector
Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations.
If memory paging is not needed, or if not all 8 page register bits are needed for memory
paging, then these bits may be used in the CPLD for general logic. See Application Note
AN1154.
Figure 11 shows the Page Register. The eight flip-flops in the register are connected to the
internal data bus D0-D7. The MCU can write to or read from the Page Register. The Page
Register can be accessed at address location CSIOP + E0h.
Figure 11. Page Register
RESET
D0
D0 - D7
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
PGR0
INTERNAL
SELECTS
AND LOGIC
PGR1
PGR2
PGR3
PGR4
DPLD
AND
CPLD
PGR5
PGR6
PGR7
R/W
PAGE
REGISTER
48/118
PLD
AI02871B
PSD835G2V
14
Memory ID registers
Memory ID registers
The 8-bit Read-Only Memory Status Registers are included in the CSIOP space. The user
can determine the memory configuration of the PSD device by reading the Memory ID0 and
ID1 Registers. The contents of the registers are defined in Table 25 and Table 26. on page
28.
15
PLDs
The PLDs bring programmable logic functionality to the PSD. After specifying the logic for
the PLDs in PSDsoft, the logic is programmed into the device and available upon Power-up.
The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The
PLDs are briefly discussed in the next few paragraphs, and in more detail in Decode PLD
(DPLD) on page 52, and in Complex PLD (CPLD) on page 53. Figure 12. on page 51 shows
the configuration of the PLDs.
The DPLD performs address decoding for Select signals for internal components, such as
memory, registers, and I/O ports.
The CPLD can be used for logic functions, such as loadable counters and shift registers,
state machines, and encoding and decoding logic. These logic functions can be constructed
using the 16 Output Macrocells (OMC), 24 Input Macrocells (IMC), and the AND Array. The
CPLD can also be used to generate External Chip Select (ECS0-ECS2) signals.
The AND Array is used to form product terms. These product terms are specified using
PSDsoft. An Input Bus consisting of 82 signals is connected to the PLDs. The signals are
shown in Table 30.
15.1
The Turbo Bit in PSD
The PLDs in the PSD can minimize power consumption by switching to standby when inputs
remain unchanged for an extended time of about 70ns. Resetting the Turbo bit to 0 (Bit 3 of
PMMR0) automatically places the PLDs into standby if no inputs are changing. Turning the
Turbo mode off increases propagation delays while reducing power consumption. See
Power management on page 84, on how to set the Turbo bit.
Additionally, five bits are available in PMMR2 to block MCU control signals from entering the
PLDs. This reduces power consumption and can be used only when these MCU control
signals are not used in PLD logic equations.
Each of the two PLDs has unique characteristics suited for its applications. They are
described in the following sections.
49/118
PLDs
PSD835G2V
Table 30.
DPLD and CPLD Inputs
Input Source
Number of Signals
MCU Address Bus(1)
A15-A0
16
MCU Control Signals
CNTL2-CNTL0
3
Reset
RST
1
Power-down
PDN
1
Port A Input Macrocells
PA7-PA0
8
Port B Input Macrocells
PB7-PB0
8
Port C Input Macrocells
PC7-PC0
8
Port D Inputs
PD3-PD0
4
Port F Inputs
PF7-PF0
8
Page Register
PGR7-PGR0
8
Macrocell A Feedback
MCELLA.FB7-FB0
8
Macrocell B Feedback
MCELLB.FB7-FB0
8
Secondary Flash memory Program Status Bit
Ready/Busy
1
1. The address inputs are A19-A4 in 80C51XA mode.
50/118
Input Name
DATA
BUS
16
1
2
1
1
4
8
CPLD
PT
ALLOC.
OUTPUT MACROCELL FEEDBACK
DECODE PLD
24 INPUT MACROCELL
(PORT A,B,C)
INPUT MACROCELL & INPUT PORTS
PORT D AND F INPUTS
24
12
AI02872D
3
8
MCELLB
TO PORT B
EXTERNAL CHIP SELECTS
TO PORT C OR F
8
MCELLA
TO PORT A
DIRECT MACROCELL ACCESS FROM MCU DATA BUS
JTAG SELECT
PERIPHERAL SELECTS
CSIOP SELECT
SRAM SELECT
SECONDARY NON-VOLATILE MEMORY SELECTS
PRIMARY FLASH MEMORY SELECTS
16 OUTPUT
MACROCELL
DIRECT MACROCELL INPUT TO MCU DATA BUS
82
73
PAGE
REGISTER
I/O PORTS
8
PSD835G2V
PLDs
Figure 12. PLD diagram
51/118
PLD INPUT BUS
PLDs
15.2
PSD835G2V
Decode PLD (DPLD)
The DPLD, shown in Figure 13, is used for decoding the address for internal and external
components. The DPLD can be used to generate the following decode signals:
●
8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms
each)
●
4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three
product terms each)
●
1 internal SRAM Select (RS0) signal (three product terms)
●
1 internal CSIOP Select (PSD Configuration Register) signal
●
1 JTAG Select signal (enables JTAG/ISP on Port E)
●
2 internal Peripheral Select signals
(Peripheral I/O mode).
Figure 13. DPLD logic array
(INPUTS)
I /O PORTS (PORT A,B,C,F)
3
CSBOOT 0
3
CSBOOT 1
3
CSBOOT 2
3
CSBOOT 3
3
(32)
3
MCELLA.FB7-FB0 (FEEDBACKS)
(8)
MCELLB.FB7-FB0 (FEEDBACKS)
(8)
PGR0 - PGR7
(8)
3
3
3
A15-A0(1,2)
(16)
3
PD3-PD0 (ALE,CLKIN,CSI)
(4)
PDN (APD OUTPUT)
(1)
3
3
FS0
FS1
FS2
FS3
FS4
8 PRIMARY FLASH
MEMORY SECTOR
SELECTS
FS5
FS6
FS7
CNTRL2-CNTRL0 (READ/WRITE CONTROL SIGNALS) (3)
RESET
(1)
RD_BSY
(1)
3
RS0
CSIOP
SRAM SELECT
I/O DECODER
SELECT
PSEL0
PSEL1
PERIPHERAL I/O
MODE SELECT
JTAGSEL
AI02873E
1. The address inputs are A19-A4 in 80C51XA mode.
2. Additional address lines can be brought into PSD via Port A, B, C, D or F.
52/118
PSD835G2V
15.3
PLDs
Complex PLD (CPLD)
The CPLD can be used to implement system logic functions, such as loadable counters and
shift registers, system mailboxes, handshaking protocols, state machines, and random logic.
The CPLD can also be used to generate three External Chip Select (ECS0-ECS2), routed to
Port D.
Although External Chip Select (ECS0-ECS2) can be produced by any Output Macrocell
(OMC), these three External Chip Select (ECS0-ECS2) on Port D do not consume any
Output Macrocells (OMC).
As shown in Figure 12. on page 51, the CPLD has the following blocks:
●
24 Input Macrocells (IMC)
●
16 Output Macrocells (OMC)
●
Macrocell Allocator
●
Product Term Allocator
●
AND Array capable of generating up to 137 product terms
●
Four I/O Ports.
Each of the blocks are described in the sections that follow.
The Input Macrocells (IMC) and Output Macrocells (OMC) are connected to the PSD
internal data bus and can be directly accessed by the MCU. This enables the MCU software
to load data into the Output Macrocells (OMC) or read data from both the Input and Output
Macrocells (IMC and OMC).
This feature allows efficient implementation of system logic and eliminates the need to
connect the data bus to the AND Array as required in most standard PLD macrocell
architectures.
53/118
PLD INPUT BUS
PLD INPUT BUS
Q
CK
PT INPUT LATCH GATE/CLOCK
CL
D/T/JK FF
SELECT
D/T
MACROCELL FEEDBACK
I/O PORT INPUT
MCU LOAD
MCU DATA IN
PR DI LD
PT OUTPUT ENABLE (OE)
PT CLEAR
CLOCK
SELECT
GLOBAL
CLOCK
PT
CLOCK
POLARITY
SELECT
UP TO 10
PRODUCT TERMS
PRODUCT TERM
ALLOCATOR
PT PRESET
COMB.
/REG
SELECT
MUX
CPLD MACROCELLS
MUX
MACROCELL
OUT TO
MCU
DATA
LOAD
CONTROL
MCU ADDRESS / DATA BUS
D
Q
Q
DIR
REG.
D
INPUT
SELECT
MUX
ALE/AS
G
Q D
Q D
INPUT MACROCELLS
WR
PDR
CPLD OUTPUT
WR
DATA
LATCHED
ADDRESS OUT
I/O PORTS
MUX
54/118
MUX
PRODUCT TERMS
FROM OTHER
MACROCELLS
AI02874b
I/O PIN
PLDs
PSD835G2V
Figure 14. Macrocell and I/O Port
AND ARRAY
PSD835G2V
15.4
PLDs
Output macrocell (OMC)
Eight of the Output Macrocells (OMC) are connected to Port A pins and are named as
McellA0-McellA7. The other eight macrocells are connected to Port B pins and are named
as McellB0-McellB7.
The Output Macrocell (OMC) architecture is shown in Figure 15. on page 57. As shown in
the figure, there are native product terms available from the AND Array, and borrowed
product terms available (if unused) from other Output Macrocells (OMC). The polarity of the
product term is controlled by the XOR gate. The Output Macrocell (OMC) can implement
either sequential logic, using the flip-flop element, or combinatorial logic.
The multiplexer selects between the sequential or combinatorial logic outputs. The
multiplexer output can drive a port pin and has a feedback path to the AND Array inputs.
The flip-flop in the Output Macrocell (OMC) block can be configured as a D, T, JK, or SR
type in the PSDsoft program. The flip-flop’s clock, preset, and clear inputs may be driven
from a product term of the AND Array. Alternatively, CLKIN (PD1) can be used for the clock
input to the flip-flop. The flip-flop is clocked to the rising edge of CLKIN (PD1). The preset
and clear are active High inputs. Each clear input can use up to two product terms.
Table 31.
Output macrocell port and data bit assignments
Output
macrocell
Port
assignment
Native product
terms
Maximum borrowed
product terms
Data bit for loading
or reading
McellA0
Port A0
3
6
D0
McellA1
Port A1
3
6
D1
McellA2
Port A2
3
6
D2
McellA3
Port A3
3
6
D3
McellA4
Port A4
3
6
D4
McellA5
Port A5
3
6
D5
McellA6
Port A6
3
6
D6
McellA7
Port A7
3
6
D7
McellB0
Port B0
4
5
D0
McellB1
Port B1
4
5
D1
McellB2
Port B2
4
5
D2
McellB3
Port B3
4
5
D3
McellB4
Port B4
4
6
D4
McellB5
Port B5
4
6
D5
McellB6
Port B6
4
6
D6
McellB7
Port B7
4
6
D7
55/118
PLDs
15.5
PSD835G2V
Product term allocator
The CPLD has a Product Term Allocator. The PSDsoft uses the Product Term Allocator to
borrow and place product terms from one macrocell to another. The following list
summarizes how product terms are allocated:
●
McellA0-McellA7 all have three native product terms and may borrow up to six more
●
McellB0-McellB3 all have four native product terms and may borrow up to five more
●
McellB4-McellB7 all have four native product terms and may borrow up to six more.
Each macrocell may only borrow product terms from certain other macrocells. Product
terms already in use by one macrocell are not available for another macrocell.
If an equation requires more product terms than are available to it, then “external” product
terms are required that consume other Output Macrocells (OMC). If external product terms
are used, extra delay is added for the equation that required the extra product terms.
This is called product term expansion. PSDsoft performs this expansion as needed.
15.5.1
Loading and reading the output macrocells (OMC)
The Output Macrocells (OMC) block occupies a memory location in the MCU address
space, as defined by the CSIOP block (see I/O ports on page 71). The flip-flops in each of
the 16 Output Macrocells (OMC) can be loaded from the data bus by a MCU. Loading the
Output Macrocells (OMC) with data from the MCU takes priority over internal functions. As
such, the preset, clear, and clock inputs to the flip-flop can be overridden by the MCU. The
ability to load the flip-flops and read them back is useful in such applications as loadable
counters and shift registers, mailboxes, and handshaking protocols.
Data can be loaded to the Output Macrocells (OMC) on the trailing edge of the Write Strobe
(WR, CNTL0) signal.
15.6
The OMC mask register
There is one Mask Register for each of the two groups of eight Output Macrocells (OMC).
The Mask Registers can be used to block the loading of data to individual Output Macrocells
(OMC). The default value for the Mask Registers is 00h, which allows loading of the Output
Macrocells (OMC). When a given bit in a Mask Register is set to a 1, the MCU is blocked
from writing to the associated Output Macrocells (OMC). For example, suppose McellA0McellA3 are being used for a state machine. You would not want a MCU write to McellA to
overwrite the state machine registers. Therefore, you would want to load the Mask Register
for McellA (Mask Macrocell AB) with the value 0Fh.
15.7
The Output Enable of the OMC
The Output Macrocells (OMC) block can be connected to an I/O port pin as a PLD output.
The output enable of each port pin driver is controlled by a single product term from the
AND Array, OR’ed with the Direction Register output. The pin is enabled upon Power-up if
no output enable equation is defined and if the pin is declared as a PLD output in PSDsoft.
If the Output Macrocell (OMC) output is declared as an internal node and not as a port pin
output in the PSDabel file, the port pin can be used for other I/O functions. The internal node
feedback can be routed as an input to the AND Array.
56/118
AND ARRAY
PLD INPUT BUS
CLKIN
PT CLK
PT
PT
PT
PT
ALLOCATOR
PRESET(.PR)
ENABLE (.OE)
PORT INPUT
FEEDBACK (.FB)
MUX
CLEAR (.RE)
POLARITY
SELECT
WR
RD
MACROCELL CS
MASK
REG.
MUX
PROGRAMMABLE
FF (D / T/JK /SR)
CLR
IN
Q
DIN PR
LD
COMB/REG
SELECT
INTERNAL DATA BUS
DIRECTION
REGISTER
INPUT
MACROCELL
PORT
DRIVER
AI02875C
I/O PIN
PSD835G2V
PLDs
Figure 15. CPLD output macrocell
57/118
PLDs
15.8
PSD835G2V
Input macrocells (IMC)
The CPLD has 24 Input Macrocells (IMC), one for each pin on Ports A, B, and C. The
architecture of the Input Macrocells (IMC) is shown in Figure 16. on page 59. The Input
Macrocells (IMC) are individually configurable, and can be used as a latch, register, or to
pass incoming Port signals prior to driving them onto the PLD input bus. The outputs of the
Input Macrocells (IMC) can be read by the MCU through the internal data bus.
The enable for the latch and clock for the register are driven by a multiplexer whose inputs
are a product term from the CPLD AND Array or the MCU Address Strobe (ALE/AS). Each
product term output is used to latch or clock four Input Macrocells (IMC). Port inputs 3-0 can
be controlled by one product term and 7-4 by another.
Configurations for the Input Macrocells (IMC) are specified by PSDsoft. Outputs of the Input
Macrocells (IMC) can be read by the MCU via the IMC buffer. See I/O ports on page 71.
Input Macrocells (IMC) can use Address Strobe (ALE/AS, PD0) to latch address bits higher
than A15. Any latched addresses are routed to the PLDs as inputs.
Input Macrocells (IMC) are particularly useful with handshaking communication applications
where two processors pass data back and forth through a common mailbox. Figure 17. on
page 60 shows a typical configuration where the Master MCU writes to the Port A Data Out
Register. This, in turn, can be read by the Slave MCU via the activation of the “Slave-Read”
output enable product term.
The Slave can also write to the Port A Input Macrocells (IMC) and the Master can then read
the Input Macrocells (IMC) directly.
Note that the “Slave-Read” and “Slave-Wr” signals are product terms that are derived from
the Slave MCU inputs Read Strobe (RD, CNTL1), Write Strobe (WR, CNTL0), and
Slave_CS.
58/118
AND ARRAY
PLD INPUT BUS
FEEDBACK
PT
PT
ENABLE ( .OE )
MUX
OUTPUT
MACROCELLS A
AND
MACROCELLS B
G
D
D
LATCH
Q
D FF
Q
INPUT MACROCELL _ RD
ALE/AS
PT
DIRECTION
REGISTER
INPUT MACROCELL
MUX
INTERNAL DATA BUS
PORT
DRIVER
AI02876C
I/O PIN
PSD835G2V
PLDs
Figure 16. Input macrocell
59/118
PLDs
PSD835G2V
D
MCU -RD
MCU -WR
Q
PORT A
INPUT
MACROCELL
SLAVE – WR
Q
D
D [ 7:0]
MCU - WR
MASTER
MCU
MCU - RD
PSD
CPLD
PORT A
DATA OUT
REGISTER
SLAVE – READ
WR
RD
SLAVE – CS
D [ 7:0]
PORT A
SLAVE
MCU
AI02877C
Figure 17. Handshaking communication using input macrocells
15.9
External chip
The CPLD also provides eight Chip Select outputs that can be used to select external
devices. The Chip Selects can be routed to either Port C or Port F, depending on the pin
declaration in the PSDsoft. Each Chip Select (ECS0-ECS7) consists of one product term
that can be configured active High or Low.
The Output Enable of the pin is controlled by either the Output Enable product term or the
Direction Register (see Figure 18).
60/118
PSD835G2V
PLDs
Figure 18. External Chip Select
CPLD AND ARRAY
PLD INPUT BUS
ENABLE (.OE) PT
DIRECTION
REGISTER
ECS TO
PORT C OR F
ECS PT
PD0 PIN
POLARITY
BIT
PORT C OR PORT F
AI07654
61/118
MCU bus interface
16
PSD835G2V
MCU bus interface
The “no-glue logic” MCU Bus Interface block can be directly connected to most popular
MCUs and their control signals. Key 8-bit MCUs, with their bus types and control signals, are
shown in Table 32. The interface type is specified using the PSDsoft.
Table 32.
MCU
MCUs and their control signals
Data Bus
CNTL0 CNTL1 CNTL2
Width
PC7
PD0(1) ADIO0 PA3-PA0 PA7-PA4
8031/8051
8
WR
RD
PSEN
Note (2) ALE
A0
Note (2)
Note (2)
80C51XA
8
WR
RD
PSEN
Note (2) ALE
A4
A3-A0
Note (2)
80C251
8
WR
PSEN
Note (2) Note (2) ALE
A0
Note (2)
Note (2)
80C251
8
WR
RD
PSEN
Note (2) ALE
A0
Note (2)
Note (2)
80198
8
WR
RD
Note (2) Note (2) ALE
A0
Note (2)
Note (2)
68HC11
8
R/W
E
Note (2) Note (2) AS
A0
Note (2)
Note (2)
68HC05C0
8
WR
RD
Note (2) Note (2) AS
A0
Note (2)
Note (2)
68HC912
8
R/W
E
Note (2) DBE
A0
Note (2)
Note (2)
Z80
8
WR
RD
(Note
Note (2) Note (2) 1
)
A0
D3-D0
D7-D4
Z8
8
R/W
DS
Note (2) Note (2) AS
A0
Note (2)
Note (2)
68330
8
R/W
DS
Note (2) Note (2) AS
A0
Note (2)
Note (2)
M37702M2
8
R/W
E
Note (2) Note (2) ALE
A0
D3-D0
D7-D4
AS
1. ALE/AS input is optional for MCUs with a non-multiplexed bus
2. Unused CNTL2 pin can be configured as PLD input. Other unused pins (PD3-PD0, PA3-PA0) can be
configured for other I/O functions.
16.1
PSD interface to a multiplexed 8-bit bus
Figure 19 shows an example of a system using a MCU with an 8-bit multiplexed bus and a
PSD. The ADIO port on the PSD is connected directly to the MCU address/data bus.
Address Strobe (ALE/AS, PD0) latches the address signals internally. Latched addresses
can be brought out to Port E, For G. The PSD drives the ADIO data bus only when one of its
internal resources is accessed and Read Strobe (RD, CNTL1) is active. Should the system
address bus exceed sixteen bits, Ports A, B, C, or F may be used as additional address
inputs.
62/118
PSD835G2V
MCU bus interface
Figure 19. An example of a typical 8-bit multiplexed bus interface
PSD
MCU
AD7-AD0
A15-A8
ADIO
PORT
WR
WR (CNTRL0)
RD
RD (CNTRL1)
BHE (CNTRL2)
BHE
RST
ALE
A7-A0
PORT
F
(OPTIONAL)
PORT
G
(OPTIONAL)
PORT
A, B
or C
A15-A8
A23-A16
(OPTIONAL)
ALE (PD0)
PORT D
RESET
16.2
AI02878D
PSD interface to a non-multiplexed 8-bit bus
Figure 20 shows an example of a system using a MCU with an 8-bit non-multiplexed bus
and a PSD. The address bus is connected to the ADIO Port, and the data bus is connected
to Port F. Port F is in tri-state mode when the PSD is not accessed by the MCU. Should the
system address bus exceed sixteen bits, Ports A, B or C may be used for additional address
inputs.
16.3
MCU bus interface examples
Figures 21 through Figure 24. on page 70 show examples of the basic connections between
the PSD and some popular MCUs. The PSD Control input pins are labeled as to the MCU
function for which they are configured. The MCU bus interface is specified using the
PSDsoft.
63/118
MCU bus interface
PSD835G2V
Figure 20. An example of a typical 8-bit non-multiplexed bus interface
PSD
MCU
D7-D0
ADIO
PORT
PORT
F
D7-D0
A15-A0
PORT
G
WR
WR (CNTRL0)
RD
RD (CNTRL1)
BHE (CNTRL2)
BHE
RST
ALE
PORT
A, B
or C
A23-A16
(OPTIONAL)
ALE (PD0)
PORT D
RESET
AI02879D
16.4
80C31
Figure 21 shows the bus interface for the 80C31, which has an 8-bit multiplexed
address/data bus. The lower address byte is multiplexed with the data bus. The MCU control
signals Program Select Enable (PSEN, CNTL2), Read Strobe (RD, CNTL1), and Write
Strobe (WR, CNTL0) may be used for accessing the internal memory and I/O Ports blocks.
Address Strobe (ALE/AS, PD0) latches the address.
64/118
PSD835G2V
MCU bus interface
Figure 21. Interfacing the PSD with an 80C31
A15-A8
AD[15:8]
AD7-AD0
AD[ 7:0 ]
VCC
PSD
80C31
19
CRYSTAL
18
9
RESET
12
13
14
15
X1
X2
RESET
INT0
INT1
T0
T1
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
WR
RD
PSEN
10
RXD
11
TXD
ALE/P
VCC VCC VCC
39
38
37
36
35
34
33
32
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
5
6
7
10
11
12
21
22
23
24
25
26
27
28
A8
A9
A10
A11
A12
A13
A14
A15
13
14
15
16
17
18
19
20
16
WR
59
17
RD
60
29
30
31
PSEN
ALE
40
79
80
1
2
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
CNTL0 (WR)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
CNTL1(RD)
CNTL2 (PSEN)
PD0 (ALE)
PD1 (CLKIN)
PD2 (CS)
PD3
EA/VP
39
RESET
RESET
71
72
73
74
75
76
77
78
RESET
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
31
32
33
34
35
36
37
38
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
GND GND GND GND GND
8
30 49 50 70
AI02880D
65/118
MCU bus interface
16.5
PSD835G2V
80C251
The Intel 80C251 MCU features a user-configurable bus interface with four possible bus
configurations, as shown in Table 33.
The first configuration is 80C31 compatible, and the bus interface to the PSD is identical to
that shown in Figure 21. on page 65. The second and third configurations have the same
bus connection as shown in Table 34. on page 67. There is only one Read Strobe (PSEN)
connected to CNTL1 on the PSD. The A16 connection to PA0 allows for a larger address
input to the PSD. The fourth configuration is shown in Figure 22. on page 68. Read Strobe
(RD) is connected to CNTL1 and Program Select Enable (PSEN) is connected to CNTL2.
The 80C251 has two major operating modes: Page mode and Non-page mode. In Nonpage mode, the data is multiplexed with the lower address byte, and Address Strobe
(ALE/AS, PD0) is active in every bus cycle. In Page mode, data (D7-D0) is multiplexed with
address (A15-A8). In a bus cycle where there is a Page hit, Address Strobe (ALE/AS, PD0)
is not active and only addresses (A7-A0) are changing. The PSD supports both modes. In
Page Mode, the PSD bus timing is identical to Non-Page Mode except the address hold time
and setup time with respect to Address Strobe (ALE/AS, PD0) is not required. The PSD
access time is measured from address (A7-A0) valid to data in valid.
Table 33.
80C251 configurations
Configuration 80C251 Read/Write pins Connecting to PSD pins
66/118
Page mode
1
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Non-Page Mode, 80C31
compatible A7-A0 multiplex
with D7-D0
2
WR
PSEN only
CNTL0
CNTL1
Non-Page Mode
A7-A0 multiplex with D7-D0
3
WR
PSEN only
CNTL0
CNTL1
Page Mode
A15-A8 multiplex with D7D0
4
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Page Mode
A15-A8 multiplex with D7D0
PSD835G2V
Table 34.
MCU bus interface
Interfacing the PSD with the 80C251, with one read input
A17-A8
A17
AD[15:8]
AD7-AD0
AD[ 7:0 ]
VCC
U1
2
3
4
5
6
7
8
9
21
CRYSTAL
20
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
X1
X2
PSD
80C31
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
WR
RD/A16
RESET
10
PSEN
43
42
41
40
39
38
37
36
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
5
6
7
10
11
12
VCC VCC VCC
ADIO0(2)
PF0
ADIO1
PF1
ADIO2
PF2
ADIO3
PF3
PF4
ADIO4
PF5
ADIO5
PF6
ADIO6
PF7
ADIO7
24
25
26
27
28
29
30
31
A8
A9
A10
A11
A12
A13
A14
A15
13
14
15
16
17
18
19
20
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
WR
59
CNTL0 (WR)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
18
19
32
A16
RD
ALE
RESET
ALE
33
35
60
40
CNTL1(RD)
CNTL2 (PSEN)
79
80
1
2
PD0 (ALE)
PD1 (CLKIN)
PD2 (CS)
PD3
EA
39
RESET
RESET
71
72
73
74
75
76
77
78
RESET
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
31
32
33
34
35
36
37
38
A16(1)
A17
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
GND GND GND GND GND
8
30 49 50 70
AI02881D
1. The A16 and A17 connections are optional.
2. In non-Page-Mode, AD7-AD0 connects to ADIO7-ADIO0.
67/118
MCU bus interface
PSD835G2V
Figure 22. Interfacing the PSD with the 80C251, with RD and PSEN Inputs
A15-A8
AD[15:8]
AD7-AD0
AD[ 7:0 ]
VCC
PSD
80C31
2
3
4
5
6
7
8
9
21
CRYSTAL
20
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
X1
X2
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
WR
RD/A16
RESET
10
PSEN
RESET
ALE
35
43
42
41
40
39
38
37
36
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
5
6
7
10
11
12
VCC VCC VCC
ADIO0(2)
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
24
25
26
27
28
29
30
31
A8
A9
A10
A11
A12
A13
A14
A15
13
14
15
16
17
18
19
20
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
18
WR
59
19
CNTL0 (WR)
RD
60
32
PSEN
40
CNTL1(RD)
CNTL2 (PSEN)
33
ALE
79
80
1
2
PD0 (ALE)
PD1 (CLKIN)
PD2 (CS)
PD3
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
EA
39
RESET
RESET
71
72
73
74
75
76
77
78
RESET
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
31
32
33
34
35
36
37
38
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
GND GND GND GND GND
8
30 49 50 70
AI02882D
68/118
PSD835G2V
16.6
MCU bus interface
80C51XA
The Philips 80C51XA MCU family supports an 8- or 16-bit multiplexed bus that can have
burst cycles. Address bits (A3-A0) are not multiplexed, while (A19-A4) are multiplexed with
data bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4) are multiplexed with data bits
(D7-D0).
The 80C51XA can be configured to operate in eight-bit data mode (as shown in Figure 23).
The 80C51XA improves bus throughput and performance by executing burst cycles for code
fetches. In Burst Mode, address A19-A4 are latched internally by the PSD, while the
80C51XA changes the A3-A0 signals to fetch up to 16 bytes of code. The PSD access time
is then measured from address A3-A0 valid to data in valid. The PSD bus timing
requirement in Burst Mode is identical to the normal bus cycle, except the address setup
and hold time with respect to Address Strobe (ALE/AS, PD0) does not apply.
Figure 23. Interfacing the PSD with the 80C51X, 8-bit data bus
A[19:12] D[7:0]
A[3:0 ]
VCC
PSD
80C31
21
CRYSTAL
20
11
13
6
7
9
8
16
RESET
VCC
10
14
15
35
XTAL1
XTAL2
RXD0
TXD0
RXD1
TXD1
T2EX
T2
T0
RESET
INT0
INT1
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12D8
A13D9
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
A3
A2
A1
A0/WRH
WRL
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
5
6
7
10
11
12
24
25
26
27
28
29
30
31
A8
A9
A10
A11
A12
A13
A14
A15
13
14
15
16
17
18
19
20
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
WR
59
CNTL0 (WR)
60
40
CNTL1(RD)
CNTL2 (PSEN)
79
80
1
2
PD0 (ALE)
PD1 (CLKIN)
PD2 (CS)
PD3
5
4
3
2
18
A3
A2
A1
A0
RD
19
RD
EA/WAIT
PSEN
ALE
32
33
PSEN
ALE
39
RESET
RESET
9
29 69
VCC VCC VCC
ADIO0(2)
PF0
ADIO1
PF1
ADIO2
PF2
ADIO3
PF3
PF4
ADIO4
PF5
ADIO5
PF6
ADIO6
PF7
ADIO7
43
42
41
40
39
38
37
36
71
72
73
74
75
76
77
78
RESET
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
31
32
33
34
35
36
37
38
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
GND GND GND GND GND
8
30 49 50 70
AI02883D
69/118
MCU bus interface
16.7
PSD835G2V
68HC11
Figure 24 shows a bus interface to a 68HC11 where the PSD is configured in 8-bit
multiplexed mode with E and R/W settings. The DPLD can be used to generate the READ
and WR signals for external devices.
Figure 24. Interfacing the PSD with a 68HC11
A15-A8
A[15:8]
AD7-AD0
A[3:0 ]
VCC
PSD
80C31
34
33
32
31
30
29
28
27
8
CRYSTAL
7
19
18
20
21
22
23
24
25
43
44
45
46
47
48
49
50
52
51
2
3
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
XT
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
EX
IRQ
XIRQ
PD0
PD1
PD2
PD3
PD4
PD5
R/W
E
AS
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
5
6
7
10
11
12
42
41
40
39
38
37
36
35
A8
A9
A10
A11
A12
A13
A14
A15
13
14
15
16
17
18
19
20
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
6
R/W
E
59
CNTL0 (R/W)
60
CNTL1(RD)
40
CNTL2 (E)
79
80
1
2
PD0 (AS)
PD1 (CLKIN)
PD2 (CS)
PD3
5
4
AS
RESET
RESET
VRH
VRL
MODB
MODA
RESET
RESET
9
29 69
VCC VCC VCC
ADIO0(2)
PF0
ADIO1
PF1
ADIO2
PF2
ADIO3
PF3
PF4
ADIO4
PF5
ADIO5
PF6
ADIO6
PF7
ADIO7
9
10
11
12
13
14
15
16
39
71
72
73
74
75
76
77
78
RESET
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
31
32
33
34
35
36
37
38
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
GND GND GND GND GND
8
30 49 50 70
AI02884D
70/118
PSD835G2V
17
I/O ports
I/O ports
There are seven programmable I/O ports: Ports A, B, C, D, E and F. Each of the ports is
eight bits except for Port D, which is 4 bits. Each port pin is individually user-configurable,
thus allowing multiple functions per port. The ports are configured using PSDsoft or by the
MCU writing to on-chip registers in the CSIOP space.
The topics discussed in this section are:
17.1
●
General Port architecture
●
Port operating modes
●
Port Configuration Registers (PCR)
●
Port Data Registers
●
Individual Port functionality.
General port architecture
The general architecture of the I/O Port block is shown in Figure 25. on page 72. Individual
Port architectures are shown in Figure 27. on page 80 to Figure 29. on page 83. In general,
once the purpose for a port pin has been defined, that pin is no longer available for other
purposes. Exceptions are noted.
As shown in Figure 25. on page 72, the ports contain an output multiplexer whose select
signals are driven by the configuration bits in the Control Registers (Ports E, F and G only)
and PSDsoft Configuration. Inputs to the multiplexer include the following:
●
Output data from the Data Out register
●
Latched address outputs
●
CPLD macrocell output
●
External Chip Select (ECS0-ECS2) from the CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be
read. The Port Data Buffer (PDB) is connected to the Internal Data Bus for feedback and
can be read by the MCU. The Data Out and macrocell outputs, Direction and Control
Registers, and port pin input are all connected to the Port Data Buffer (PDB).
The Port pin’s tri-state output driver enable is controlled by a two input OR gate whose
inputs come from the CPLD AND Array enable product term and the Direction Register. If
the enable product term of any of the Array outputs is not defined and that port pin is not
defined as a CPLD output in the PSDabel file, then the Direction Register has sole control of
the buffer that drives the port pin.
The contents of these registers can be altered by the MCU. The Port Data Buffer (PDB)
feedback path allows the MCU to check the contents of the registers.
Ports A, B, and C have embedded Input Macrocells (IMC). The Input Macrocells (IMC) can
be configured as latches, registers, or direct inputs to the PLDs. The latches and registers
are clocked by Address Strobe (ALE/AS, PD0) or a product term from the PLD AND Array.
The outputs from the Input Macrocells (IMC) drive the PLD input bus and can be read by the
MCU. See Input macrocell on page 59.
71/118
I/O ports
17.2
PSD835G2V
Port operating modes
The I/O Ports have several modes of operation. Some modes can be defined using
PSDabel, some by the MCU writing to the Registers in CSIOP space, and some by both.
The modes that can only be defined using PSDsoft must be programmed into the device
and cannot be changed unless the device is reprogrammed. The modes that can be
changed by the MCU can be done so dynamically at run-time. The PLD I/O, Data Port,
Address Input, Peripheral I/O and MCU Reset modes are the only modes that must be
defined before programming the device. All other modes can be changed by the MCU at
run-time.
Table 35. on page 74 summarizes which modes are available on each port. Table 38. on
page 77 shows how and where the different modes are configured. Each of the port
operating modes are described in the following sections.
Figure 25. General I/O port architecture
DATA OUT
REG.
D
Q
D
Q
DATA OUT
WR
ADDRESS
ALE
ADDRESS
PORT PIN
OUTPUT
MUX
G
MACROCELL OUTPUTS
EXT CS
INTERNAL DATA BUS
READ MUX
P
OUTPUT
SELECT
D
DATA IN
B
CONTROL REG.
D
Q
ENABLE OUT
WR
DIR REG.
D
Q
WR
ENABLE PRODUCT TERM (.OE)
INPUT
MACROCELL
CPLD-INPUT
AI02885
72/118
PSD835G2V
17.3
I/O ports
MCU I/O mode
In the MCU I/O mode, the MCU uses the I/O Ports block to expand its own I/O ports. By
setting up the CSIOP space, the ports on the PSD are mapped into the MCU address
space. The addresses of the ports are listed in Table 5. on page 23.
A port pin can be put into MCU I/O mode by writing a 0 to the corresponding bit in the
Control Register (Ports E, F and G). The MCU I/O direction may be changed by writing to
the corresponding bit in the Direction Register, or by the output enable product term. See
Direction Register on page 77. When the pin is configured as an output, the content of the
Data Out Register drives the pin. When configured as an input, the MCU can read the port
input through the Data In buffer. See Figure 25. on page 72.
Ports A, B and C do not have Control Registers, and are in MCU I/O mode by default. They
can be used for PLD I/O if they are specified in PSDsoft.
17.4
PLD I/O mode
The PLD I/O Mode uses a port as an input to the CPLD’s Input Macrocells (IMC), and/or as
an output from the CPLD’s Output Macrocells (OMC). The output can be tri-stated with a
control signal. This output enable control signal can be defined by a product term from the
PLD, or by resetting the corresponding bit in the Direction Register to 0. The corresponding
bit in the Direction Register must not be set to 1 if the pin is defined as a PLD input pin in
PSDsoft. The PLD I/O mode is specified in PSDsoft by declaring the port pins, and then
specifying an equation in PSDsoft.
17.5
Address out mode
For MCUs with a multiplexed address/data bus, Address Out Mode can be used to drive
latched addresses on to the port pins. These port pins can, in turn, drive external devices.
Either the output enable or the corresponding bits of both the Direction Register and Control
Register must be set to a 1 for pins to use Address Out Mode. This must be done by the
MCU at run-time. See Table 37. on page 75 for the address output pin assignments on Ports
E, F and G for various MCUs.
Note: Do not drive address signals with Address Out Mode to an external memory device if
it is intended for the MCU to Boot from the external device. The MCU must first Boot from
PSD memory so the Direction and Control register bits can be set.
73/118
I/O ports
PSD835G2V
Table 35.
Port operating modes
Port Mode
Port A
Port B
Port C
Port D
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
No
Yes
No
Yes
No
No
Yes
Yes
No
No
No
Yes
No
No
No
No
No
No
Yes
Yes
No
No
No
No
Address Out
No
No
No
No
Yes (A7-A0) Yes (A7-A0)
Yes (A7-A0)
or (A15-A8)
Address In
Yes
Yes
Yes
Yes
No
Yes
No
Data Port
No
No
No
No
No
Yes
No
Peripheral I/O
No
No
No
No
No
Yes
No
No
No
MCU I/O
PLD I/O
McellA Outputs
McellB Outputs
Additional Ext. CS
Outputs
PLD Inputs
JTAG ISP
No
No
No
Port E
1
No
Yes
Port F
Port G
1. Can be multiplexed with other I/O functions.
Table 36.
Port operating mode settings
Mode
Defined in PSDsoft
Control
Register
Setting
Direction
Register
Setting
1 = output,
0 (Note 4) 0 = input
(Note 2)
VM
Register
Setting
JTAG Enable
N/A
N/A
(Note 2)
N/A
N/A
Selected for MCU with
N/A
non-mux bus
N/A
N/A
N/A
Address Out
(Port E, F, G)
Declare pins only
1
1 (Note 2)
N/A
N/A
Address In
(Port A,B,C,D, F)
Declare pins or logic
equations for Input
Macrocells
N/A
N/A
N/A
N/A
Peripheral I/O
(Port F)
Logic equations
(PSEL0 & 1)
N/A
N/A
PIO bit = 1 N/A
N/A
N/A
N/A
MCU I/O
Declare pins only
PLD I/O
Declare pins and logic
N/A
equations
Data Port (Port F)
JTAG ISP (Note 3) Declare pins only
JTAG_Enable
1. N/A = Not Applicable
2. The direction of the Port A,B,C, and F pins are controlled by the Direction Register OR’ed with the
individual output enable product term (.oe) from the CPLD AND Array.
3. Any of these three methods enables the JTAG pins on Port E.
4. Control Register setting is not applicable to Ports A, B and C.
74/118
PSD835G2V
I/O ports
Table 37.
I/O port latched address output assignments(1)
MCU
Port E
Port E
Port F
Port F
(PE3-PE0) (PE7-PE4) (PF3-PF0) (PF7-PF4)
Port G
Port G
(PG3-PG0)
(PG7-PG4)
8051XA
N/A
Address
(A7-A4)
N/A
Address
(A7-A4)
Address
(A11-A8)
Address
(A15-A12)
80C251
(Page Mode)
N/A
N/A
N/A
N/A
Address
(A11-A8)
Address
(A7-A4)
All Other
8-Bit Multiplexed
Address
(A3-A0)
Address
(A7-A4)
Address
(A3-A0)
Address
(A7-A4)
Address
(A3-A0)
Address
(A7-A4)
8-Bit
Non-Multiplexed Bus
N/A
N/A
N/A
N/A
Address
(A3-A0)
Address
(A7-A4)
1. N/A = Not Applicable.
17.6
Address In mode
For MCUs that have more than 16 address signals, the higher addresses can be connected
to Port A, B, C, D or F and are routed as inputs to the PLDs. The address input can be
latched in the Input Macrocell (IMC) by Address Strobe (ALE/AS, PD0). Any input that is
included in the DPLD equations for the SRAM, or primary or secondary Flash memory is
considered to be an address input.
17.7
Data Port mode
Port F can be used as a data bus port for an MCU with a non-multiplexed address/data bus.
The Data Port is connected to the data bus of the MCU. The general I/O functions are
disabled in Port F if the port is configured as a Data Port. Data Port Mode is automatically
configured in PSDsoft when a non-multiplexed bus MCU is selected.
17.8
Peripheral I/O mode
Peripheral I/O mode can be used to interface with external 8-bit peripherals. In this mode, all
of Port F serves as a tri-state, bidirectional data buffer for the MCU. Peripheral I/O Mode is
enabled by setting Bit 7 of the VM Register to a 1. Figure 26 shows how Port A acts as a
bidirectional buffer for the MCU data bus if Peripheral I/O Mode is enabled. An equation for
PSEL0 and/or PSEL1 must be written in PSDsoft. The buffer is tri-stated when PSEL0 or
PSEL1 is not active.
75/118
I/O ports
PSD835G2V
Figure 26. Peripheral I/O mode
RD
PSEL0
PSEL
PSEL1
VM REGISTER BIT 7
D0 - D7
DATA BUS
PF0 - PF7
WR
AI02886b
17.9
JTAG in-system programming (ISP)
Port E is JTAG compliant, and can be used for In-System Programming (ISP). You can
multiplex JTAG operations with other functions on Port E because In-System Programming
(ISP) is not performed in normal Operating mode. For more information on the JTAG Port,
see Programming in-circuit using the JTAG/ISP interface on page 91.
17.10
Port Configuration Registers (PCR)
Each Port has a set of Port Configuration Registers (PCR) used for configuration. The
contents of the registers can be accessed by the MCU through normal read/write bus cycles
at the addresses given in Table 5. on page 23. The addresses in Table 5 are the offsets in
hexadecimal from the base of the CSIOP register.
The pins of a port are individually configurable and each bit in the register controls its
respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three Port
Configuration Registers (PCR), shown in Table 38, are used for setting the Port
configurations. The default Power-up state for each register in Table 38 is 00h.
17.11
Control Register
Any bit reset to 0 in the Control Register sets the corresponding port pin to MCU I/O Mode,
and a 1 sets it to Address Out Mode. The default mode is MCU I/O. Only Ports E, F and G
have an associated Control Register.
76/118
PSD835G2V
17.12
I/O ports
Direction Register
The Direction Register, in conjunction with the output enable (except for Port D), controls the
direction of data flow in the I/O Ports. Any bit set to 1 in the Direction Register causes the
corresponding pin to be an output, and any bit set to 0 causes it to be an input. The default
mode for all port pins is input.
Figure 27. on page 80 and Figure 28. on page 81 show the Port Architecture diagrams for
Ports A/B/C and E/F/G, respectively. The direction of data flow for Ports A, B, C and F are
controlled not only by the direction register, but also by the output enable product term from
the PLD AND Array. If the output enable product term is not active, the Direction Register
has sole control of a given pin’s direction.
An example of a configuration for a Port with the three least significant bits set to output and
the remainder set to input is shown in Table 41. Since Port D only contains four pins (shown
in Figure 28. on page 81), the Direction Register for Port D has only the four least significant
bits active.
17.13
Drive Select Register
The Drive Select Register configures the pin driver as Open Drain or CMOS for some port
pins, and controls the slew rate for the other port pins. An external pull-up resistor should be
used for pins configured as Open Drain.
A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is
set to a 1. The default pin drive is CMOS.
Note that the slew rate is a measurement of the rise and fall times of an output. A higher
slew rate means a faster output response and may create more electrical noise. A pin
operates at a high slew rate when the corresponding bit in the Drive Register is set to 1. The
default rate is slow slew.
Table 42. on page 78 shows the Drive Register for Ports A, B, C, D, E and F. It summarizes
which pins can be configured as Open Drain outputs and which pins the slew rate can be set
for.
Table 38.
Port Configuration Registers (PCR)
Register name
Control
Direction
Drive Select
1
Port
MCU access
E, F, G
Write/Read
A,B,C,D, E, F, G
Write/Read
A,B,C,D, E, F, G
Write/Read
1. See Table 42. on page 78 for Drive Register bit definition.
77/118
I/O ports
PSD835G2V
Table 39.
Table 40.
Port pin direction control, Output Enable P.T. not defined
Direction Register bit
Port Pin mode
0
Input
1
Output
Port pin direction control, Output Enable P.T. defined
Direction Register Bit
Output Enable P.T.
Port Pin Mode
0
0
Input
0
1
Output
1
0
Output
1
1
Output
Table 41.
Port direction assignment example
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
1
1
Table 42.
Drive
Register
Drive Register pin assignment(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port A
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port B
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port C
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port D
NA
NA
NA
NA
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port E
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port F
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port G
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
1. NA = Not Applicable.
17.14
Port Data Registers
The Port Data Registers, shown in Table 43, are used by the MCU to write data to or read
data from the ports. Table 43 shows the register name, the ports having each register type,
and MCU access for each register type. The registers are described below.
78/118
PSD835G2V
17.15
I/O ports
Data In
Port pins are connected directly to the Data In buffer. In MCU I/O input mode, the pin input is
read through the Data In buffer.
17.16
Data Out Register
Stores output data written by the MCU in the MCU I/O output mode. The contents of the
Register are driven out to the pins if the Direction Register or the output enable product term
is set to 1. The contents of the register can also be read back by the MCU.
17.17
Output macrocells (OMC)
The CPLD Output Macrocells (OMC) occupy a location in the MCU’s address space. The
MCU can read the output of the Output Macrocells (OMC). If the OMC Mask Register bits
are not set, writing to the macrocell loads data to the macrocell flip-flops. See PLDs on
page 49 for more information.
17.18
OMC Mask Register
Each OMC Mask Register bit corresponds to an Output Macrocell (OMC) flip-flop. When the
OMC Mask Register bit is set to a 1, loading data into the Output Macrocell (OMC) flip-flop
is blocked. The default value is 0 or unblocked.
Table 43.
Port Data Registers
Register name
17.19
Port
MCU access
Data In
A, B, C, D, E, F, G Read – input on pin
Data Out
A, B, C, D, E, F, G Write/Read
Output Macrocell
A, B
Read – outputs of macrocells
Write – loading macrocell flip-flops
Mask Macrocell
A, B
Write/Read – prevents loading into a given macrocell
Input Macrocell
A, B, C
Read – outputs of the Input Macrocells
Enable Out
A, B, C, F
Read – the output enable control of the port driver
Input macrocells (IMC)
The Input Macrocells (IMC) can be used to latch or store external inputs. The outputs of the
Input Macrocells (IMC) are routed to the PLD input bus, and can be read by the MCU. See
PLDs on page 49.
79/118
I/O ports
17.20
PSD835G2V
Enable Out
The Enable Out register can be read by the MCU. It contains the output enable values for a
given port. A ‘1’ indicates the driver is in output mode. A ‘0’ indicates the driver is in tri-state
and the pin is in input mode.
17.21
Ports A,B and C – Functionality and Structure
Ports A and B have similar functionality and structure, as shown in Figure 27.
The two ports can be configured to perform one or more of the following functions:
●
MCU I/O Mode
●
CPLD Output – Macrocells McellA7-McellA0 can be connected to Port A, McellB7McellB0 can be connected to Port B, External Chip Select ECS7-ECS0 can be
connected to Port C.
●
CPLD Input – Via the Input Macrocells (IMC).
●
Address In – Additional high address inputs using the Input Macrocells (IMC).
●
Open Drain/Slew Rate – pins PC7-PC0 can be configured to fast slew rate, pins PA7PA0 and PB7-PB0 can be configured to Open Drain Mode.
Figure 27. Port A, B and C structure
DATA OUT
REG.
D
DATA OUT
Q
WR
PORT PIN
OUTPUT
MUX
MCELLA7-MCELLA0 (PORT A)
MCELLB7-MCELLB0 (PORT B)
EXT.CS (PORT C)
INTERNAL DATA BUS
READ MUX
P
OUTPUT
SELECT
D
DATA IN
B
ENABLE OUT
DIR REG.
D
Q
WR
ENABLE PRODUCT TERM (.OE)
INPUT
MACROCELL
CPLD-INPUT
AI02887b
80/118
PSD835G2V
17.22
I/O ports
Port D – functionality and structure
Port D has four I/O pins. It can be configured to program one or more of the following
functions (see Figure 28):
●
MCU I/O Mode
●
CPLD Input – direct input to CPLD, no Input Macrocell (IMC).
Port D pins can be configured in PSDsoft as input pins for other dedicated functions:
●
PD0 – ALE, as Address Strobe input.
●
PD1 – CLKIN, as Clock input to the Macrocell flip-flops and APD counter.
●
PD2 – CSI, as active Low Chip Select input. A High input will disable the Flash/SRAM
memories and the CSIOP.
●
PD3 – as DBE input from 68HC912.
Figure 28. Port D structure
DATA OUT
REG.
D
Q
DATA OUT
WR
PORT D PIN
OUTPUT
MUX
INTERNAL DATA BUS
READ MUX
P
OUTPUT
SELECT
D
DATA IN
B
DIR REG.
D
WR
Q
CPLD - INPUT
AI02888C
81/118
I/O ports
17.23
PSD835G2V
Port E – functionality and structure
Port E can be configured to perform one or more of the following functions:
17.24
●
MCU I/O Mode
●
In-System Programming – JTAG port can be enabled for programming/erase of the
PSD device. Refer to Programming in-circuit using the JTAG/ISP interface on page 91
for more information.
●
Open Drain – Port E pins can be configured in Open Drain Mode.
●
Battery Backup features – PE6 can be configured as a Battery Input (VSTBY) pin. PE7
can be configured as a Battery On Indicator output pin, indicating when VCC is less
than VBAT.
●
Latched Address Output – Provided latched address (A7-A0) output.
Port F – functionality and structure
Port F can be configured to perform one or more of the following functions:
17.25
●
MCU I/O Mode
●
CPLD Output – External Chip Select ECS7-ECS0 can be connected to Port F (or Port
C).
●
CPLD Input – as direct input of the CPLD array.
●
Address In – addition high address inputs. Direct input to the CPLD array, no Input
Macrocell (IMC) latching is available.
●
Latched Address Out – Provide latched address out per Table 47. on page 90.
●
Slew Rate – pins can be set up for fast slew rate.
●
Data Port – connected to D7-D0 when Port F is configured as Data Port for a nonmultiplexed bus.
●
Peripheral I/O Mode.
Port G – functionality and structure
Port G can be configured to perform one or more of the following functions:
82/118
●
MCU I/O Mode
●
Latched Address Out – Provide latched address out per Table 47. on page 90.
●
Open Drain – pins can be configured in Open Drain Mode.
PSD835G2V
I/O ports
Figure 29. Port E, F, G structure
DATA OUT
REG.
D
Q
D
Q
DATA OUT
WR
ADDRESS
ALE
PORT
E, F OR G PIN
ADDRESS
A7-A0 OR A15-A8
G
OUTPUT
MUX
EXT.CS (PORT F)
INTERNAL DATA BUS
READ MUX
P
OUTPUT
SELECT
D
DATA IN
B
CONTROL REG.
D
ENABLE OUT
Q
WR
DIR REG.
D
Q
WR
ENABLE PRODUCT TERM (.OE)
CPLD - INPUT
ISP OR BATTERY BACK-UP (PORT E)
CONFIGURATION
BIT
AI02889b
83/118
Power management
18
PSD835G2V
Power management
The PSD835G2 offers configurable power saving options. These options may be used
individually or in combinations, as follows:
●
All memory blocks in a PSD (primary and secondary Flash memory, and SRAM) are
built with Power Management technology. In addition to using special silicon design
methodology, power management technology puts the memories into standby mode
when address/data inputs are not changing (zero DC current). As soon as a transition
occurs on an input, the affected memory “wakes up”, changes and latches its outputs,
then goes back to standby. The designer does not have to do anything special to
achieve memory standby mode when no inputs are changing—it happens
automatically.
The PLD sections can also achieve Stand-by mode when its inputs are not changing,
as described in the sections on the Power Management Mode Registers (PMMR).
●
As with the Power Management mode, the Automatic Power Down (APD) unit allows
the PSD to reduce to standby current automatically. The APD Unit can also block MCU
address/data signals from reaching the memories and PLDs. This feature is available
on all the devices of the PSD family. The APD Unit is described in more detail in
Automatic Power-down (APD) unit and Power-down mode on page 85.
Built-in logic monitors the Address Strobe of the MCU for activity. If there is no activity
for a certain time period (MCU is asleep), the APD Unit initiates Power-down mode (if
enabled). Once in Power-down mode, all address/data signals are blocked from
reaching PSD memory and PLDs, and the memories are deselected internally. This
allows the memory and PLDs to remain in standby mode even if the address/data
signals are changing state externally (noise, other devices on the MCU bus, etc.). Keep
in mind that any unblocked PLD input signals that are changing states keep the PLD
out of Stand-by mode, but not the memories.
●
PSD Chip Select Input (CSI, PD2) can be used to disable the internal memories,
placing them in standby mode even if inputs are changing. This feature does not block
any internal signals or disable the PLDs. This is a good alternative to using the APD
Unit. There is a slight penalty in memory access time when PSD Chip Select Input
(CSI, PD2) makes its initial transition from deselected to selected.
●
The PMMRs can be written by the MCU at run-time to manage power. All PSD devices
support “blocking bits” in these registers that are set to block designated signals from
reaching both PLDs. Current consumption of the PLDs is directly related to the
composite frequency of the changes on their inputs (see Figure 33. on page 93).
Significant power savings can be achieved by blocking signals that are not used in PLD
logic equations at run-time. PSDsoft creates a fuse map that automatically blocks the
low address Byte (A7-A0) or the Control signals (CNTL0-CNTL2, ALE and WRH/DBE)
if none of these signals are used in PLD logic equations.
PSD devices have a Turbo bit in PMMR0. This bit can be set to turn the Turbo mode off
(the default is with Turbo mode turned on). While Turbo mode is off, the PLDs can
achieve standby current when no PLD inputs are changing (zero DC current). Even
when inputs do change, significant power can be saved at lower frequencies (AC
current), compared to when Turbo mode is on. When the Turbo mode is on, there is a
significant DC current component and the AC component is higher.
84/118
PSD835G2V
18.1
Power management
Automatic Power-down (APD) unit and Power-down mode
The APD Unit, shown in Figure 30, puts the PSD into Power-down mode by monitoring the
activity of Address Strobe (ALE/AS, PD0). If the APD Unit is enabled, as soon as activity on
Address Strobe (ALE/AS, PD0) stops, a four bit counter starts counting. If Address Strobe
(ALE/AS, PD0) remains inactive for fifteen clock periods of CLKIN (PD1), Power-down
(PDN) goes High, and the PSD enters Power-down mode, as discussed next.
18.1.1
Power-down mode
By default, if you enable the APD Unit, Power-down mode is automatically enabled. The
device enters Power-down mode if Address Strobe (ALE/AS, PD0) remains inactive for
fifteen periods of CLKIN (PD1).
The following should be kept in mind when the PSD is in Power-down mode:
●
If Address Strobe (ALE/AS, PD0) starts pulsing again, the PSD returns to normal
Operating mode. The PSD also returns to normal Operating mode if either PSD Chip
Select Input (CSI, PD2) is Low or the Reset (RESET) input is High.
●
The MCU address/data bus is blocked from all memories and PLDs.
●
Various signals can be blocked (prior to Power-down mode) from entering the PLDs by
setting the appropriate bits in the PMMR registers. The blocked signals include MCU
control signals and the common CLKIN (PD1). Note that blocking CLKIN (PD1) from
the PLDs does not block CLKIN (PD1) from the APD Unit.
●
All PSD memories enter Standby mode and are drawing standby current. However, the
PLD and I/O ports blocks do not go into Standby Mode because you don’t want to have
to wait for the logic and I/O to “wake-up” before their outputs can change. See Table 44
for Power-down mode effects on PSD ports.
●
Typical standby current is of the order of microamperes. These standby current values
assume that there are no transitions on any PLD input.
Table 44.
Power-down mode’s effect on ports
Port function
Pin level
MCU I/O
No Change
PLD Out
No Change
Address Out
Undefined
Data Port
Tri-State
Peripheral I/O
Tri-State
85/118
Power management
PSD835G2V
Figure 30. APD unit
APD EN
PMMR0 BIT 1=1
TRANSITION
DETECTION
DISABLE BUS
INTERFACE
ALE
CLR
SECONDARY FLASH SELECT
APD
COUNTER
RESET
PRIMARY FLASH SELECT
EDGE
DETECT
CSI
PD
PD
PLD
CLKIN
SRAM SELECT
POWER DOWN
(PDN) SELECT
DISABLE PRIMARY AND
SECONDARY FLASH/SRAM MEMORIES
Table 45.
Mode
AI02891b
PSD timing and Standby current during Power-down mode
PLD propagation
delay
Power-down Normal tPD (1)
3 V VCC
Memory
access time
Access recovery time to
normal access
Typical Standby current
No Access
tLVDV
25 µA(2)
1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo bit.
2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo bit is 0.
18.2
Other power saving options
The PSD offers other reduced power saving options that are independent of the Powerdown mode. Except for the SRAM Standby and Chip Select Input (CSI, PD2) features, they
are enabled by setting bits in the PMMR0 and PMMR2 registers (see Table 22 and Table 23.
on page 27 for a bit definition of the two registers).
18.3
PLD power management
The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in PMMR0. By
setting the bit to 1, the Turbo mode is off and the PLDs consume the specified standby
current when the inputs are not switching for an extended time of 70ns. The propagation
delay time is increased after the Turbo bit is set to 1 (turned off) when the inputs change at a
composite frequency of less than 15MHz. When the Turbo bit is reset to 0 (turned on), the
PLDs run at full power and speed. The Turbo bit affects the PLD’s DC power, AC power, and
propagation delay. Refer to Maximum rating on page 96 for PLD timings.
Blocking MCU control signals with the bits of PMMR2 can further reduce PLD AC power
consumption.
86/118
PSD835G2V
18.3.1
Power management
SRAM Standby mode (battery backup)
The PSD supports a battery backup mode in which the contents of the SRAM are retained
in the event of a power loss. The SRAM has a Voltage Standby pin (VSTBY, PC2) that can
be connected to an external battery. When VCC becomes lower than VSTBY then the PSD
automatically connects to Voltage Stand-by (VSTBY, PC2) as a power source to the SRAM.
The SRAM Standby Current (ISTBY) is typically 0.5µA. The SRAM data retention voltage is
2 V minimum. The Battery-on Indicator (VBATON) can be routed to PE7. This signal
indicates when the VCC has dropped below VSTBY and the SRAM is running on battery
power.
18.4
PSD Chip Select input (CSI, PD2)
PD2 of Port D can be configured in PSDsoft as the PSD Chip Select Input (CSI). When Low,
the signal selects and enables the internal (primary) Flash memory, secondary Flash
memory, SRAM, and I/O blocks for Read or Write operations involving the PSD. A High on
PSD Chip Select Input (CSI, PD2) disables the primary Flash memory, secondary Flash
memory, and SRAM, and reduces the PSD power consumption. However, the PLD and I/O
signals remain operational when PSD Chip Select Input (CSI, PD2) is High.
There may be a timing penalty when using PSD Chip Select Input (CSI, PD2) depending on
the speed grade of the PSD that you are using. See the timing parameter tSLQV in Table 64.
on page 109.
18.5
Input Clock
The PSD provides the option to turn off CLKIN (PD1) to the PLD to save AC power
consumption. CLKIN (PD1) is an input to the PLD AND Array and the Output Macrocells
(OMC).
During Power-down mode, or, if CLKIN (PD1) is not being used as part of the PLD logic
equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from
the PLD AND Array or the Macrocells block by setting bits 4 or 5 to a 1 in PMMR0.
87/118
Power management
PSD835G2V
Figure 31. Enable power-down flow chart
RESET
Enable APD
Set PMMR0 Bit 1 = 1
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bit 0.
No
ALE/AS idle
for 15 CLKIN
clocks?
Yes
PSD in Power
Down Mode
18.6
AI02892B
Input control signals
The PSD provides the option to turn off the address input (A7-A0) and input control signals
(CNTL0, CNTL1, CNTL2, Address Strobe (ALE/AS, PD0) and DBE) to the PLD to save AC
power consumption. These signals are inputs to the PLD AND Array. During Power-down
mode, or, if any of them are not being used as part of the PLD logic equation, these signals
should be disabled to save AC power. They are disconnected from the PLD AND Array by
setting bits 0, 2, 3, 4, 5, and 6 to a ‘1’ in PMMR2.
Table 46.
88/118
APD counter operation
APD Enable bit
ALE PD polarity
ALE level
APD counter
0
X
X
Not Counting
1
X
Pulsing
Not Counting
1
1
1
Counting (Generates PDN after 15 Clocks)
1
0
0
Counting (Generates PDN after 15 Clocks)
PSD835G2V
Reset timing and device status at reset
19
Reset timing and device status at reset
19.1
Power-up reset
Upon Power-up, the PSD requires a Reset (RESET) pulse of duration tNLNH-PO (1ms
minimum) after VCC is steady. During this period, the device loads internal configurations,
clears some of the registers and sets the Flash memory into Operating mode. After the
rising edge of Reset (RESET), the PSD remains in the Reset mode for an additional period,
tOPR (120ns maximum), before the first memory access is allowed.
The Flash memory is reset to the Read mode upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be Low, Write Strobe (WR, CNTL0) High, during Power-Up
Reset for maximum security of the data contents and to remove the possibility of a byte
being written on the first edge of Write Strobe (WR, CNTL0). Any Flash memory Write cycle
initiation is prevented automatically when VCC is below VLKO.
19.2
Warm reset
Once the device is up and running, the device can be reset with a pulse of a much shorter
duration, tNLNH (150ns minimum). The same tOPR period is needed before the device is
operational after warm reset. Figure 32 shows the timing of the Power-up and warm reset.
19.3
I/O pin, Register and PLD status at reset
Table 47. on page 90 shows the I/O pin, register and PLD status during Power-Up Reset,
warm reset and Power-down mode. PLD outputs are always valid during warm reset, and
they are valid in Power-Up Reset once the internal PSD Configuration bits are loaded. This
loading of PSD is completed typically long before VCC ramps up to operating level. Once the
PLD is active, the state of the outputs are determined by the equations specified in PSDsoft.
19.4
Reset of Flash memory Erase and Program cycles
A Reset (RESET) also resets the internal Flash memory state machine. During a Flash
memory Program or Erase cycle, Reset (RESET) terminates the cycle and returns the Flash
memory to the Read mode within a period of tNLNH-A (25µs minimum).
Figure 32. Power-up and warm reset (RESET) timing
VCC
VCC(min)
tNLNH-PO
Power-On Reset
tOPR
tNLNH
tNLNH-A
Warm Reset
tOPR
RESET
AI02866b
89/118
Reset timing and device status at reset
Table 47.
PSD835G2V
Status during power-up reset, warm reset and power-down mode
Port configuration
Power-up reset
Warm reset
Power-down mode
MCU I/O
Input mode
Input mode
Unchanged
PLD Output
Valid after internal PSD
configuration bits are
loaded
Valid
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Address Out
Tri-stated
Tri-stated
Not defined
Data Port
Tri-stated
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
Tri-stated
Register
Power-Un Reset
Warm Reset
Power-down Mode
PMMR0 and PMMR2 Cleared to 0
Unchanged
Unchanged
Macrocells flip-flop
status
Cleared to 0 by internal
Power-Up Reset
Depends on .re and
.pr equations
Depends on .re and .pr
equations
VM Register(1)
Initialized, based on the
selection in PSDsoft
Configuration menu
Initialized, based on
the selection in
PSDsoft
Configuration menu
Unchanged
All other registers
Cleared to 0
Cleared to 0
Unchanged
1. The SR_cod and PeriphMode bits in the VM Register are always cleared to 0 on Power-Up Reset or Warm
Reset.
90/118
PSD835G2V
20
Programming in-circuit using the JTAG/ISP interface
Programming in-circuit using the JTAG/ISP interface
The JTAG/ISP Interface block can be enabled on Port E (see Table 48. on page 92). All
memory blocks (primary and secondary Flash memory), PLD logic, and PSD Configuration
Register bits may be programmed through the JTAG/ISP Interface block. A blank device can
be mounted on a printed circuit board and programmed using JTAG/ISP.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up Program and
Erase cycles.
By default, on a blank PSD (as shipped from the factory or after erasure), four pins on Port E
are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
See Application Note AN1153 for more details on JTAG In-System Programming (ISP).
20.1
Standard JTAG signals
The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three
different conditions that are logically OR’ed. When enabled, TDI, TDO, TCK, and TMS are
inputs, waiting for a JTAG serial command from an external JTAG controller device (such as
FlashLINK or Automated Test Equipment). When the enabling command is received, TDO
becomes an output and the JTAG channel is fully functional inside the PSD. The same
command that enables the JTAG channel may optionally enable the two additional JTAG
signals, TSTAT and TERR.
The following symbolic logic equation specifies the conditions enabling the four basic JTAG
signals (TMS, TCK, TDI, and TDO) on their respective Port E pins. For purposes of
discussion, the logic label JTAG_ON is used. When JTAG_ON is true, the four pins are
enabled for JTAG.
When JTAG_ON is false, the four pins can be used for general PSD I/O.
JTAG_ON = PSDsoft_enabled +
/* An NVM configuration bit inside the PSD is set by the designer
in the PSDsoft Configuration utility. This dedicates the pins for
JTAG at all times (compliant with IEEE 1149.1 */
Microcontroller_enabled +
/* The microcontroller can set a bit at run-time by writing to the
PSD register, JTAG Enable. This register is located at address CSIOP
+ offset C7h. Setting the JTAG_ENABLE bit in this register will
enable the pins for JTAG use. This bit is cleared by a PSD reset or
the microcontroller. See Table 20. on page 27 for bit definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT) inside the PSD can be used to
enable the JTAG pins. This PT has the reserved name JTAGSEL. Once
defined as a node in PSDabel, the designer can write an equation for
JTAGSEL. This method is used when the Port E JTAG pins are
multiplexed with other I/O signals. It is recommended to logically
tie the node JTAGSEL to the JEN\ signal on the Flashlink cable when
multiplexing JTAG signals. See Application Note 1153 for details. */
The PSD supports JTAG/ISP commands, but not Boundary Scan. The PSDsoft software
tool and FlashLINK JTAG programming cable implement the JTAG/ISP commands.
91/118
Programming in-circuit using the JTAG/ISP interface
20.2
PSD835G2V
JTAG extensions
TSTAT and TERR are two JTAG extension signals enabled by an JTAG command received
over the four standard JTAG signals (TMS, TCK, TDI, and TDO). They are used to speed
Program and Erase cycles by indicating status on PSD signals instead of having to scan the
status out serially using the standard JTAG channel. See Application Note AN1153.
TERR indicates if an error has occurred when erasing a sector or programming a Byte in
Flash memory. This signal goes Low (active) when an Error condition occurs, and stays Low
until a special JTAG command is executed or a chip Reset (RESET) pulse is received after
an “ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy described in Ready/Busy (PE4) on page 31.
TSTAT is High when the PSD device is in Read mode (primary and secondary Flash
memory contents can be read). TSTAT is Low when Flash memory Program or Erase cycles
are in progress, and also when data is being written to the secondary Flash memory.
TSTAT and TERR can be configured as open-drain type signals during a JTAG command.
20.3
Security and Flash memory protection
When the security bit is set, the device cannot be read on a Device Programmer or through
the JTAG Port. When using the JTAG Port, only a Full Chip Erase command is allowed.
All other Program, Erase and Verify commands are blocked. Full Chip Erase returns the part
to a non-secured blank state. The Security Bit can be set in PSDsoft.
All primary and secondary Flash memory sectors can individually be sector protected
against erasures. The sector protect bits can be set in PSDsoft.
Table 48.
92/118
JTAG port signals
Port E Pin
JTAG Signals
Description
PE0
TMS
Mode Select
PE1
TCK
Clock
PE2
TDI
Serial Data In
PE3
TDO
Serial Data Out
PE4
TSTAT
Status
PE5
TERR
Error Flag
PSD835G2V
AC/DC parameters
The tables provided below describe the AD and DC parameters of the PSD:
❏ DC Electrical Specification
❏ AC Timing Specification
●
●
PLD Timing
–
Combinatorial Timing
–
Synchronous Clock Mode
–
Asynchronous Clock Mode
–
Input Macrocell Timing
MCU Timing
–
Read Timing
–
Write Timing
–
Peripheral Mode Timing
–
Power-down and Reset Timing
The following are issues concerning the parameters presented:
●
In the DC specification the supply current is given for different modes of operation.
Before calculating the total power consumption, determine the percentage of time that
the PSD is in each mode. Also, the supply power is considerably different if the Turbo
bit is 0.
●
The AC power component gives the PLD, Flash memory, and SRAM mA/MHz
specification. Figure 33 show the PLD mA/MHz as a function of the number of Product
Terms (PT) used.
●
In the PLD timing parameters, add the required delay when Turbo bit is 0.
Figure 33. PLD ICC /frequency consumption
60
VCC = 3V
50
ON
RBO
%)
(100
TU
OF
F
40
RB
O
30
TU
ICC – (mA)
21
AC/DC parameters
BO
TUR
20
10
PT 100%
PT 25%
F
O
)
25%
ON (
OF
RB
TU
0
0
5
10
15
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
AI07656
93/118
AC/DC parameters
PSD835G2V
Table 49.
Example of PSD typical power calculation at VCC = 3.0 V (with Turbo
mode on)
Conditions
Highest Composite PLD input frequency
(Freq PLD)
= 8MHz
MCU ALE frequency (Freq ALE)
= 4MHz
% Flash memory Access
= 80%
% SRAM access
= 15%
% I/O access
= 5% (no additional power above base)
Operational Modes
% Normal
= 10%
% Power-down Mode
= 90%
Number of product terms used
(from fitter report)
= 54 PT
% of total product terms
= 54/217 = 25%
Turbo Mode
= ON
Calculation (using typical values)
ICC total
= Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 1.2mA/MHz
x Freq ALE
+ %SRAM x 0.8mA/MHz x Freq ALE
+ % PLD x 1.1mA/MHz x Freq PLD
+ #PT x 200µA/PT)
= 50µA x 0.90 + 0.1 x (0.8 x 1.2mA/MHz x 4MHz
+ 0.15 x 0.8mA/MHz x 4MHz
+ 1.1mA/MHz x 8MHz
+ 54 x 0.2mA/PT)
= 45µA + 0.1 x (3.84 + 0.48 + 8.8 + 10.8)
= 45µA + 0.1 x 23.92
= 45µA + 2.39mA
= 2.43mA
This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation
is based on IOUT = 0mA.
94/118
PSD835G2V
AC/DC parameters
Table 50.
Example of PSD typical power calculation at VCC = 3.0 V (with Turbo
mode Off)
Conditions
Highest Composite PLD input frequency
(Freq PLD)
= 8MHz
MCU ALE frequency (Freq ALE)
= 4MHz
% Flash memory Access
= 80%
% SRAM access
= 15%
% I/O access
= 5% (no additional power above base)
Operational Modes
% Normal
= 10%
% Power-down Mode
= 90%
Number of product terms used
(from fitter report)
= 54 PT
% of total product terms
= 54/217 = 25%
Turbo Mode
= Off
Calculation (using typical values)
ICC total
= Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 1.2mA/MHz
x Freq ALE
+ %SRAM x 0.8mA/MHz x Freq ALE
+ % PLD x (from graph using Freq PLD))
= 50µA x 0.90 + 0.1 x (0.8 x 1.2mA/MHz x 4MHz
+ 0.15 x 0.8mA/MHz x 4MHz
+ 15mA)
= 45µA + 0.1 x (3.84 + 0.48 + 15)
= 45µA + 0.1 x 18.84
= 45µA + 1.94mA
= 1.98mA
This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation
is based on IOUT = 0mA.
95/118
Maximum rating
22
PSD835G2V
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 51.
Absolute maximum ratings
Symbol
Parameter
TSTG
Storage temperature
TLEAD
Lead temperature during soldering
Min.
Max.
Unit
–65
125
°C
See (1)
°C
VIO
Input and output voltage (Q = VOH or Hi-Z)
–0.6
4.0
V
VCC
Supply voltage
–0.6
4.0
V
VPP
Device programmer supply voltage
–0.6
14.0
V
VESD
Electrostatic discharge voltage (human body model) (2)
–2000
2000
V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU
2. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 Ω, R2=500 Ω)
96/118
PSD835G2V
23
AC and DC parameters
AC and DC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 52.
Operating conditions
Symbol
Parameter
VCC
TA
Min.
Max.
Unit
Supply voltage
3.0
3.6
V
Ambient operating temperature (industrial)
–40
85
°C
0
70
°C
Ambient operating temperature (commercial)
AC signal letters for PLD timing(1)
Table 53.
A
Address Input
C
CEout Output
D
Input Data
E
E Input
G
Internal WDOG_ON signal
I
Interrupt Input
L
ALE Input
N
RESET Input or Output
P
Port Signal Output
Q
Output Data
R
WR, UDS, LDS, DS, IORD, PSEN Inputs
S
Chip Select Input
T
R/W Input
W
Internal PDN Signal
B
VSTBY Output
M
Output Macrocell
1. Example: tAVLX = Time from Address Valid to ALE Invalid.
97/118
AC and DC parameters
PSD835G2V
AC signal behavior symbols for PLD timing(1)
Table 54.
t
Time
L
Logic Level Low or ALE
H
Logic Level High
V
Valid
X
No Longer a Valid Logic Level
Z
Float
PW
Pulse Width
1. Example: tAVLX = Time from Address Valid to ALE Invalid.
Table 55.
AC measurement conditions(1)
Symbol
CL
Parameter
Min.
Load capacitance
Max.
30
Unit
pF
1. Output Hi-Z is defined as the point where data out is no longer driven.
Table 56.
Symbol
CIN
Capacitance(1)
Parameter
Test condition
Typ.(2)
Max.
Unit
VIN = 0 V
4
6
pF
Input capacitance (for input pins)
COUT
Output capacitance (for
input/output pins)
VOUT = 0 V
8
12
CVPP
Capacitance (for CNTL2/VPP)
VPP = 0 V
18
25
1. Sampled only, not 100% tested.
2. Typical values are for TA = 25°C and nominal supply voltages.
Figure 34. AC measurement I/O waveform
3.0V
Test Point
1.5V
0V
AI03103b
Figure 35. AC measurement load circuit
2.01 V
195 Ω
Device
Under Test
CL = 30 pF
(Including Scope and
Jig Capacitance)
AI03104b
98/118
pF
pF
PSD835G2V
AC and DC parameters
Figure 36. Switching waveforms – key
WAVEFORMS
INPUTS
OUTPUTS
STEADY INPUT
STEADY OUTPUT
MAY CHANGE FROM
HI TO LO
WILL BE CHANGING
FROM HI TO LO
MAY CHANGE FROM
LO TO HI
WILL BE CHANGING
LO TO HI
DON'T CARE
CHANGING, STATE
UNKNOWN
OUTPUTS ONLY
CENTER LINE IS
TRI-STATE
AI03102
99/118
AC and DC parameters
Table 57.
DC characteristics
Symbol
Parameter
PSD835G2V
Test condition (in
addition to those in
Table 52. on page 97)
Min.
Typ.
Max.
Unit
VIH
Input high voltage
3.0 V < VCC < 3.6 V
0.7VCC
VCC +0.5
V
VIL
Input low voltage
3.0 V < VCC < 3.6 V
–0.5
0.8
V
Reset high level input voltage
(1)
0.8VCC
VCC +0.5
V
VIL1
Reset low level input voltage
(1)
–0.5
0.2VCC –0.1
V
VHYS
Reset pin hysteresis
0.3
VLKO
VCC (min) for Flash Erase and
Program
1.5
VOL
Output low voltage
VOH
Output high voltage except
VSTBY on
VOH1
Output high voltage VSTBY on
VSTBY
SRAM Standby voltage
ISTBY
SRAM Standby current (VSTBY
pin)
IIDLE
Idle current (VSTBY input)
VDF
SRAM data retention voltage
ISB
Standby Supply current for
Power-down mode
ILI
Input leakage current
VSS < VIN < VCC
ILO
Output leakage current
0.45 < VIN < VCC
VIH1
V
2.3
V
IOL = 20 µA, VCC = 3.0 V
0.01
0.1
V
IOL = 4, VCC = 3.0 V
0.15
0.45
V
IOH = –20 µA, VCC = 3.0 V
2.9
2.99
V
IOH = –1, VCC = 3.0 V
2.7
2.8
V
IOH1 = –1 µA
VSTBY – 0.8
V
2.0
VCC = 0 V
0.5
VCC > VSTBY
–0.1
Only on VSTBY
2
CSI >VCC –0.3 V(2),(3)
VCC
V
1
µA
0.1
µA
V
50
100
µA
–1
±0.1
1
µA
–10
±5
10
µA
ZPLD_TURBO = Off,
f = 0 MHz(3)
0
ZPLD_TURBO = On,
f = 0MHz
400
700
µA/PT
During Flash memory
Write/Erase Only
10
25
mA
Read Only, f = 0 MHz
0
0
mA
0
0
mA
mA
PLD Only
ICC
(DC)(4)
Operating
supply current
Flash memory
SRAM
f = 0 MHz
PLD AC base
ICC
(AC)(4)
(5)
Figure 33
Flash memory AC adder
1.5
2.0
mA/MHz
SRAM AC adder
0.8
1.5
mA/MHz
1. Reset (Reset) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC.
2. CSI deselected or internal Power-down mode is active.
3. PLD is in non-Turbo mode, and none of the inputs are switching.
4. IOUT = 0
5. Please see Figure 33. on page 93 for the PLD current calculation.
100/118
PSD835G2V
AC and DC parameters
Figure 37. Input to Output Disable / Enable
INPUT
tER
tEA
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
Figure 38. Combinatorial Timing – PLD
CPLD INPUT
tPD
CPLD OUTPUT
AI07655
Table 58.
CPLD combinatorial timing
-90
Symbol
Parameter
-12
Conditions
Min Max Min Max
tPD
CPLD Input
Pin/Feedback to CPLD
Combinatorial Output
38
43
tEA
CPLD Input to CPLD
Output Enable
43
tER
CPLD Input to CPLD
Output Disable
tARP
CPLD Register Clear
or Preset Delay
tARPW
CPLD Register Clear
or Preset Pulse Width
tARD
CPLD Array Delay
+ 20
–6
ns
45
+ 20
–6
ns
43
45
+ 20
–6
ns
38
43
+ 20
–6
ns
28
Any
macrocell
PT Turbo Slew
Unit
Aloc Off rate(1)
+4
30
23
+ 20
27
+4
ns
ns
1. Fast Slew Rate output available on Ports C and F.
101/118
AC and DC parameters
Table 59.
PSD835G2V
CPLD Macrocell Synchronous clock mode timing
-90
Symbol
Parameter
Min
Maximum Frequency
External Feedback
fMAX
-12
Conditions
Maximum Frequency
Internal Feedback (fCNT)
Maximum Frequency
Pipelined Data
Max
Min
Max
PT
Aloc
Turbo
Off
Slew
rate(1)
Unit
1/(tS+tCO)
24.3
20.4
MHz
1/(tS+tCO–10)
32.2
25.6
MHz
1/(tCH+tCL)
45.0
35.7
MHz
tS
Input Setup Time
18
23
tH
Input Hold Time
0
0
ns
tCH
Clock High Time
Clock Input
11
14
ns
tCL
Clock Low Time
Clock Input
11
14
ns
tCO
Clock to Output Delay
Clock Input
23
26
tARD
CPLD Array Delay
Any macrocell
23
27
tMIN
Minimum Clock Period (2)
tCH+tCL
22
+4
+ 20
ns
–6
+4
ns
ns
28
ns
1. Fast Slew Rate output available on Ports C and F.
2. CLKIN (PD1) tCLCL = tCH + tCL.
Table 60.
CPLD Macrocell Asynchronous clock mode timing
-90
Symbol
Parameter
Min
fMAXA
-12
Conditions
Max
Min
Max
PT
Aloc
Turbo
Off
Slew
Rate
Unit
Maximum frequency
external feedback
1/(tSA+tCOA)
23.8
20.8
MHz
Maximum frequency
internal feedback
(fCNTA)
1/(tSA+tCOA–10)
31.25
26.3
MHz
Maximum frequency
pipelined data
1/(tCHA+tCLA)
38.4
30.3
MHz
tSA
Input setup time
8
10
tHA
Input hold time
10
12
tCHA
Clock input high time
15
18
+ 20
ns
tCLA
Clock input low time
12
15
+ 20
ns
tCOA
Clock to output delay
tARDA
CPLD array delay
tMINA
Minimum Clock period
102/118
Any macrocell
1/fCNTA
32
+4
ns
ns
34
38
23
27
38
+ 20
+ 20
+4
–6
ns
ns
ns
PSD835G2V
AC and DC parameters
Figure 39. Synchronous Clock mode timing – PLD
tCH
tCL
CLKIN
tS
tH
INPUT
tCO
REGISTERED
OUTPUT
AI02860
Figure 40. Asynchronous Reset / Preset
tARPW
RESET/PRESET
INPUT
tARP
REGISTER
OUTPUT
AI02864
Figure 41. Asynchronous Clock mode timing (product term clock)
tCHA
tCLA
CLOCK
tSA
tHA
INPUT
tCOA
REGISTERED
OUTPUT
AI02859
103/118
AC and DC parameters
PSD835G2V
Figure 42. Input macrocell timing (product term clock)
t INH
t INL
PT CLOCK
t IS
t IH
INPUT
OUTPUT
t INO
AI03101
Table 61.
Input macrocell timing
-90
Symbol
Parameter
-12
Conditions
Min Max Min Max
PT
Aloc
Turbo
Unit
Off
Input setup time
(1)
0
0
Input hold time
(1)
20
23
tINH
NIB input high time
(1)
13
13
ns
tINL
NIB input low time
(1)
12
13
ns
tINO
NIB input to combinatorial
delay
(1)
tIS
tIH
46
ns
+ 20
62
+4
+ 20
1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to
tAVLX and tLXAX.
104/118
ns
ns
PSD835G2V
AC and DC parameters
Figure 43. Read timing
tAVLX
tLXAX
1
ALE /AS
tLVLX
A /D
MULTIPLEXED
BUS
DATA
VALID
ADDRESS
VALID
tAVQV
ADDRESS
NON-MULTIPLEXED
BUS
ADDRESS
VALID
DATA
NON-MULTIPLEXED
BUS
DATA
VALID
tSLQV
CSI
tRLQV
tRHQX
tRLRH
RD
(PSEN, DS)
tRHQZ
tEHEL
E
tTHEH
tELTL
R/W
tAVPV
ADDRESS OUT
AI02895
1. tAVLX and tLXAX are not required for 80C51XA in Burst Mode.
105/118
AC and DC parameters
Table 62.
PSD835G2V
Read timing
-90
Symbol
Parameter
Min
tLVLX
-12
Conditions
ALE or AS pulse width
tAVLX
Address Setup time
(1)
tLXAX
Address Hold time
(1)
tAVQV
Address Valid to Data Valid
(1)
tSLQV
CS Valid to Data Valid
Max
Min
Max
Turbo
Off
22
24
ns
7
9
ns
8
10
ns
90
120
+ 20
ns
90
120
ns
RD to Data Valid 8-Bit Bus
(2)
35
35
ns
tRLQV
RD or PSEN to Data Valid
8-Bit Bus, 8031, 80251
(3)
45
48
ns
tRHQX
RD Data Hold time
(4)
0
0
ns
RD pulse width
(4)
36
40
ns
tRHQZ
RD to Data High-Z
(4)
tEHEL
E pulse width
38
42
ns
tTHEH
R/W setup time to Enable
10
16
ns
tELTL
R/W Hold time after Enable
0
0
ns
tAVPV
Address input valid to address
output delay
tRLRH
(5)
38
30
40
35
1. Any input used to select an internal PSD function.
2. RD timing has the same timing as DS signal.
3. RD and PSEN have the same timing for 80C51.
4. RD timing has the same timing as DS and PSEN signals.
5. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
106/118
Unit
ns
ns
PSD835G2V
AC and DC parameters
Figure 44. Write timing
tAVLX
t LXAX
ALE/AS
t LVLX
A/D
MULTIPLEXED
BUS
ADDRESS
VALID
DATA
VALID
tAVWL
ADDRESS
NON-MULTIPLEXED
BUS
ADDRESS
VALID
DATA
NON-MULTIPLEXED
BUS
DATA
VALID
tSLWL
CSI
tDVWH
t WLWH
WR
(DS)
t WHDX
t WHAX
t EHEL
E
t THEH
t ELTL
R/ W
t WLMV
tAVPV
t WHPV
ADDRESS OUT
STANDARD
MCU I/O OUT
AI02896
107/118
AC and DC parameters
Table 63.
PSD835G2V
Write timing
-90
Symbol
Parameter
Unit
Min
tLVLX
-12
Conditions
ALE or AS pulse width
Max
Min
Max
22
24
ns
7
9
ns
tAVLX
Address Setup time
(1)
tLXAX
Address Hold time
(1)
8
10
ns
(1),(2)
15
18
ns
CS Valid to leading edge of WR
(2)
15
18
ns
tDVWH
WR Data Setup time
(2)
40
45
ns
tWHDX
WR Data Hold time
(2),(3)
5
8
ns
40
45
ns
tAVWL
tSLWL
Address Valid to leading edge of WR
tWLWH
WR pulse width
(2)
tWHAX1
Trailing edge of WR to Address
invalid
(2)
8
10
ns
tWHAX2
Trailing edge of WR to DPLD
Address invalid
(2),(4)
0
0
ns
tWHPV
Trailing edge of WR to port output
valid using I/O Port Data Register
tDVMV
Data valid to port output valid using
Macrocell Register Preset/Clear
tAVPV
Address input valid to Address
output delay
tWLMV
WR valid to port output valid using
Macrocell Register Preset/Clear
(2)
33
33
ns
(2),(5)
65
70
ns
(6)
65
68
ns
(2),(7)
30
35
ns
1. Any input used to select an internal PSD function.
2. WR has the same timing as E and DS signals.
3. tWHDX is 11ns when writing to Output Macrocell Registers AB and BC.
4. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for
internal PSD memory.
5. Assuming write is active before data becomes valid.
6. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
7. Assuming data is stable before active write signal.
108/118
PSD835G2V
AC and DC parameters
Figure 45. Peripheral I/O Read timing
ALE /AS
A /D BUS
ADDRESS
DATA VALID
tAVQV ( PF)
tSLQV ( PF)
CSI
tRLQV ( PF)
tQXRH ( PF)
tRHQZ ( PF)
tRLRH ( PF)
RD
tDVQV ( PF)
DATA ON PORT F
AI02897b
Table 64.
Port F peripheral data mode read timing
-90
Symbol
Parameter
-12
Conditions
Min Max Min Max
tAVQV–PF
Address Valid to Data Valid
tSLQV–PF
CSI Valid to Data Valid
(1)
Turbo
Off
Unit
50
50
+ 20
ns
35
40
+ 20
ns
35
40
ns
RD to Data Valid 8031 Mode
45
45
ns
tDVQV–PF
Data In to Data Out Valid
34
38
ns
tQXRH–PF
RD Data Hold Time
RD to Data Valid
tRLQV–PF
tRLRH–PF
tRHQZ–PF
(2),(3)
RD Pulse Width
(2)
RD to Data High-Z
(2)
0
0
ns
35
36
ns
38
40
ns
1. Any input used to select Port F Data Peripheral mode.
2. RD has the same timing as DS and PSEN.
3. Data is already stable on Port F.
109/118
AC and DC parameters
PSD835G2V
Figure 46. Peripheral I/O Write timing
ALE /AS
ADDRESS
A / D BUS
DATA OUT
tWLQV
tWHQZ (PF)
(PF)
WR
tDVQV (PF)
PORT F
DATA OUT
AI02898B
Table 65.
Port F peripheral data mode write timing
-90
Symbol
Parameter
Unit
Min
tWLQV–PF
tDVQV–PF
tWHQZ–PF
-12
Conditions
Max
Min
Max
WR to data propagation delay
(1)
40
43
ns
Data to Port A data propagation delay
(2)
35
38
ns
WR Invalid to Port A tri-state
(1)
33
33
ns
1. WR has the same timing as the E and DS signals.
2. Data stable on ADIO pins to data on Port F.
Table 66.
Program, Write and Erase times
Symbol
Parameter
Min.
Flash Program
Flash Bulk
Erase(1)
Typ.
Max.
Unit
8.5
(pre-programmed to 00)
3
Flash Bulk Erase (not pre-programmed)
10
tWHQV3
Sector Erase (pre-programmed)
1
tWHQV2
Sector Erase (not pre-programmed to 00)
2.2
tWHQV1
Byte Program
14
Program / Erase Cycles (per Sector)
tWHWLO
Sector Erase Time-Out
tQ7VQV
DQ7 Valid to Output (DQ7-DQ0) Valid (Data
Polling)(2)
s
30
s
s
30
s
s
1200
100,000
µs
cycles
100
µs
30
1. Programmed to all zero before erase.
2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.
110/118
ns
PSD835G2V
Table 67.
AC and DC parameters
Power-down timing
-90
Symbol
Parameter
-12
Conditions
Unit
Min
tLVDV
ALE access time from Power-down
tCLWH
Maximum delay from APD Enable to Internal
PDN valid signal
Max
Min
Max
128
135
15 * tCLCL(1)
Using CLKIN (PD1)
ns
µs
1. tCLCL is the period of CLKIN (PD1).
Figure 47. Reset (RESET) timing
VCC
VCC(min)
tNLNH-PO
tNLNH
tNLNH-A
Warm Reset
tOPR
Power-On Reset
tOPR
RESET
AI02866b
Table 68.
Reset (RESET) Timing
Symbol
Parameter
tNLNH
RESET Active low time(1)
tNLNH–PO
Power Up Reset Active low time
Conditions
(2)
tNLNH–A
Warm Reset
tOPR
RESET High to operational device
Min
Max
Unit
300
ns
1
ms
25
µs
300
ns
1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles.
Table 69.
Symbol
tBVBH
tBXBL
VSTBYON timing
Parameter
Conditions
Min
Typ
Max
Unit
VSTBY detection to VSTBYON output high
(1)
20
µs
VSTBY Off detection to VSTBYON output low
(1)
20
µs
1. VSTBYON timing is measured at VCC ramp rate of 2 ms.
111/118
AC and DC parameters
PSD835G2V
Figure 48. ISC timing
t ISCCH
TCK
t ISCCL
t ISCPSU
t ISCPH
TDI/TMS
t ISCPZV
t ISCPCO
ISC OUTPUTS/TDO
t ISCPVZ
ISC OUTPUTS/TDO
AI02865
Table 70.
ISC timing
-90
Symbol
Parameter
Unit
Min Max Min
Max
15
12
tISCCF
Clock (TCK, PC1) frequency (except for
PLD)
(1)
tISCCH
Clock (TCK, PC1) high time (except for
PLD)
(1)
30
40
ns
tISCCL
Clock (TCK, PC1) low time (except for
PLD)
(1)
30
40
ns
tISCCFP
Clock (TCK, PC1) frequency (PLD only)
(2)
Clock (TCK, PC1) high time (PLD only)
(2)
240
240
ns
tISCCLP
Clock (TCK, PC1) low time (PLD only)
(2)
240
240
ns
tISCPSU
ISC Port Set Up time
11
12
ns
tISCPH
ISC Port Hold Up time
5
5
ns
tISCPCO
ISC Port Clock to Output
26
32
ns
tISCPZV
ISC Port high-impedance to Valid Output
26
32
ns
tISCPVZ
ISC Port Valid Output to High-Impedance
26
32
ns
tISCCHP
1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For Program or Erase PLD only.
112/118
-12
Conditions
2
2
MHz
MHz
PSD835G2V
24
Package mechanical
Package mechanical
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: http://www.st.com with specific Application Notes
covering the main technical aspects related to lead-free conversion (AN2033, AN2034,
AN2035 and AN2036).
Figure 49. TQFP80 - 80 lead Plastic Quad Flatpack, package outline
D
D1
D2
A2
e
E2 E1 E
Ne
b
N
1
A
Nd
CP
L1
c
QFP-A
A1
α
L
1. Drawing is not to scale.
113/118
Package mechanical
Table 71.
PSD835G2V
TQFP80 - 80 lead Plastic Quad Flatpack, package mechanical data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
1.200
Max
0.0472
A1
0.050
0.150
0.0020
0.0059
A2
0.950
1.050
0.0374
0.0413
0.170
0.270
0.0067
0.0106
0.090
0.200
0.0035
0.0079
–
–
b
0.220
c
114/118
Max
0.0087
D
14.000
0.5512
D1
12.000
0.4724
D2
9.500
E
14.000
0.5512
E1
12.000
0.4724
E2
9.500
–
–
0.3740
–
–
e
0.500
–
–
0.0197
–
–
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0.0394
CP
0.080
0.0031
α
3.5°
0.0°
7.0°
–
0.0°
–
7.0°
0.3740
3.5°
N
80
80
Nd
20
20
Ne
20
20
PSD835G2V
25
Part numbering
Part numbering
Table 72.
Ordering information scheme
Example:
PSD8
3
5
G
2
V
– 90
U
I
T
Device type
PSD8 = 8-bit PSD with Register Logic
SRAM size
3 = 64 Kbit
Flash memory size
5 = 4 Mbit (512 Kb x8)
I/O count
G = 52 I/O
2nd Flash memory
2 = 256 Kbit (32 Kb x8) Flash memory
Operating voltage
V = VCC = 3.0 to 3.6 V
Speed
90 = 90 ns
12 = 120 ns
Package
U = ECOPACK TQFP80
Temperature range
blank = 0 to 70 °C (Commercial)
I = –40 to 85 °C (Industrial)
Shipping option
T = Tape & Reel Packing
Blank =
For other options, or for more information on any aspect of this device, please contact the
ST Sales Office nearest you.
115/118
Pin assignments
PSD835G2V
Appendix A
Pin assignments
Table 73.
116/118
PSD835G2V TQFP80
Pin
No.
Pin
assignments
Pin
No.
Pin
assignments
Pin
No.
Pin
assignments
Pin
No.
Pin
assignments
1
PD2
21
PG0
41
PC0
61
PB0
2
PD3
22
PG1
42
PC1
62
PB1
3
AD0
23
PG2
43
PC2
63
PB2
4
AD1
24
PG3
44
PC3
64
PB3
5
AD2
25
PG4
45
PC4
65
PB4
6
AD3
26
PG5
46
PC5
66
PB5
7
AD4
27
PG6
47
PC6
67
PB6
8
GND
28
PG7
48
PC7
68
PB7
9
VCC
29
VCC
49
GND
69
VCC
10
AD5
30
GND
50
GND
70
GND
11
AD6
31
PF0
51
PA0
71
PE0
12
AD7
32
PF1
52
PA1
72
PE1
13
AD8
33
PF2
53
PA2
73
PE2
14
AD9
34
PF3
54
PA3
74
PE3
15
AD10
35
PF4
55
PA4
75
PE4
16
AD11
36
PF5
56
PA5
76
PE5
17
AD12
37
PF6
57
PA6
77
PE6
18
AD13
38
PF7
58
PA7
78
PE7
19
AD14
39
RESET
59
CNTL0
79
PD0
20
AD15
40
CNTL2
60
CNTL1
80
PD1
PSD835G2V
Revision history
Revision history
Document revision history
Date
Version
31-May-04
1.0
24-Apr-2007
2
Changes
Document reformatted; split from original with both voltage options
Document maturity promoted from Preliminary Data to full Datasheet.
TLEAD removed from Table 51: Absolute maximum ratings, Note 1.
Added ECOPACK text in Package mechanical on page 113.
Document reformatted. Notes modified below Table 24: VM Register.
117/118
PSD835G2V
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