SSM1105V Scalar System Memory (SSM) for Image Processor ICs NOT FOR NEW DESIGN FEATURES SUMMARY ■ System solution for use with image processing scalar ICs decoders, chip-selects, inverters; and to prioritize interrupts from DDC, I2C, PWM – For LCD monitors, projectors, and TVs – Compatible with Pixelworks PW11x/PWx64 families (and similar image processors or micro-controllers) ■ Figure 1. Packages Single integrated package, including: – Dual bank Flash memories – DDC, I2C, and PWM channels – General purpose I/O – Programmable logic – In-System Programming via JTAG ■ Dual bank Flash memories – Provide concurrent operation – 5 Mbit main Flash memory – 384 Kbit secondary Flash memory (divided into 10 small sectors) TQFP100 (U) – Programmable Decode PLD for flexible address mapping of both memories ■ Dual Display Data Channels (DDC) – Supports DDC for both analog RGB and digital DVI video input channels – DDC1/DDC2B VESA standard compliant – 256 byte SRAM buffer for each DDC channel ■ – Program entire chip in 30-40 seconds with no involvement of the processor – Each capable of master or slave operation – Program with low-cost FlashLINK Four Pulse Width Modulator (PWM) channels ■ Content Security: Programmable Security Bit blocks access of device programmers / readers ■ Zero-Power Technology: memory and PLD blocks automatically switch to stand-by current between input changes ■ Package and Specifications – 16-bit resolution for period and for duty cycle – 16-bit clock prescalers ■ ■ In-System Programming (ISP) with JTAG Dual independent I2C channels – Control A/D converters, video decoders, and future devices (tuner, audio, etc.) ■ ■ Seven I/O ports with 52 I/O pins for Multifunction I/O: GPIO, DDC, I2C, PWM, PLD I/O, and JTAG 3000 gate PLD with 16 macrocells, for creating glue logic, state machines, clock dividers, – 100-pin TQFP, 14 x 14mm – 90 ns memory access time – VCC Operating Voltage: 2.7V to 3.6V November 2002 This is information on a product still in production but not recommended for new designs. 1/4 SSM1105V SUMMARY DESCRIPTION SSM1105V devices bring in-system programmable (ISP) and in-application programmable (IAP) flash memory to LCD monitor, projector and television applications utilizing a scalar IC from either Pixelworks or other similar image processors or micro-controllers (MCU). Figure 3 shows a typical SSM based system with Pixelworks processor. The SSM1105V devices feature a dual -bank flash architecture, Dual Display Data Channels (DDC), I2C, PWM channels, general purpose I/O, programmable logic, and in-system programming via either JTAG or I2C. The dual-bank Flash memory architecture supports full concurrent operation permitting IAP in the field, which means that firmware can be remotely updated with little interruption of system operation. During run-time, the secondary Flash memory array is ideal for EEPROM emulation, thus eliminating the need for a separate external EEPROM. An on-chip, decode PLD provides for flexible address mapping for both memories. Dual 256 byte SRAMs provide buffer storage for the DDC channels, thus removing the burden from the processor. Figure 2. SSM Block Diagram INTERNAL ADDR, DATA, CONTROL BUS LINKED TO CPU CPU ADDR AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 640 KBytes total 6 BLOCKS, 8 KB 48 KBytes total CSBOOT0-5 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 RUNTIME CONTROL REG FILES DDC I2C PWM GPIO POWER MNGMT CSIP PLD INPUT BUS I/O PORT DDC SRAMs 256 byte 256 byte DDC-SRAM CSIOP I/O PORT PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 GENERAL PLD AND ARRAY PD0 PD1 PD2 PD3 SECONDARY FLASH FS0-9 DECODE PLD PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 TO PLD IN BUS 10 BLOCKS, 64 KB PAGE REG CPU DATA I/O PORT MAIN FLASH SECURITY LOCK A A A A A A A A B B B B B B B B 16 OUTPUT MICROCELLS A A A A A A A A C C C C B B B B B B B B C C C C I/O PORT 24 INPUT MICROCELLS CPU CNTL CNTL0 CNTL1 CNTL2 RST\ PIN FEEDBACK DUAL I2C I2C0 I2C1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 NODE FEEDBACK INTERNAL ADDR, DATA, CONTROL BUS LINKED TO CPU DUAL DDC DDC0 DDC1 JTAG ISP CONTROLLER QUAD PWM PW0 PW1 PW2 PW3 I/O PORT I/O PORT I/O PORT P P P P P P P P E E E E E E E E 0 1 2 3 4 5 6 7 P P P P P P P P H HH H H HHH 0 1 2 3 4 5 6 7 P P P P P P P P I I I I I I I I 0 1 2 3 4 5 6 7 AI04976 Note: Additional address lines can be brought in to the device via Port A, B, C or D. 2/4 SSM1105V Table 1. Pin Assignments – TQFP100 Pin No. Pin Assign ments Pin No. Pin Assign ments Pin No. Pin Assign ments Pin No. Pin Assign ments 1 PD2 26 PG1 51 PI0 76 PA5 2 PD3 27 PG2 52 PI1 77 PA6 3 GND 28 PG3 53 PI2 78 PA7 4 VDD 29 PG4 54 PI3 79 CNTL0 5 ADIO0 30 PG5 55 PI4 80 CNTL1 6 ADIO1 31 PG6 56 PI5 81 PB0 7 ADIO2 32 PG7 57 PI6 82 PB1 8 ADIO3 33 PF0 58 PI7 83 PB2 9 ADIO4 34 PF1 59 GND 84 PB3 10 ADIO5 35 PF2 60 VDD 85 PB4 11 ADIO6 36 PF3 61 PC0 86 PB5 12 ADIO7 37 PF4 62 PC1 87 PB6 13 ADIO8 38 PF5 63 PC2 88 PB7 14 ADIO9 39 PF6 64 PC3 89 VDD 15 ADIO10 40 PF7 65 PC4 90 GND 16 ADIO11 41 VDD 66 PC5 91 PE0 17 GND 42 GND 67 PC6 92 PE1 18 VDD 43 PH0 68 PC7 93 PE2 19 ADIO12 44 PH1 69 GND 94 PE3 20 ADIO13 45 PH2 70 VDD 95 PE4 21 ADIO14 46 PH3 71 PA0 96 PE5 22 ADIO15 47 PH4 72 PA1 97 PE6 23 RESET 48 PH5 73 PA2 98 PE7 24 CNTL2 49 PH6 74 PA3 99 PD0 25 PG0 50 PH7 75 PA4 100 PD1 3/4 SSM1105V Figure 3. SSM1105V-Based System Applications ADC ADDR DDC 5 Mb FLASH DVI DATA ROMOE TMDS R,G,B,CLK CPU INTFC I2C DDC / I2C Logic analog or digital Inputs ROMWE OPTIONAL VIDEO INPUT BHE I2C 384Kb FLASH OPTIONAL NTSC/PAL DECODER YUV I2C Pixelworks PW11x PWx64 PLD - 16 MACRO CELLS CONTROL 8 GPIO KEYBD 8 GPIO PWM PWM PWM PWM 4 Channels PWM PANEL CONTROLS ANALOG RBG DDC BACKLIGHT VOLUME TREBEL BASS I2C MASTER/ SLAVE I2C I2C MASTER/ SLAVE I2C Future FEATURES MANU FACTUR ING JTAG In-Sytem Programming (ISP) JTAG TFT DISPLAY SSM1105V DISPLAY DATA AI04977 Table 2. Ordering Information Scheme Example: Device Type SSM1105 = SSM for image processor ICs Operating Voltage V = VCC = 2.7 to 3.6V Speed 90 = 90 ns Package T = TQFP100 Temperature Range 1 = 0 to 70 °C (commercial) Option T = Tape & Reel Packing 4/4 SSM1105 V – 90 T 1 T