CYW2325
Serial Input PLL with 2.5-GHz Prescaler
Features
Applications
• Operating voltage 2.7V to 5.5V
• Operating frequency: up to 2.5 GHz with prescaler
ratios of 32/33 and 64/65
• Lock detect feature
• Power-down mode
• 20-pin TSSOP (Thin Shrink Small Outline Package)
•
•
•
•
Wireless LAN
Wireless communication handsets
Base Stations
Microcells
CYW2325 PLL Block Diagram
VCC (5)
GND (7)
VP (4)
(6)
FIN
(10)
Prescaler
64/65 or
128/129
Binary 7-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
fp
Phase
Detector
Charge
Pump
(15)
FC
(20)
∅r
(18)
∅p
18-Bit
Latch
OSC_IN
OSC_OUT
LE
DATA
CLOCK
PWDN
DO
(16)
BISW
(8)
fr
(1)
LD
14-Bit
Reference Counter
(3)
Latch
Selector
(14)
15-Bit
Latch
Divider
Output
(fr/fp)
MUX
(13)
(17)
FOUT
Cntrl 19-Bit
Shift
Reg
(11)
(19)
Pin Configuration
OSC_IN
1
20
∅r
NC
2
19
PWDN
OSC_OUT
3
18
∅p
VP
4
17
Fout
VCC
5
16
BISW
DO
6
15
FC
GND
7
14
LE
LD
8
13
DATA
NC
9
12
NC
FIN
10
11
CLOCK
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
February 14, 2000, rev. **
CYW2325
R5
R4
Q1
(1)
1000p
Crystal
Osc.
Input
∅r
OSCIN
(2)
(20)
R6
Q2
(19)
NC
PWDN
(3)
(18)
R7
∅p
OSCOUT
Q4
100p
Q3
0.1µ
(4)
VP
0.1µ
(17)
VP
FOUT
(16)
VCC
VCC
BISW
(6)
(15)
DO
FC
GND
LE
C1
C2
(7)
R2
C3
(14)
R3
(8)
(13)
LD
DATA
NC
NC
FIN
CLOCK
VCC
VP
(9)
VCO*
100k
MMBT200
LD
33k
10k
18Ω
18Ω
18Ω
(12)
Lock
Detect
0.01 µF
R9
Vp
(5)
100p
R8
(10)
(11)
100 pF
50Ω
RFOUT
From
Controller
Figure 1. Application Diagram Example - CYW2325 2.5-GHz PLL
2
CYW2325
Pin Definitions
Pin
No.
Pin
Type
OSC_IN
1
I
NC
2
Oscillator Input: This input has a VCC/2 threshold and CMOS logic level sensitivity.
No Connect
OSC_OUT
3
O
Oscillator Output
VP
4
P
Charge Pump Rail Voltage: This supply for charge pump. Must be > VCC.
VCC
5
P
Power Supply Connection for PLL: When power is removed from VCC all latched
data is lost.
DO
6
O
Charge Pump Output: The phase detector gain is IP/2π. Sense polarity can be reversed by setting FC LOW (pin 15).
GND
7
G
Analog and Digital Ground Connection: This pin must be grounded.
O
Pin Name
Pin Description
Lock Detect Pin: This output is HIGH with narrow LOW pulses when the loop is locked.
LD
8
NC
9
FIN
10
I
Input to Prescaler: Maximum frequency 2.5 GHz.
CLOCK
11
I
Data Clock Input: One bit of data is loaded into the Shift Register on the rising edge
of this signal.
NC
12
DATA
13
I
Serial Data Input
LE
14
I
Load Enable: On the rising edge of this signal, the data stored in the Shift Register is
latched into the counters and configuration controls.
FC
15
I
Phase Sense Control for Phase Detector with Internal Pull-up: When pulled LOW,
the polarity of the Phase Detector is reversed.
BISW
16
O
Analog Switch Output: Connects to output of charge pump when LE is HIGH.
FOUT
17
O
Monitor Point for Phase Detector Input
∅P
18
O
External Charge Pump Output: Open drain N-Channel FET, pull-up resistor required.
PWDN
19
I
Power Down Pin with Internal Pull-up: When pin is HIGH, device is in normal state.
When pin is LOW, device is in power-down mode. When device enters power-down
mode the charge pump is in the three-state condition.
∅R
20
O
External Change Pump: (CMOS logic output).
No Connect
No Connect
3
CYW2325
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating
Parameter
Description
VCC or VP
Power Supply Voltage
VOUT
Output Voltage
Rating
Unit
–0.5 to +6.5
V
–0.5 to V CC+0.5
V
IOUT
Output Current
±15
mA
TL
Lead Temperature
+260
°C
TSTG
Storage Temperature
–55 to +150
°C
Handling Precautions
Always turn off power before adding or removing devices from
system.
Devices should be transported and stored in antistatic containers.
Protect leads with a conductive sheet when handling or transporting PC boards with devices.
These devices are static sensitive. Ensure that equipment and
personnel contacting the devices are properly grounded.
If devices are removed from the moisture protective bags for
more than 36 hours, they should be baked at 85°C in a moisture free environment for 24 hours prior to assembly in less
than 24 hours.
Cover workbenches with grounded conductive mats.
Recommended Operating Conditions
Rating
Unit
VCC
Parameter
Power Supply Voltage
Description
Test Condition
2.7 to 5.5
V
VP
Charge Pump Voltage
VCC to +5.5
V
TA
Operating Temperature
–40 to +85
°C
Ambient air at 0 CFM flow
4
CYW2325
Electrical Characteristics: VCC = 3.0V, VP = 3.0V, TA = –40°C to +85°C, Unless otherwise specified
Parameter
Description
Test Condition
Pin
ICC
Power Supply Current
IPD
Power-down Current
FIN
Maximum Operating
Frequency
FIN
FOSC
Oscillator Input Frequency No load on OSC_OUT
OSC_IN
Fφ
Maximum Phase Detector
Frequency
PFIN
Input Sensitivity
Power-down, VCC = 3.0V
8
VCC
6
IIH, IIL
Oscillator Input Current
Max.
VCC = 2.7V
FIN
OSC_IN
100
2.5
µA
GHz
2
60
MHz
2
25
MHz
MHz
–15
4
dBm
–10
4
dBm
0.5
VP–P
–100
VCC = 5.0V
Unit
mA
10
VCC = 5.5V
Oscillator Input Sensitivity
Typ.
VCC
With OSC_OUT loaded
VOSC
Min.
100
µA
VCC * 0.3
V
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIH
High Level Input Current
–10
1
10
µA
IIL
Low Level Input Current
–10
1
10
µA
0.4
V
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
IDO(SO)
IDO, Source Current
DATA,
CLOCK,
LE
FO/LD
VP = 3.0V, VDO = V P/2
DO
VP = 5.0V, VDO = V P/2
IDOH(SI)
IDO High, Sink Current
VP = 3.0V, VDO = V P/2
VP = 5.0V, VDO = V P/2
DO
VCC * 0.8
V
2.2
V
–3.2
mA
–3.8
mA
3.2
mA
3.8
mA
∆IDO
IDO Charge Pump Sink
and Source Mismatch
VD O = VP/2
[IIDO(SI)I – IIDO(SO)I]/
[1/2*{IIDO(SI)]I+IIDO(SO)I}]*100%
5
%
IDO vs T
Charge Pump Current
Variation vs. Temperature
–40°C<T<85°C, VDO = V P/2[1]
5
%
IDO-tri
Charge Pump HighImpedance Leakage
Current
±2
nA
Note:
1. IDOVS T; Charge pump current variation vs. temperature.
[IIDO(SI)@T I – IIDO(SI)@25° CI]/IIDO(SI)@25°CI * 100% and
[IIDO(SO)@TI – IIDO(SO)@25°CI]/IIDO(SO)@25°CI *100%.
5
CYW2325
Timing Waveforms
Phase Characteristics
For normal operation, the FC pin is used to select the output polarity of the
phase detector. Both the internal and any external charge pump are affected.
(1)
Depending upon VCO characteristics, FC pin should be set accordingly:
When VCO characteristics are like (1), FC should be set HIGH or OPEN
CIRCUIT:
When VCO characteristics are like (2), FC should be set LOW.
VCO
Output
Frequency
When FC is set HIGH or OPEN CIRCUIT, Fout pin is set to the reference
divider output, Fr. When FC is set LOW, Fout pin is set to the programmable
divider output Fp.
(2)
VCO Input Voltage
Phase Comparator Sense
Phase Detector Output Waveform
FR
FP
tw
tw
LD
DO Charge Pump Output Current Waveform
FR
FP
tw
tw
Do
IDO
Three-state
6
CYW2325
Timing Waveforms (continued)
Serial Data Input Timing Waveform[2, 3, 4, 5]
//
B11 = MSB
DATA
B10
//
B1
A7
A1
//
//
//
//
CNT = LSB
CLOCK
t1
t3
t2
t4
LE
t5
//
//
Serial Data Input
Data is input serially using the DATA, CLOCK, and LE pins.
Two control bits direct data into the locations given in Table 1.
Table 1. Control Configuration
CNT
Function
1
Reference Counter: R = 3 to 16383, set prescaler ratio PRE =0:64/65, PRE=1:32/33
0
Program Counter: A = 0 to 63, B = 3 to 2047
Table 2. Shift Register Configuration[6]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
B9
B10
B11
Reference Counter and Configuration Bits
CNT
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
PRE
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
B8
Programmable Counter Bits
CNT
A1
A2
A3
A4
Bit(s) Name
Function
CNT
Control Bit: Directs programming data to reference or programmable counters.
R1–R14
Reference Counter Setting Bits: 14 bits, R = 3 to 16383.[7]
PRE
Prescaler Divide Bit: LOW = 64/65 and HIGH = 32/33.
A1–A7
Swallow Counter Divide Ratio: A = 0 to 63.
B1–B11
Programmable Counter Divide Ratio: B = 3 to 2047.[7]
Notes:
2. t1–t5 = 50 µs > t > 0.5 µs.
3. CLOCK may remain HIGH after latching in data.
4. DATA is shifted in with the MSB first.
5. For DATA definitions, refer to Table 2.
6. The MSB is loaded in first.
7. Low count ratios may violate frequency limits of the phase detector.
7
CYW2325
Table 3. 7-Bit Swallow Counter (A) Truth Table[8]
Divide Ratio A
A7
A6
A5
A4
A3
A2
A1
0
X
0
0
0
0
0
0
1
X
0
0
0
0
0
1
:::
X
:::
:::
:::
:::
:::
:::
62
X
1
1
1
1
1
0
63
X
1
1
1
1
1
1
Table 4. 11-Bit Programmable Counter (B) Truth Table[9]
Divide Ratio B
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
0
0
0
0
0
0
0
0
0
1
1
3
4
0
0
0
0
0
0
0
0
1
0
0
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
2046
1
1
1
1
1
1
1
1
1
1
0
2047
1
1
1
1
1
1
1
1
1
1
1
Table 5. 14-Bit Programmable Reference Counter Truth Table[9]
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
3
Divide Ratio R
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
1
0
0
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
16382
1
1
1
1
1
1
1
1
1
1
1
1
1
0
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Ordering Information[10]
Ordering Code
CYW2325
Package
Name
Package Type
ZI
20-pin TSSOP (0.173” wide)
TR
Tape and Reel Option
Notes:
8. B is greater than or equal to A.
9. Divide ratio less than 3 is prohibited. The divide ratio can be calculated using the following equation:
fvco = {(P * B) + A} * fosc / R where (A < B)
fvco: Output frequency of the external VCO.
fosc: The crystal reference oscillator frequency.
A: Preset divide ratio of the 7-bit swallow counter.
B: Preset ratio of the 11-bit programmable counter (3 to 2047).
P: Preset divide ratio of the dual modulus prescaler.
R: Preset ratio of the 15-bit programmable reference counter (3 to 16383).
The divide ratio N = (P * B) + A.
10. Operating temperature range: –40°C to +85°C.
Document #: 38-00920
8
CYW2325
Package Diagram
20-Pin Thin Shrink Small Outline Package (TSSOP, 0.173” wide)
Physical Dimensions In Millimeters
20 Lead (0.173" Wide) TSSOP Package Order Number X
20" clear antistatic tubes, 76 units/tube
JEDEC Outline MO-153
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.