ST10F166 16-BIT MCU WITH 256K FLASH MEMORY ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High Performance 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20 MHz CPU Clock 500 ns Multiplication (16 × 16 bit), 1 µs Division (32 / 16 bit) Enhanced Boolean Bit Manipulation Facilities Register-Based Design with Multiple Variable Register Banks Single-Cycle Context Switching Support Up to 256 KBytes Linear Address Space for Code and Data 1 KByte On-Chip RAM 32 KBytes On-Chip Flash EPROM with Bank Erase Feature Protection-Optional Flash Memory Dedicated Flash Control Register with Operation Lock Mechanism 12 V External Flash Programming Voltage Flash Program Verify and Erase Verify Modes 1000 Flash Program/Erase Cycles guaranteed Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus Multiplexed or Demultiplexed External Address/ Data Buses Hold and Hold-Acknowledge Bus Arbitration Support 512 Bytes On-Chip Special Function Register Area Idle and Power Down Modes 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) PQFP100 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 16-Priority-Level Interrupt System 10-Channel 10-bit A/D Converter with 9.7 µs Conversion Time (ST10F166) 16-Channel Capture/Compare Unit Two Multi-Functional General Purpose Timer Units with 5 Timers Two Serial Channels (USARTs) Programmable Watchdog Timer Up to 76 General Purpose I/O Lines Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader 100-Pin Plastic PQFP Package February 1996 This is preliminary information from SGS-THOMSON. Details are subject to change without notice. 1/62 Table of Contents Page Number ST10F166 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 EXTERNAL BUS CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 FLASH MEMORY PROGRAMMING AND ERASURE . . . . . . . . . . . . . . . . . 12 6 FLASH MEMORY SECURITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 CENTRAL PROCESSING UNIT (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 INTERRUPT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 A/D CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SERIAL CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 15 17 20 21 11 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 12 PARALLEL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 13 14 15 16 17 CAPTURE/COMPARE UNIT (CAPCOM) . . . . . . . . . . . . . . . . . . . . . . . . . . GENERAL PURPOSE TIMER (GPT) UNIT . . . . . . . . . . . . . . . . . . . . . . . . SOFTWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INSTRUCTION SET SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPECIAL FUNCTION REGISTER OVERVIEW . . . . . . . . . . . . . . . . . . . . . 23 25 28 31 33 18 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 18.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 18.2 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 18.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 18.4 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 18.5 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 18.6 Memory Cycle Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 18.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 19 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2/62 ST10F166 1 INTRODUCTION The ST10F166 is the FLASH memory members of the ST10 family of microcontrollers developed and produced by SGS-THOMSON Microelectronics in CMOS technology. they combine high CPU performance (up to 10 million instructions per second) with high peripheral functionality, enhanced IO-capabilities and an on-chip reprogrammable 32 KByte Flash Memory. The ST10F166-16 derives its CPU clock signal (operating clock) directly from the onchip oscillator without using a prescaler. With a clock duty cycle of 0.4 to 0.6, the recommended clock frequency is 16MHz for the ST10F166. The ST10F166 operates at half the oscillator clock frequency (using a 2:1 oscillator prescaler). Figure 1. Logic Symbol VDD VSS Port 0 = 16-Bit Port 1 = 16-Bit Port 2 = 16-Bit ST10F160 / F166 Port 3 = 16-Bit Port 4 = 2-Bit VPP/EBC1 Port 5 = 10-Bit VR02058 3/62 ST10F166 VSS VDD Figure 2. Pin Configuration Rectangular PQFP-100 (top view) VDD VS S VSS VDD ST10F160 / ST10F166 VDD VDD VSS VS S VDD VSS VPP / EBC1 VR02056 4/62 ST10F166 Table 1. Pin Definition and Function Symbol Pin Input (I) Number Output (O) 16 - 17 I/O P4.0 – P4.1 16 17 Port 4 is a 2-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: O O P4.0A16Least Significant Segment Addr. Line P4.1A17Most Significant Segment Addr. Line XTAL1:Input to the oscillator amplifier and input to the internal clock generator XTAL2:Output of the oscillator amplifier circuit. XTAL1 20 I XTAL2 19 O BUSACT, 22 23 24 EBC1, EBC0 Function To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. External Bus Configuration selection inputs. These pins are sampled during reset and select either the single chip mode or one of the four external bus configurations: BUSACTEBC1EBC0Mode/Bus Configuration I I I VPP 23 RSTIN 27 I RSTOUT 28 O 5/62 00 0 8-bit demultiplexed bus 00 1 8-bit multiplexed bus 01 0 16-bit muliplexed bus 01 1 16-bit demultiplexed bus 10 0 Single chip mode 10 1 Reserved. 11 0 Reserved. 11 1 Reserved. After reset pin EBC1 accepts the programming voltage for the Flash Memory as an “alternate function”: Flash Memory Programming Voltage V PP = 12 V. Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10R165. An internal pullup resistor permits power-on reset using only a capacitor connected to V SS. Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. ST10F166 Table 1. Pin Definition and Function Symbol NMI Pin Input (I) Number Output (O) 29 I ALE 25 O RD 26 O P1.0 – P1.15 30 - 37 40 - 47 I/O P5.0 – P5.9 48 – 53 56 – 59 I I 62 – 77 P2.0 – P2.15 62 ... 75 76 77 I/O I/O I/O O I/O O I/O I Function Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10R165 to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pull NMI high externally. Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. External Memory Read Strobe. RD is activated for every external instruction or data read access. Port 1 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode.. Port 5 is a 10-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as the (up to 10) analog input channels for the A/D converter, where P5.x equals ANx (Analog input channel x) for ST10F166 & ST10F166-16. Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. The following Port 2 pins also serve for alternate functions: P2.0CC0IOCAPCOM: CC0 Cap.-In/Comp.Out ... ... ... P2.13CC13IOCAPCOM: CC13 Cap.-In/Comp.Out, BREQExternal Bus Request Output P2.14CC14IOCAPCOM: CC14 Cap.-In/Comp.Out, HLDAExternal Bus Hold Acknowl. Output P2.15CC15IOCAPCOM: CC15 Cap.-In/Comp.Out, HOLDExternal Bus Hold Request Input 6/62 ST10F166 Table 1. Pin Definition and Function Symbol P3.0 – P3.15 Pin Input (I) Number Output (O) I/O 80 – 92, I/O 95 – 97 80 81 82 83 84 85 I O I O I I 86 87 I I 88 89 90 91 92 95 96 97 O I/O O I/O O O I O P0.0 – P0.15 98 – 5 8 – 15 I/O VAREF 54 - VAGND 55 - VDD VSS 7/62 7, 18, 38, 61, 79, 93 6, 21, 39, 60, 78, 94 - - Function Port 3 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. The following Port 3 pins also serve for alternate functions: P3.0T0INCAPCOM Timer T0 Count Input P3.1T6OUTGPT2 Timer T6 Toggle Latch Output P3.2CAPINGPT2 Register CAPREL Capture Input P3.3T3OUTGPT1 Timer T3 Toggle Latch Output P3.4T3EUDGPT1 Timer T3 Ext.Up/Down Ctrl.Input P3.5T4INGPT1 Timer T4 Input for Count/Gate/Reload/Capture P3.6T3INGPT1 Timer T3 Count/Gate Input P3.7T2INGPT1 Timer T2 Input for Count/Gate/Reload/Capture P3.8TxD1ASC1 Clock/Data Output (Asyn./Syn.) P3.9RxD1ASC1 Data Input (Asyn.) or I/O (Syn.) P3.10T×D0ASC0 Clock/Data Output (Asyn./Syn.) P3.11R×D0ASC0 Data Input (Asyn.) or I/O (Syn.) P3.12BHEExt. Memory High Byte Enable Signal, P3.13WRExternal Memory Write Strobe P3.14READYReady Signal Input P3.15CLKOUTSystem Clock Output (=CPU Clock) Port 0 is a 16-bit bidirectional IO port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, Port 0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width:8-bit 16-bit P0.0 – P0.7:D0 – D7 D0 - D7 P0.8 – P0.15:output! D8 - D15 Multiplexed bus modes: Data Path Width:8-bit 16-bit P0.0 – P0.7:AD0 – AD7AD0 - AD7 P0.8 – P0.15:A8 - A15 AD8 - AD15 Reference voltage for the A/D converter for ST10F166 & ST10F166-16.. Reference ground for the A/D converter for ST10F166 & ST10F166-16.. Digital Supply Voltage: + 5 V during normal operation and idle mode. ≥ 2.5 V during power down mode Digital Ground. ST10F166 2 MEMORY ORGANIZATION The memory space of the ST10F166 is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which currently includes 256 Kbytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. The ST10F166 contains 32 Kbytes of FLASH EPROM for code or constant data, mapped in segment 0 or in segment 1 by software. A large dual port RAM of 1 Kbyte is provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, . . ., RL7, RH7) called General Purpose Registers (GPRs). 512 bytes of the address space are reserved for the Special Function Register (SFR) area. SFRs are registers which are used for controlling and monitoring functions of the different on-chip units. 118 SFRs are currently implemented. Unused SFR addresses are reserved for future members of the ST10 Family. In order to meet the needs of designs where more memory is required than is provided on chip, up to 256 Kbytes of external RAM and/or ROM can be connected to the microcontroller. 8/62 ST10F166 3 EXTERNAL BUS CONTROLLER All external memory accesses are performed by the on-chip External Bus Controller (EBC). During Reset, it can be programmed to either the Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follow: 16/18 bit Addresses, 8 bit Data, Demultiplexed 16/18 bit Addresses, 8 bit Data, Multiplexed 16/18 bit Addresses, 16 bit Data, Demultiplexed 16/18 bit Addresses, 16 bit Data, Multiplexed In the demultiplexed bus mode, Port 1 is used as an output for addresses and Port 0 is used as an input/output for data. In the multiplexed bus modes, one of the two 16 bit ports, Port 0, is used as an input/output for both addresses and data. For applications which require less than 64 Kbytes of memory space, a non-segmented memory model can be selected. During the initialization phase, the bus configuration and mapping of the Flash Memory to segment 1 may be programmed. After the EINIT instruction, only the external bus configuration can be changed at any time. In this case,all memory locations can be addressed by 16 bits, and thus port 4 is not needed as an output for the two significant address biss (A17 and A16, as is the case when using the segmented memory model. 9/62 Stack Pointer Context Pointer 0FE00h 0FA00h 0FBFFh INTERNAL MEMORY 1 Kbyte Internal RAM System Stack GPRs 0FD00h PEC Source and 0FDFFh Destination Pointers 0FDE0h 512 Bytes Internal SFRs 0FF00h 0FFDFh 0FFFFh 0FFE0h Bit Addressable space 00000h 07FFFh Memory Internal or 20000h Code Segment 2 Code Segment 1 10000h 30000h Code Segement 3 INTERNAL/EXTERNAL MEMORY Code Segment 0 External Memory 64 KBytes External Memory 1FFFFh 32 KBytes 17FFFh External Memoryl or 32 KBytes Internal Internal FLASH FLASH Memory Memory 31,5 KBytes External Memory 0FFFFh 32 KBytes External Memory 64 KBytes External Memory 2FFFFh 3FFFFh ST10F166 Figure 3. Memory Organization 10/62 ST10F166 4 FLASH MEMORY The ST10F166 provides, in addition to the RAM, 32 k bytes of Electrically Erasable and reprogram-mable non-volatile (FLASH) memory. This memory is organised as 8K x 32 bit allowing a complete instruction to be read during one instruction fetch cycle. Data values stored can be read as 16 bit operands using all addressing modes of ST10F166 instruction set. The FLASH memory is located in segment 0 (0 to 07FFFh) during reset, and thus contains the reset and interrupt vectors. To provide full flexibility in the use of the ST10F166, the FLASH memory may be remapped to segment ~ ( 0000 to 17FFFh) during initialization. This allows the interrupt vector to be programmed from external memory, while retaining the common routines and constants programmed into the FLASH memory. For ease of program updating, the FLASH memory is organised into 4 banks, each of which may be independently Erased. Table 2. FLASH memory Bank Organisation 0 Addresses (Segment 0) 00000h to 02FFFh Size (bytes) 12K 1 03000h to 05FFFh 12K 2 06000h to 077FFh 6K 3 07800h to 07FFFh 2K Bank 11/62 ST10F166 5 FLASH MEMORY PROGRAMMING AND ERASURE The FLASH memory is programmed using the PRESTO F Program Write algorithm for reliability. This algorithm provides a typical programming time of 25µs per word and erasing of 1s per bank. Erasure of the FLASH memory is performed in the program mode using the PRESTO F Erase algo-rithm, and operates on the selected bank of the memory. Timing of the Write/Erase cycles is automatically generated by a programmable timer and completion is indicated by a flag. A second flag indicates that the VPP voltage was correct for the whole programming cycle to ensure reliability. The FLASH memory features a typical endurance of 100 Erase/Program cycles. 6 FLASH MEMORY SECURITY Security and reliability are enhanced by the built-in features. A key code sequence is used to enter the Write/Erase mode preventing false write cycles, while a programmable option (set by the programming board) prevent any access to the FLASH memory from the internal RAM or from External Memory. If the security option is set, the FLASH memory is accessed only from program within the FLASH memory area. This protection may be disabled by instructions executed from the FLASH memory only (when not in write/erase mode). 12/62 ST10F166 Figure 4. PRESTO F Program Write Algorithm =0 PCOUNT=PNmax? PCOUNT=PCOUNT+1 VR02057A 13/62 ST10F166 Figure 5. PRESTO F Erase Algorithm =0 PCOUNT=ENmax? PCOUNT=PCOUNT+1 VR02057B 14/62 ST10F166 7 CENTRAL PROCESSING UNIT (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware provide a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the ST10F166 instructions can be executed in just one machine cycle which requires 100 ns at 20 MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. For fast execution: All multiple-cycle instructions have been optimized . A 32-/16 bit division in 1 µs, a 16 × 16 bit multiplication in 0.5 µs, and program branches in 200 ns. Another pipeline optimization, the ’Jump Cache’, allows reducing the execution time of repeatedly performed jumps in a loop from 200 ns to 100 ns. The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at the time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, register banks can also be organized to overlapping. A system stack of up to 512 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. 15/62 ST10F166 C.P.U. (Cont’d) The high performance offered by the hardware implementation of the CPU can efficiently be used by a programmer via the highly functional ST10F166 instruction set which includes the following instruction classes: – Arithmetic Instructions – Logical Instructions – Boolean Bit Manipulation Instructions – Compare and Loop Control Instructions – Shift and Rotate Instructions – Prioritize Instruction – Data Movement Instructions – System Stack Instructions – Jump and Call Instructions – Return Instructions – System Control Instructions – Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands Figure 6. CPU Block Diagram 16/62 ST10F166 8 INTERRUPT SYSTEM With an interrupt response time within a range from 250 ns to 500 ns (in case of internal program execution), the ST10F166 is capable of reacting very fast to the occurance of non-deterministic events. The architecture of the ST10F166 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ’stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an optional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when operating in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corres-ponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data, or for transferring A/D converted results to a memory table. The ST10F166 has 8 PEC chan-nels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bit field exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Software interrupts are supported by means of the ’TRAP’ instruction in combination with an individual trap (interrupt) number. The ST10F166 also provides an efficient mechanism to identify and to process ’HardwareTraps’ exceptions or error conditions that arise during run-time. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). 17/62 ST10F166 Interrupt System (Cont’d) The following table shows all of the possible ST10F166 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Table 3. Interrupt Sources and Hardware Location Source of Interrupt or PEC Service Request Request Flag CAPCOM Register 0 CAPCOM Register1 CC0IR CC1IR CAPCOM Register 2 CAPCOM Register 3 Enable Flag Interrupt Vector Vector Location Trap Number CC0IE CC1IE CC0INT CC1INT 40h 44h 10h 11h CC2IR CC3IR CC2IE CC3IE CC2INT CC3INT 48h 4Ch 12h 13h CAPCOM Register 4 CC4IR CC4IE CC4INT 50h 14h CAPCOM Register 5 CC5IR CC5IE CC5INT 54h 15h CAPCOM Register 6 CAPCOM Register 7 CC6IR CC7IR CC6IE CC7IE CC6INT CC7INT 58h 5Ch 16h 17h CAPCOM Register 8 CAPCOM Register 9 CC8IR CC9IR CC8IE CC9IE CC8INT CC9INT 60h 64h 18h 19h CAPCOM Register 10 CC10IR CC10IE CC10INT 68h 1Ah CAPCOM Register 11 CC11IR CC11IE CC11INT 6Ch 1Bh CAPCOM Register 12 CAPCOM Register 13 CC12IR CC13IR CC12IE CC13IE CC12INT CC13INT 70h 74h 1Ch 1Dh CAPCOM Register 14 CAPCOM Register 15 CC14IR CC15IR CC14IE CC15IE CC14INT CC15INT 78h 7Ch 1Eh 1Fh CAPCOM Timer 0 T0IR T0IE T0INT 80h 20h CAPCOM Timer 1 T1IR T1IE T1INT 84h 21h GPT 1 Timer 2 GPT 1 Timer 3 T2IR T3IR T2IE T3IE T2INT T3INT 88h 8Ch 22h 23h GPT 1 Timer 4 GPT 1 Timer 5 T4IR T5IR T4IE T5IE T4INT T5INT 90h 94h 24h 25h GPT 1 Timer 6 T6IR T6IE T6INT 98h 26h GPT 2 CAPREL Register CRIR CRIE CRINT 9Ch 27h A/D Conversion Complete A/D Overrun Error ADCIR ADEIR ADCIE ADEIE ADCINT ADEINT A0h A4h 28h 29h Serial Channel 0 Transmit Serial Channel 0 Receive S0TIR S0RIR S0TIE S0RIE S0TINT S0RINT A8h ACh 2Ah 2Bh Serial Channel 0 Error S0EIR S0EIE S0EINT B0h 2Ch Serial Channel 1 Transmit S1TIR S1TIE S1TINT B4h 2Dh Serial Channel 1 Receive Serial Channel 1 Error S1RIR S1EIR S1RIE S1EIE S1RINT S1EINT B8h BCh 2Eh 2Fh 18/62 ST10F166 Interrupt System (Cont’d) Except when another higher prioritized trap service being in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during run-time: Table 4. Exceptions and Errors during Runtime Exception Condition Trap Flag Trap Vector Vector Location Trap Number Trap priority Reset Functions: Hardware Reset RESET 0h 0h III Software Reset Watchdog Timer Overflow RESET RESET 0h 0h 0h 0h III III 08h 2h II 10h 18h 4h 6h II II Class A Hardware Traps: NMITRAP Non-Maskable Interrupt NMI Stack Overflow Stack Underflow STKOF STKUF STOPTRAP STUTRAP Undefined Opcode UNDOPC BTRAP 28h Ah I Protected Instruction Fault Illegal Word Operand Access PRTFLT ILLOPA BTRAP BTRAP 28h 28h Ah Ah I I Illegal Instruction Access Illegal External Bus Access ILLINA ILLBUS BTRAP BTRAP 28h 28h Ah Ah I I Reserved [2Ch - 3Ch] [Bh - Fh] Software Traps Any [0h - 1FCh] in steps of 4h Class B Hardware Traps: TRAP Instruction 19/62 Any [0h - 7Fh] Current CPU Priority ST10F166 9 A/D CONVERTER For analog signal measurement, a 10-bit A/D converter with 10 multiplexed input channels, a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation which returns the conversion result for an analog channel within 9.75 µs (@fosc = 40 MHz). Overrun error detection capability is provided for the conversion result register (ADDAT): an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete. For applications which require less than 10 analog input channels, the remaining channels can be used as digital input port pins. The A/D converter of the ST10F166 supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is once sampled and converted into a digital result. In the Single Channel Continuous mode, the analog level is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. 20/62 ST10F166 10 SERIAL CHANNELS Serial communication with other microcontrollers, processors, terminals, or external peripheral components is provided by two serial interfaces with identical functionality, Serial Channel 0 (ASC0) and Serial Channel 1 (ASC1). They support full-duplex asynchronous communication up to 625 Kbaud and half-duplex synchronous communication up to 2.5 Mbaud. Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning. For transmission, reception, and erroneous reception 3 separate interrupt vectors are provided for each serial channel. In the synchronous mode, one data byte is transmitted or received synchronously to a shift clock which is generated by the ST10F166. In the asynchronous mode, an 8or 9-bit data frame is transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data + wake up bit mode), and a loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. 21/62 ST10F166 11 WATCHDOG TIMER The Watchdog Timer of the ST10F166 represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer of the ST10F166 is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored. When the software has been designed to service the Watchdog Timer before it overflows, the Watchdog Timer times out if the program does not progress properly due to hardware or software related failures. When the Watchdog Timer overflows, it generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to reset. The Watchdog Timer of the ST10F166 is a 16-bit timer which can either be clocked with fosc/4 or fosc/256. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 25 µs and 420 ms can be monitored (@fosc = 40 MHz). The default Watch-dog Timer interval after reset is 6.55 ms. 12 PARALLEL PORTS The ST10F166 provides 76 I/O lines which are organized into four 16-bit I/O ports (Port 0 through 3), one 2-bit I/O port (Port 4), and one 10-bit input port (Port 5). All port lines are bit addressable, and all lines of Port 0 through 4 are individually bit programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to the high impedance state when configured as inputs. During the internal reset, all port pins are configured as inputs. Each port line has one programmable alternate input or output function associated with it. Ports 0 and 1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A16 and A17 in systems where segmentation is enabled to access more than 64 Kbytes of memory. Port 2 is associated with the capture inputs/compare outputs of the CAPCOM unit, and Port 3 includes alternate functions of timers, serial interfaces, optional bus control signals (WR, BHE, READY), and the system clock output (CLKOUT). Port 5 is used for the analog input channels to the A/D converter. When none of the alternate functions is not used, the respective port line may be used as general purpose I/O line. 22/62 ST10F166 13 CAPTURE/COMPARE UNIT (CAPCOM) The CAPCOM unit supports generation and control of timing sequences on up to 16 channels, with a maximum resolution of 400 ns. The CAPCOM unit is typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PWM), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Two 16-bit timers (T0/T1) with reload registers provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustment to the application specific requirements. In addition, an external count input for CAPCOM timer T0 allows event scheduling for the capture/compare registers relative to external events. The capture/compare register array contains 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1, and programmed for capture or compare function. Each register has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (’captured’) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode. 23/62 ST10F166 CAPCOM (Cont’d) Table 5. Compare Modes Compare Modes Mode 0 Functions Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated Mode 3 Pin set to ’1’ on match; pin reset to ’0’ on compare timer overflow; only one compare event per timer period is generated Double Register Mode Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible. Figure 7. CAPCOM Block Diagram 24/62 ST10F166 14 GENERAL PURPOSE TIMER (GPT) UNIT The GPT unit represents a very flexible multifunctional timer counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for one of three basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the input clock for a timer is derived from the internal system clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the ’gate’ level on an external input pin. For these purposes, each timer has one associated port pin (T2IN, T3IN, T4IN) which serves as gate or clock input. The maximum resolution of the timers in the GPT1 module is 400 ns (@fosc = 40 MHz). The count direction (up/down) for each timer is programmable by software. For timer T3, the count direction may additionally be altered dynamically by an external signal on a port pin (T3EUD) to facilitate functions such as position tracking. Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on a port pin (T3OUT) e. g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. 25/62 ST10F166 G.P.T. (Cont’d) In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 are captured into T2 or T4 in response to a signal at their associated input pins (T2IN, T4IN). Timer T3 is reloaded with the contents of T2 or T4 either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. With its maximum resolution of 200 ns (@fosc = 40 MHz), the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can independently count up or down, clocked with an input clock which is derived from a programmable prescaler. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the same signal transition. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. 26/62 ST10F166 G.P.T. (Cont’d) Figure 8. GPT1 Block Diagram System Clock (fosc2) /2n n=3...10 T2 Mode Reload U/D Control Capture T2in-P3.7 System Clock (fosc2) Interrupt Request GPT1 Timer T2 /2n n=3...10 T3in-P3.6 T3 Mode Control GPT1 Timer T3 U/D T3out-P3.3 T3OTL Toggle FF T3Eud-P3.4 Capture T4in-P3.5 System Clock (fosc2) /2n n=3...10 T4 Reload Mode Control GPT1 Timer T4 U/D Interrupt Request VR02074A Figure 9. GPT2 Block Diagram System Clock (fosc2) /2n n=2...9 Input Control Interrupt Request GPT2 Timer T5 Clear U/D CAPin-P3.2 Interrupt Request GPT2 CAPREL Interrupt Request To CAPCOM Timers T0,T1 System Clock (fosc2) /2n n=2...9 GPT2 Timer T6 U/D T6OTL T6out-P3.1 Toggle FF VR02074B 27/62 ST10F166 15 SOFTWARE DESCRIPTION Addressing Modes The ST10F166 offers different powerful addressing modes to facilitate rapid access on word, byte and bit data, or to specify the destination address of a branch instruction. The addressing modes are subdivided in six different categories as follows. Short addressing modes: an implicit base offset address is used to specify a physical 18-bit address. EA = Base Address + k Short Address. k = 1 or 2 EA = Effective Address This mode allows direct access to any GPR or SFR and any word in the bit-addressable memory space. (in case of a byte operation on an SFR, only the low byte can be accessed via ‘reg’). Long addressing modes: one of the four DPP registers, selected by bit 15 and 14 of the 16-bit address, is used to specify a physical 18-bit address. EA = Contents of DPPi + Page Offset Address i: specified by bit 15, 14 of the 16 bit address. Page Offset Address: bit 13 to 0 of the 16 bit address. In this mode, any word or byte data within the entire memory space can be accessed directly . Word accesses may not be performed on odd byte addresses, otherwise a hardware trap will occur. Indirect addressing modes: a 16-bit long address is specified indirectly by the contents of a word GPR which is specified directly by a short address. Any word GPR can be used, except for arithmetic, logical and compare instructions, where only R0 to R3 are allowed. There are also certain modes which allow decrementing or incrementing the indirect address pointers by a data-type-dependent value. Long Address = [GPR Address] + Constant EA = Contents of DPPi + Page Offset Address i: specified by bit 15, 14 of the Long Address. Page Offset Address: bit 13 to 0 of the long address Long Address Long Address bit15,14 specify i bit 13 to 0 28/62 ST10F166 Immediate data: these data are represented in the instruction formats by either 3,4,8 or 16 bits. Branch target addressing modes: to specify the destination address and segment of jump or call instructions, relative, absolute and indirect modes can be used to update the Instruction Pointer (IP) register while the Code Segment Pointer (CSP) register can be updated only with absolute values. Condition Flags: The condition flags of the PSW register (N,C,V,Z,E) indicate the ALU status due to the last performed ALU operation. They are set by most of the instructions due to specific rules which depend on the ALU or data movement operation performed by an instruction. If the PSW register is the destination operand of an instruction, the PSW flags do NOT represent the condition flags of this instruction as usual. E: End of a table in a table search operation Z: Zero V: Overflow C: Carry N: Negative 29/62 ST10F166 Software Description (Cont’d) Table 6. Addressing Mode Summary Addressing Mode 3 bit Immediate Data Notation #data3 4 bit Immediate Data 8 bit Immediate Data #data4 #data8 16 bit Immediate Data #data16 8 bit Immediate Mask #mask GPR register direct Rw SFR or GPR register direct reg Memory direct Mem Memory indirect [Rw] Memory indirect with Post-increment Memory indirect with Pre-decrement [Rw+] [-Rw] Memory indirect with a 16-bit cinstant [Rw+#data16] Direct Word Offset bitoff Bit Address bitaddr.b Rb Table 7. Condition Code Summary UC Z NZ V NV N NN C NC EQ NE ULT UGE ULE UGT SLT SGE SLE SGT NET Unconditional Zero No Zero Overflow No Overflow Negative Not Negative Carry No Carry Equal Not Equal Unsigned Less Than Unsigned Greater Than or Equal Unsigned Less Than or Equal Unsigned Greater Than Signed Less Than Signed Greater Than or Equal Signed Less Than or Equal Signed Greater Than Not Equal AND Not End of Table 1=1 Z=1 Z=0 V=1 V=0 N=1 N=0 C=1 C=0 Z=1 Z=0 C=1 C=0 (Z or C)=1 (Z or C)=0 (N xor V)=1 (N xor V)=0 (Z or (N xor V))=1 (Z or (N xor V))=0 (Z or E)=0 30/62 ST10F166 16 INSTRUCTION SET SUMMARY The table below lists the instructions of the ST10F166 in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “ST10 Programming Manual”. This document also provides a detailed description of each instruction. Mnemonic ADD(B) Description Add word (byte) operands Bytes 2/4 ADDC(B) SUB(B) Add word (byte) operands with Carry Subtract word (byte) operands 2/4 2/4 SUBC(B) Subtract word (byte) operands with Carry 2/4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2 DIV(U) DIVL(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 2 CPL(B) NEG(B) Complement direct word (byte) GPR Negate direct word (byte) GPR 2 2 AND(B) Bitwise AND, (word/byte operands) 2/4 OR(B) Bitwise OR, (word/byte operands) 2/4 XOR(B) BCLR Bitwise XOR, (word/byte operands) Clear direct bit 2/4 2 BSET BMOV(N) Set direct bit Move (negated) direct bit to direct bit 2 4 BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 CMP(B) Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2/4 CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2/4 BFLDH/L 4 2/4 SHL / SHR Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR ROL / ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2 MOV(B) Move word (byte) data 2/4 PRIOR 31/62 2 2 ST10F166 Instruction Set Summary (Cont’d) Mnemonic Description Bytes MOVBS MOVBZ Move byte operand to word operand with sign extension Move byte operand to word operand. with zero extension 2/4 2/4 JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4 JMPS Jump absolute to a code segment 4 J(N)B JBC Jump relative if direct bit is (not) set Jump relative and clear bit if direct bit is set 4 4 JNBS CALLA, CALLI, CALLR Jump relative and set bit if direct bit is not set Call absolute/indirect/relative subroutine if condition is met 4 4 CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call absolute subroutine 4 TRAP PUSH, POP Call interrupt service routine via immediate trap number Push/pop direct word register onto/from system stack 2 2 SCXT RET RETS Push direct word register onto system stack and update register with word operand Return from intra-segment subroutine 4 2 Return from inter-segment subroutine Return from intra-segment subroutine and pop direct word register from system stack 2 RETI SRST Return from interrupt service subroutine Software Reset 2 4 IDLE 4 4 SRVWDT Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer DISWDT EINIT Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin 4 4 NOP Null operation 2 RETP PWRDN 2 4 32/62 ST10F166 17 SPECIAL FUNCTION REGISTER OVERVIEW The following table lists all SFRs which are implemented in the ST10F166 in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers). Name Physical Address 8-Bit Address Description Reset Value ADCIC b FF98h CCh A/D Converter End of Conversion Interrupt Control Register 0000h ADCON ADDAT b FFA0h FEA0h D0h 50h A/D Converter Control Register A/D Converter Result Register 0000h 0000h FE18h 0Ch Address Select Register 0000h 0000h ADDRSEL1 b FF9Ah CDh A/D Converter Overrun Error Interrupt Control Register BUSCON1 b FF14h 8Ah Bus Configuration Register 0000h CAPREL FE4Ah 25h GPT2 Capture/Reload Register 0000h b FE80h FF78h 40h BCh CAPCOM Register 0 CAPCOM Register 0 Interrupt Control Register 0000h 0000h b FE82h FF7Ah 41h BDh CAPCOM Register 1 CAPCOM Register 1 Interrupt Control Register 0000h 0000h FE84h 42h CAPCOM Register 2 0000h b FF7Ch BEh CAPCOM Register 2 Interrupt Control Register 0000h CC3 CC3IC b FE86h FF7Eh 43h BFh CAPCOM Register 3 CAPCOM Register 3 Interrupt Control Register 0000h 0000h CC4 CC4IC b FE88h FF80h 44h C0h CAPCOM Register 4 CAPCOM Register 4 Interrupt Control Register 0000h 0000h FE8Ah 45h CAPCOM Register 5 0000h ADEIC CC0 CC0IC CC1 CC1IC CC2 CC2IC CC5 CC5IC b FF82h C1h CAPCOM Register 5 Interrupt Control Register 0000h CC6 CC6IC b FE8Ch FF84h 46h C2h CAPCOM Register 6 CAPCOM Register 6 Interrupt Control Register 0000h 0000h b FE8Eh FF86h 47h C3h CAPCOM Register 7 CAPCOM Register 7 Interrupt Control Register 0000h 0000h FE90h 48h CAPCOM Register 8 0000h FF88h C4h CAPCOM Register 8 Interrupt Control Register 0000h CC7 CC7IC CC8 CC8IC 33/62 b ST10F166 Special Function Register Overview (Cont’d) Name CC9 Physical Address 8-Bit Address FE92h 49h CAPCOM Register 9 0000h Description Reset Value CC9IC CC10 b FF8Ah FE94h C5h 4Ah CAPCOM Register 9 Interrupt Control Register CAPCOM Register 10 0000h 0000h CC10IC CC11 b FF8Ch FE96h C6h 4Bh CAPCOM Register 10 Interrupt Control Register CAPCOM Register 11 0000h 0000h CC11IC b FF8Eh C7h CAPCOM Register 11 Interrupt Control Register 0000h FE98h 4Ch CAPCOM Register 12 0000h CC12 CC12IC CC13 b FF90h FE9Ah C8h 4Dh CAPCOM Register 12 Interrupt Control Register CAPCOM Register 13 0000h 0000h CC13IC CC14 b FF92h FE9Ch C9h 4Eh CAPCOM Register 13 Interrupt Control Register CAPCOM Register 14 0000h 0000h CC14IC b FF94h CAh CAPCOM Register 14 Interrupt Control Register 0000h FE9Eh 4Fh CAPCOM Register 15 0000h CC15 CC15IC b FF96h CBh CAPCOM Register 15 Interrupt Control Register 0000h CCM0 CCM b b FF52h FF54h A9h AAh CAPCOM Mode Control Register 0 CAPCOM Mode Control Register 1 0000h 0000h CCM2 CCM3 b b FF56h FF58h ABh ACh CAPCOM Mode Control Register 2 CAPCOM Mode Control Register 3 0000h 0000h FE10h 08h CPU Context Pointer Register FC00h FF6Ah B5h GPT2 CAPREL Interrupt Control Register 0000h FE08h 04h CPU Code Segment Pointer Register (2 bits, read only) 0000h CP CRIC b CSP DP0 b FF02h 81h Port 0 Direction Control Register 0000h DP1 DP2 b b FF06h FFC2h 83h E1h Port 1 Direction Control Register Port 2 Direction Control Register 0000h 0000h DP3 DP4 b b FFC6h FF0Ah E3h 85h Port 3 Direction Control Register Port 4 Direction Control Register (2 bits) 0000h 0000h DPP0 FE00h 00h CPU Data Page Pointer 0 Register (4 bits) 0000h DPP1 FE02h 01h CPU Data Page Pointer 1 Register (4 bits) 0001h DPP2 DPP3 FE04h FE06h 02h 03h CPU Data Page Pointer 2 Register (4 bits) CPU Data Page Pointer 3 Register (4 bits) 0002h 0003h FF0Eh FE0Ch 87h 06h CPU Multiply Divide Control Register CPU Multiply Divide Register – High Word 0000h 0000h MDL FE0Eh 07h CPU Multiply Divide Register – Low Word 0000h ONES FF1Eh 8Fh Constand Value 1’s Register (read only) FFFFh FF00h 80h Port 0 Register 0000h MDC MDH P0 b b 34/62 ST10F166 Special Function Register Overview (Cont’d) Name Physical Address 8-Bit Address Description Reset Value P1 b FF04h 82h Port 1 Register 0000h P2 P3 b b FFC0h FFC4h E0h E2h Port 2 Register Port 3 Register 0000h 0000h P4 P5 b b FF08h FFA2h 84h D1h Port 4 Register (2 bits) Port 5 Register (10 bits, read only) 0000h XXXXh PECC0 FEC0h 60h PEC Channel 0 Control Register 0000h PECC1 FEC2h 61h PEC Channel 1 Control Register 0000h PECC2 PECC3 FEC4h FEC6h 62h 63h PEC Channel 2 Control Register PEC Channel 3 Control Register 0000h 0000h PECC4 PECC5 FEC8h FECAh 64h 65h PEC Channel 4 Control Register PECChannel 5 Control Register 0000h 0000h PECC6 FECCh 66h PEC Channel 6 Control Register 0000h PECC7 FECEh 67h PEC Channel 7 Control Register 0000h FF10h 88h FEB4h 5Ah CPU Program Status Word 0000h Serial Channel 0 Baud Rate Generator Reload Reg0000h ister PSW b S0BG S0CON b FFB0h D8h Serial Channel 0 Control Register 0000h S0EIC S0RBUF b FF70h FEB2h B8h 59 Serial Channel 0 Error Interrupt Control Register Serial Channel 0 Receive Buffer Register (read only) 0000h XXXXh S0RIC b FF6Eh B7h 0000h FEB0h 58h Serial Channel 0 Receive Interrupt Control Register Serial Channel 0 Transmit Buffer Register (write only) FF6Ch B6h 0000h FEBCh 5Eh Serial Channel 0 Transmit Interrupt Control Register Serial Channel 1 Baud Rate Generator Reload Register FFB8h FF76h DCh BBh Serial Channel 1 Control Register Serial Channel 1 Error Interrupt Control Register 0000h 0000h FEBAh 5Dh Serial Channel 1 Receive Buffer Register (read only) XXXXh FF74h BAh Serial Channel 1 Receive Interrupt Control Register 0000h FEB8h 5Ch Serial Channel 1 Transmit Buffer Register (write only) 0000h S0TBUF S0TIC b S1BG S1CON S1EIC b b S1RBUF S1RIC b S1TBUF S1TIC 0000h FF72h B9h Serial Channel 1 Transmit Interrupt Control Register 0000h SP STKOV FE12h FE14h 09h 0Ah CPU System Stack Pointer Register CPU Stack Overflow Pointer Register FC00h FA00h STKUN SYSCON b FE16h FF0Ch 0Bh 86h CPU Stack Underflow Pointer Register CPU System Configuration Register FC00h 0XX0h*) T0 FE50h 28h CAPCOM Timer 0 Register 0000h FF50h A8h CAPCOM Timer 0 and Timer 1 Control Register 0000h T01CON 35/62 b 0000h b ST10F166 Special Function Register Overview (Cont’d) Name T0IC b T0REL T1 T1IC T1REL b T2 Physical Address 8-Bit Address FF9Ch CEh CAPCOM Timer 0 Interrupt Control Register 0000h FE54h FE52h 2Ah 29h CAPCOM Timer 0 Reload Register CAPCOM Timer 1 Register 0000h 0000h FF9Eh FE56h CFh 2Bh CAPCOM Timer 1 Interrupt Control Register CAPCOM Timer 1 Reload Register 0000h 0000h Description Reset Value FE40h 20h GPT1 Timer 2 Register 0000h T2CON b FF40h A0h GPT1 Timer 2 Control Register 0000h T2IC T3 b FF60h FE42h B0h 21h GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Register 0000h 0000h T3CON T3IC b b FF42h FF62h A1h B1h GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register 0000h 0000h FE44h 22h GPT1 Timer 4 Register 0000h T4 T4CON b FF44h A2h GPT1 Timer 4 Control Register 0000h T4IC T5 b FF64h FE46h B2h 23h GPT1 Timer 4 Interrupt Control Register GPT2 Timer 5 Register 0000h 0000h T5CON T5IC b b FF46h FF66h A3h B3h GPT2 Timer 5 Control Register GPT2 Timer 5 Interrupt Control Register 0000h 0000h T6 FE48h 24h GPT2 Timer 6 Register 0000h T6CON b FF48h A4h GPT2 Timer 6 Control Register 0000h T6IC b FF68h B4h GPT2 Timer 6 Interrupt Control Register 0000h TFR WDT b FFACh FEAEh D6h 57h Trap Flag Register Watchdog Timer Register (read only) 0000h 0000h WDTCON ZEROS b FFAEh FF1Ch D7h 8Eh Watchdog Timer Control Register Constant Value 0’s Register (read only) 0000h 0000h *) The system configuration is selected during reset. 36/62 ST10F166 18 ELECTRICAL CHARACTERISTICS 18.1 Absolute Maximum Ratings Ambient temperature under bias (T A): . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +70 °C Storage temperature (TST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65 to +125 °C Voltage on VCC pins with respect to ground (VSS) . . . . . . . . . . . . . . . . . –0.5 to +6.5 V Voltage on any pin with respect to ground (VSS) . . . . . . . . . . . . . –0.3 to VCC +0.3 V Input current on any pin during overload condition . . . . . . . . . . . . . . -10 to +10 mA. Absolute sum of all input currents during overload condition . . . . . . . . . . . .100 mA. Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5 W Flash programming voltage (VPP). . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 to + 13.5 V Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN>VCC or VIN<VSS) the voltage on pins with respect to ground (VSS) must not exceed the values defined by the Absolute Maximum Ratings. 18.2 Parameter Interpretation The parameters listed in the following partly represent the characteristics of the ST10R165 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (Controller Characteristics): The logic of the ST10R165 will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the ST10R165. 37/62 ST10F166 18.3 DC Characteristics VCC = 5 V ± 10 %; TA = 0 to +70 °C VSS = 0 V; fCPU = 20 MHz for ST10F166/166-16 Parameter Symbol Limit Values min. max. Unit Test Condition Input low voltage EBC1/V PP VIL1 SR – 0.3 0.2 VCC – 0.1 V – Input low voltage (all except EBC1/VPP) VIL2 SR – 0.5 0.2 VCC – 0.1 V – Input high voltage (all except RSTIN and XTAL1) VIH SR 0.2 VCC + 0.9 VCC + 0.5 V – Input high voltage RSTIN VIH1 SR 0.6 VCC VCC + 0.5 V – Input high voltage XTAL1 VIH2 SR 0.7 VCC VCC + 0.5 V – Output low voltage (Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) VOL CC – 0.45 V IOL = 2.4 mA Output low voltage (all other outputs) VOL1 CC – 0.45 V IOL1 = 1.6 mA Output high voltage (Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) VOH CC 0.9 VCC 2.4 – V V IOH = – 500 µA IOH = – 2.4 mA Output high voltage (all other outputs) VOH1 CC 0.9 VCC 2.4 – V V IOH = – 250 µA IOH = – 1.6 mA IOZ1 CC – ±5008) nA 0 V < VIN < VCC Input leakage current (all other) IOZ2 CC – ±18) µA 0 V < VIN < VCC VPP leakage current EBC1/V PP IPPS CC – ±100 µA 0 ≤ VPP ≤ VCC RRST CC 50 150 kΩ IRH 3) – -40 µA VOUT = VOHmin IRL 4) -500 – µA VOUT = VOLmax Input leakage current (Port 5) RSTIN pullup resistor 6) 5) Read inactive current 5) Read active current ALE inactive current ALE active current 5) XTAL1 input current 5) 1) – IALEL 3) – 150 µA VOUT = VOLmax IALEH 4) 2100 – µA VOUT = VOHmin – ±20 µA 0 V < VIN < VCC IIL CC 38/62 ST10F166 DC Characteristics (Cont’d) Parameter Symbol Limit Values min. max. – 10 Unit Test Condition Pin capacitance 6) (digital inputs/outputs) CIO Power supply current ICC – Idle mode supply current IID – Power-down mode supply current IPD TBD TBD µA – IPPR – 200 µA VPP > VCC 1/TCL = 40 MHz 32-bit programming VPP = 12 V VPP read current 6) CC 80 + 5 * f CPU 35 + 1.5 * fCPU pF mA mA VPP write current 6) IPPW – 50 mA VPP during write/read VPP 11.4 12.6 V f = 1 MHz TA = 25 °C RSTIN = VIL2 fCPU in [MHz] RSTIN = VIH1 fCPU in [MHz] 7) 7) Notes: 1) This specification does not apply to the analog input (Port 5.x) which is currently converted. 3) The maximum current may be drawn while the respective signal line remains inactive. 4) The minimum current must be drawn in order to drive the respective signal line active. 5) This specification is only valid during Reset, or during Hold-mode. 6) Not 100% tested, guaranteed by design characterization. 7) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at V CCmax and 20 MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. 8) 39/62 This value is guaranteed also after ESD qualification trials at 25 degrees ST10F166 DC Characteristics (Cont’d) Figure 10. Supply/Idle Current as a Function of Operating Frequency Current (mA) 250 ICC Iid 200 150 100 50 0 0 5 10 CPU Frequency (MHz) 15 20 VR02049 40/62 ST10F166 18.4 A/D Converter Characteristics VCC = 5 V ± 10 %; VSS = 0 V TA = 0 to +70 °C for ST10F166/166-16 4.0 V ≤ VAREF ≤ VCC+0.1 V; VSS-0.1 V ≤ VAGND ≤ VSS+0.2 V Parameter Symbol Limit Values min. max. VAREF Unit V Test Condition Analog input voltage range VAIN SR VAGND 1) Sample time tS CC – 2 tSC 2) 4) 3) 4) Conversion time tC CC – 10 tCC + tS + 4TCL Total unadjusted error TUE CC – ±3 LSB 5) Internal resistance of reference voltage source 7) RAREF CC – tCC / 250 - 0.25 kΩ tCC in [ns] 6) 7) Internal resistance of analog source 7) RASRC CC – tS / 500 - 0.25 kΩ tS in [ns] 2) 7) ADC input capacitance 7) CAIN – 50 pF 7) VAREF Supply Current IREF – 5 mA CC Notes: 41/62 1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FF H, respectively. 2) During the sample time the input capacitance CI can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitors to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. The value for the sample clock is tSC = TCL * 32. 3) This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. The value for the conversion clock is tCC = TCL * 32. 4) This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. 5) TUE is tested at VAREF=5.0V, VAGND=0V, VCC=4.8V. It is guaranteed by design characterization for all other voltages within the defined voltage range. 6) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitors to reach their respective voltage level within tCC. The maximum internal resistance results from the CPU clock period. 7) Not 100% tested, guaranteed by design characterization. ST10F166 18.5 Testing Waveforms Figure 11. Input Output Waveforms AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.4 V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 12. Float Waveforms For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a100mV change from the loaded VOH/VOL leveloccurs (IOH/IOL = 20 mA). 18.6 Memory Cycle Variables The timing tables below use three variables which are derived from registers SYSCON and BUSCON1 and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Description Symbol Values ALE Extension tA TCL * <ALECTL> Memory Cycle Time Waitstates tC 2TCL * (15 - <MCTC>) Memory Tristate Time tF 2TCL * (1 - <MTTC>) 42/62 ST10F166 18.7 AC Characteristics The specification of the timings depends on the CPU clock signal that is used in the respective device. In this regard the specification for the ST10F166 and the ST10F166-16 are different. While the ST10F166-16 directly uses the clock signal fed to XTAL1 and therefore has to take into account the duty cycle variation of this signal, the ST10F166 derives its CPU clock from the XTAL1 signal via a 2:1 prescaler and therefore is independant from these variations. For these reasons the following pages provide the timing specifications for ST10F166 and for ST10F166-16 separately (where applicable). External Clock Drive XTAL1 for the ST10F166 VCC = 5 V ± 10 %; TA = 0 to +70 °C Parameter VSS = 0 V Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit Oscillator period TCL SR min. 25 High time t1 SR 6 – 6 – ns Low time t2 SR 6 – 6 – ns Rise time Fall time t3 t4 SR SR – – 5 5 – – 5 5 ns ns Figure 13. External Clock Drive XTAL1 43/62 max. 25 min. 25 max. 500 ns ST10F166 AC Characteristics (Cont’d) External Clock Drive XTAL1 for the ST10F166-16 VCC = 5 V ± 10 %;VSS = 0 V TA = 0 to +70 °C Parameter Oscillator period Symbol CPU Clock = 16 MHz Duty cycle 0.4 to 0.6 min. max. Variable CPU Clock 1/CLP = 1 to 20 MHz min. max. CLP SR 62.5 62.5 50 Unit 1000 ns High time TCLH SR 25 – 25 CLP-TCLL ns Low time Rise time TCLL tR SR SR 25 – – 10 25 – CLP-TCLH 10 ns ns Fall time Oscillator duty cycle tF DC SR SR – 0.4 10 0.6 – 25 / CLP 10 1 - 25 / CLP ns Clock cycle TCL SR 25 37.5 CLP * DCmin CLP * DCmax ns Note: In order to run the ST10F166-16 at a CPU clock of 20 MHz the duty cycle of the oscillator clock must be 0.5, ie. the relation between the oscillator high and low phases must be 1:1. So the variation of the duty cycle of the oscillator clock limits the maximum operating speed of the device. The 16 MHz values in the tables are given as an example for a typical duty cycle variation of the oscillator clock from 0.4 to 0.6. Figure 14. External Clock Drive XTAL1 44/62 ST10F166 AC Characteristics (Cont’d) Multiplexed Bus for the ST10F166 VCC = 5 V ± 10 %;VSS = 0 V TA = 0 to +70 °C CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20-MHz CPU clock without waitstates) Parameter ALE high time Symbol Max. CPU Clock = 20 MHz min. max. t5 15 + tA – TCL - 10 + tA – ns CC Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. Uni t Address setup to ALE t6 CC 10 + tA – TCL - 15 + tA – ns Address hold after ALE ALE falling edge to RD, WR (with RW-delay) t7 CC 15 + tA – TCL - 10 + tA – ns t8 CC 15 + tA – TCL - 10 + tA – ns t9 CC -10 + tA – -10 + tA – ns t10 CC – 5 – 5 ns t11 CC – 30 – TCL + 5 ns t12 CC 40 + tC – 2TCL - 10 + tC – ns t13 CC 65 + tC – 3TCL - 10 + tC – ns RD to valid data in (with RW-delay) t14 SR – 30 + tC – 2TCL - 20 + tC ns RD to valid data in (no RW-delay) t15 SR – 55 + tC – ALE low to valid data in t16 SR – 55 + tA + tC – Address to valid data in t17 SR – 75 + 2tA + tC – 4TCL - 25 + 2tA + t C ns Data hold after RD rising edge t18 SR 0 – 0 – ns Data float after RD t19 SR – 35 + tF – 2TCL - 15 + tF ns Data valid to WR Data hold after WR t22 t23 CC CC 35 + tC 35 + tF – – 2TCL - 15 + tC 2TCL - 15 + tF – – ns ns ALE rising edge after RD, WR t25 Address hold after RD, WR t27 CC CC 35 + tF 35 + tF – – 2TCL - 15 + tF 2TCL - 15 + tF – – ns ns ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD WR low time (no RW-delay) 45/62 3TCL - 20 + tC 3TCL - 20 + tA + tC ns ns ST10F166 AC Characteristics (Cont’d) Multiplexed Bus for the ST10F166-16 VCC = 5 V ± 10 %; TA = 0 to +70 °C VSS = 0 V CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20-MHz CPU clock without waitstates) Parameter Symbol CPU Clock = 16 MHz Duty cycle 0.4 to 0.6 min. max. ALE high time t5 CC 15 + t A – Address setup to ALE t6 CC 10 + t A – Address hold after ALE t7 CC 15 + t A – t8 CC 15 + t A t9 CC Variable CPU Clock 1/CLP = 1 to 20 MHz min. max. TCLmin - 10 + tA TCLmin - 15 + tA Unit – ns – ns TCLmin - 10 + tA – ns – TCLmin - 10 + tA – ns -10 + tA – -10 + tA – ns t10CC – 5 – 5 ns t11CC – 42.5 – TCLmax + 5 ns t12 CC 52.5 + tC – CLP - 10 + tC – ns t13 CC 77.5 + tC – CLP+TCLmin - 10 + tC – ns t14 SR – 47.5 + tC – CLP - 20 + tC ns RD to valid data in (no RW-delay) t15 SR – 72.5 + tC – ALE low to valid data in t16 SR – 72.5 + tA + tC – Address to valid data in t17 SR – 100 + 2tA + tC – 2CLP - 25 + 2tA + tC ns Data hold after RD rising edge t18 SR 0 – 0 – ns Data float after RD t19 SR – 47.5 + t F – CLP - 15 + tF ns Data valid to WR Data hold after WR t22 CC t23 CC 47.5 + tC 47.5 + t F – – CLP - 15 + tC CLP - 15 + tF – – ns ns ALE rising edge after RD, WR t25 CC 47.5 + t F – CLP - 15 + tF – ns Address hold after RD, WR t27 CC 47.5 + t F – CLP - 15 + tF – ns ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD WR low time (no RW-delay) RD to valid data in (with RW-delay) CLP+TCLmin - 20 + tC CLP+TCLmin - 20 + tC ns ns 46/62 ST10F166 AC Characteristics (Cont’d) Figure 15. External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE t5 t16 t25 ALE t17 A17-A16 (A15-A8) BHE t27 Address t6 t7 t19 t18 Read Cycle BUS Address t8 Data In t10 t14 RD t12 Write Cycle BUS t23 Address t8 Data Out t10 t22 WR t12 47/62 ST10F166 AC Characteristics (Cont’d) Figure 16. Ext. Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE t5 t16 t25 t17 t27 ALE A17-A16 (A15-A8) Address BHE t6 t7 t19 Read Cycle BUS t18 Address Data In t8 t10 t14 RD t12 Write Cycle BUS t23 Address t8 Data Out t10 t22 WR t12 48/62 ST10F166 AC Characteristics (Cont’d) Figure 17. External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE t5 t16 t25 ALE t17 A17-A16 (A15-A8) t27 Address BHE t6 t7 t19 t18 Read Cycle BUS Address t9 Data In t11 RD t15 t13 Write Cycle BUS t23 Address t9 Data Out t11 t22 WR t13 49/62 ST10F166 AC Characteristics (Cont’d) Figure 18. Ext. Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE t5 t16 t25 t17 t27 ALE A17-A16 (A15-A8) Address BHE t6 t7 t19 t18 Read Cycle BUS Address t9 Data In t11 RD t15 t13 Write Cycle BUS t23 Address t9 Data Out t11 t22 WR t13 50/62 ST10F166 AC Characteristics (Cont’d) Demultiplexed Bus for the ST10F166 VCC = 5 V ± 10 %; VSS = 0 V TA = 0 to +70 °C CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20-MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. min. max. Unit ALE high time t5 CC 15 + tA – TCL - 10 + tA – ns Address setup to ALE ALE falling edge to RD, WR (with RW-delay) t6 CC 10 + tA – – ns t8 CC 15 + tA – TCL - 15 + tA TCL - 10 + tA – ns ALE falling edge to RD, WR (no RW-delay) t9 CC -10 + tA – -10 + tA – ns RD, WR low time (with RW-delay) t12 CC 40 + tC – 2TCL - 10 + tC – ns t13 CC 65 + tC – 3TCL - 10 + tC – ns t14 SR – 30 + tC – t15 SR – 55 + tC – ALE low to valid data in t16 SR – 55 + tA + tC – 3TCL - 20 + tA + tC ns Address to valid data in t17 SR – 75 + 2t A + tC – 4TCL - 25 + 2t A + tC ns t18 SR 0 – 0 – ns t20 SR – 35 + tF – 2TCL - 15 + tF ns Data float after RD rising edge (no RW-delay) t21 SR – 15 + tF – TCL - 10 + tF ns Data valid to WR t22 CC 35 + tC – – ns Data hold after WR t24 CC 15 + tF – – ns – ns – ns RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) Data hold after RD rising edge Data float after RD rising edge (with RW-delay) ALE rising edge after RD, WR t26 CC -10 + tF – Address hold after RD, WR t28 CC 0 + tF – 51/62 2TCL - 15 + tC TCL - 10 + tF -10 + tF 0 + tF 2TCL - 20 + tC 3TCL - 20 + tC ns ns ST10F166 AC Characteristics (Cont’d) Demultiplexed Bus for the ST10F166-16 VSS = 0 V VCC = 5 V ± 10 %; TA = 0 to +70 °C CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20-MHz CPU clock without waitstates) Parameter Symbol CPU Clock = 16 MHz Duty cycle 0.4 to 0.6 min. max. Variable CPU Clock 1/CLP = 1 to 20 MHz min. TCLmin - 10 + tA Unit max. ALE high time t5 CC 15 + tA – Address setup to ALE t6 CC 10 + tA – ALE falling edge to RD, WR (with RW-delay) t8 CC 15 + tA – t9 CC -10 + tA – t12 CC 52.5 + t C – RD, WR low time (no RW-delay) t13 CC 77.5 + t C – CLP+TCLmin - 10 + tC RD to valid data in (with RW-delay) t14 SR – 47.5 + tC RD to valid data in (no RW-delay) t15 SR – 72.5 + tC ALE low to valid data in t16 SR – Address to valid data in t17 SR – Data hold after RD rising edge t18 SR 0 – 0 – ns Data float after RD rising edge (with RW-delay) t20 SR – 47.5 + tF – CLP - 15 + tF ns Data float after RD rising edge (no RW-delay) t21 SR – 15 + tF – TCLmin - 10 + tF ns Data valid to WR t22 CC 47.5 + t C – CLP - 15 + tC – ns Data hold after WR t24 CC 15 + tF – TCLmin - 10 + tF – ns ALE rising edge after RD, WR t26 CC -10 + tF – -10 + tF – ns 0 + tF – 0 + tF – ns ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) Address hold after RD, WR t28 CC 72.5 + t A + tC 100 + 2t A + tC – ns TCLmin - 15 + tA – ns TCLmin - 10 + tA – ns – ns – ns – ns – CLP - 20 + tC ns – CLP+TCLmin - 20 + tC ns -10 + tA CLP - 10 + tC – – CLP+TCLmin - 20 + tA + t C 2CLP - 25 + 2tA + tC ns ns 52/62 ST10F166 AC Characteristics (Cont’d) Figure 19. Ext. Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE t5 t16 t26 ALE t17 A17-A16 A15-A0 t28 Address BHE t6 t20 t18 Read Cycle BUS (D15-D8) D7-D0 Data In t8 t14 RD t12 Write Cycle BUS (D15-D8) D7-D0 t24 Data Out t8 t22 WR t12 53/62 ST10F166 AC Characteristics (Cont’d) Figure 20. Ext. Mem. Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE t5 t16 t26 t17 t28 ALE A17-A16 A15-A0 Address BHE t6 t20 Read Cycle BUS (D15-D8) D7-D0 t18 Data In t8 RD t14 t12 Write Cycle BUS (D15-D8) D7-D0 t24 Data Out t8 t22 WR t12 54/62 ST10F166 AC Characteristics (Cont’d) Figure 21. Ext. Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE t5 t16 t26 ALE t17 A17-A16 A15-A0 t28 Address BHE t6 t21 t18 Read Cycle BUS (D15-D8) D7-D0 Data In t9 t15 RD t13 Write Cycle BUS (D15-D8) D7-D0 t24 Data Out t9 t22 WR t13 55/62 ST10F166 AC Characteristics (Cont’d) Figure 22. Ext. Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE t5 t16 t26 t17 t28 ALE A17-A16 A15-A0 Address BHE t6 t21 t18 Read Cycle BUS (D15-D8) D7-D0 Data In t9 RD t15 t13 Write Cycle BUS (D15-D8) D7-D0 t24 Data Out t9 t22 WR t13 56/62 ST10F166 AC Characteristics (Cont’d) CLKOUT and READY for ST10F166, VSS = 0 V VCC = 5 V ± 10 %; TA = 0 to +70 °C CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. min. max. Unit CLKOUT cycle time CLKOUT high time t29 CC t30CC 50 15 50 – 2TCL TCL – 10 2TCL – ns ns CLKOUT low time CLKOUT rise time t31CC t32 CC 15 – – 5 TCL – 10 – – 5 ns ns CLKOUT fall time t33 CC – 5 – 5 ns CLKOUT rising edge to ALE falling edge t34 CC 0 + tA 10 + tA 0 + tA 10 + t A ns Synchronous READY setup time to CLKOUT t35 SR 10 – 10 – ns t36 SR 10 – 10 – ns t37 SR 65 – 2TCL + 15 – ns Asynchronous READY setup time 1) t58SR 20 – 20 – ns Asynchronous READY hold time 1) t59SR 0 – 0 – ns 0 0 + 2t A + tF 0 TCL - 25 + 2tA + t F ns Synchronous READY hold time after CLKOUT Asynchronous READY low time Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) t60SR 2) 2) Notes: 57/62 1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. ST10F166 AC Characteristics (Cont’d) CLKOUT and READY for ST10F166-16 VSS = 0 V VCC = 5 V ± 10 %; TA = 0 to +70 °C CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF Parameter Symbol CPU Clock = 16 MHz Duty cycle 0.4 to 0.6 Variable CPU Clock 1/CLP = 1 to 20 MHz min. max. min. max. Unit CLKOUT cycle time CLKOUT high time t29 CC t30CC 62.5 15 62.5 – CLP TCLmin – 10 CLP – ns ns CLKOUT low time CLKOUT rise time t31CC t32 CC 15 – – 5 TCLmin – 10 – – 5 ns ns CLKOUT fall time t33 CC – 5 – 5 ns CLKOUT rising edge to ALE falling edge t34 CC 0 + tA 10 + tA 0 + tA 10 + tA ns Synchronous READY setup time to CLKOUT t35 SR 10 – 10 – ns t36 SR 10 – 10 – ns t37 SR 77.5 – CLP + 15 – ns Asynchronous READY setup time 1) t58SR 20 – 20 – ns Asynchronous READY hold time 1) t59SR 0 – 0 – ns 0 0 + 2t A + tF 0 TCL - 25 + 2tA + tF ns Synchronous READY hold time after CLKOUT Asynchronous READY low time Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) t60SR 2) 2) Notes: 1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA refer to the next following bus cycle. 58/62 ST10F166 AC Characteristics (Cont’d) Figure 23. CLKOUT and READY READY waitstate Running cycle 1) t32 CLKOUT MUX/Tristate 6) t33 t30 t29 t31 t34 ALE 7) 2) Command RD, WR t35 Sync t36 t58 Async t59 t58 3) t36 3) 3) READY t35 t59 t60 4) 3) READY 5) t37 see 6) Notes: 59/62 1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2) The leading edge of the respective command depends on RW-delay. 3) READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point terminates the currently running bus cycle. 4) READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). 5) If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (eg. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed, if READY is removed in reponse to the command (see Note 4)). 6) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. 7) The next external bus cycle may start here ST10F166 AC Characteristics (Cont’d) External Bus Arbitration VSS = 0 V VCC = 5 V ± 10 %; TA = 0 to +70 °C for ST10R165 CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF Parameter Max. CPU Clock = 20 MHz Symbol HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay Other signals release Other signals drive Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max. t61 SR 20 – 20 – ns t62 CC – 30 – 30 ns t63 CC – 30 – 30 ns t66CC t67CC – -5 25 35 – -5 25 35 ns ns Figure 24. External Bus Arbitration, Releasing the Bus CLKOUT t61 HOLD t63 HLDA 1) t62 BREQ 2) t66 Other Signals 1) Notes: 1) The ST10R165 will complete the currently running bus cycle before granting bus access. 2) This is the first possibility for BREQ to get active. 60/62 ST10F166 AC Characteristics (Cont’d) Figure 25. External Bus Arbitration, (Regaining the Bus) 2) CLKOUT t61 HOLD t62 HLDA t62 BREQ t62 t63 1) t67 Other Signals Notes: 61/62 1) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10R165 requesting the bus. 2) The next ST10R165 driven bus cycle may start here. ST10F166 19 GENERAL INFORMATION Figure 26. Package Outline PQFP100 (14 x 20 mm) mm inches Dim Min Typ A Max Min Typ 3.40 Max 0.134 A2 2.55 2.80 3.05 0.100 0.110 0.120 D 22.95 23.20 23.45 0.931 0.913 0.923 D1 19.90 20.00 20.10 0.783 0.787 0.791 D3 18.85 0.742 E 16.95 17.20 17.45 0.695 0.667 0.687 E1 13.90 14.00 14.10 0.547 0.551 0.555 E3 12.35 0.486 e 0.65 0.026 Number of Pins ND 30 NE 20 N 100 Table 8. Ordering Information Type Package ST10F166BQ1 PQFP-100 ST10F166BQ1-16 Function 16-bit microcontroller, 0 °C to +70 °C, 1 KByte RAM, 32 KByte Flash EPROM 16-bit microcontroller, 0 °C to +70°C, w/o Prescaler, 1 KByte RAM, 32 KByte Flash EPROM Information furnished is believed to be accurate and reliable. However, SGS-TH OMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THO MSON Microelectronics. 1996 SGS-THOMSON Microelectronics -Printed in Italy - All Rights Reserved. SGS-THO MSON Microelectronics GROUP OF COMPANIE S Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 62/62