ST75C520 HIGH SPEED FAX MODEM DATA PUMP . . . . . . . . . PRELIMINARY DATA ITU-T V.17, V.29, V.27ter, V.21 WITH FAX SUPPORT ITU-T V.23, V.21, BELL 103 V.17, V.29 (T104), V.27ter SHORT TRAINS V.33 HALF-DUPLEX DESCRIPTION The SGS-THOMSON Microelectronics ST75C520 chip is a highly integrated modem engine, which can operate with all currently used FAX group III standards up to 14400bps. Full V.21, V.23 and Bell 103 full duplex modem standards are implemented. 1800Hz OR 1700Hz CARRIER SINGLE CHIP COMPLETE DATA PUMP SINGLE 5V POWER SUPPLY : - TYPICAL ACTIVE POWER CONSUMPTION : 375mW - LOW POWER MODE (typ. 5mW) EXTENDED MODES OF OPERATIONS : - FULL IMPLEMENTATION OF THE V.17, V.33, V.29 AND V.27ter HANDSHAKES - AUTODIAL AND AUTOANSWER CAPABILITY - PROGRAMMABLE TONE DETECTION AND FSK V.21 FLAG PATTERN DETECTION DURING HIGH SPEED RECEPTION - PROGRAMMABLE CALL PROGRESS AND CALL WAITING TONE DETECTORS INCLUDING DTMF - PROGRAMMABLE CLASS DETECTION CAPABILITY - WIDE DYNAMIC RANGE (>48dB) - A-LAW VOICE PCM MODE PQFP64 (Plastic Quad Flat Pack) ORDER CODE : ST75C520 PQFP VERSATILE INTERFACES : - PARALLEL 64 x 8-BIT DUAL PORT RAM - SYNCHRONOUS/HDLC PARALLEL DATA HANDLING - HDLC FRAMING SUPPORT - V.24 INTERFACE - FULL OPERATING STATUS REAL TIME MONITORING - FULL DIAGNOSTIC CAPABILITY - DUAL 8-BIT DAC FOR CONSTELLATION DISPLAY June 1995 This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without no tice. 1/45 ST75C520 CONTENTS Page I PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 I.1 I.2 I.3 I.4 I.5 I.6 I.7 PIN CONNECTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HOST INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ANALOG INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V.24 INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MISCELLANOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BOUNDARY SCAN INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 4 4 4 4 5 II III BLOCK DIAGRAMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 III.1 III.2 III.3 MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 8 IV FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 IV.1 IV.2 IV.3 SYSTEM ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 11 V. USER INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 V.1 V.2 V.3 V.4 V.5 DUAL PORT RAM DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMMAND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMMAND SET SHORT FORM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STATUS - REPORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DATA EXCHANGES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 14 16 17 17 VI COMMAND SET DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 VII STATUS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 VII.1 VII.2 COMMAND ACKNOWLEDGE AND REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODEM STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 28 VIII TONE DETECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 VIII.1 VIII.2 VIII.3 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 34 38 IX BUFFER OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 IX.1 IX.2 IX.3 IX.4 IX.5 IX.6 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVE OPERATIONS OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSMIT OPERATIONS OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFFER STATUS AND FORMAT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVE BUFFER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DATA BUFFER MANAGEMENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 39 39 40 40 40 X XI DEFAULT CALL PROGRESS TONE DETECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . DEFAULT ANSWER TONE DETECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 42 XII ELECTRICAL SCHEMATICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 XIII PCB DESIGN GUIDELINES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2/45 ST75C520 EYEX EYEY TEST1 TEST2 EBS TXA1 TXA2 16 15 14 13 12 11 10 9 GND V DD RING RTS CTS CD CLK RXD TXD I - PIN DESCRIPTION I.1 - Pin Connections 8 7 6 4 3 2 1 5 SA0 17 64 AGNDT SA1 18 63 VCM SA2 19 62 AVDD SA3 20 61 RXA2 SA4 21 60 RXA1 SA5 22 59 AGNDR SA6 23 58 VREFP GND 24 57 VREFN V DD 25 56 EXTAL SD0 26 55 XTAL SD1 27 54 CLKOUT SD2 28 53 HALT SD3 29 52 RESET SD4 30 51 SCOUT SD5 31 50 BOS SD6 32 49 EOS 75C52001.EPS MC0 MC1 MC2 MCI RDYS SCCLK SCIN V DD GND INT/MOT SINTR SDTACK SCS SR/W (SWR) SD7 SDS (SRD) 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I.2 - Host Interface The exchanges with the control processor proceed through a 64 Bytes DUAL port RAM shared between the ST75C520 and the Host. The signals associated with this interface are : Pin Name SD0..SD7 Type Description I/O System Data Bus. 8-bit data bus used for asynchronous exchanges between the ST75C520 and the Host through the dual port RAM. High impedance when exchanges are not active. SA0..SA6 I System Address Bus. 7-bit address bus for dual port RAM. SDS (SRD) I System Data Strobe. Active low. Synchronizes all the exchanges. In Motorola mode initiates the exchange, active low. In Intel mode initiates a read exchange, active low. SR/W (SWR) I System Read/Write. In Motorola mode defines the type of exchange read/write. In Intel mode initiates a write exchange, active low. SCS I System Chip Select. Active low. SDTACK OD System Bus Data Acknowledge. Active low. Open drain. SINTR OD System Interrupt Request. Active low. This signal is asserted by the ST75C520 and negated by the host. Open drain. RESET I Reset. Active low. RING I Ring Detect Signal. Active low. INT/MOT I Select Intel/Motorola Interface. 3/45 ST75C520 I.3 - Analog Interface Pin Name TXA1 TXA2 Type Description O O Transmit Analog Output 1 Transmit Analog Output 2. Outputs TXA1 and TXA2 provide analog signals with maximum peak to peak amplitude 2 x VREF, and must be followed by an external continous-time two pole smoothing filter (where VREF = VREFP - VREFN). Receive Analog Input 1 Receive Analog Input 2. The analog differential input peak to peak signal must be less than 2 x VREF. It must be preceded by an external continous-time single pole anti-aliasing filter. This filter must be as close as possible to the RXA1 and RXA2 Pins (where VREF = VREFP - VREFN). Analog Common Voltage (nominal +2.5V). This input must be decoupled with respect to AGND. Analog Negative Reference (nominal VCM - 1.25V). This input must be decoupled with respect to V CM. Analog Positive Reference (nominal V CM+1.25V). This input must be decoupled with respect to VCM. RXA1 RXA2 I I VCM VREFN VREFP I/O I I I.4 - V.24 Interface Pin Name RTS CLK CTS RxD TxD CD Type I O O O I O Description Request to Send. Active low. Data Bit Clock. Falling edge coïncides with DATA change. Clear to Send. Active low. Receive Data Transmit Data sampled with rising edge of CLK Carrier Detect. Active low. I.5 - Miscellaneous Pin Name XTAL EXTAL EYEX EYEY TEST1 TEST2 Type O I O O Description Internal Oscillator Output. Left open if not used. Internal Oscillator Input, or External Clock Constellation X analog coordinate Constellation Y analog coordinate To be left open To be left open Note : The nominal external clock frequency of the ST75C520 is 29.4912MHz with a precision better than ± 5.10-5 I.6 - Boundary Scan Interface A set of 13 signals are dedicated for Testing the ST75C520 Component. These signals can be used in a development phase, associated with the SGS-THOMSON ST18932 Boundary Scan Development Tools, to Debug the application Hardware and Software. If not used all input signals must be grounded and all output signals left open. Pin Name SCIN SCCLK SCOUT BOS EOS MC0..MC2 HALT MCI RDYS EBS CLKOUT 4/45 Type I I O I I I I O O I O Description Scan Data Input Scan Clock Scan Data Output Begin of Scan Control End of Scan Mode Control Stop ST75C520 Execution Multicycle Instruction Ready to Scan Flag Enable Boundary Scan. Active low (must be set low in normal mode). Internal ST75C520 Clock (XTAL frequency divided by 2) ST75C520 I.7 - Power Supply Symbol VDD GND AVDD AGNDT AGNDR Parameter Digital +5V (Pin 9, 25, 41). To be connected to AVDD (see below). Digital Ground (Pin 8, 24, 40). To be connected to AGNDT and AGNDR (see below). Analog +5V (Pin 62). To be connected to VDD (see below). Analog Transmit Ground (Pin 64). To be connected to GND (see below). Analog Receive Ground (Pin 59). To be connected to GND (see below). AGNDT and AGNDR must be connected together as close as possible to the chip. GND and AGNDR board plans should be separated, then connected together as close as possible to the chip, at a single point. Similarly VDD and AVDD must ne connected as close as possible to the chip, at a single point. RXD TXD CLK II - BLOCK DIAGRAMS II.1 - Functional Block Diagram 15 16 14 ST75C520 HDLC TX V.17, V.29, V.27 FAX TRANSMITTER DUAL RAM INTERFACE TX ANALOG 1 TXA2 2 TXA1 DPLL V.17, V.29, V.27 FAX RECEIVER HDLC RX HANDSHAKE AND STATUS REPORT SINTR 38 13 12 11 10 CTS RTS RING RING DETECTOR CD V.24 INTERFACE RX ANALOG 60 RXA1 61 RXA2 TONE DETECTOR V.21 FLAG DETECTOR 75C52002.EPS SD [0..7] (26 to 33) MUX 5/45 ST75C520 II.2 - Hardware Block Diagram ST75C520 PROGRAM ROM 8K x 32 XTAL 55 EXTAL 56 12 BOUNDARY SCAN (42 to 51 - 53-54) EBS ST18932 DSP CORE RAM 2K x 16 1 TXA2 FIFO 8 x 16 3 IIR FIR 2 TXA1 RESET 52 SA [0..6] (17 to 23) SD [0..7] (26 to 33) SDS (SDR) 34 58 V REFP 7 DPLL AND CONTROL 63 V CM 57 V REFN 8 DUAL PORT RAM 64 x 8 SR/W (SWR) 35 S S S I O SCS 36 SDTACK 37 P A G E E Y E CROM 8K x 16 FIFO 8 x 16 60 RXA1 FIR IIR FIR 61 RXA2 SINTR 38 V.24 INTERFACE 9-25 41 64 75C52003.EPS 62 DD 59 AV EYEX 4 AGNDT TXD RXD 5 DD RING 6 DV 7 DGND 15 TEST2 16 EYEY 10 TEST1 14 CD CTS 13 CLK 12 RTS 8-24 40 11 AGNDR INT/MOT 39 III - ELECTRICAL SPECIFICATIONS Unless otherwise noted, electrical characteristics are specified over the operating range. Typical value are given for VDD = +5V and tamb = 25°C. III.1 - Maximum Ratings (referenced to GND) Symbol VDD VI, VIN II, IIN Parameter DC Supply Voltage Digital or Analog Input Voltage Digital or Analog Input Current Value -0.3 to 7.0 -0.3 to (VDD + 0.3) ±1 Unit V V mA IO Digital Output Current ± 20 mA IOUT Analog Output Current Operating Temperature Storage Temperature (plastic) Maximum Power Dissipation ± 10 0, + 70 - 40, + 125 1000 mA Toper Tstg Ptot °C °C mW Stresses above those hereby listed may cause damage to the device. The ratings are stress related only and functional operation of the device at conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Standard MOS circuits handling procedure should be used to avoid possible damage to the device. III.2 - DC Characteristics VDD = 5.0V ± 5%, GND = 0V, Tamb = 0 to 70°C (unless otherwise specified). III.2.1 - Power Supply and Common Mode Voltage Symbol VDD IDD IDD-lp VCM 6/45 Parameter Supply Voltage Supply Current (internal oscillator) Supply Current in Low Power Mode Common Mode Voltage Min. 4.75 VDD/2 -5% Typ. 5 75 1 VDD/2 Max. 5.25 100 VDD/2 + 5% Unit V mA mA V ST75C520 III.2.2 - Digital Interface All digital pins except XTAL Pins. Symbol VIL VIH II Parameter Low Level Input Voltage High Level Input Voltage Input Current VI = VDD or VI = GND VOH VOL IOZ High Level Output Voltage (Iload = 2mA) Low Level Output Voltage (Iload = 2mA) Three State Input Leakage Current (GND < VO < VDD) CIN Input Capacitance Min. -0.3 2.2 -10 Typ. Max. 0.8 Unit V V 0 +10 µA 0 0.4 50 V V µA 2.4 -50 5 pF Crystal oscillator interface (XTAL, EXTAL). Symbol VIL VIH IL Parameter Low Level Input Voltage High Level Input Voltage Low Level Input Current GND < VI < VILmax IH High Level Input Current VIHmin < VI < VDD Min. Typ. Max. 1.5 Unit V V µA 15 µA Max. 2.60 300 2 x VREF 200 2 x VREF 100 Unit V mV VPP mV VPP mV 20 kΩ Ω 50 kΩ pF 3.5 -15 III.2.3 - Analog Interface Symbol VREF VCMOin VDIFin VCMOout VDIFout VOFFOut Rin Parameter Differential Reference Voltage Input = VREFP - VREFN Input Common Mode Offset, v = (RXA1+RXA2)/2 - VCM Differential Input Voltage RXA1 - RXA2 Output Common Mode Voltage Offset = (TXA1+TXA2)/2 - VCM Differential Output Voltage TXA1 - TXA2 Differential Output DC Offset (TXA1 - TXA2) Input Resistance RXAx Rout Output Resistance Min. 2.40 -300 -200 -100 100 TXAx RL Load Resistance TXAx CL Load Capacitance TXAx Typ. 2.50 10 7/45 ST75C520 III.3 - AC Electrical Characteristics III.3.1 - Dual Port RAM Host Timing WRITE-CYCLE TIMING READ-CYCLE TIMING NSCS SA[0..6] Valid Address Valid Address Motorola mode SR/NW 1 7 4 1 NSDS 9 4 8 3 12 5 10 Valid Data IN SD[0..7] 2 5 Valid Data OUT 6 2 6 NSDTACK 11 NSINTR 75C52004.EPS Intel mode SR/NW (= NWRITE) NSDS (= NREAD) Number Description Min. Typ. Max. 5 Unit 1 Address and Control Set-up Time ns 2 SDTACK Acknowledge 3 Data Set-up Time 10 ns 4 Address and Control Hold Time 0 ns 5 Data Hold Time 5 ns 6 SDTACK Hold Time 0 ns 7 Write Enable Low State 45 ns 8 Access Inhibition High State (see Note) 70 ns 9 Read Enable Low State 45 ns 10 Read Data Access 35 ns 11 SINTR Clear Delay 50 ns 12 Data Valid to Tristate 15 ns 20 ns Note : A minimum delay of 70ns is required only from the rizing edge of NWRITE to the falling edge of the next selected NREAD or NWRITE. 8/45 ST75C520 III.3.2 - Serial V.24 Interface Timing CLK 1 TXD 2 Valid Data In 3 75C52005.EPS Valid Data Out RXD 4 Number Description Min. 1 TXD to CLK Set-up Time 30 2 TXD to CLK Hold Time 10 3 RXD Valid to CLK Delay Time 4 RXD Valid to CLK Hold Time Typ. Max. ns ns 100 0 Unit ns ns 9/45 ST75C520 IV - FUNCTIONAL DESCRIPTION IV.1 - System Architecture The chip allows the design of a complete FAX data-pump without any external component. Aversatile dual port RAM allows an easy interface with most micro-controllers. IV.2 - Operation IV.2.1 - Modes The modem implementation is fully compatible with FAX modulation recommendations. The modulation can be either Trellis Coded Modulation (TCM) as in V.17 14400, 12000, 9600, 7200bps rates, Quadrature Amplitude Modulation (QAM) as in V.29 9600, 7200, 4800 and V.27ter 4800 and 2400bps. Other modes of operation include tone and DTMF detection or generation, or speech mode. IV.2.2 - Transmitter Description The signal pulses are shaped in a dedicated filter further combined with a compromise transmit equalizer suited for transmission over strongly distorted lines. 3 different compromise equalizers are available and can be selected by software. IV.2.3 - Receiver Description The receiver section handles complex signals and uses a fractionally spaced complex equalizer. It is able to cope with distant modem timing drifts up to 10-4 as specified in the ITU-T recommendations. It also compensate for frequency drift up to 10Hz and for phase jitter at multiple and simultaneous frequencies. IV.2.4 - Tone Generator Description Four tones can be simultaneously generatedby the ST75C520. The tones are determined by their frequenciesand by the output amplitude level. A set of specific commands are also available for DTMF generation (using two of the four generators available). IV.2.5 - Tone Detector Description Sixteen tones can be simultaneously detected by the ST75C520. Each of the tones to be detected is defined by the coefficients of a 4th order programmable IIR. Detection thresholds are also programmable from -45dBm up to -10dBm. DTMF detection is also available and is performed by a specific filter section (that requires no programming). 10/45 IV.2.6 - DTMF Detector Description A DTMF Detector is included in the ST75C520, it allows detectionof valid DTMF Digits. Avalid DTMF Digit is defined as a dual Tone with a total power higher than -35dBm, a duration higher than 40ms and a differential amplitude within 8dB (negative or positive). IV.2.7 - Voice Mode The ST75C520 voice mode allows the implementation of enhanced telephone functions like answering machines. The incoming samples (9600Hz), received from the line are PCM A-law coded and writen into the dual port RAM. The outpoing samples are decompressed using the same A-law and output to the telephone line. The voice mode is entered using a CONF command, it can be either transmit voice from the dual RAM Tx buffer to the telephone line, receive voice from the telephone line to the dual RAM buffer, or both of these functions simultaneously. The format of the signal is A-law coded without complementation of the even bits. The buffer mechanism, between the host micro-controler and the ST75C520, is identical to the mechanism used for parallel data exchanges except that it starts immediately after CONF command, the size of the transmit and received buffer, are and must be 8 bytes, there is no need for a XMIT command, and if an overrun or underrun condition occurs no error will be reported to the host processor. IV.2.8 - Analog Loop Back Test Mode In any transmission standard and serial data format, the ST75C520 can be configured for analog loop back test. IV.2.9 - Low Power Mode Sleep state can be attained by a SLEEP command. Activating the reset signal will wake up the datapump. When in sleep mode, the dual port RAM is unavailable and the clocks are disabled. When entering the low power mode, the ST75C520 stops its oscillator, all the peripherals of the DSP core are stopped in order to reduce the power consumption. The dual RAM is made inacessible. The ST75C520 can be awakened by a hardware reset. There is a maximum time of 20ms to restart the oscillator after waking up and an additional 5ms after the interrupt to be able to accept any command coming from the host. ST75C520 IV.2.10 - Reset After a hardware reset, or an INIT command, the ST75C520 clears all its internal memories, clears the whole dual RAM and starts to initialize the delta sigma analog converters. As soon as these initializations are completed, the ST75C520 clears the dual RAM address 0 (COMSYS), generates an interrupt IT6 (command acknoledge) and is programmed to send and receive tones, the bit clock and the sample clock are programmed to 9600Hz. The total duration of the reset sequence is about 5ms. After that time the ST75C520 is ready to execute commands sent by the host micro-controller. The durationof the reset signal shouldbe greater than 700ns. IV.3 - Modem Interface IV.3.1 - Analog Interface The modem designer must provide a proper hybrid interface to the ST75C520. An example of hybrid design is given in paragraphs XII and XIII. The inputs and outputs of the MAFE are differential, achieving thus a better noise immunity. The D/A converter output amplifier includes a single pole low-pass filter, its cut-off frequency is : Fc - 3dB # 19200Hz. Continuous-time filtering of the analog differential output is necessary using an off-chip amplifier and a few external passive components. IV.3.2 - Host Interface The host interface is seen by the micro as a 64x8 RAM, with additional registers accessible through an 8-bit address space. A selection Pin (INT/MOT) allows to configure the host bus for either INTEL or MOTOROLA type control signals. V - USER INTERFACE V.1 - Dual Port Ram Description The dual port RAM is the standard interface between the controller and the ST75C520, for either commands or data. This memory is addressedthrough a 7-bit address bus. The locations from $00 to $3F are RAM locations, while locations from $40 to $50 are control registers dedicated to the interrupt handling. Several functional areas are defined in the dual port RAM, namely : - the command area, - the report area, - the status area, - the data buffer area. V.1.1 - Mapping V.1.1.1 - Command Area The command area is located from $00 to $04. Address $00 holds the command byte COMSYS, and the next four locations hold the parameters COMPAR[0..3]. The command parameters must be entered before the command word is issued. Once the command has been entered, the command byte is reset and an acknowledge report is issued. A new command should not be issued before the acknowledgecounter COMACK isincremented. V.1.1.2 - Report Area The report area is located from address $05 to address $07. Location $05 holds the acknowledge counter COMACK. Each time a command is acknowledged, the report bytes COMREP[0..1] (if any) are written by the ST75C520 into locations $06 and $07, and the content of COMACK is incremented. This counter allows the ST75C520 to accurately monitor the command processing. V.1.1.3 - Status Area The statusarea is located from address $08 to $0A. The error status word SYSERR is located at address $08. This error status word is updated each time an error condition occurs. An optionalinterruption IT0 may additionally be triggered in the case of an error condition. Locations $09 and $0A hold the general status bytes STATUS[0..1]. The meaning of the bits depends on the mode of operation, and is described in Chapter VII. The third byte at address $0B holds the Quality Monitor byte STAQUA. V.1.1.4 - Optional Status Area The user can program (through the DOSR command) the three locations STAOPT[0..2] of the Optional Status Area ($0C to $0E) for the real time monitoring of three arbitrary memory locations. V.1.1.5 - Data Buffer Area The data area is made of four 8-byte buffers. Two are dedicated to transmission and the two others to reception. Each of the four buffers is attached to a status byte. the meaning of the status byte depends on the selected format of transmission. Within each buffer, D0 represents the first bit in time. 11/45 ST75C520 V.1.2 - Interruptions The ST75C520 can generate 5 interrupts for the controller. The interrupt handling is made with a set of registers located from $40 to $50. The interruptions generated by the ST75C520 come from several different sources. Once the ST75C520 raises an interrupt, a signal is sent to the controller. The controller has then to process the interrupt and clear it. The interrupt source can be examined in the Interrupt Source Register ITSRCR located at $50. According to this status byte, the interrupt source can be determined.Then, writing a zero at one of the memory location $40 to $46 (Reset Interrupt Registers ITREST[0..6]) will reset the corresponding interrupt (and thus acknowledge it). These sources of interruptions can be masked globally or individually using the Interrupt Mask Register ITMASK located at $4F. The interrupt sources are : - IT0 : Error/Warning This signifies that an error has occurred and the error code is available in the error status byte SYSERR. This byte can be selectively cleared by the CSE command. - IT2 : Tx Buffer Each time the ST75C520 frees a buffer, this interrupt is generated. 12/45 - IT3 : Rx Buffer Each time the ST75C520 has filled a buffer, this interrupt is generated. - IT4 : Status Byte This signifies that the status byte has changed and must be checked by the controller. - IT6 : Command Acknowledge This signifies that the ST75C520 has read the last command entered by the host, incremented the command counter COMACK, and is ready for a new command. ITSRCR X D0 = 1 D2 = 1 Dn = 1 ITMASK D6 X D4 D3 D2 X D0 D3 D2 X D0 IT0 Pending IT2 Pending ITn Pending D7 D7 and D0 = 1 D7 and D2 = 1 ...................... D7 and D6 = 1 D6 X D4 IT0 Enable D IT2 Enable D ..................... IT6 Enable D ST75C520 V.1.3 - Host Interface Summary Address (hex) Description Size (Byte) Mnemonic COMMAND AREA $00 Command 1 COMSYS $01-$04 Command Parameters 4 COMPAR[0..3] $05 Acknowledge Counter 1 COMACK $06-$07 Report 2 COMREP[0..1] $08 Error Status 1 SYSERR $09-$0A General Status 2 STATUS[0..1] $0B Quality Monitor 1 STAQUA $0C-$0E Optional Report 3 STAOPT[0..2] $1C Data Rx Buffer 0 Status 1 DTRBS0 $1D-$24 Data Rx Buffer 0 8 DTRBF0[0..7] $25 Data Rx Buffer 1 Status 1 DTRBS1 $26-$2D Data Rx Buffer 1 8 DTRBF1[0..7] $2E Data Tx Buffer 0 Status 1 DTTBS0 $2F-$36 Data Tx Buffer 0 8 DTTBF0[0..7] $37 Data Tx Buffer 1 Status 1 DTTBS1 $38-$3F Data Tx Buffer 1 8 DTTBF1[0..7] $40-$46 Reset Interrupt Reg. 7 ITREST[0..6] $4F Interrupt Mask Reg. 1 ITMASK $50 Interrupt Source Reg. 1 ITSRCR REPORT AREA STATUS AREA DATA AREA INTERRUPT AREA 13/45 ST75C520 V.2 - Command Set The Command Set has the following attractive features : - user friendly with easy to remember mnemonics, - possibility of straightforward expansion with new commands to suit specific customer requirements, - easy upgrade of existing software using previous modem based SGS-THOMSON products. The command set has been designed to provide the necessary functional control on the ST75C520. Each command is classified according to its syntax and the presence/absence of parameters. In the case of a parametric command, parameters must first be written into the dual port RAM before the command is issued. Acknowledge and error report is issued for each command entered. V.2.1 - Command Set Summary V.2.1.1 - Operational Control Commands INIT Initialize. Initialize the modem engine. Set all parameters to their default values and wait for commands of the control processor. Non parametric command. IDT Identify. Return the product identification code. Non parametric command. SLEEP Turn to low power mode, the ST75C520 enters the low power mode and stops its crystal oscillator to reduce power consumption. In this mode all the clocks are stopped and the dual RAM is unreachable. HSHK Handshake. Begins the handshake se q u e nc e. Th e mo d em e n gine generates all the sequences defined in the ITU-T recommendations. A status report indicates to the control processor the state of the handsha ke. This command only applies to modes where a handshake sequence is defined. A CONF command must have been issued prior to the use of HSHK. Non parametric command. STOP FAX S to p. Stop FAX Half-dup le x transmitter. Non parametric command. SYNC FAX Synchronize. Start/Stop of FAX Half-du ple x rec eiver. P arame t ric command. CSE Clear Status Error. Selectively clears the Error status byte SYSERR. Parametric command. 14/45 SETGN Set Gain. This command sets the global gain factor, which is used for the transmit samples. Parametric command. V.2.1.2 - Data Communication Commands XMIT Tra n smit Da t a. S t art / st o p t he transmission of data in parallel mode. After a XMIT command, the ST75C520 sends the data contained in its dual port RAM. SERIAL Select Serial or Parallel Mode. This command selects the data source, i.e. either parallel or serial. The parallel mode uses a part of the dual port RAM as a double buffer. The serial mode uses the serial synchronous I/O. Parametric command. FORM Selects the Transmission Format (only in p a ra lle l mod e ). Th is c o mma nd configures the data interface for both receiver and transmitter according to the selected da ta fo rmat. Parametric command (HDLC or synchronous). In s er ia l mo d e , f o rmat is a lwa y s synchronous. V.2.1.3 - Memory Handling Commands MW MR CR Memory Write. This command is used to write an arbitrary 16-bit value into the writable memory location currently specified by a parameter. Parametric command. Memory Read. This command allows the controller to read any of the ERAM or CROM (ST75C520 memory spaces) loc a tion wit ho ut in t erru pt in g t h e processor. Parametric command. Complex Read. This command allows the controller to read at the same time the real and imaginary part of a complex value stored in a double ERAM or CROM location. This feature is very interesting for eye pattern software control and for equalization monitoring. This command insures that the real and imaginary parts are sampled in the memory at the same time (integrity). Parametric command. ST75C520 V.2.1.4 - Configuration Control Commands CONF Configure. This command configuresthe modem enginefor data transmission and handshake procedures (if any) in any of the supported modes. The transmission parameters are set to their default values and can be modified with the MODC command. Parametric command. MODC Modify Configuration. This command allows modification of some of the parameters which have been set up by the CONF command. It can also be used to alter the mode of operations (short train). Parametric command. DOSR Define Optional Status Report. This command allows the modification of the optional status report located in the status area of the dual port RAM. One can thus select a particular parameter to be monit ored during all modes of operation. Parametric command. DSIT Define Status Interrupt. This command allows the programming of the status word bit that will generate an Interrupt to the controller. Parametric command. V.2.1.5 - Tone Generation Commands TONE Se le ct Ton e . P ro gra ms the ton e generator(s) for the desired default tone(s). Additional mnemonics provide quick programming of DTMF tones or other currently used tones. Parametric command. DEFT TGEN De fine Ton e . P ro g rams t h e t one generator(s) for arbitrary tone synthesis. Parametric command. Tone Generator Control. Enables or d isa b le s t h e t o n e ge n e rat o r(s ). Parametric command. IV.2.1.6 - Tone Detection Commands TDRC TDWC TDRW TDWW TDZ Read Tone Detector Coefficient. Read o n e To ne Det e c to r Co ef f icien t . Parametric command. Write Tone Detector Coefficient. Write o n e To ne Det e c to r Co ef f icien t . Parametric command. Read Tone Detector Wiring. Read one Tone Detector Wirin g co nnection. Parametric command. Write Tone Detector Wiring. Write one Tone Detector Wirin g co nnection. Parametric command. Clear Tone Detector Cell. Clear internal variables of a Tone Detector Cell. Parametric command. V.2.1.7 - Miscellaneous Commands CALL JSR Call a Subroutine. Call a subroutine with one Parameter. Parametric command. Call a Low Level Subroutine. Call an internal subroutine with one parameter. Parametric command. 15/45 ST75C520 V.3 - Command Set Short Form CCI Command 16/45 Mnemonic Value XMIT 0x01 Transmit Data Description SETGN 0x02 Set Transmit Gain SLEEP 0x03 Power Down the ST75C520 HSHK 0x04 Start Handshake INIT 0x06 Initialize (Software Master RESET) SERIAL 0x07 Enable/disable Data Serial Mode CSE 0x08 Clear Error Status Word FORM 0x09 Define Parallel Data Format DOSR 0x0A Define Optional Status Report TONE 0x0C Generate Predefined Tones TGEN 0x0D Enable Tone Generator DEFT 0x0E Define Arbitrary Tone MR 0x10 Memory Read CR 0x11 Complex Read MW 0x12 Memory Write DSIT 0x13 Define Status Interrupt IDT 0x14 Return Product Identification Code JSR 0x18 Call a Low Level Subroutine CALL 0x19 Call a Subroutine TDRC 0x1A Tone Detector Read Coefficient TDRW 0x1B Tone Detector Read Wiring TDWC 0x1C Tone Detector Write Coefficient TDWW 0x1D Tone Detector Write Wiring TDZ 0x1E Tone Detector Clear Cell CONF 0x20 Configure MODC 0x21 Modify Default Configuration STOP 0x25 FAX Stop Transmitter SYNC 0x26 FAX Synchronize Receiver ST75C520 V.4 - Status - Reports V.4.1 - Status The ST75C520 has a dedicated status reporting area located in its dual port RAM. This allow a continuous monitoring of the status variables without interrupting the ST75C520. The first status byte gives the error status. Issuing of an error status can also be flagged by a maskable interrupt for the controller. The signification of the error codes are given in Chapter VII. The second and third status bytes give the general status of the modem. These status include for example the ITU-T circuit status and other items described in appendix. These two status can generate, when a change occurs, an interrupt to the controller ; each bit of the two byte word can be masked independently. The forth byte gives in real time a measure of the reception quality. This information may be used by the controller to monitor the quality of the received bits. Three other locations are dedicated for custom status reporting. The controller can program the ST75C520 for a real time monitoring of any of its internal RAM location. High byte or low byte of any word can thus be monitored. V.4.2 - Reports The ST75C520 features an acknowledge and report facility. The acknowledge of a command is monitored by a counter COMACK located in the dual port RAM. Each time a command is read from the command area, the ST75C520 will increment this counter. For instance, when a MR (Memory Read) command is issued, the data is first written in the report area, and the counter is incremented afterwards. This way of processing insures data integrity and gives additional synchronization between the controller and the data pump. V.5 - Data Exchanges The ST75C520 accepts many kinds of data exchange : the default mode uses the synchronous serial exchange. Other modes include HDLC framing support and synchronous parallel exchanges. Detailed description of the Data Buffer Exchanges modes is available in the paragraph IX. V.5.1 - Synchronous Parallel Mode The data exchanges are made through the dual port RAM and are byte synchronous oriented. The double buffer facilities of the ST75C520 allow an efficient buffering of the data. V.5.1.1 - Transmit Thecontrollermust firstfill at leastthe first bufferof data (Tx Buffer 0) with the bits to be transmitted. In order to perform this operation, the controller must first check the Tx Buffer 0 status word DTTBS0. If this buffer is empty, the controller fills the data buffer locations (up to 64 bits), and then writes in DTTBS0 the number of bytes contained in the buffer. The controller can then either proceed with the second buffer or initiate the transmission with a XMIT command. The ST75C520 copies the contents of the data buffer and then clears the buffer status word in order to make it again available, then generates an IT2 interrupt. The number of bytes specified by the status word is then queued for transmission. The process goes on with the two buffers until an XMIT command stops the transmission. After the finishing XMIT command has been issued, the last buffers are emptied by the ST75C520. Errors occur when both buffers are empty while the transmit bit queue is also empty. Error is signalled with an IT0 interruption to the controller. V.5.1.2 - Receive The controller should take care of releasing the Rx buffers before the Data Carrier Detect goes true. This is made by writing zero in the Rx Buffer Status 0 and 1. The ST75C520 then fills the first buffer, and oncefilled sets the status word with the number of bytes received and then generates an IT3 interrupt. It then takes control of the second buffer and operates the same way. The controller must check the status of the buffers and empty them. Once the data read, the controller must release the used buffer and wait for the next buffer to be filled. Error occurs when both buffers are declared full, and incoming bits continue to arrive from the line. Error is signaled by an IT0 interrupt. V.5.2 - HDLC Parallel Mode This mode implements part of the High Level Data Link Control formats and procedures. It is well suited for error correcting protocols like ECM or FAX T4/T30 recommendations.It supports the flagging generation,16-bit Frame Check Sequence,as well as the Zero insertion/deletion mechanism. V.5.3 - Serial Exchanges The other mode of operation for data exchanges is the Serial Synchronous Mode. In this mode, the data I/O is made through the V.24 interface (page 4). Even when using the parallel mode described above, the received bits are available on the ST75C520 RxD Pin. See paragraph VII.2.1 table for clock values. 17/45 ST75C520 VI - COMMAND SET DESCRIPTION The appendixA containsthe description of the complete command set. Commands are presented according to the following form : COMMAND Opcode Hexadecimal digit X Synopsis X X X X X Field Byte Pos. Name X b..a Explanation of the parameter Default value Parameters 18/45 CALL Call a Subroutine 19 0 Synopsis Definition Name of the addressed bit field. Index (or address in the dual port RAM) of the parameter byte (from 1 to 4). Bit field position inside the parameter byte. Can either be a single position (from 0 to 7, 0 being LSB) or a range. Possible values for the bit (resp. bit field). Range means all values are allowed. A star means a default value. Values are expressed either under the form of a bit string, or under hexadecimal format. CALL Opcode: X Value xx * Value X Short description of the functions performed by the command. Parameters Field Byte Pos. COMMAND Command Name Meaning 0 0 1 1 0 0 1 CALL allows to execute a part of the ST75C520 firmware with a specific argument. Field Byte Pos. Value Definition C_ADDR_L 1 7..0 Low byte of the call address C_ADDR_H 2 7..0 High byte of the call address C_DATA_L 3 7..0 Low byte of the argument C_DATA_H 4 7..0 High byte of the argument ST75C520 CONF Opcode 20 0 Synopsis Parameters CONF Configure for Operations 0 1 0 0 0 0 0 CONF allows the complete definition of the ST75C520 operation, including the mode of operation (tone, FAX transmit, FAX receive, voice transmit, voice receive, DTMF receive, ...) and the modem parameters (standard, speed, ...). Field CONF_OPER CONF_ANAL Byte 1 1 Pos. 3..0 4 CONF_PSTN 1 5 CONF_AO 1 6 CONF_V24 1 7 CONF_MODE 2 5..0 CONF_TXEQ 2 7..6 CONF_CAR 3 0 CONF_SP0 3 7..5 CONF_SP1 4 2..0 Value 0 1 0 1 0 1 0 1 1 3 4 7 8 9 C D Other 0 1 2 3 0 1 xx1 x1x 1xx xx1 x1x 1xx Definition Mode of operation, see below Normal mode Analog loop back (test mode only) PSTN (carrier detect set to -43/-48dBm) Leased line (carrier detect -33/-38dBm) Answer mode (FSK full duplex only) Originate mode (FSK full duplex only) Do not use RTS pin signal Use RTS pin signal Bell 103 (full duplex) V.21 (full duplex) V.23 (full duplex) V.27ter V.29 V.17 V.33 (half duplex) V.21 channel 2 Reserved No transmit equalizer Transmit equalizer #1 Transmit equalizer #2 Transmit equalizer #3 1800Hz carrier (V.17/V.33 only) 1700Hz carrier (V.17/V.33 only) 2400bps allowed (V.27) 4800bps allowed (V.27, V.29) 7200bps allowed (V.29, V.17) 9600bps allowed (V.29, V.17) 12000bps allowed (V.17, V.33) 14400bps allowed (V.17, V.33) According with the 4 first bits of the CONF_OPER the ST75C520 is put into the following mode of operation. CONF_OPER Transmit Received 0000* Tones Tones 0010 Voice Tones 0100 Tone DTMF 0110 Voice DTMF 1000 Tones Voice 1010 Voice Voice 1111 Modem Modem Other Not allowed Not allowed 19/45 ST75C520 CR Opcode: 0 Synopsis Parameters 0 0 1 Field CR_ADDR_L CR_ADDR_H Parameters Byte 1 2 Parameters 0 Field ERR_MASK Parameters 20/45 Value Definition Low byte of the 16-bit address High byte of the 16-bit address CSE 0 0 1 0 0 0 Byte 1 Pos. 7..0 Value Definition Error mask See report appendix for detailed meaning DEFT 0E 0 0 0 1 1 1 0 DEFT programs one of the four tone generator for arbitrary tone generation.The parameter is the frequency of the generated tone expressed in Hertz between 0 and 3600Hz. Field TONE_GEN_SL TONE_FREQ_L TONE_FREQ_H Byte 1 2 3 Pos. 1..0 7..0 7..0 TONE_SCALE 4 7..0 Value Definition Index of the tone generator (3..0) Low byte of the frequency High byte of the frequency (internally masked with 0F) Amplitude scaling factor (high byte) 3F gives the nominal amplitude DOSR Define Optional Status Report 0A 0 Synopsis Pos. 7..0 7..0 Define Arbitrary Tone DOSR Opcode: 1 CSE is used to clear the ST75C520 error status SYSERR byte. It is also used as an acknowledge to the error condition handler. For details, please refer to the corresponding appendix. 0 Synopsis 0 08 DEFT Opcode: 0 Clear Error Status 0 Synopsis 0 CR allows the reading of a complex parameter. The parameter specifies the parameter address (for the real part : the imaginary part is next location). CR returns the high byte value of both real and imaginary part of the addressed complex parameter. CSE Opcode: CR Complex Read 11 0 0 0 1 0 1 0 DOSR specifies the address of the RAM variables to be monitored in the 3 locations STAOPT[0..2] of the dual port RAM. It also specifies the assignment within the 3 locations. Field STA_OPT_ASS STA_OPT_ADL STA_OPT_ADH STA_OPT_HL Byte 1 2 3 3 Pos. 1..0 7..0 3..0 7 Value 0..2 0 1 Definition Index of the STAOPT destination Low byte of source address High byte of source address Select low byte of source Select high byte of source ST75C520 DSIT Opcode: 13 0 Synopsis 0 0 Pos. 7..0 Status[0] bit mask pattern STA_IT_MSK1 2 7..0 Status[1] bit mask pattern Parameter 0 0 0 Parameter Notes : 0 Field Byte Pos. Value X_SYNC 1 1..0 00* 01 10 11 0 1 Definition Synchronous format (1) Transmit continous ”1” HDLC framing Transmit continous ”0” (1) 1. This format is only valid for the transmiter. HSHK Handshake 04 0 0 0 0 1 0 0 HSHK is used to command the ST75C520 to begin the transmit handshake sequence processing. The progress of the handshake is reported to the control processor. Non parametric command. IDT Identify 14 0 0 1 0 1 0 0 IDT Return the ST75C520 Hardware and Software release number. See paragraph VII.1.4. Non parametric command. INIT Initialization 06 0 Synopsis 1 FORM defines the type of transmission used. This format is valid only in the parallel data mode. The default format, unless specified, is synchronous. INIT Opcode: FORM 09 0 Synopsis Parameter Definition Select Transmission Format IDT Opcode: Value The default IT Status is 0x3F for STATUS[0] and 0xFF for STATUS[1]. 0 Synopsis 1 1 HSHK Opcode: 1 Byte Parameters Notes : 0 Field 0 Synopsis 0 STA_IT_MSK0 FORM Opcode: 1 DSIT specifies the bit mask used with the STATUS[0] and STATUS[1] byte to generate an interrupt IT4 to controller. Each time a bit change happens in the status words, assuming the corresponding bit mask will be set, an interrupt will be generated. Parameters Notes : DSIT Define Status Interrupt 0 0 0 0 1 1 0 INIT forces the ST75C520 to reset all parameters to their default conditions and restart operations. Non parametric command. This command makes a software reset of the ST75C520 and so cannot have the regular handshake protocol. It does not increment the COMACK, neither generate an Interrupt. 21/45 ST75C520 JSR Opcode: 18 0 Synopsis 0 0 Field Byte Pos. Low byte of the call address High byte of the call address C_DATA_L 3 7..0 Low byte of the argument C_DATA_H 4 7..0 High byte of the argument 0 1 0 0 0 0 1 MODC allows modification of the configuration for special purpose. This command has no effect while in data mode, the parameters are just sampled when starting to transmit or receive. The value of these parameters are not affected when sending a CONF command. Field Byte Pos. Value MODC_SH 1 6 0* 1 Normal training sequence (1) Short training sequence MODC_FPT 2 3..2 00* 01 10 No echo protection tone Long echo protection tone (180ms) Short echo protection tone (30ms) Definition 1. Short train sequence must be preceded by at least one normal training sequence. MR Memory Read 10 0 0 1 0 0 0 0 MR allows the reading of a 16-bit parameter. The parameter specifies the parameter address. Field Byte Pos. MR_ADDR_L 1 7..0 Low byte of the 16-bit address MR_ADDR_H 2 7..0 High byte of the 16-bit address Value Definition MW Memory Write 12 0 22/45 MODC Modify Configuration 21 MW Parameters Definition 7..0 Parameters Synopsis Value 7..0 0 Opcode: 0 1 MR Synopsis 0 2 Parameters Opcode: 0 C_ADDR_L 0 Notes : 1 C_ADDR_H MODC Synopsis 1 JSR allows to execute a part of the ST75C520 firmware with a specific argument. Parameters Opcode: JSR Call a Low Level Subroutine 0 0 1 0 0 1 0 MW allows the writing of a 16-bit parameter. The parameter specifies the address as well as the value to be transferred. Field Byte Pos. Value Definition MW_ADDR_L 1 7..0 MW_ADDR_H 2 7..0 Low byte of the 16-bit address High byte of the 16-bit address MW_VALUE_L 3 7..0 Low byte of the 16-bit value MW_VALUE_H 4 7..0 High byte of the 16-bit value ST75C520 SERIAL Opcode: 07 0 Synopsis 0 0 0 1 1 Field Byte Pos. Value 1 0 0* 1 Use serial link for Tx Data Use parallel link for Tx Data RX_SDATA 1 1 0* 1 Use only serial link for Rx Data Use also parallel link for Rx Data Definition The received Bits always go to the output pin RXD, even when the RX_SDATA bit is set. SETGN Set Output Gain 02 0 Synopsis 1 TX_SDATA SETGN Opcode: 0 SERIAL defines the data path, i.e. either serial or parallel. Parameters Notes : SERIAL Select Serial or Parallel Mode 0 0 0 0 0 1 0 SETGN is a command which sets the scaling factor of the transmit samples. It is used for setting the output level or for setting the level of the tone generators. The gain value is given in the form of a 2’s complement 16-bit value. Parameters Field Byte Pos. Value GAIN_L 1 7..0 range FF* Low byte of the 16-bit gain value Definition GAIN_H 2 7..0 range 7F* High byte of the 16-bit gain value Example Gain (dB) Gain (Hex) Gain (dB) Gain (Hex) Gain (dB) Gain (Hex) 0 7FFF -5 47FA -10 287A -1 7214 -6 4026 -11 2413 -2 65AC -7 392C -12 2026 -3 5A9D -8 32F5 -13 1CA7 -4 50C3 -9 2D6A -14 198A SLEEP Opcode: SLEEP Turn to Sleep Mode 03 0 0 0 0 0 0 1 1 Synopsis SLEEP is used to force the ST75C520 to turn to low power mode. Parameter Non parametric command. Notes : When receiving this command the ST75C520 will stop processing and so cannot have the regular handshake protocol. It does not increment the COMACK, neither generate an Interrupt. STOP Opcode: STOP FAX Stop Transmitter 25 0 0 1 0 0 1 0 1 Synopsis STOP is used, in FAX Modes, to force the ST75C520 to turn off the transmitter in accordance with the corresponding ITU-T V.33/V.17/V.29/V.27recommendation. Parameter Non parametric command. Notes : When receiving this command the ST75C520 will stop sending regular Data. In parallel mode this command must be preceded by a XMIT Stop command. In parallel mode the ST75C520 will wait until all the transmit buffers are sent before starting the Stop sequence. 23/45 ST75C520 SYNC Opcode: 26 0 Synopsis 0 0 0 1 Field Byte Pos. Value RX_SYNC 1 0 0* 1 TDRC 1 0 Definition Stop receiver Start receiver synchronization TDRC Tone Detector Read Coefficient 1A 0 Synopsis 1 SYNC is used, in FAX Modes, to force the ST75C520 to Start/Stop the receiver in accordance with the corresponding ITU-T V.33/V.17/V.29/V.27recommendation.As soon as the ST75C520 receives the SYNC Start command it sets its receiver to detect the FAX synchronization signal.This command is the equivalent HSHK command for the receiver. Parameters Opcode: SYNC FAX Synchronize the Receiver 0 0 1 1 0 1 0 TDRC Read one Coefficient of the selected Tone Detector Cell. Parameters Field Byte Pos. Value TD_CELL 1 3..0 0..F TD_C_ADDR 2 7..0 0..B 10 20 Other Definition Tone detector cell number Biquad coefficient Energy coefficient Static level Reserved The command answer is : Low Byte of Coefficient followed by High Byte of Coefficient. TDRW Opcode: 1B 0 Synopsis Parameters TDRW Tone Detector Read Wiring 0 0 1 1 0 1 1 TDRC Read Wiring of the selected Tone Detector Cell. Field Byte Pos. Value TD_CELL 1 3..0 0..F TD_W_ADDR 2 0 0 1 Other Definition Tone detector cell number Biquad and energy input Comparator inputs Reserved The command answer is: a) If TD_W_ADDR = 0 : - First Byte is the Node Number of the Signal connected to Biquadratic Filter input. - Second Byte is the Node Number of the Signal connected to the Energy estimator input. b) if TD_W_ADDR = 1 : - First Byte is the Node Number of the Signal connected to Comparator Negative input. - Second Byte is the Node Number of the Signal connectedto the Comparator Positive input. 24/45 ST75C520 TDWC Opcode: 1C 0 Synopsis 0 0 1 Field Byte Pos. 1 0 0 Value Definition TD_CELL 1 3..0 0..F TD_C_ADDR 2 7..0 0..B 10 20 Other TD_COEFL 3 7..0 Low byte of coefficient TD_COEFH 4 7..0 High byte of coefficient TDWW Tone detector cell number Biquad coefficient Energy coefficient Static level Reserved TDWW Tone Detector Write Wiring 1D 0 Synopsis 1 TDWC Write one Coefficient of the selected Tone Detector Cell. Parameters Opcode: TDWC Tone Detector Write Coefficient 0 0 1 1 1 0 1 TDRC Write Wiring of the selected Tone Detector Cell. Parameters Field Byte Pos. Value TD_CELL 1 3..0 0..F TD_W_ADDR 2 0 0 1 Other Definition Tone detector cell number Biquad and energy input Comparator inputs Reserved If TD_W_ADDR = 0 (Select Biquad and Energy Inputs) Parameters Field Byte Pos. Value Definition TD_W_ERN 3 0..3F Energy estimator signal input TD_W_BIQ 4 0..3F Biquad filter signal input If TD_W_ADDR = 1 (Select Comparator Inputs) Parameters Field Byte TD_W_CN 3 0..3F Negative comparator signal input TD_W_CP 4 0..3F Positive comparator signal input TDZ Opcode: Parameters Value Definition TDZ Tone Detector Clear Cell 1E 0 Synopsis Pos. 0 0 1 1 1 1 0 TDZ Clears all internal variables of one Tone detector cell including Filter local variables and energy estimator. This command must be sent after changing coefficients of a cell to avoid instability. Field Byte Pos. Value TD_CELL 1 3..0 0..F Definition Tone detector cell number 25/45 ST75C520 TGEN Opcode: 0D 0 Synopsis 0 0 0 Pos. Value 1 0 0* 1 Generator #0 disabled Generator #0 enabled TONE_1_ENA 1 1 0* 1 Generator #1 disabled Generator #1 enabled TONE_2_ENA 1 2 0* 1 Generator #2 disabled Generator #2 enabled TONE_3_ENA 1 3 0* 1 Generator #3 disabled Generator #3 enabled TONE 0C 0 0 0 1 1 0 0 TONE programs the tone generators for the predefined tones. The tone generators #0 and eventually #1 are reprogrammed with this command. Eventually the tone generator #0 and #1 are enabled. Using a value not in the following table will disable tone generator #0 and #1. Field Byte Pos. Value TONE_SELECT 1 5..0 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 Definition DTMF 0 (941 & 1336Hz) DTMF 1 (697 & 1209Hz) DTMF 2 (697 & 1336Hz) DTMF 3 (697 & 1477Hz) DTMF 4 (770 & 1209Hz) DTMF 5 (770 & 1336Hz) DTMF 6 (770 & 1477Hz) DTMF 7 (852 & 1209Hz) DTMF 8 (852 & 1336Hz) DTMF 9 (852 & 1477Hz) DTMF A (697 & 1633Hz) DTMF B (770 & 1633Hz) DTMF C (852 & 1633Hz) DTMF D (941 & 1633Hz) DTMF * (941 & 1209Hz) DTMF # (941 & 1477Hz) Answer tone (2100Hz) Tone (1650Hz) Answer tone (2225Hz) Tone (1300Hz) XMIT Start/stop Transmission 01 0 26/45 Definition Predefined Tones XMIT Parameters 1 Byte Parameters Synopsis 0 Field 0 Opcode: 1 TONE_0_ENA TONE Synopsis 1 TGEN causes the ST75C520 to enable or disable the four tone generators. Parameters Opcode: TGEN Enable/disable Tone Generators 0 0 0 0 0 0 1 XMIT start or stop the transmission of the Parallel Transmit Data. This command work only if the Parallel Transmit Data mode has been selected with a SERIAL command. Field Byte Pos. Value TX_START 1 0 0* 1 Definition Stop transmission Start transmission ST75C520 VII - STATUS DESCRIPTION In the case of a memory reading command (CR, TDRC, TDRW, IDT or MR) once the command entered is executed, the report area is filled and the acknowledge counter is incremented afterwards. This insures that the controller will read the value corresponding to its request. This appendix is dedicated to the ST75C520 reporting features. in the following sections the command acknowledge process and the report and status definitions are explained. VII.1 - Command Acknowledge and Report VII.1.1 - Command Acknowledge Process (see Figure 1) The ST75C520 features an acknowledge process based on a counter COMACK. On power-on reset (or INIT command), this counter’s value is set to 0. Each time a command is successfully executed by the ST75C520, the acknowledge counter COMACK is incremented. This allows a precise monitoring of the command entered and avoids command collision. Furthermore, the ST75C520 resets the value of the COMSYS register once the command has been read. The interruption IT6 is raised just after the counter is incremented. VII.1.2 - Reports Specification The report section of the Dual Port RAM is dedicated to memory reading. In response to a CR, MR, TDRC, TDRW, IDT commands, the value read is transferred to the report registers COMREP[0..1]. Figure 1 : Command Acknowledge Process BEGIN COMSYS = 0 No Yes COMMAND EXIST No CLEAR ANSWER EXECUTE COMMAND COPY ANSWER INTO COMREP INC REMENT COMACK SET SY SERR SET SYSERR ERR_IPRM ERR _IOCD ASSERT ASS ERT INTER RUPT INTE RRUP T IT0 IT0 CLEAR COMSYS ASSERT INTERRUPT IT6 75C52006.EPS Yes END 27/45 ST75C520 VII.1.3 - CR Command Issuing a CR command causes the ST75C520 to dump a specific memory location in complex mode. This instruction is particularly useful for equalizer state analysis or for software eye-pattern display. The report area has this meaning : RP7 RP6 RP5 RP4 RP3 RP2 RP1 RP0 COMREP[0] IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 COMREP[1] RP0..RP7 is the MSB part of the 16-bit value of the real part and IP0..IP7 is the MSB part of the imaginary part. The CR command insures that the real and imaginary part of the desired complex value are sampled internally at the same time. The address given in the parameter field of CR is the address of the real part. VII.1.4 - MR/TDRC/TDRW/IDT Commands The report issued by the MR/TDRC/TDRW/IDT commands follow the same rules as for CR. The report meaning is : D7 D6 D5 D4 D3 D2 D1 D0 COMREP[0] D15 D14 D13 D12 D11 D10 D9 D8 COMREP[1] D0..D15 is the 16-bit value required by the MR/TDRC command. In the case of IDT, D15..D12 contains the product identification (2 for ST75C520), D11..D8 contains the hardware revision identification and D7..D0 contains the software revision identification. VII.2 - Modem Status VII.2.1 - Modem Status Description The Status of ST75C520 is divided into 4 fields : - The error status byte SYSERR that provides information about error. This status can trigger an IT0 interrupt, - The general status byte STATUS[0] and STATUS[1] that contains all the modem signals. These status bytes can trigger an IT4 interrupt, - The quality status STAQUA, that contains the quality of the received transmission, - The optional status bytes STAOP[0], STAOP[1] and STAOP[2], that contains additional information regarding the ST75C520 operatingmode. This defaultinformation can be changed to monitor any internal variables using the DOSR command. All these informations are updated on a Baud basis : Mode Baud Rate (2) (Hz) CLK (Hz) Tone, DTMF, Voice 2400 9600 Bell 103 (full duplex) 2400 9600 V.21 (full duplex) 2400 9600 V.23 (full duplex) 2400 9600 V.27ter 2400bps 1200 2400 V.27ter 4800bps 1600 (1) 4800 V.29 2400 9600/7200/4800 V.17 2400 14400/12000/9600/7200 V.33 2400 14400/12000 V.21 channel 2 2400 300 Notes : 1. The tone detectors outputs are update 800 times by second. 2. This baud rate defines also, the maximum command rate. Each baud time the ST75C520 looks at the COMSYS location (addesss $00) to see if a command have been sent by the host processor. If the content of this location is different from zero the ST75C520 execute the command. 28/45 ST75C520 Starting at the adddress $08 the status area have the following format : Add. $08 Bit Name SYSERR 7 6 5 ERR_RTK - - 4 3 ERR_IPRM ERR_IOCD $09 STATUS0 STA_109F STA_CPT10 STA_CPT1 STA_CPT0 STA_RING $0A STATUS1 STA_DTMF STA_FLAG $0B STAQUA $0C STAOP0 $0D STAOP1 $0E STAOP2 - - STA_HR STA_AT 2 1 0 - ERR_RX ERR_TX STA_106 STA_CCITT STA_107 STA_109 - STA_H Quality Depend on operating mode (see below) VII.2.2 - Error Status The error status changes each time an error occurs. When the ST75C520 signals an error by setting one of the SYSERR bit, it generates an interrupt IT0. These bits can only be cleared by the host controler using the CSE command. The meaning of the different bits of the SYSERR byte is discribed below : Field ERR_TX Pos. 0 ERR_RX 1 ERR_IOCD ERR_IPRM ERR_RTK 3 4 7 SYSERR Meaning when set Transmit buffer underflow. Loss of synchronisation between the host and ST75C520 transmit data buffer managment. Receive buffer overflow. Loss of synchronisation between the host and ST75C520 receive data buffer managment. Incorrect CCI command Incorrect parameter for the CCI command Real time kernel error. ST75C520 not able to perform all its tasks within the baud period (transmit or receive samples lost). VII.2.3 - Modem General Status The modem general status word is composed of two bytes STATUS[0] and STATUS[1]. Any bit change can generate an IT4 interrupt. Using the DSIT command allows the selection of the corresponding bit that will generate an interrupt each time they will change. The default pattern is $3F for STATUS[0] and $FF for STATUS[1]. The different bits have the following meaning : Field STA_109 Pos. 0 STA_107 STA_106 1 2 STA_RING 3 STA_CPT0 STA_CPT1 STA_CPT10 STA_109F 4 5 6 7 STATUS[0] Meaning when set CCITT circuit 109 (carrier detect). Indicates that valid data are received. When 0 the output data RxD are clamped to constant mark. Valid only in modem mode. CCITT circuit 107 (data set ready). Valid only in modem mode. CCITT circuit 106 (clear to send). Indicates that the training sequence has been completed and that any data at TxD pin (serial mode) or in the transmit buffer (parallel mode) will be transmitted. valid only in modem mode. Ring detected. A ring signal (from 15Hz to 68Hz) is present at the RING pin. Valid only in tones modes. The precise frequency can be read in the optional status byte STAOP2. The detection time is 1 period of the ring signal. The detection lost time in 20ms after the last transition on the ring signal. Call progress tone detector #0. Low pass filter 650Hz. Valid only in tones modes. Call progress tone detector #1. High pass filter 600Hz. Valid only in tones modes. Signal in filter #0 is highter than #1. Valid only in tones modes. Fast Carrier Detect. Valid only in modem mode. 29/45 ST75C520 STATUS[1] Field STA_H STA_CCITT Pos. 0 2 STA_AT STA_HR STA_FLAG STA_DTMF 3 4 6 7 Meaning Transmit synchronisation in progress. Valid only in modem mode. CCITT 2100Hz versus 2225Hz answer tone detect. Valid if STA_AT is set. Valid only in tones modes. Answer tone (either 2100Hz or 2225Hz) detected. Valid only in tones modes. Receive synchronisation in progress. Valid only in modem mode. V.21 channel 2 flag detect. Valid only in FAX modem mode and tone mode. DTMF digit detect. The digit itself is available in the optional status byte STAOP2. Valid only in DTMF receive mode. VII.2.4 - Quality Status The quality byte STAQUA monitors an evaluation of the line quality. It is updated once per baud and its value ranges from 127 (perfect quality) to 0 (terrible quality). This value is automaticaly adjusted according to the current receiving mode. Refer to the following chart to convert the value into its Bit Error Rate equivalence. BER -2 1e -3 1e -4 1e -5 1e -6 1e -7 -8 75C52020.EPS 1e STAQUA 1e -9 1e 0 31 63 95 127 VII.2.5 - Optional Status According to the operating mode of the ST75C520 the optional status is displaying different informations. The optional status are automatically reprogrammed after each CONF command with the address of the variables to monitor according with the operating mode selected (CONF_OPER). After the CONF command the user must overwrite this default programming by using the DOSR command. VII.2.6 - Default Optional Status in Tone Mode While in tone mode the format of the STAOP word is as follows : Add. Name Bit 7 6 5 4 3 2 1 0 $0C STAOP0 TDT7 TDT6 TDT5 TDT4 TDT3 TDT2 TDT1 TDT0 $0D STAOP1 TDT15 TDT14 TDT13 TDT12 TDT11 TDT10 TDT9 TDT8 $0E STAOP2 RING_PERIOD (1) Notes : 1. RING_PERIOD is valid when the bit 3 of the STATUS[0] (STA_RING) goes high. This value is updated at each falling edge of the RING signal. The RING_PERIOD value must be divided by 2400 to obtain the period in seconds. 2. TDTx is the output of the tone detector x. 30/45 ST75C520 VII.2.7 - Default Optional Status in DTMF Receiver Mode While in DTMF receiver mode the format of the STAOP word is as follows : Add. Bit Name 7 6 (1) $0C STAOP0 TDT7 $0D STAOP1 TDT15 $0E (1) TDT6 5 (1) TDT14 (1) TDT5 4 (1) TDT13 (1) STAOP2 3 (1) TDT4 TDT12 2 TDT3 (1) TDT11 DTMF_DIGIT (1) 1 TDT2 TDT10 0 TDT1 (1) TDT9 TDT0 (1) TDT8 (1) (2) Notes : 1. These cells are used by the DTMF detector. 2. DTMF_DIGIT is valid when the bit 7 of STATUS[1] (STA_DTMF) goes high. This value remains unchanged until a new DTMF digit is detected. VII.2.8 - Default Optional Status in Modem Mode While in modem mode the format of the STAOP word is as follows : Add. Bit Name $0C STAOP0 $0D STAOP1 $0E STAOP2 7 6 5 x x x 4 3 2 1 0 SPEED (2) SPVAL (1) Not used PNSUCs PRDETs PNDETs SCR1s PRs PNs P2s P1s Notes : 1. SPVAL is active in V.33 receiver only at the same time as the rising transition of the SCR1s signal. Went SPVAL is set, it indicates that the SPEED bits contain the data speed information. 2. SPEED is valid in V.33 receiver only. It can have 2 values, after the SCR1s signal goes high : 1000 for 14400bps and 0111 for 12000bps. 3. The STAOP2 bit reflects the progression of the synchronization. The STAOP2 bits have the following meaning : Name Position P1s 0 Unmodulated carrier sequence. Optional, used for echo protection. Description Tx Rx X P2s 1 Continuous 180° phase reversal sequence X X PNs 2 Equalizer trainning sequence X X PRs 3 V.33 and V.17 rate sequence X X SCR1s 4 Continuous scrambled 1 sequence PNDETs 5 Turned on after PN sequence detection X X PRDETs 6 Turned on after PR sequence detection (V.33 and V.17 only) X PNSUCs 7 Turned on after succesfull training of the receive equalizer. When on at the end of the synchronization, the transmition BER is statisticaly bellow 10ppm. X 31/45 ST75C520 With the following timing : P1 T2 T1 Transmit P2 PN R SCR1 T3 T4 T5 T6 Data S TA_H P1s P2s PNs PRs (6) S CR1s T7 Receive T7 T8 T8 T8 T8 (7) S TA_HR S TA_109F P2s PNDETs PNs PRDETs P NSUCs (1) (2) S CR1s 75C52021.EPS S TA_109 RxData Mode T1 (4) T1p (5) T2 T3 T4 T5 T6 T7 T8 V.17 192 30 22 107 1240 27 20 5 7 Unit ms V.17 short 192 30 22 107 16 0 20 5 7 ms V.29 192 30 22 53 160 0 20 5 7 ms V.29 short 192 30 22 41 26 0 8 5 7 ms V.27 4800 192 30 22 31 670 0 5 5 7 ms V.27 4800 short 192 30 22 9 36 0 5 5 7 ms V.27 2400 192 30 22 42 895 0 7 6 7 ms V.27 2400 short 192 30 22 12 48 0 7 6 7 ms 32/45 ST75C520 Data SCR1 T10 Transmit T11 m in STA_H P1s P2s PN s PR s (6) SCR1s T12 Receive T13 (3) STA_HR STA_109F PN DETs (3) PN s PR DETs (3) PN SUC s (3) 75C52022.EPS STA_109 RxData Mode T10 T11 T12 T13 Unit V.17 13 20 8 25 ms V.17 short 13 20 8 25 ms V.29 13 20 8 25 ms V.29 short 13 20 8 25 ms V.27 4800 20 30 8 25 ms V.27 4800 short 20 30 8 25 ms V.27 2400 27 40 8 25 ms V.27 2400 short 27 40 8 25 ms Notes : 1. 2. 3. 4. 5. 6. 7. In the case of V.29 or V.27, PRs and PRDETs bits are not active. PNSUC s indicates the quality of the Rx signal that will give a ber of approximation of 1e-5. After sending the command SYNC0, all bits are reset. When using long echo protection tone, otherwise 0. When using short echo protection tone, otherwise 0. STA-106 is set at the end of T6 and reset at the beginning of T10. After sending the command SYNC1, this bit is set. 33/45 ST75C520 VIII - TONE DETECTORS Each Biquadratic Filter, Power Estimator and Static Level can be programmed using a complete set of Commands (TDRC, TDRW, TDWC, TDWW, TDZ). The wiring between the different Cells can be defined by the user, using the associatedCommand allowing a wide range of applications. The 16 Comparator Outputs give, on a baud basis, the information into two 8 bits words TONEDET0 (for cells number 0 to 7) and TONEDET1 (for cells number 8 to F). These TONEDET variables can be accessed using a MR command or, more easily, monitored on a baud basis using the DOSR command. VIII.1 - Overview The general purpose TS75C520 tone detectors block is a powerful module that covers a lot of applications : - call progress tone detection, fully programmable for all countries, - DTMF detection, - FAX, voice, data automatic detection, - call waiting detection,while in voice or data mode. VIII.2 - Description VIII.2.1 - Biquadratic Filters Each Biquadratic Filter is a double regular section that can perform any Transfer function with 4 Poles and 4 Zeros. This routine is run on a sample basis. The tone detectorblock is a set of 16 identical Cells. Each cell is composed of a Double Biquadratic Filter, a Power estimator section, a Static level and a Level comparator. Figure 2 : Biquadratic IIR Filter C0 C5 C6 CB 2 2 Z -1 Z -1 C1 C3 C7 OUT C9 Z -1 Z -1 C2 Z -1 C4 C8 CA The corresponding transfer function is : Out Input = C0 ⋅ ±1 C5 + 2 ⋅ C3 ⋅ z + 2 ⋅ C4 ⋅ z ±2 1 ± 2 ⋅ C1 ⋅ z±1 ± 2 ⋅ C2 ⋅ z±2 ⋅ C6 ⋅ CB + 2 ⋅ C9 ⋅ z±1 + 2 ⋅ CA ⋅ z±2 ±1 ⋅z 1 ± 2 ⋅ C7 ⋅ z±1 ± 2 ⋅ C8 ⋅ z±2 Note : All coefficients are coded on 16 bits 2’s complement in the range +1, -1 (Q15). To avoid the possibility of overflow the user must check that the internal node must not be higher that 0.5 (in Q15 representation). 34/45 75C52007.EPS IN ST75C520 VIII.2.2 - Power Estimation The Power estimation Cell is needed to measure the amplitude of the different tones. It is run on a sample basis. corresponding bit into the TONEDET[0..1] word; if not it clear this bit. VIII.2.5 - Wiring The user must specify the connection (wiring) between the input/outputof the Filter, the input/output of the Power estimator, the output of the static levels and the two inputs of the Comparators. The output signals have an absolute address: Figure 3 : Power Estimator OUT + ABS(.) Z -1 P1 Z -1 The corresponding transfer function is : Out = | Input | ⋅ z ±1 ⋅ P1 1 ± (1 ± P1) ⋅ z±1 VIII.2.3 - Static Level A single Threshold level is associated with each Cell. It can be use to compare the outputof a Power Estimation with an Absolute Value. VIII.2.4 - Comparator The Comparator computes, on a baud basis, the difference of the signal on its Positive and Negative Inputs. If the result is Higher that zero it sets the 75C52008.EPS IN Node Address Signal Name Address Description Ground 00 Signal always equal to 0000 RxSig 01 Receive signal from the Analog front end RxSig2 02 Receive signal multiplied by 2 03 Receive signal multiplied by 4 RxSig4 04..0F Reserved Filter[0..F] 10..1F Biquadratic Filter Outputs Power[0..F] 20..2F Power Estimator Outputs Level[0..F] 30..3F Static Levels The user will specify the inputs of the filters, Power and Comparator. At leastone input must come from the RxSig (node 01, 02 or 03). It is mandatory to connect all unused cell inputs to the Ground signal (node 00). 35/45 ST75C520 Figure 4 : Tone Detector Wiring Address (first half) BIQUADR ATIC FILTER #0 @10 POWER #0 @2 0 @3 0 COMP. #0 LEVEL #0 BIQUADRATIC FILTER #1 @11 POWER #1 @2 1 @3 1 COMP. #1 LEVEL #1 BIQUADRATIC FILTER #2 @12 POWER #2 @2 2 @3 2 COMP. #2 LEVEL #2 @00 GROUND BIQUADR ATIC FILTER #3 @13 POWER D0 @2 3 #3 @3 3 COMP. #3 2 D3 BIQUADRATIC FILTER #4 @14 POWER #4 D4 @2 4 @3 4 LEVEL #4 COMP. D5 #4 D6 @03 2 D2 LEVEL #3 @01 RX SIGNAL @02 D1 D7 BIQUADRATIC FILTER #5 @15 POWER #5 @2 5 @3 5 TONEDET0 COMP. #5 LEVEL #5 BIQUADRATIC FILTER #6 @16 POWER #6 @2 6 @3 6 COMP. #6 LEVEL #6 @17 POWER #7 @2 7 @3 7 LEVEL #7 36/45 COMP. #7 75C52009.EPS BIQUADRATIC FILTER #7 ST75C520 Figure 5 : Tone Detector Wiring Address (second half) BIQUADRATIC FILTER #8 @18 POWER #8 @28 @38 COMP. #8 LEVEL #8 BIQUADRATIC FILTER #9 @19 POWER #9 LEVEL #9 BIQUADRATIC FILTER #A @1A POWER #A @29 @39 COMP. #9 @2A @3A COMP. #A LEVEL #A BIQU AD RATIC FILTE R #B @1B POWER #B LEVEL #B D0 @2B @3B COMP. #B D1 D2 D3 BIQUADRATIC FILTER #C @1C POWER #C D4 @2C @3C COMP. #C LEVEL #C D5 D6 D7 BIQUADRATIC FILTER #D @1D POWER #D @2D @3D TONEDET1 COMP. #D LEVEL #D BIQUADRATIC FILTER #E @1E POWER #E @2E @3E COMP. #E LEVEL #E @1F POWER #F @2F @3F COMP. #F 75C52010.EPS BIQUADRATIC FILTER #F LEVEL #F 37/45 ST75C520 VIII.3 - Example Hereunder is an example of programming a single Tone detection (using Cell #3) and a complex differential tone detection (using Cell #4 and #5). Bit 3 of the TONEDET variable will be triggered each time the energy of that filtered signal is higher than Static Level number 3. Bit 4 of the TONEDET variable will be on each time a receive signal has an energy higher than the Static Level number 4. Bit 5 will be on only when the Filtered (Filter section 4 and 5) received signal higher than the energy of the wide-band signal number 4 ; this prevents triggering on noise. Figure 6 : Wiring Example @00 GROUND BIQUADRATIC @13 FILTER #3 POWER #3 @23 @33 @01 BIQUADRATIC @02 @14 FILTER POWER #4 2 @24 D3 #4 @34 COMP. #4 LEVEL #4 D5 @03 2 D4 BIQUADRATIC FILTER #5 @15 POWER @25 TONEDET0 #5 @35 LEVEL #5 Program Cell #3 : TDWW 03 00 13 Connect Received signal to Filter and Filter to Energy. TDWW 03 01 33 Connect Level to Comparator Neg Input and Energy to Pos Input. Program Cell #4 and #5 : TDWW 04 00 01 Connect Received Signal to Filter and Energy. TDWW 04 01 34 Connect Level to Comparator Neg Input and Energy to Pos Input. TDWW 05 00 15 Connect Filter#4 Output to Filter and Filter to Energy. TDWW 05 01 24 COMP. #5 01 23 01 24 14 25 Connect Wide-band Energy to Neg Input and Energy to Pos Input. IX - BUFFER OPERATIONS IX.1 - Introduction This appendixis dedicatedto buffer operation, either the data buffersused in data exchanges or in particular Modes (like Voice). The first part is oriented towards a functional description of the buffer operation, while the second section is more oriented towards the management of the buffers. 38/45 75C52011.EPS RX SIGNAL COMP. #3 LEVEL #3 ST75C520 IX.2 - Receive Operations Overview Figure 7 describes the receive data flow. The ST75C520 can handle the following types of format for the data : - parallel synchronous mode : 8-bit words are synchronously available in the receive buffers. The buffer status holds the number of valid bytes received, - parallel HDLC framing mode : 8-bit data is available in the receive buffers. Framing information (like flags, CRC, additional ”0”) is interpreted by the ST75C520 and reported when necessary in the receive buffer status (CRC error, aborted frame, framing error, etc). This feature greatly eases the implementation of protocols as well as FAX data management. Each time the receive deframer has filled up a new buffer, it sets the correspondingflag with the proper status then generates the IT3 interrupt. The availability of the buffers is tested just before starting to fill them. This further means that the host must not perform any buffer operation on the data part while the status remains 0. IX.3 - Transmit Operations Overview Figure 8 describes the transmit data flow. The following modes are available : - parallel synchronous mode : 8-bit words are synchronously read from the transmit buffers. The transmit status buffer holds the number of valid bytes to be transmitted (up to 8 per buffer), - parallel HDLC framing mode : 8-bit data is received from the transmit buffers. Framing information (frame open, frame close, frame abort, number of byte per buffer) is carried by the transmit buffe r s tat us a nd processed by th e ST75C520. CRC, padding and other operations are automatically handled by the ST75C520. Each time the transmit framer has emptied a buffer, the IT2 interrupt is raised. Figure 7 : Rx Buffer Schematics ER ROR R X (SYSERR ) DA TA FO R M AT R EC E I V E R IT 3 S TA TU S R X B U FF E R ST A T U S RECEIVE DEFRAMER RX DATA BU F F E R D ATA S ER IA L OUT RXD 75C52012.EPS R EC E I V E R RX C LK Figure 8 : Tx Buffer Schematics E RR OR TX (SYSER R) D ATA FO RM A T TRAN SM ITTER STATU S IT2 T X B U FF E R S T A TU S SERIAL TRANSM ITTER FRAMER MU X T X D AT A BUFFER S E RI AL IN TXD 75C52013.EPS TRAN SM ITTER DATA T X C LK 39/45 ST75C520 IX.4 - Buffer Status and Format Description The following section describes the meaning and use of the buffer status words. IX.4.1 - Transmit Buffer The transmit buffer status words are DTTBS0 and DTTBS1 (see the Host Interface Summary section in the main document) and are more likely to be seen as control words. These words must be set by the host and are reset by the ST75C520. The data buffer exchanges are synchronized through these status words, (see Buffer Status and format description)an impropersetting will trigger the error Err_Tx in the error status SYSERR. A value of 0 for DTTBS0 or DTTBS1 means that the corresponding buffers are empty : this value is written by the ST75C520. The unused bits of DTTBSx must be set to 0 by the host. In FSK Mode, when working in the parallel data mode, the transmitter expands each bit to the nominal baud time (1200Hz/300Hz/75Hz). IX.4.2 - Synchronous Mode Field Pos. Val. BUFF_LENG 3..0 1..8 DTRBS1 (see the Host Interface Summary section in the main document). These flags are set by the ST75C520 and must be reset by the host. The data buffer exchanges are synchronized through these status words, an improper resetting will trigger the error Err_Rx in the error status SYSERR. A value of 0 for DTRBS0 or DTRBS1 means that the corresponding buffers are empty : this value must be written by the host. In FSK or V.21 Channel 2 Mode, when working in the parallel data mode, the receiver extract each b it u s in g t h e n o min al b a u d rat e (1200Hz/300Hz/75Hz). IX.5.1 - Synchronous Mode Field Pos. Val. BUFF_LENG 3..0 1..8 IX.5.2 - HDLC Framing Mode Field Pos. Val. BUFF_LENG 3..0 1..8 Number of valid bytes in the buffer BUFF_ERRS 5..4 00 01 10 11 No error CRC error Non byte-aligned frame Aborted frame BUFF_SFRM 6 0 1 Data stream Start of frame BUFF_EFRM 7 0 1 Data stream End of frame Description Number of valid bytes in the buffer IX.4.3 - HDLC Framing Mode Field Pos. Val. Description BUFF_LENG 3..0 1..8 BUFF_SFRM 4 0 1 Data stream Start of frame BUFF_EFRM 5 0 1 Data stream End of frame BUFF_FRAB 6 0 1 Normal process Abort frame (no data in buffer) Number of valid bytes in the buffer IX.5 Receive Buffer The receive buffer status words are DTRBS0 and 40/45 Description Number of valid bytes in the buffer Description IX.6 - Data Buffer Management Figure 9 shows the general flow chart for transmit data buffer management. In the transmit path, the data buffer exchanges should always begin with the filling of buffer 0, then with the update of the buffer 0 status word. The initiation of the data exchanges is initiated then with the XMIT command. ST75C520 Figure 9 : Buffer Operations Synchronization Tx MAIN PROGRAM INTERRUPT ROUTINE BEGIN INTERRUPT NEED TO TRANSMIT N 106 ON N Y Y FILL BUFFER #IBUFF FILL BUFFER #0 UPDATE STATUS BUFFER #IBUFF UPDATE STATUS BUFFER #0 CLEAR IT2 IBUFF = 1 TOGGLE IBUFF XMIT ON ENABLE IT2 N 106 OFF or ERROR TX RETURN Y DISABLE IT2 XMIT OFF CSE ERRTX (only if ERR) Rx MAIN PROGRAM INTERRUPT ROUTINE BEGIN INTERRUPT READ BUFFER #IBUFF N 109 ON Y WRITE $00 IN DATA STATUS BUFFER #IBUFF WRITE $00 IN DATA STATUS BUFFER #0 AND #1 CLEAR IT3 IBUFF = 0 TOGGLE IBUFF ENABLE IT3 RETURN Y N 75C52025.EPS / 75C52014.EPS 109 ON DISABLE IT3 CSE ERRRX (only if ERR) 41/45 ST75C520 XI - DEFAULT ANSWER TONE DETECTORS Figure 10 : Call Progress Tone Detector Band 1 Figure 12 : 2100Hz Answer Tone Detector 75C52018.TIF Figure 13 : 2225Hz Answer Tone Detector 75C52016.TIF Figure 11 : Call Progress Tone Detector Band 2 75C52017.TIF 75C52015.TIF X - DEFAULT CALL PROGRESS TONE DETECTORS XII - ELECTRICAL SCHEMATICS Oscillator When using a third harmonic crystal oscillator in series resonance mode (RS < 40Ω, C0 = 6pF, Pe = 0.1mW), we recommend the following schematic : EX TA L X TA L 56 55 2 9 .4 91 2 M Hz 3 3p F 42/45 10n F 75C52023.EPS 5p F (opti onal) 1µH ST75C520 XII - ELECTRICAL SCHEMATICS (continued) Figure 14 22kΩ 220pF 40kΩ 13.2kΩ 22kΩ 8 TXA1 1.2kΩ 3 4 1 2 1 3 20kΩ 320Ω 8 RXA 2 2 4 15kΩ TL072 TL072 680pF 2.2nF 82kΩ 20kΩ 8 13.2kΩ TL072 5 22kΩ 6 TXA2 220Ω 4 7 6 2.2nF RXA 1 1.2kΩ 8 40kΩ 22kΩ 7 5 4 15kΩ TL072 TIP 220pF AVDD RING TRANSFORMER 1kΩ VREFP 100 nF 1 0µF 1kΩ 100nF 1 0µF 1kΩ VCM 10µF VREFN AGND 1kΩ AGND 75C52019.EPS 100nF AGND XIII - PCB DESIGN GUIDELINES Performances of the FAX modem depends on the ST75C520 intrinsic performances and on the proper PC board layout. All aspects of the proper engineering practices, for PC board design, are beyond the scope of this paragraph. We recommend the following points : - in a 4-layer PC board : Separated digital ground and analog ground, connected together at one point, as close as possible to the ST75C520, - in a 2-layer PC board : Provide a ground grid in all space around and - under components on both sides of the band and connect to avoid small islands, both AGNDR and AGNDT must be connected with very low impedance to a single point, (see Chapter I.7, Power Supply), the two 2.2nF capacitorsconnectedto the RXA1 and RXA2 Pins must be as close as possible to them, thetwo 100nFcapacitorsconnectedto the VREFPand VREFN pins must be as close as possible to them, analog and digital supplies must be connected together, at a single point, as close as possible to the chip (see Chapter I.7, Power Supply). 43/45 ST75C520 TYPICAL APPLICATION (third harmonic series resonance oscillator) L1 1µH C1 29.4912MHz Y1 5pF C2 33pF C3 10nF +5VA SCCLK EXTAL 56 * BOS 45 RDYS TXA1 2 TXA1 51 SCOUT TXA2 1 TXA2 42 SCIN 44 MCI RXA1 60 54 CLKOUT RXA2 61 48 MC0 47 MC1 AVDD 62 46 MC2 V REFP 58 D0 26 SD0 VCM 63 D1 27 SD1 D2 28 SD2 D3 29 SD3 D4 30 SD4 D5 31 SD5 D6 32 SD6 EYEX 7 TP1 D7 33 SD7 EYEY 6 TP2 DTACKl 37 SDTACK INTRl 38 SINTR CSl 36 SCS SR/W (WRl) 35 SR/W TXD 16 SDSl (RDl) 34 SDS CLK RXD 15 +5V R8 470 Ω R7 10k Ω XTAL 55 HALT/NOP 53 VREFN +5V R1 1.2kΩ * * 57 AGNDR 59 EYECLK 5 INT/MOT SA0 CD 13 A1 18 SA1 RTS 11 A2 19 SA2 CTS 12 A3 20 SA3 RING 10 A4 21 SA4 A5 22 SA5 A6 23 SA6 52 RESET DGND 8 9 DV DD DGND 24 25 DV DD DGND 41 DV DD MOTOROLA mode 10µF (select one of the two) * * EBS C9 100nF 14 17 +5V RXA2 R3 1.2k Ω EYESYNC 4 39 +5V C7 2.2µ F AGNDT 64 A0 RESE Tl DAA RXA1 C6 2.2µ F R2 1.2kΩ * 3 * C8 100nF R4 1.2k Ω C10 1 µF R5 1.2k Ω C11 1 µF VCM R6 1.2k Ω AGND (connec t close to the ST75C52) TxD RxD 40 * C12 C13 C14 10nF 10nF 10nF Notes : All capacitor with a ”*” must be implanted close to the ST75C520 pin. All signal name ending with a ”1” are active low. R3, R4, R5, R6 are needed if the hybrid will sink a current on VCM. 44/45 C5 10 µF EOS 50 +5V INTEL mode C4 100nF 49 CLK CDl V.24/RS232 RTSl CTSl RINGl 75C52024.EPS 43 ST75C520 PACKAGE MECHANICAL DATA 64 PINS - PLASTIC QUAD FLAT PACK A A2 (Seating Plane) 16 17 1 32 33 D D1 D2 64 B A1 e 49 48 C E2 E PMPQFP64.EPS L F E1 K A A1 A2 B C D D1 D2 e E E1 E2 F K L Min. 0.25 2.55 0.30 0.13 16.95 13.90 16.95 13.90 0.65 Millimeters Typ. 2.80 17.20 14.00 12.00 0.80 17.20 14.00 12.00 1.60 0.80 Max. 3.40 Min. 3.05 0.45 0.23 17.45 14.10 0.01 0.10 0.012 0.005 0.667 0.547 17.45 14.10 0.667 0.547 0o (min.), 7o (max.) 0.95 0.025 Inches Typ. 0.11 0.677 0.551 0.472 0.031 0.677 0.551 0.472 0.063 0.031 Max. 0.134 0.12 0.018 0.009 0.687 0.555 0.687 0.555 PQFP64.TBL Dimensions 0.037 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1995 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 45/45