STMICROELECTRONICS ST75C540

ST75C530
ST75C540
SUPER INTEGRATED DEVICES WITH DSP, AFE & MEMORIES
FOR TELEPHONY, MODEM, FAX OVER INTERNET & POTS LINES
SUMMARIZED FEATURES
(for detailed features, see page 4)
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SINGLE CHIP FAX Up to 14.4Kbps (V.17)
FULL DUPLEX DATA MODEM UP TO
14.4Kbps (V.32Bis)
DIGITAL ANSWERING MACHINE :
- 4.8Kbps VOCODER
- VARIABLEPLAYBACK SPEED (+50% to -50%)
- ADPCM 32, 34, 16Kbps VOCODER
FULL-DUPLEX DIGITAL SPEAKERPHONE
WITH ECHO CANCELLATION
PROGRAMMABLE RING DETECTION
16 PROGRAMMABLE TONE DETECTORS
FOR CLID AND SCWID
DTMF DETECTION
VERSATILE HOST INTERFACES
16 GENERAL PURPOSE I/O PORTS
2 RELAY DRIVE OUTPUTS
SINGLE 5V POWER SUPPLY
TYPICAL ACTIVE POWER CONSUMPTION :
650mW (ST75C530), 750 mW (ST75C540)
LOW POWER MODE < 30mW
80-PIN TQFP PACKAGE (14mm x 14mm)
DESCRIPTION
ST75C530 and ST75C540 are two super-integrated devices including DSP, Modem and Audio
Analog Front Ends and memories for Telephony,
Modem and FAX applications.
These devices can be used for classical applications over POTS lines or over Internet.
The super integration technology allows a significant cost reduction on bill of materials for equipment like High-End phones, INTERNET phones,
phone-Fax, INTERNET FAX, ...
The devices are used with a host processor
through a Dual Port RAM allowing the use of any
kind of microcontroller (RISC, CISC, General Purpose 8-bit µC, ...).
February 1999
TQFP80 (14 x 14 x 1.4mm)
(Full Thin Plastic Quad Flat Pack)
ORDER CODE : ST75C530FP-A
ST75C540FP-A
The embedded software includes :
- handset with listening group capability,
- full duplex handsfree,
- voice coder/decoderat 4.8Kbpsfor staticanswering machine applications and ADPCM 16Kbps,
24Kbps and 32Kbps for high quality message
recording,
- Tone and DTMF generators,
- Tone and DTMF detectors,
- FAX up to 14.4Kbps,
- Data-Modem up to 14.4Kbps (ST75C540 only).
The DSP sofware is extensively user configurable
allowing specific functions to be supported like
Caller Identifier (CLID) and Second Call Waiting
Identifier (SCWID).
The DSP software includes a transparent mode
allowing the host controller to access directly the
modem Analog Front End and the Audio AFE
through the dual Port RAM. This is very useful for
hostprocessing modem solutions (or soft modem)
where the modulation and the demodulation (V.34,
V.90) are done by the application main processor.
In transparent mode, the embedded DSP can be
used simultaneously with the same samples.
The transparentmode for audio AFE is provided to
play audio files or to record voice and/or audio.
1/84
ST75C530 - ST75C540
CONTENTS
Page
I
DETAILED FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
II
II.1
II.2
II.3
II.4
II.5
II.6
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN CONNECTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOST INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ANALOG INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GENERAL PURPOSE IO AND RELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5
6
6
6
7
7
III
BLOCK DIAGRAMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
III.1
III.2
ANALOG INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTERNAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
8
IV
ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
IV.1
IV.2
IV.3
IV.4
IV.5
IV.6
MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DIGITAL INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODEM ANALOG INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUDIO ANALOG INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
9
10
11
11
12
V
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
V.1
V.2
V.3
V.3.1
V.3.2
V.3.3
V.3.4
V.3.5
V.3.6
V.3.7
V.3.8
V.3.9
V.3.10
V.3.11
V.3.12
V.3.13
V.3.14
V.4
V.4.1
V.4.2
V.4.3
V.4.4
V.4.5
SYSTEM ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODES OF OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modem Transmitter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modem Receiver Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tone Generator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tone Detector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V.21 Channel 2 Flag Detector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HDLC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DTMF Detector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ring Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VOCODER Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voice Activity Detector (VAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Telephony Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General I/O and Relay Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Application Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
13
13
13
13
13
13
13
13
13
13
14
14
15
18
18
18
18
18
19
19
19
VI
VI.1
VI.2
VI.3
VI.4
VI.5
USER INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DUAL PORT RAM DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COMMAND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COMMAND SET SHORT FORM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STATUS - REPORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DATA EXCHANGES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
25
26
27
27
2/84
ST75C530 - ST75C540
VII
COMMAND SET DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
VIII
STATUS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
VIII.1
VIII.2
COMMAND ACKNOWLEDGE AND REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODEM STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
44
IX
TONE DETECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
IX.1
IX.2
IX.3
OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EXAMPLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
53
59
X
PARALLEL DATA EXCHANGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
X.1
X.2
X.3
X.4
X.5
X.6
OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRANSMIT BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RECEIVE BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTERRUPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DATA FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FORM COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
60
61
61
61
63
XI
TRANSMITTING DATA IN PARALLEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
XI.1
XI.2
XI.3
XI.4
XI.5
XI.6
XI.7
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODEM FLOW CHART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOST FLOW CHART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ERROR DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYNCHRONOUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HDLC MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART MODE DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
65
65
66
66
67
69
XII
XII.1
XII.2
XII.3
XII.4
XII.5
XII.6
XII.7
RECEIVING IN PARALLEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODEM FLOW CHART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOST FLOW CHART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ERROR DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYNCHRONOUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HDLC MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
70
70
70
71
72
72
74
XIII
VOCODER DATA EXCHANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
XIII.1
XIII.2
XIII.3
XIII.4
OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VOCODER BUFFER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRANSMIT (DECODER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RECEIVE (CODER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
74
74
75
XIV
TRANSPARENT MODE DATA EXCHANGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
XV
DEFAULT CALL PROGRESS TONE DETECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . .
76
XVI
DEFAULT ANSWER TONE DETECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
76
XVII
ELECTRICAL SCHEMATICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
XVIII
PCB DESIGN GUIDELINES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78
XIX
APPENDIX A : MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78
XX
PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
83
3/84
ST75C530 - ST75C540
I - DETAILED FEATURES
Single Chip Fax
- ITU-T V.17, V.29, V.27ter, V.21 with Fax support
- V.17 , V.29 (T104 ), V.2 7te r sho rt tra in s,
V.33 half-duplex
- V.21 flag detection and 4 tone detection during
high speed reception modes
- V.21 flag detection, DTMF detection and 4
tone detection duringV.21 channel 2 reception
modes
- Programmable call progress and call waiting
detection
- Parallel data handling
- HDLC and UART framing support
- 1700Hz and 1800Hz carrier
- Full implementation of the V.17, V.33, V.29 and
V.27 handshakes
- 0 to -15dBm programmable transmit power
- 0 to -47dBm receiver dynamic range (ST75C530)
0 to-45dBm receiver dynamic range (ST75C540)
Full Duplex Data Modem
- ITU-T V.32bis, V.32 (14400, 12000, 9600, 7200,
4800bps) (*)
- Maximum round trip delay : 1.2s (satellite hops)
(*)
- Up to 10Hz of phase roll on far end echo (*)
- ITU-T V.22bis, V.22 (2400, 1200bps) (*)
- V.32bis/V.32/V.22bis/V.22automode (*)
- ITU- V.23, V.21, bell 103 full-duplex,
Bell202 demodulator
- -10 to -25dBm programmable transmit power
- -10 to -38dBm receiver dynamic range (*)
- HDLC and UART framing support
- Train based on quality line sampling (*)
(*) ST75C540 only
Digital Answering Machine
- Low bit rate speech coder (4800bps)
- Variable playback speed (+50% to -50%)
- ARAM compatibility (error correction)
- ADPCM 32, 24, 16Kbps
- Line echo cancellation
- Voice activity detector
- Concurrent DTMF and tone detection
4/84
Handset Mode
- Rx and Tx AGC versus line current for line
losses compensation comply with most of
country regulations
- Dynamic limiter in transmit path to prevent
distortion
- Two way conversation recording
Hands-free Mode
- Full duplex speakerphone using LMS adaptative
filtering including line echo cancellation and
acoustic echo cancellation
- Rx and Tx AGC versus line current for line
losses compensation comply with most of
country regulations
- Dynamic limiter in transmit path to prevent
distortion
- Loudspeaker volume control
- Two way conversation recording
Extended Modes of Operations
- Programmable ring detection
- 16 programmable tone detectors
- Tone and DTMF generators
- Caller ID reception
- Transparent mode allowing direct transfer of Modem AFE and audio AFE samples to and from
host processor for soft Modem applications and
sound files playing
- DTMF detection
- Wide dynamic range (>48dB)
Versatile Interfaces
- Parallel 128 x 8-bit dual port RAM
- General purpose 16 I/O ports
- 2 relay drive outputs
- Full diagnostic capability
- Dual 8-bit DAC for constellation display
Single 5V Power Supply
- Typical active power consumption :
650mW (ST75C530), 725mW (ST75C540)
- Low power mode < 30mW
ST75C530 - ST75C540
II - PIN DESCRIPTION
GIO11
GIO12
GIO13
GIO14
GIO15
GIO16
GIO17
CLKOUT
XPLL
DGND5
DVDD5
XTALL
EXTALL
TEST0
RESET
SPK3N
SPK3P
SPK2N
SPK2P
AVDDA
II.1 - Pin Connections
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
SPK1N
1
60
GIO10
SPK1P
2
59
DVDD4
AGNDTA
3
58
DGND4
VREFN
4
57
GIO07
VREFP
5
56
GIO06
VCM
6
55
GIO05
AGNDRA
7
54
GIO04
MIC1
8
53
GIO03
MIC2
9
52
GIO02
MIC3
10
51
DVDD3
RxA
11
50
DGND3
AVDDM
12
49
GIO01
AGNDM
13
48
GIO00
TxA2
14
47
RING
TxA1
15
46
RELAY1
EYEX
16
45
RELAY0
EYEY
17
44
RGND
DGND6
18
43
INT/MOT
DVDD6
19
42
SINTR
DGND1
20
41
SCS
75C53001.EPS
SA6
SA5
SA4
SA3
SA2
SA1
SA0
SDS
SR/W
DVDD2
DGND2
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
DVDD1
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
5/84
ST75C530 - ST75C540
II - PIN DESCRIPTION (continued)
II.2 - Host Interface
The exchanges with the control processor proceed through a 128 x 8 DUAL port RAM shared between the
ST75C530/540 and the Host. The signals associated with this interface are :
Pin Name
Type
Description
SD0..SD7
I/O
System Data Bus. 8-bit data bus used for asynchronous exchanges between the
ST75C530/540 and the Host through the dual port RAM. High impedance when exchanges
are not active.
SA0..SA6
I
System Address Bus. 7-bit address bus for dual port RAM, IO and interrupt registers.
SDS (SRD)
I
System Data Strobe. In Motorola mode SDS initiates the exchange, active low. In Intel mode
SRD initiates a read exchange, active low.
SR/W (SWR)
I
System Read/Write. In Motorola mode SR/W defines the type of exchange read/write. In Intel
mode SWR initiates a write exchange, active low.
SCS
I
System Chip Select. Active low.
SINTR
OD
System Interrupt Request. Open drain. Active low. This signal isasserted by the ST75C530/540
and negated by the host.
RESET
I
Reset. Active low.
INT/MOT
I
Select Intel or Motorola Interface
II.3 - Analog Interface
Pin Name
Type
Description
TxA1
O
Transmit Analog Output 1
TxA2
O
Transmit Analog Output 2
RxA
I
Receive Analog Input
SPK1P
O
Speaker Output 1, (differential positive), must be connected through Amplifier to the
loudspeaker.
SPK1N
O
Speaker Output 1, (differential negative)
SPK2P
O
Speaker Output 2, (differential positive), must be connected through Amplifier to the Handset
loudspeaker.
SPK2N
O
Speaker Output 2, (differential negative)
SPK3P
O
Speaker Output 3, (differential positive)
SPK3N
O
Speaker Output 3, (differential negative)
MIC1
I
Microphone Input 1
MIC2
I
Microphone Input 2
MIC3
I
Microphone Input 3
VCM
I/O
Analog Common Voltage (nominal +2.5V). This input must be decoupled with respect to AGND.
VREFN
I
Analog Negative Reference (nominal 1.25V). This input must be decoupled with respect to
VCM.
VREFP
I
Analog Positive Reference (nominal 3.75V). This input must be decoupled with respect to VCM.
II.4 - General Purpose IO and Relay
Pin Name
Type
Description
GIO[0,7]
I/O
GIO[10,17]
I/O
General Purpose I/O Pins, can be independently selected as input or output.
RELAY0,
RELAY1
OD
Relay Outputs, Open Drain, Active Low. Can sink -10mA to RGND.
RING
I
RGND
PWR
6/84
General Purpose I/O Pins, can be independently selected as input or output.
Ring detect signal. Active low. If the ST75C530/540 is in low power mode, a low level will awake
the chip. This input is a Schmidt’s trigger.
Relay Digital Ground. To connect to GND.
ST75C530 - ST75C540
II - PIN DESCRIPTION (continued)
II.5 - Miscellaneous
Pin Name
Type
Description
EYEX
O
Constellation X analog coordinate
EYEY
O
Constellation Y analog coordinate
XTAL
O
Internal Oscillator Output. Left open if not used.
EXTAL
I
Internal Oscillator Input, or External Clock Input.
XPLL
I
Reserved for future use, must be connected to digital ground.
CLKOUT
O
Output Clock, EXTAL/2 (not available in low power mode).
TEST0
I
Test pin for normal operation, must be connected to digital ground.
Note : The nominal frequency of the crystal oscillator is 44.2368MHz with a precision better than ± 100ppm.
II.6 - Power Supply
Symbol
DVDD
Nber
6
Parameter
Digital +5V.
DGND
6
Digital Ground.
AVDD
2
Analog +5V.
AGND
3
Analog Ground.
7/84
ST75C530 - ST75C540
III - BLOCK DIAGRAMS
III.1 - Analog Interface
TXA1
15
DAC
MUTE
HYBRID
14
Line
TXA2
11
ADC
RXA
MUTE
[0..-30]dB
Step 3dB
1
2
DAC
SPK1
76
MUTE
SPK3
77
78
MUTE
9
ADC
8
SPK2
MIC2
MIC1
75C53002.EPS
79
10 MIC3
ST75C530/540
RELAY1
46
GIO AND RELAY
16 EYEX
EYE DAC
17 EYEY
SINTR 42
RAM
6144 WORDS
ANALOG
FRONT
END
TIME BASE
ROM
16368 WORDS
AUTOTEST
1024
INSTRUCTIONS
8/84
72 XTAL
OSC
Instruction
Bus
PROM
26624
INSTRUCTIONS
68 CLKOUT
73 EXTAL
ST18932
DSP
(24Mips)
47 RING
75C53003.EPS
Pins 22 to 29
SD[0..7]
45
DUAL
PORT RAM
Data Bus
Pins 34 to 40
SA[0..6]
RELAY0
ST75C530/540
Pins 60 to 67
GIO1[10..17]
Pins 48-49
Pins 52 to 57
GIO0[0..7]
III.2 - Internal Block Diagram
ST75C530 - ST75C540
IV - ELECTRICAL SPECIFICATIONS
IV.1 - Maximum Ratings (AGND = DGND = RGND = 0V, all voltages with respect to 0V)
Symbol
Parameter
AVDD
Analog Power Supply
DVDD
Value
Unit
-0.3, 6.0
V
Digital Power Supply
-0.3, 6.0
V
II
Input Current per Pin (except supply pins and RELAY0 and RELAY1)
-10, +10
mA
IO
Output Current per Pin (except supply pins and RELAY0 and RELAY1)
-20, +20
mA
IO2
Output Current per Pin RELAY0 or RELAY1 (respect to RGND)
-40, 0
mA
VIA
Analog Input Voltage
-0.3, AVDD + 0.3
V
VID
Digital Input Voltage
-0.3, DVDD + 0.3
V
5.25
V
0, +70
°C
- 40, +125
°C
1500
mW
VIDGPIO
Digital Input Voltage at GPIO
Toper
Operating Temperature
Tstg
Storage Temperature
Ptot
Maximum Power Dissipation
Warning : Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranted at these extremes.
IV.2 - Recommended Operating Conditions
(AGND = DGND = RGND = 0V, all voltages with respect to 0V)
Symbol
Parameter
VDD
Supply Voltage
IDD
Supply Current
PDLP
Min.
Typ.
Max.
Unit
4.75
5
5.25
V
130
145
150
165
mA
mA
30
mW
790
866
mW
mW
ST75C530
ST75C540
Low Power
PD
Power
VCM
Common Mode Voltage Output (refer to AVDD/2)
ICM
Common Mode Current (see Note 1)
ST75C530
ST75C540
650
725
-5
+5
100
%
µA
Note 1 : DC current only. If dynamic load exists, the VCM output must be buffered or the performances of ADCs and DACs will be degraded.
9/84
ST75C530 - ST75C540
IV - ELECTRICAL SPECIFICATIONS (continued)
IV.3 - Digital Interface
(AVDD = DVDD = 5V, AGND = DGND = RGND = 0V) except XTAL, EXTAL, RING.
Symbol
Parameter
Min.
VIH
High Level Input Voltage
2.2
VIL
Low Level Input Voltage
-0.3
VOH
High Level Output Voltage (Iload = -2mA, Iload = -4mA for SD[7..0])
2.4
VOL
Low Level Output Voltage (Iload = 2mA, Iload = 4mA for SD[7..0])
ILEAK
Input Leakage Current
-10
IOL
Low Level Output Current (except RELAY0 and RELAY1, and SINTR)
(0 < VOL < VOLMax.)
-2
IOH
High Level Output Current (except RELAY0 and RELAY1, and SINTR)
(0 < VOL < VOLMax.)
IOZ
GIO Three State Input Leakage Current (GND < VO < VDD)
-50
IOZ
SD Three State Input Leakage Current (GND < VO < VDD)
-50
Low Level Output Current RELAY0 or RELAY1 (VOL = 0.8V)
-10
IOLRELAY
Typ.
Max.
Unit
V
0.8
V
V
0.4
V
10
µA
mA
2
mA
0
50
µA
0
50
µA
0
mA
CRYSTAL OSCILLATOR
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IH
High Level Input Current
IL
Low Level Input Current
3.5
V
1.5
V
µA
-20
20
µA
2.8
V
RING (this input have hysteresis)
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
1
IH
High Level Input Current
-20
IL
Low Level Input Current
10/84
2.4
1.2
V
µA
20
µA
ST75C530 - ST75C540
IV - ELECTRICAL SPECIFICATIONS (continued)
IV.4 - Modem Analog Interface
AVDD = DVDD = 5V, Tamb = 25oC
Measurement bandwidth is flat from 100Hz to 4800Hz ;Load impedance 10kΩ, 20pF
For differential output (TxA1/TxA2) : 0dBr = 1.77VRMS 1kHz sinwave (equivalent to 5VPP).
For single input (RxA) : 0dBr = 886mVRMS 1kHz sinwave (equivalent to 2.5VPP).
Symbol
Pin Name
Rxrin
RxA
Rxmac
Input Impedance
Min.
Typ.
DC Reference Voltage
Rxsndr
Signal to (Noise + Distortion), at -6dBr
Rxin
TxA1/TxA2
TxAcl
Unit
2.5
VPP
kΩ
2.5
V
75
dB
Idle Noise
Rxov
Max.
100
Maximum AC Input Voltage = 0dBr
Rxdc
TxAdrl
Parameter
DC Offset Voltage (Input = VCM)
-50
Minimum Differential Load
10
-81
dBr
100
mV
kΩ
Maximum Differential Load
20
TxArout
Output Impedance
100
Ω
TxAmac
Maximum AC Differential Output = 0dBr
5
VPP
TxAdc
DC Reference Voltage
TxAov
DC Offset Voltage
TxAsndr
-200
Signal to (Noise + Distortion), at -6dBr
TxAin
2.5
pF
V
200
mV
-85
dBr
79
dB
Idle Noise
IV.5 - Audio Analog Interface
AVDD = DVDD = 5V, Tamb = 25oC
Measurement bandwidth is flat from 100Hz to 4800Hz ;Load impedance 10kΩ, 20pF
For differential output (SPK1N/SPK1P, SPK2N/SPK2P, SPK3N/SPK3P) : 0dBr = 1.77VRMS 1kHz sinwave
(equivalent to 5VPP).
For single input (MIC1, MIC2, MIC3) : 0dBr = 886mVRMS 1kHz sinwave (equivalent to 2.5VPP).
Symbol
Pin Name
RArin
MIC1,
MIC2,
MIC3
RAmac
Parameter
Input Impedance
Min.
RAdc
DC Reference Voltage
Distortion at -6dBr
RAin
Idle Noise
DC Offset Voltage (Input = VCM)
-50
Minimum Differential Load
10
TArout
TAmac
Maximum AC Differential Output = 0dBr
DC Reference Voltage
TAov
DC Offset Voltage
TAdis
Distortion at -6dBr
TAin
Idle Noise
2.5
VPP
2
%
-81
dBr
50
mV
V
kΩ
Output Impedance
TAdc
Unit
2.5
RAov
SPK1N/SPK1P,
SPK2N/SPK2P,
SPK3N/SPK3P
Max.
kΩ
Maximum AC Input Voltage = 0dBr
RAdis
TAdrl
Typ.
100
100
Ω
5
VPP
2.5
-200
V
200
mV
1
%
-81
dBr
11/84
ST75C530 - ST75C540
IV - ELECTRICAL SPECIFICATIONS (continued)
IV.6 - AC Electrical Characteristics
WRITE CYCLE
READ CYCLE
SCS
Motorola mode
SA[0..6]
SR/W
1
3
2
1
4
2
5
SDS
Intel mode
WR
RD
11
6
SD[0..7]
7
10
12
IN
OUT
8
9
SINTR
GIO(out),
RELAY
13
14
Number
12/84
75C53004.EPS
GIO(in)
Description
Min.
Typ.
Max.
5
Unit
1
Address and Control Set-up Time
ns
2
Address and Control Hold Time
3
Write Enable Low State
45
ns
4
Read Enable Low State
45
ns
5
Access Inhibition High State
70
ns
6
Data Set-up Time
10
ns
7
Data Hold Time
5
ns
8
GIO Output, Relay, SINTR Clear Delay
9
GIO Output Hold Time
10
Read Data Access Time
35
ns
11
Data Valid to Tristate Time
15
ns
12
Data Hold Time
13
GIO Input Delay Time
14
GIO Input Hold Time
20
50
0
ns
ns
5
ns
40
0
ns
ns
ns
ST75C530 - ST75C540
V - FUNCTIONAL DESCRIPTION
V.1 - System Architecture
The chip allows the designof a completeFAX, Data
Modem, Hands-Free Telephone and Answering
Machine system. A versatile dual port RAM allows
an easy interface with most micro-controllers.
V.2 - Modes of Operation
Refer to Appendix A for Block Diagrams.
V.3 - Operations
V.3.1 - Modem Transmitter Description
The signal pulses are shaped in a dedicated filter
further combined with a compromise transmit
equalizer suited for transmission over strongly distorted lines. 3 different compromise equalizers are
available and can be selected by software.
V.3.2 - Modem Receiver Description
The receiver section handles complex signals and
uses a fractionally spaced complex equalizer. It is
able to cope with distant modem timing drifts up to
10-4 as specified in the ITU-T recommendations. It
also compensates for frequency drift up to 10Hz
and for phase jitter at multiple and simultaneous
frequencies.
V.3.3 - Tone Generator Description
Four tones canbe simultaneouslygeneratedby the
ST75C530/540. These tones are determined by
their frequenciesand by the output amplitude level.
A set of specific commands are also available for
DTMF generation.Any of the4 tonegeneratorscan
be output independently either on the Audio DAC
or the line DAC.
V.3.4 - Tone Detector Description
During TONE (respectively TONECID) Mode sixteen (respectively eight) tones can be simultaneously detected by the ST75C530/540. Each of the
tones to be detected is defined by the coefficients
of a 4th order programmable IIR. Detection thresholds are programmable from -51dBm up to -6dBm.
These primary detectors can detect tone up to
3.3kHz (sampling rate 7.2kHz in all modes). They
also have a programmable internal wiring feature
(see Chapter IX).
In all modes, except Handset (HANDSET) and Full
Duplex V.3 2bis/V.3 2/V.22bis/V.22 (Modem)
modes, 4 additional tone detectors (each of them
being a 4th order programmable IIR) are concurrently running. In Handset mode only 2 additional
tone detectors are available. Detection thresholds
are programmable from -51dBm up to -6dBm. This
secondary programmable detector can detect
tones up to 1.8kHz by default set-up with a sam-
pling rate at 4.8kHz. But this 4 additional tone
detectors can also detect tones up to 3.3kHz with
a sampling rate at 9.6kHz. In order to avoid wrong
detectgion, relative detectgion is also provided.
V.3.5 - V.21 Channel 2 Flag Detector Description
In all the ReceiveFAX Modes, including V.21 Channel 2 Mode, the ST75C530/540 processes a V.21
Flag “7E” detector, either in the idle state, the train
sequence or the data mode. The detection time is
3 consecutive flags to detect and 1 byte to loose
the detection.
V.3.6 - HDLC Description
In all FAX Modes (MODEM), including V.21 Channe l 2 Mo d e, a n d a ls o F u ll Du p le x
V.32bis/V.32/V.22bis/V.22 (Modem) modes, a
HDLC framing and deframing is supported by the
ST75C530/540. The number of transmitted flags
can be programmed.
V.3.7 - UART Description
In Full Duplex V.32bis/V.32/V.22bis/V.22 Modem
Modes and TONECIDV.23receive mode, a parallel
UART is performed by the ST75C530/540. This
UART manage the Break signal either at the transmit and the receive bit stream. The Data format
supported are 7 and 8 bit of Data; even, odd or no
Parity, 1 or 2 stop bits.
V.3.8 - DTMF Detector Description
ADTMF Detector is includedin the ST75C530/540,
it allows detection of valid DTMF Digits. A valid
DTMF Digit is defined as a dual tone with a total
power higher than -43dBm, a duration higher than
40ms and a differentialamplitude within ±8dB. This
DTMF Detector is enabled in all modes except in
Fax Modem, Data Modem and Handset modes. It
is also enabled in V.21 Channel 2 Receive Mode.
The DTMF thresholds and duration can be
changed from they default value by overwriting
DSP’s RAM locations. In the default setup, this
detector is compliant with the NET4 standard. The
frequencydeviation can be changedby overwriting
the default DTMF’s filters coefficients.
V.3.9 - Ring Detector
This detector detects RING signal from 15Hz to
68Hz, it can be programmed to expand the minimum and maximum detection frequency up to
12Hz (for min) and 144Hz (for max). The detection
time is equal to one period of the ring signal, and
the loose time to the minimum between one period
of the ring signal and the inverse of the minimum
frequency.
The associated STA_RING status is as Figure 1.
13/84
ST75C530 - ST75C540
V - FUNCTIONAL DESCRIPTION (continued)
Figure 1
RING
T1
T2
T3
1/Fmax prog. < T1 < 1/Fmin prog.
T2 < 1/Fmax prog.
T3 ≈ 1/Fmin prog.
V.3.10 - VOCODER Description
The Vocoder mode allows the implementation of
an answering machine function. In the CODER
mode the received samples from one of the two
analog inputs, Line or Audio, are compressed by
the ST75C530/540 and written into the dual port
RAM Vocoder Buffer (VOCxxx). At the same time
the ST75C530/540 is looking for an incoming
DTMF tone and 4 different programmable tones.
In the DECODER mode the compressed samples
are read from the dual port RAM, decompressed
and transmitted to one of the two analog output,
Line or Micx. The ST75C530/540 synthesises an
estimation of its echo and subtracts it from the
re ce iv e d s ig n a l. A t t he s a me t ime th e
ST75C530/540 is looking for an incoming DTMF
tone and 4 different tones.
Two algorithms of voice coding are implemented :
- Low bit rate speech coder (4800bps or 5300bps
with forward error correction).
- ADPCM (ST proprietary algorithm) at 32, 24 and
16Kbps.
If the low bit rate coder algorithm is selected the
ST75C530/540 has the capability to slow down or
speed up the DECODER flow up to ±50%. This
75C53005.EPS
STA_RING
function allows a quick message listening if speed
up is used, or at the opposite if slow down is used,
an enhancement of the voice intelligibility.
V.3.11 - Voice Activity Detector (VAD)
In CODER Mode, for both of the Voice Coding
algorithms, a Voice Activity Detector is implemented while coding by the ST75C530/540. The
STA_109 bit and STA_109F bit reflect the state of
the VAD. After the CONF command the VAD is on
(assume voice). The default time-out to detect silence is 2 secondsand the set-up time to detect the
voice is 15ms. This VAD information is also copied
into the Receive Buffer Status Word MSB (VOCSTA bit7). This detector is fully programmable in
level sensitivity (down to -60dBm), hysteresis, and
various criteria.
An optional silence suppressor is implemented in
the Coder section to suppress long silence in the
incoming message. When enabled (CONF_SUPSIL equal 1) if a long silence is detected (STA_109
equal 0) the ST75C530/540stops generating Buffer Interrupts. After that if a voice is again detected
the ST75C530/540will resume the Buffer Interrupt
mechanism.
Figure 2
Rx Signal
Interrupt (IT1)
14/84
75C53006.EPS
2s
STA_109
(or VOCSTA bit 7)
ST75C530 - ST75C540
V - FUNCTIONAL DESCRIPTION (continued)
V.3.12 - Telephony Functions
ST75C530/540 telephony software provides both
handset and handsfree modes. ST75C530/540 is
connected to the phone line through a D.A.A.,
handset and loudspeaker are connected to
ST75C530/540 through amplifiers.
tions. The software implementedin ST75C530/540
allows functions such as softclipping, AGC in both
modes, and full duplex mode in handsfree(see Figure 3).
Though the D.A.A. has to comply with modem/fax
regulations in most of the applications, the microphone and the earphone amplifier gains will be
adjusted in compliance with the telephony regula-
In handset mode, all the attenuations (_SPKGAIN,
_TXGAIN, _MIKGAIN) are from 0dB to -inf
(32768 steps). AGC and softclipping functions can
beenabledand disabledby software (see Figure 4).
V.3.12.1 - Handset Mode
Figure 3 : Handset/HandsfreeMode Operation
TxA1
ATT_TX
2 TONE
GENERATOR
15
DAC
MUTE
HYBRID
14
Line
TxA2
11
ADC
RxA
MUTE
[0..-30]dB
Step 3dB
CODER
AGC
DAC
1
2
SPK1
76
MUTE
SPK3
77
HANDSFREE/
HANDSET
ALGORITHMS
AGC
78
MUTE
79
9
2 TONE
DETECTORS
ATT_MIC
DG
ADC
8
SPK2
MIC2
75C53007.EPS
DUAL
RAM
INTERFACE
MIC1
10 MIC3
Figure 4 : Handset Mode
_MIKGAIN
AGC = F(ILINE)
_TXGAIN
MIC2
Softclipping
TxA1
TxA2
DP_RING
_SPKGAIN
SPK2_1
SPK2_2
75C53008.EPS
RxA
AGC = F(ILINE)
15/84
ST75C530 - ST75C540
V - FUNCTIONAL DESCRIPTION (continued)
Tx Characteristics
Symbol
Gtx
Ntx
Mmic
VLpeak
Dtx
Parameter
Test Conditions
Transmit Gain
Min.
Typ.
Max.
Unit
_MIKGAIN=7FFF,_TXGAIN=7FFF, AGC disabled
VMIC2 = -21dBV
VMIC2 = -9dBV
18
8
dB
dB
Transmit noise
2kΩ between MIC2 and GND
-73
dBmp
Microphone mute
VMIC2 = -21dBV
60
dB
Transmit softclipping
level on TxA1-TxA2
_MIKGAIN=7FFF,_TXGAIN=7FFF, AGC disabled
see Figure 3, VMIC2 = -9dBV
2.5
Vpp
Transmit distortion
_MIKGAIN=7FFF,_TXGAIN=7FFF, AGC disabled
see Figure 3, VMIC2 = -9dBV
2
%
Max.
Unit
Rx Characteristics
Parameter
Test Conditions
Min.
Typ.
_SPKGAIN=7FFF , AGC disabled, VRXA = -16 dBV
Grx
Receive Gain
Nrx
Receive noise
Mrx
Mute
VRXA = dBV
Dtx
Receive distortion
(SPK2 output)
_SPKGAIN=7FFF , AGC Disabled, V RXA = -16dBV
6
dB
-79
dBmp
60
AGC
The line current information is coming from the
D.A.A. on DP_RING pin (frequencycoded information using by example a TS555 general purpose
timer). The AGC has a 6dB depth . Theattenuation
table can be loaded to comply with each country
regulation. The default table has the following values. The value of the AGC gain is applied to both
Tx and Rx path (see Table 1).
The address of the table is given in the register
@_TABLE.
The table length is 53. The AGC is enabled using
CONF or MODC command (see paragraph ”VII COMMAND SET DESCRIPTION”.
Once the AGC is running, it is possible to freeze the
AGC gain with the register AGC_FRZ.
Softclipping
The softclipping introduces a 12dB gain and has a
18dB depth.
The softclipping value is half digital range
(4000 Hex) (see Figure 5).
dB
2
%
Figure 5 : Softclipping Static Gain
Tx Softclipping and Distortion
(mVRMS)
104
VTxA1-TxA2 (VRMS)
Distortion
D (%)
12
10
8
103
6
4
102
2
0
2
10
3
10
VMICX (mVRMS)
10
Table 1 : AGC Gain versus Period Information
Period (ms)
<9
10
10.8
11.6
14.5
13.3
14.1
15.5
16.6
17.5
18.3
19.1
20
>20
Table Index
<13
13
14
15
16
17
18
19
20
21
22
23
24
>24
0
0.7
1.5
2.2
3
3.4
4
4.5
4.8
5.1
5.4
5.6
5.8
6
Gain (dB)
16/84
75C53009.EPS
Symbol
ST75C530 - ST75C540
V - FUNCTIONAL DESCRIPTION (continued)
V.3.12.2 - Handsfree Mode
The ha ndsfree uses a MIC1 and a SPK1 as microphone and loudspeaker interface (see Figure 6).
Figure 6 : Handsfree Mode : Full Duplex
+
-
_TXGAIN
ACOUSTIC
FILTER
ADAPTIVE
ATTENUATOR
ADAPTIVE
FIR
FILTER
NLMS
ADAPTIVE
FIR
FILTER
CONTROL
NLMS
_SPKGAIN
SPK1P
SPK1N
AGC = F(IL)
TxA1
TxA2
AGC = F(IL)
ADAPTIVE
ATTENUATOR
-
75C53010.EPS
_MIKGAIN
MIC1
RxA
+
Softclipping
Tx Characteristics
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Gtx
Transmit Gain
_MIKGAIN=7FFF,_TXGAIN=7FFF ,AGC disabled,
VMIC1 = -21dBV
24
dB
Ntx
Transmit noise
2kΩ between MIC1 and GND
-70
dBmp
Mmic
Microphone mute
VMIC1 = - dBV
60
Dtx
Transmit distortion
_MIKGAIN=7FFF,_TXGAIN=7FFF ,AGC disabled,
VMIC1 = -9dBV
dB
2
%
Max.
Unit
Rx Characteristics
Symbol
Parameter
Grx
Receive Gain
Mrx
Mute
Dtx
Receive distortion
(SPK1 output)
Test Conditions
Min.
_SPKGAIN=7FFF, AGC disabled, V RXA = -33dBV
Typ.
24
dB
60
_SPKGAIN=7FFF, AGC disabled, V RXA = -33dBV
dB
2
%
AGC
The AGC has the same behavior as in Handset mode. Furthermore, the maximum gain added by AGC can
be fixed by using the RX_GAINMAX and TX_GAINMAX registers.
Softclipping
See Figure 7.
System Stability
Parameter
Loop attenuation in Rx RxA to TxA1-TxA2
Test Conditions
Min.
Speaker gain is 12dB, Mike gain is 14dB
20
dB
20
dB
Loop attenuation in Tx MICx to SPK1P-SPK1N Analogique sidetone not used
(see DAA schematics)
Typ.
Max.
Unit
It is possible to add some gain switching in the Tx and Rx path (to reduce the gain of the loop) by using
the GAIN_RCV and GAIN_XMT registers.
17/84
ST75C530 - ST75C540
V - FUNCTIONAL DESCRIPTION (continued)
Figure 7 : SPK1 Distortion versus RxA
V.3.13 - Low Power Mode
Sleep state can be attained by a SLEEPcommand.
When in sleep mode, the dual port RAM is unavailable and the clocks are disabled.
Wh en e ntering th e lo w p ower mod e, th e
ST75C530/540stops its oscillator, all the peripherals of the DSP core are stopped in order to reduce
the power consumption. The dual port RAM is
made inaccessible.
The ST75C530/540 can be awakened by a hardware reset, a RING signal or a dummy write at any
location in the dual port RAM.
There is a maximum time of 20ms to restart the
oscillator after waking up and an additional 5ms
after the interrupt to be able to accept any command coming from the host.
Rx Softclipping and Distortion
(mVRMS)
103
D (%)
12
10
8
102
6
4
VSPK1 (VRMS)
Distortion
10
0
103
102
VMIC2 (mVRMS)
75C53011.EPS
2
Figure 8 : Speaker and Line Tx Power Spectrums
POWER SPEC1
POWER SPEC2
64Avg
64Avg
0%Ovlp
0%Ovlp
Ftop
Ftop
0.0
0.0
dBm
Speaker Output
RMS
V2
dB
Line Tx
-80.0
-80.0
Fxd Y O
Hz
Note :
Acoustic echo from speaker to microphone input with no
local speech. Receiving speech on line input.
5k
75C53012.EPS
RMS
Vv2
V.3.14 - Reset
After a hardware reset, or an INIT command, the
ST75C530/540 clears all its internal memories,
clears the whole dual port RAM and starts to initialize the delta sigma analog converters. As soon as
t he se in it ia lizat ion s are c omplete d, t he
ST75C530/540 generates an interrupt IT6 (command acknoledge) and is programmed to send and
receive tones, the sample clock are programmed to
9600Hz. The total duration of the reset sequence is
about 5ms. After that time the ST75C530/540 is
readyto executecommands sent by the host microcontroller. The duration of the reset signalshould be
greater than 700ns.
V.4 - Modem Interface
V.4.1 - Analog Interface
Refer to Block Diagram on page 7.
V.4.2 - General I/O and Relay Interface
16 pins are dedicated to the general I/O port. Two
are dedicatedto Relaydriver. The equivalent schematic is as follows : see Figure 9.
Figure 9
GIO0[x]
RELAY[y]
IODIR0[x]
IODATA0[x]
(read)
18/84
D Q
IORELAY[y]
(write)
IORELAY[y]
(read)
D Q
N
RGND
75C53013.EPS
IODATA0[x]
(write)
ST75C530 - ST75C540
V - FUNCTIONAL DESCRIPTION (continued)
V.4.3 - Crystal
The crystal frequency must be 44.2368MHz for
ST75C530 and 49.152MHz for ST75C540 with an
accuracy better that ±100 ppm. When using a third
harmonic crystal the schematic must be as follow :
see Figure 10.
The crystal features are :
- third harmonic,
- parallel, load capacitance = 10pF,
- æ 100ppm from 0oC to 70oC,
- RS < 50Ω,
- ATcut (example : SM55-10 MATEL).
to allow transmission of Modem signal up to 10dBm and reception up to -10dBm. The OPAmps
are +12/0V powered. With this application schematic the out of band transmit spectrum(from 4kHz
to 50kHz) is below -72dBm.
Figures 13 and 14 are examples of applicationschematicswhich respectsgainvalue(respectivelyforfax
and voice application and for Modem application)
andthe minimum differentialloadonTxA1 andTxA2.
V.4.5 - Host Interface
The host interface is seen by the micro as a 128x8
RAM, with additional registers accessible through
an 8-bit address space. A selection Pin (INT/MOT)
allows to configurethe host bus for either INTEL or
MOTOROLA type control signals.
Figure 10
ST75C540
73
Figure 11
72
XTALL
XTAL H3 **
600Ω
TxA1
1:1
+8dB
RxA
Cb
10nF
* Wire wound inductor recommanded (Example : SIGMA-SC30)
** Thrird harmonic (Example : MATEL-SM55-10)
XTAL H3 : 44.2368MHz (ST75C530)
49.152MHz (ST75C540)
V.4.4 - Typical Application Schematic
The Figure 11 is a block diagram designedto allow
transmission of fax signals up to +0dBm and sine
wave up to +6dBm on the telephone line. It allows
receptionof fax signals up to 0dBm and sine waves
up to +6dBm.Figure12 is a blockdiagramdesigned
-10dB
75C53015.EPS
C1
10pF
COG
-1/2
2.2nF
VCM
75C53014.EPS
C2
27pF
COG
Line
TxA2
L*
0.82µH (ST75C530)
0.68µH (ST75C540)
Figure 12
600Ω
TxA1
0dB
1:1
Line
TxA2
-1/2
RxA
0dB
75C53016.EPS
EXTALL
2.2nF
VCM
19/84
ST75C530 - ST75C540
V - FUNCTIONAL DESCRIPTION (continued)
Figure 13 : Fax Mode
56.2kΩ 1%
270pF
470nF 18.2kΩ 1%
+12V
TxA1
560Ω
TxA2
470nF 18.2kΩ 1%
1:1 *
470nF
GND
470pF
47.5kΩ
30kΩ 1%
22nF
6.21kΩ 1%
+6V +6V
+12V
470nF
1.2kΩ
+6V
+6V
+6V
+6V
2.2nF
24.3kΩ 1% 470nF
VCM
GND
10kΩ 1%
* Insertion loss = 2.5dB between 0 and 3.4kHz
75C53017.EPS
RxA
Figure 14 : Data Mode
24kΩ 1%
270pF
470nF 18.2kΩ 1%
+12V
TxA1
560Ω
TxA2
1:1 *
470nF
470nF 18.2kΩ 1%
GND
470pF
47.5kΩ
22nF
30kΩ 1%
6.21kΩ 1%
+6V +6V
+12V
1.2kΩ
470nF
+6V
+6V
+6V
+6V
2.2nF
VCM
GND
33kΩ 1%
20/84
24.3kΩ 1% 470nF
* Insertion loss = 2.5dB between 0 and 3.4kHz
75C53018.EPS
RxA
ST75C530 - ST75C540
VI - USER INTERFACE
VI.1 - Dual Port Ram Description
The dual port RAM is the standard interface between the host controller and the ST75C530/540,
for either commands or data. This memory is addressed through a 7-bit address bus. The locations
from $00 to $3F are RAM location, while locations
from $40 to $60 are control registers dedicated to
the interrupt handling and the general IO port and
Relay output.
Severalfunctionalareas are defined in the dual port
RAM mapping :
- the command area,
- the report area,
- the status area,
- the optional status area,
- the data buffer area,
- the interrupt control area,
- the general I/O and Relay Output area.
VI.1.1 - Mapping
VI.1.1.1 - Command Area
The command area is located from $00 to $04.
Address $00 holds the command byte COMSYS,
and the next four locations hold the parameters
COMPAR[0..3].The command parametersmust be
entered before the command word is issued. Once
the command has been entered,the commandbyte
is reset and an acknowledge report is issued. Anew
command should not be issued before the acknowledge counter COMACK is incremented.
VI.1.1.2 - Report Area
The report area is located from address $05 to
address $07. Location $05 holds the acknowledge
counter COMACK. Each time a command is acknowledged, the report bytes COMREP[0..1] (if
any) are written by the ST75C530/540 into locations $06 and $07, and the content of COMACK is
in c re me n t e d. T h is c o u nt er allo ws t he
ST75C530/540 to accurately monitor the command processing.
VI.1.1.3 - Status Area
The statusarea is located from address$08 to $0B.
The errorstatusword SYSERRislocatedat address
$08. This error status word is updatedeach time an
error condition occurs. An optional interruption IT0
may additionallybe triggeredin the case of an error
condition. Locations $09 and $0A hold the general
status bytes STATUS[0..1]. The meaning of the bits
dependson the mode of operation,and is described
in Chapter VIII. The third byte at address $0B holds
the Quality Monitor byte STAQUA.
VI.1.1.4 - Optional Status Area
The user can program (through the DOSR command) the four locations STAOPT[0..3] of the Optional Status Area ($0C to $0F) for the real time
monitoring of four arbitrary memory locations.
VI.1.1.5 - Data Buffer Area
The data area is made of four 8-byte buffers
(see Paragraph VI.1.3 “Host Interface Summary”).
Two are dedicated to transmission and the two
others to reception. Each of the four buffers is
attached to a status byte. the meaningof the status
byte depends on the selected format of transmission. Within each buffer, D0 represents the first bit
in time.
VI.1.1.6 - VOCODER Buffer Area
(VOCODER Mode)
This area is made of a 18+2 byte buffer. This buffer
contains the VOCODER frame. The first 18 bytes
VOCDATA contain the coded frame and the other
2 bytes VOCCORR the Error corrections bit (only
valid in low bit rate mode).
In the Receive Mode (CODER) the ST75C530/540
codes the received samples and writes the corresponding bytes in the buffer. If the low bit rate mode
is selected, the ST75C530/540computes the Error
corrections 2 bytes and writes them in the buffer.
I n t h e Tran smit Mod e (DE CO DER ) t h e
ST75C530/540reads the 18 coded bytes decodes
them and sends the signal to the analog output. In
the low bit rate mode if the Error Correction is
enabled, prior the decoding, the ST75C530/540
reads the 2 Error Correction Bytes and, if any,
corrects the first 18 bytes.
A mechanism of flags to share the buffer access
between the ST75C530/540and the hostcontroller
is controlled by the VOCSTA byte :
- In CODER mode, when the ST75C530/540 has
finis-hed writing the VOCDATA and VOCCORR
bytes, it writes $14 in VOCSTA and generate an
Interrupt IT1. The host must read the Data buffer
then clear the VOCSTA byte.
- In DECODER mode, the host must feed the
VOCDATA and, optionaly,the VOCCORR bytes,
then write $14 (if low bit rate) or $12 (if ADPCM)
in VOCSTA. The ST75C530/540 will read the
VOCDATA and VOCCORR bytes, clear the
VOCSTA and generate an Interrupt IT1. A silence frame can be generated, in either low bit
rate or ADPCM mode, by writing 00 in all the
VOCDATA buffer, including the Error Correction
Bytes VOCCORR.
21/84
ST75C530 - ST75C540
VI - USER INTERFACE (continued)
VI.1.1.7 - Interrupt Control Area
The interrupt area, that start after the address $40
controls the behaviour of the Interrupts mechanism. Register ITSRCR defines the source of the
interrupt, the register ITMASK allows independent
enabling or disabling of any of the interrupt’s
source, registers ITREST0 to ITREST6 reset the
corresponding interrupt source.
Theseregistersare not affectedby a INITcommand,
they are only reseted by a Hardware RESET signal.
VI.1.1.8 - General IO and Relay Output Area
A set of 5 registers is directly accessible by the
controller to program the General IO pins and
Relay Outputs (see Paragraph VI.1.3 “Host Interface Summary”). Two registers IODIR0 and IODIR1 define the type of the IO pin, either Input or
Output (0 = input, 1 = output), and two registers
IODATA0 and IODATA1 define the IO pin signals.
The fifth register defines the Relay output signals.
Theseregistersare not affectedby a INITcommand,
they are only reseted by a Hardware RESET signal.
The general IO are setup as input after the power
up or an hardware RESET. The relay output are
open after power up or an hardware RESET.
VI.1.2 - Interruptions
The ST75C530/540 can generate 7 interrupts for
the controller. The interrupt handling is made with
a set of registers located from $40 to $5F.
The interruptions generated by the ST75C530/540
come f ro m sev eral so urces. Once th e
ST75C530/540raises an interrupt, a signal (SINTR)
is sent to the controller. The controller has then to
processthe interruptandclearit. Theinterruptsource
can be examined in the interrupt source register
ITSRCR located a $50. According to the ITSRCR
bits, the interrupt source can be determined. Then
22/84
writing a zero at one of the memory location $40 to
$46 (Reset Interrupt Register ITRES[0..6]) will reset the corresponding interrupt (and thus acknowledge it). The source of the interrupt can be masked
globally or individually using the Interrupt Mast
register ITMASK located at $4F.
The interrupt sources are :
- IT0 : Error
This signifies that an error has occurred and the
error code is available in the error status byte
SYSERR. This byte can be selectively cleared by
the CSE command.
- IT1 : VOCODER Buffer
Each time the ST75C530/540 have coded a
frame (CODER Mode) or decoded a frame (DECODER Mode) this interrupt is generated.
- IT2 : Tx Buffer
Each time the ST75530/C540frees a data buffer,
this interrupt is generated.
- IT3 : Rx Buffer
Each time the ST75C530/540 has filled a data
buffer, this interrupt is generated.
- IT4 : Status Byte
This signifies that the status byte has changed
and must be checked by the controller.
- IT5 : Low Power Mode
The ST75C530/540has been awakened from the
low power mode by a low level on the RING pin
or a dummy write issued by the host.
- IT6 : Command Acknowledge
This signifies that the ST75C530/540 has read
the last command entered by the host, incremented the command counter COMACK, and is
ready for a new command.
Note : Interrupt registers are cleared after a Hardware RESET. These registers are not affected by
a INIT Command.
ST75C530 - ST75C540
VI - USER INTERFACE (continued)
Figure 15 : Functional Schematic
ITREST 0
(write only)
R
Q
S
IT0 : Error
ITREST 1
(write only)
R
Q
S
ITREST 2
(write only)
IT1 : VOCODER
Buffer
R
Q
S
IT2 : Tx Buffer
ITREST 3
(write only)
R
Q
S
IT3 : Rx Buffer
ITREST 4
(write only)
R
Q
S
IT4 : Status
ITREST 5
(write only)
R
Q
S
IT5 : Low Power
ITREST 6
(write only)
R
Q
S
IT6 : Command
ITSRCR
(read only)
6
5
4
3
2
1
0
6
5
4
3
2
1
0
ITMASK
(read write)
7
75C53019.EPS
SINTR
(open drain)
23/84
ST75C530 - ST75C540
VI - USER INTERFACE (continued)
VI.1.3 - Host Interface Summary
Address (hex)
Description
Size (Byte)
Mnemonic
COMMAND AREA
$00
Command
1
COMSYS
$01-$04
Command Parameters
4
COMPAR[0..3]
$05
Acknowledge Counter
1
COMACK
$06-$07
Report
2
COMREP[0..1]
$08
Error Status
1
SYSERR
$09-$0A
General Status
2
STATUS[0..1]
$0B
Quality Monitor
1
STAQUA
$0C-$0F
Optional Report
3
STAOPT[0..3]
REPORT AREA
STATUS AREA
DATA BUFFER AREA (FAX Modes and Data Modes)
$1C
Data Rx Buffer 0 Status
1
DTRBS0
$1D-$24
Data Rx Buffer 0
8
DTRBF0[0..7]
$25
Data Rx Buffer 1 Status
1
DTRBS1
$26-$2D
Data Rx Buffer 1
8
DTRBF1[0..7]
$2E
Data Tx Buffer 0 Status
1
DTTBS0
$2F-$36
Data Tx Buffer 0
8
DTTBF0[0..7]
$37
Data Tx Buffer 1 Status
1
DTTBS1
$38-$3F
Data Tx Buffer 1
8
DTTBF1[0..7]
VOCODER BUFFER AREA (Vocoder Mode)
$1C
Vocoder Buffer Status
1
VOCSTA
$1D-$2E
Vocoder Buffer Data
18
VOCDATA
$2F-$30
Vocoder Buffer Corrector
2
VOCCORR
$40-$46
Reset Interrupt Register
7
ITREST[0..6]
$4F
Interrupt Mask Register
1
ITMASK
$50
Interrupt Source Register
1
ITSRCR
INTERRUPT AREA
GENERAL IO AND RELAY
$60
I/O Direction 0
1
IODIR0
$61
I/O Direction 1
1
IODIR1
$62
I/O Data 0
1
IODATA0
$63
I/O Data 1
1
IODATA1
$64
I/O Relay Register
1
IORELAY
Note : Registers which address is higher or equal to $40 are not affected by a INIT Command or a Low Power wake-up. They are reseted
only by a Hardware RESET.
24/84
ST75C530 - ST75C540
VI - USER INTERFACE (continued)
VI.2 - Command Set
The Command Set has the following attractive
features :
- user friendly with easy to remember mnemonics,
- possibility of straightforward expansion with new
commands to suit specific customer requirements,
- easy upgrade of existing software using previous
modem based SGS-THOMSON products.
The command set has been designedto providethe
necessaryfunctionalcontrolon the ST75C530/540.
Each command is classified according to its syntax
and the presence/absence of parameters. In the
case of a parametric command, parameters must
first be written into the dual port RAM before the
command is issued. Acknowledge and error report
is issued for each command entered.
SYNC
FAX Synchronize. Start/Stopof FAXHalfduplex receiver. Parametric command.
CSE
ClearStatusError.SelectivelyclearstheError
statusbyteSYSERR.Parametric command.
SETGN Set Gain. This command sets the global
gain factor, which is used for the transmit
samples. Parametric command.
VI.2.1.2 - Data Communication Commands
XMIT
FORM
VI.2.1 - Command Set Summary
VI.2.1.1 - Operational Control Commands
INIT
IDT
SLEEP
HSHK
STOP
RTRA
Initialize. Initialize the modem engine.
Set all parameters to their default values
and wait for commands of the control
processor. Non parametric command.
Identify. Return the product identification
code. Non parametric command.
Tu rn to low po we r mo d e, t h e
ST75C530/540 enters the low power
mode and stops its crystal oscillator to
reduce power consumption. In this mode
all the clocks are stopped and the dual
RAM is unreachable.
Handshake. Begins the handshake
sequence.The modem engine generates
all the sequences defined in the ITU-T
recommendations. A status report
indicatesto the controlprocessorthe state
of the handshake. This command only
applies to modes where a handshake
sequence is defined. A CONF command
must have been issued prior to the use of
HSHK. Non parametric command.
FAX Sto p. Sto p FAX Half-duplex
transmitter. Non parametric command.
Retrain. Begin a retrain sequence in
V.32bis/V.32 or V.22bis modes as
d e s cr ib e d
in
the
I TU-T
recommendations (ST75C540 only).
Tra n s mit Da ta . St a rt /st o p th e
transmission of data. After a XMIT
command, the ST75C530/540sends the
data contained in its dual port RAM.
Selects the Transmission Format. This
command configures the data interface
for bo th re ceive r and tra nsmitter
according to the selected data format.
Parametric command (HDLC, UART or
synchronous).
VI.2.1.3 - Memory Handling Commands
MWI
MWLO
MW
MRI
MRLO
MR
CR
Memory Write Indirect
Memory Write Low Word
Memory Write. This command is used to
write an arbitrary 16-bit value into the
writable memory location currently
specified by a parameter. Parametric
command.
Memory Read Indirect
Memory Read Low Word
MemoryRead. This command allows the
controller to read any of the ERAM or
CRO M (S T7 5 C5 3 0 /5 40 me mo ry
spaces) location without interrupting the
processor. Parametric command.
Complex Read. This command allows
the controller to read at the same time
the real and imaginary part of a complex
value stored in a double ERAM or
CROM location. This feature is very
interesting for eye pattern software
control and for equalization monitoring.
This command insures that the real and
imaginary parts are sampled in the
memory at the same time (integrity).
Parametric command.
25/84
ST75C530 - ST75C540
VI - USER INTERFACE (continued)
VI.2.1.4 - Configuration Control Commands
ASEL
Select the Analog path option, like
Microphone input, Speaker attenuation.
Parametric command.
CONF Configure. This command configures the
modem engine for data transmission and
handshake procedures (if any) in any of
the supported modes. The transmission
parameters are set to their default values
and can be modified with the MODC
command. Parametric command.
MODC Modify Configuration. This command
allows modification of some of the
parameters which have been set up by
the CONF command. It can also be used
to alter the mode of operations (short
train). Parametric command.
DOSR Define Optional Status Report. This
command allows the modification of the
optional status report located in the status
area of the dual port RAM. One can thus
select a particular parameter to be
monitored during all modes of operation.
Parametric command.
DSIT
Define Status Interrupt. This command
allows the programming of the status
word bit that will generate an Interrupt to
the controller. Parametric command.
VI.2.1.5 - Tone Generation Commands
TONE
DEFT
TGEN
SelectTone. Programsthe tonegenerator(s)
for the desired default tone(s). Additional
mnemonics provide quick programming of
DTMF tones or other currently used tones.
Parametric command.
De f ine To n e . Pro gra ms t h e t o n e
generator(s) for arbitrary tone synthesis.
Parametric command.
Tone Generator Control. Enables or
dis a b le s t he t on e ge n era t or(s).
Parametric command.
VI.2.1.6 - Tone Detection Commands
TDRC
TDWC
TDRW
26/84
Read Tone Detector Coefficient. Read
on e To n e De t e ct or Coe f f ic ie nt .
Parametric command.
Write Tone Detector Coefficient. Write
on e To n e De t e ct or Coe f f ic ie nt .
Parametric command.
Read Tone Detector Wiring. Read one
Tone Det ecto r Wirin g co nne ction.
Parametric command.
TDWW Write Tone Detector Wiring. Write one
Tone De tecto r Wiring connection.
Parametric command.
TDZ
Clear Tone Detector Cell. Clear internal
variables of a Tone Detector Cell.
Parametric command.
VI.2.1.7 - Miscellaneous Commands
CALL Call a Subroutine. Call a subroutine with
one Parameter. Parametric command.
JSR
Call a Low Level Subroutine. Call an
internal subroutine with one parameter.
Parametric command.
VI.3 - Command Set Short Form
Mnemonic
XMIT
SETGN
SLEEP
HSHK
RTRA*
INIT
CSE
FORM
DOSR
ASEL
TONE
TGEN
DEFT
MR
CR
MW
DSIT
IDT
JSR
CALL
TDRC
TDRW
TDWC
TDWW
TDZ
CONF
MODC
STOP
SYNC
MRI
MRLO
MWI
MWLO
* ST75C540 only.
CCI Command
Value
Description
0x01
Transmit Data
0x02
Set Transmit Gain
0x03
Power Down the ST75C530/540
0x04
FAX Start Transmitter
0x05
Retrain (V.32bis/V.32 and V.22bis)
0x06
Initialize (Software Reset)
0x08
Clear Error Status Word
0x09
Define Data Format
0x0A
Define Optional Status Report
0x0B
Select the Analog Path Options
0x0C
Generate Predefined Tones
0x0D
Enable Tone Generator
0x0E
Define Arbitrary Tone
0x10
Memory Read
0x11
Complex Read
0x12
Memory Write
0x13
Define Status Interrupt
0x14
Return Product Identification Code
0x18
Call a Low Level Routine
0x19
Call a Routine
0x1A
Tone Detector Read Coefficient
0x1B
Tone Detector Read Wiring
0x1C
Tone Detector Write Coefficient
0x1D
Tone Detector Write Wiring
0x1E
Tone Detector Clear Cell
0x20
Configure
0x21
Modify Default Configuration
0x25
FAX Stop Transmitter
0x26
FAX Synchronize Receiver
0x28
Memory Read Indirect
0x29
Memory Read Low Word
0x2A
Memory Write Indirect
0x2B
Memory Write Low Word
ST75C530 - ST75C540
VI - USER INTERFACE (continued)
VI.4 - Status - Reports
VI.4.1 - Status
The ST75C530/540 has a dedicated status reporting area located in its dual port RAM. This allow a
continuous monitoring of the status variables without interrupting the ST75C530/540.
The first status byte gives the error status. Issuing
of an error status can also be flagged by a maskable interrupt for the controller. The signification of
the error codes are given in Chapter VIII.
The second and third status bytes give the general
status of the modem. These status include for
example the ITU-T circuit status and other items
described in Chapter VIII “STATUS DESCRIPTION”. These two status can generate, when a
change occurs, an interrupt to the controller ; each
bit of the two byte word can be masked independently.
The forth byte gives in real time a measure of the
receptionquality. Thisinformationmay be used by the
controller to monitor the quality of the received bits.
Four other locations are dedicated for custom
status reporting. The controller can program the
ST75C530/540 for a real time monitoring of any of
its internal RAM location. High byte or low byte of
any word can thus be monitored.
VI.4.2 - Reports
The ST75C530/540 features an acknowledge and
report facility. The acknowledge of a command is
monitored by a counter COMACK located in the
dual port RAM. Each time a command is read from
the command area, the ST75C530/540 will increment this counter. For instance, when a MR (Memory Read) command is issued, the data is first
written in the report area, and the counter is incremented afterwards. This way of processinginsures
data integrity and gives additional synchronization
between the controller and the data pump.
VI.5 - Data Exchanges
The ST75C530/540 accepts many kinds of data
exchange: the defaultmode uses the synchronous
parallel exchange. Other modes include HDLC
framing support and UART. Detailed description of
the Data Buffer Exchanges modes is available in
the paragraph X.
VI.5.1 - Synchronous Parallel Mode
The data exchanges are made through the dual
port RAM and are byte synchronous oriented. The
double buffer facilities of the ST75C530/540 allow
an efficient buffering of the data.
VI.5.1.1 - Transmit
The controller must first fill at least the first buffer
of data (Tx Buffer 0) with the bits to be transmitted.
In order to perform this operation, the controller
must first check the Tx Buffer 0 status word
DTTBS0. If this buffer is empty, the controller fills
the data buffer locations (up to 64 bits), and then
writes in DTTBS0 the number of bytes contained in
the buffer. The controller can then either proceed
with the second buffer or initiate the transmission
with a XMIT command.
The ST75C530/540copies the contentsof the data
buffer and then clears the buffer status word in
order to make it again available, then generates an
IT2 interrupt. The number of bytes specified by the
status word is then queued for transmission. The
process goes on with the two buffers until an XMIT
command stops the transmission. After the finishing XMIT command has been issued, the last buffers are emptied by the ST75C530/540.
Errors occur when both buffersare empty while the
transmit bit queue is also empty. Error is signalled
with an IT0 interruption to the controller.
VI.5.1.2 - Receive
The controller should take care of releasing the Rx
buffers before the Data Carrier Detect goes true.
This is made by writing zero in the Rx Buffer Status
0 and 1. The ST75C530/540 then fills the first
buffer, and once filled sets the status word with the
number of bytes received and then generates an
IT3 interrupt. It then takes control of the second
buffer and operates the same way. The controller
must check the status of the buffers and empty
them. Once the data read, the controller must
release the used buffer and wait for the next buffer
to be filled.
Error occurs when both buffers are declared full,
and incoming bits continue to arrive from the line.
Error is signaled by an IT0 interrupt.
VI.5.2 - HDLC Parallel Mode
This mode implements part of the High Level Data
Link Control formats and procedures. It is well
suited for error correcting protocols like ECM or
FAXT4/T30 recommendations.It supportsthe flagging generation,16-bit Frame Check Sequence,as
well as the Zero insertion/deletion mechanism.
VI.5.3 - UART Parallel Mode
This mode implement a 7 or 8 bit data format, it is
well suited for Caller ID or Minitel applications.
27/84
ST75C530 - ST75C540
VII - COMMAND SET DESCRIPTION
Commands are presented according to the following form :
COMMAND
Opcode
COMMAND
Command Name Meaning
Hexadecimal digit
X
X
X
X
X
X
X
X
Synopsis Short description of the functions performed by the command.
Parameters
Field
Byte
Pos.
Value
Definition
Name
X
b..a
Explanation of the parameter
Default value
xx *
Field
Byte
Pos.
Value
Name of the addressed bit field.
Index (or address in the dual port RAM) of the parameter byte (from 1 to 4).
Bit field position inside the parameter byte. Can either be a single position (from 0 to 7, 0
being LSB) or a range.
Possiblevaluesforthebit(resp. bitfield). Rangemeansallvaluesare allowed.Astarmeansa default
value. Valuesare expressed eitherunderthe form of a bit string, or underhexadecimal format.
ASEL
Opcode:
ASEL
0B
0
Synopsis
Parameters
0
0
1
0
1
1
Select the analog path options. This command select the Attenuation/Mute of the outputs
TxA1/TxA2 and SPK1/SPK2/SPK3. This command select also the source of the Mic signal
MIC1/MIC2/MIC2 and the source of the Line Signal RxA/MIC3.
Field
ASEL_ASPK1
Byte
1
Pos.
7..4
ASEL_MICSEL
2
1..0
ASEL_LINESEL
2
2
ASEL_ESPK1
2
3
ASEL_ESPK2
2
4
ASEL_ESPK3
2
5
ASEL_MTXA
2
7
CALL
Opcode:
0
Value
0000*
0001
0010
...
1010
1011
Other
00*
01
10
11
0*
1
0*
1
0*
1
0*
1
0*
1
Definition
Infinity attenuation
30dB attenuation
27dB attenuation
...
3dB attenuation
0dB attenuation
Reserved
Select Rx input as MIC1
Select Rx input as MIC1
Select Rx input as MIC2
Select Rx input as MIC3
Select RxA as line input
Select Mic3 as line input
SPK1 output muted
SPK1 output normal
SPK2 output muted
SPK2 output normal
SPK3 output muted
SPK3 output normal
TxA output normal
TxA output muted
CALL
Call a Subroutine
19
0
0
0
1
1
0
0
1
Synopsis CALL allows to execute a part of the ST75C530/540 firmware with a specific argument.
Field
Byte
Pos.
Value
Definition
Parameters
C_ADDR_L
C_ADDR_H
C_DATA_L
C_DATA_H
1
2
3
4
7..0
7..0
7..0
7..0
Low byte of the call address
High byte of the call address
Low byte of the argument
High byte of the argument
This instruction can be used with SGS-THOMSON Microelectronics Application Laboratory Support for
special applications development or debugging needs. Contact your local representative.
28/84
ST75C530 - ST75C540
VII - COMMAND SET DESCRIPTION (continued)
CONF
Opcode :
0
Synopsis
0
1
0
0
0
0
0
CONF allows the complete definition of the ST75C530/540 operation, including the mode of
operation (Tone, FAX Transmit, Voice Transmit, Voice Receive, DTMF Receiver, ...) and the
Modem or Vocoder Parameters (Standard, speed, ...). According with the 4 first bits of the
CONF Parameter the ST75C530/540 is put into the following mode of operation.
CONF_
OPER
0000*
0001
0010
0100
1000
1001
1100
1111
Other
Notes :
CONF
Configure for Operations
20
Mode
TONE
TONECID(1)
DECODER
TRANSPARENT
CODER
ROOM-MONITOR
HANDSET/HANDSFREE
MODEM
Reserved
Detectors
Tone
16
6
0
6
0
0
0
0
(2)
Tone
4
4
4
4
4
4
4
2(7)
(3)
DTMF Ring VAD V.21 Flag CPT (5) Answ (6)
Yes
Yes
Yes
Yes
Yes
Yes
No(4)
Yes
Yes
Yes
Yes
No
Yes
No
No
No
No
No
No
No
Yes
No
No
No
Yes
Yes
No
No
No
No
No
Yes
Yes
Yes
No
Yes
No
No
No(4)
Yes
Yes
No
No
Yes
No
No
No
No
1. This mode includes V.23/Bell202 FSK Demodulator and UART.
2. This primary Tone Detectors allows Detection of signal up to 3.3kHz. (Sampling Rate 7.2kHz).
3. Thissecondary ToneDetectorsallowsDetectionofsignalupto1.8kHz(withSamplingRate4.8kHz) or upto3.3kHz(withSamplingRate9.6kHz).
4. The DTMF detector and Call Progress Tone detector (CPT) are available only for V.21 Channel 2.
5. STA_CPT0, STA_CPT1 and STA_CPT10 in STATUS0.
6. STA_CCITT and STA_AT in STATUS1.
7. Not available in V.32bis/V.32.
29/84
ST75C530 - ST75C540
VII - COMMAND SET DESCRIPTION (continued)
Parameters When the CONF_OPER is set to F, selecting the Modem Mode of operation,the parameters
have the following meaning :
Field
Notes :
30/84
Byte
Pos.
Value
CONF_OPER
1
3..0
1111
Definition
CONF_ANAL
1
4
0
1
Normal mode
Analog loop back (test mode only)
CONF_PSTN
1
5
0
1
PSTN (carrier detect set to -43/-48dBm)
Leased line (carrier detect -33/-38dBm)
CONF_AO
1
6
0
1
Answer mode
Originate mode
CONF_DTINIT
(only in tone mode)
1
7
0
1
Global init of secondary tone detector
Partial init of secondary tone detector (8)
CONF_MODE
2
5..0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
Other
CONF_TXEQ
2
7..6
0
1
2
3
No transmit equalizer
Transmit equalizer #1
Transmit equalizer #2
Transmit equalizer #3 (V.17/V.33/V.29/V.27ter)
CONF_CAR
3
0
0
1
1800Hz carrier (V.17/V.33 only)
1700Hz carrier (V.17/V.33 only)
CONF_TCM
3
1
0
1
Treillis coding not allowed (V.32 only)
Treillis coding allowed (V.32bis, V.32)
CONF_SP0
3
7..4
xxx1
xx1x
x1xx
1xxx
1200bps allowed (V.22, V.22bis) (10)
2400bps allowed (V.22bis, V.27) (10)
4800bps allowed (V.32bis, V.32, V.27, V.29) (10)
7200bps allowed (V.32bis, V.29, V.17) (10)
CONF_SP1
4
2..0
xx1
x1x
1xx
9600bps allowed (V.32bis, V.32, V.29, V.17) (10)
12000bps allowed (V.32bis, V.17, V.33) (10)
14400bps allowed (V.32bis, V.17, V.33) (10)
Select Modem Mode
Automode (V.32bis/V.32/V.22bis/V.22) (9)
Bell 103 (full duplex)
(9)
Bell 212A (full duplex)
V.21 (full duplex)
V.23 (full duplex)
V.22 (full duplex) (9)
V.22bis (full duplex) (9)
V.27ter
V.29
V.17
V.32 (full duplex) (9)
V.32bis (full duplex) (9)
V.33 (half duplex)
V.21 channel 2
Reserved
8.
With conf 80 00 00 00 the coefficients of secondary tone detectors are not initialized.
9.
ST75C540 only.
10. V.22bis, V.22, V.32bis and V.32 modes ST75C540 only.
ST75C530 - ST75C540
VII - COMMAND SET DESCRIPTION (continued)
Parameters CODER and DECODER Modes
In the VOCODER Modes, either CODER or DECODER, (CONF_OPER equals 2 or 8) the
parameters have the following meaning :
Byte
Pos.
Value
CONF_OPER
Field
1
3..0
-
Define mode : see table above
Definition
CONF_CODE
3
0
0
1
Low bit rate coded
ADPCM coded
CONF_VPF
3
1
0
1
Decoder post filter off
Decoder post filter on (not in ADPCM)
CONF_VASP
3
3..2
00
01
10
11
ADPCM 32000 bps
ADPCM 24000 bps
ADPCM 16000 bps
Reserved
CONF_EC
3
4
0
1
Line echo canceller disabled
Line echo canceller enabled
CONF_SRC
3
5
0
1
Coder source is line input
Coder source is audio input
CONF_SUPSIL
3
6
0
1
Coder silence supressor disabled
Coder silence supressor enabled
CONF_ERCOR
3
7
0
1
Low bit rate decoder disable error correction
Low bit rate decoder enable error correction
Parameters ROOM-MONITOR Mode
In the ROOM MONITOR Mode (CONF_OPER equals 9) the parameters have the following
meaning :
Byte
Pos.
Value
CONF_OPER
Field
1
3..0
1001
CONF_EC
3
4
0
1
Definition
Define ROOM-MONITOR mode
Line echo canceller disabled
Line echo canceller enabled
Parameters HANDSET/HANDSFREE Mode
In the HANDSET/HANDSFREE mode (CONF_OPER equals C), the parameters have the
following meaning :
Byte
Pos.
Value
CONF_OPER
Field
1
3..0
1100
Definition
CONF_INHINI
3
6
0
1
Init all telephony parameters
Disable init of telephony parameters
CONF_HFREE
3
7
0
1
Handset mode
Handsfree mode
CONF_LEC
4
0
0
1
Line echo canceller enabled
Line echo canceller disabled
CONF_AEC
4
1
0
1
Audio echo canceller enabled
Audio echo canceller disabled
CONF_FULLD
4
2
0
1
Full duplex mode enabled
Half duplex mode enabled
CONF_SOFTRx
4
3
0
1
Softclipping enabled on Rx
Softclipping disabled on Tx
CONF_AGC
4
4
0
1
AGC active
AGC frozen
CONF_SOFTTx
4
5
0
1
Softclipping enabled on Tx
Softclipping disabled on Rx
Define HANDSET/HANDSFREE mode
31/84
ST75C530 - ST75C540
VII - COMMAND SET DESCRIPTION (continued)
CR
Opcode:
11
0
Synopsis
Parameters
0
0
Field
CR_ADDR_L
CR_ADDR_H
Parameters
Byte
1
2
Parameters
0
Field
ERR_MASK
Parameters
32/84
Value
1
Definition
Low byte of the 16-bit address
High byte of the 16-bit address
CSE
0
1
0
0
Pos.
7..0
Value
0
Definition
Error mask. See report appendix for detailed meaning
DEFT
Define Arbitrary Tone
0E
0
0
0
1
1
1
0
DEFT programs one of the four tone generator for arbitrary tone generation.The parameter
is the frequency of the generated tone expressed in Hertz between 0 and 3600Hz.
Field
TONE_GEN_SL
TONE_FREQ_L
TONE_FREQ_H
TONE_SCALE
Byte
1
2
3
4
Pos.
1..0
7..0
7..0
7..0
Value
Definition
Index of the tone generator (3..0)
Low byte of the frequency
High byte of the frequency (internally masked with 0F)
Amplitude scaling factor (high byte)
3F gives the nominal amplitude
DOSR
Define Optional Status Report
0A
0
Synopsis
Pos.
7..0
7..0
0
Byte
1
DOSR
Opcode:
0
CSE is used to clear the ST75C530/540 error status SYSERR byte. It is also used as an
acknowledge to the error condition handler.
0
Synopsis
0
08
DEFT
Opcode:
0
Clear Error Status
0
Synopsis
1
CR allows thereading ofa complex parameter.The parameterspecifiestheparameteraddress(for
the real part : the imaginary part is next location). CR returns the high byte value of both real and
imaginary part of the addressedcomplex parameter(see ChapterVIII “STATUS DESCRIPTION”).
CSE
Opcode:
CR
Complex Read
0
0
0
1
0
1
0
DOSR specifies the address of the RAM variables to be monitored in the 4 locations
STAOPT[0..3] of the dual port RAM. It also specifies the assignment within the 4 locations.
Field
STA_OPT_ASS
STA_OPT_ADL
STA_OPT_ADH
STA_OPT_HL
Byte
1
2
3
3
Pos.
1..0
7..0
3..0
7
Value
0..3
0
1
Definition
Index of the STAOPT destination
Low byte of source address
High byte of source address
Select low byte of source
Select high byte of source
ST75C530 - ST75C540
VII - COMMAND SET DESCRIPTION (continued)
DSIT
Opcode:
13
0
Synopsis
Parameters
Note :
0
0
1
0
0
1
1
DSIT specifies the bit mask used with the STATUS[0] and STATUS[1] byte to generate an
interrupt IT4 to controller. Each time a bit change happens in the status words, assuming
the corresponding bit mask will be set, an interrupt will be generated.
Field
STA_IT_MSK0
STA_IT_MSK1
Byte
1
2
Pos.
7..0
7..0
Value
Definition
Status[0] bit mask pattern
Status[1] bit mask pattern
The default IT Status is 0x3F for STATUS[0]and 0xFF for STATUS[1].
FORM
Opcode:
DSIT
Define Status Interrupt
FORM
Select Transmission Format
09
0
0
0
0
1
0
0
1
Synopsis
FORM defines the type of transmission used on the line.
Parameters
Field
Byte
Pos.
Value
Note :
X_SYNC
1
2..0
X_ANBIT
2
1..0
X_APAR
2
3..2
X_ASTOP
2
5
1. Valid only when transmitting.
HSHK
Opcode:
Parameter
HSHK
Handshake
04
0
Synopsis
Definition
Synchronous format
Transmit continous “1” (1)
HDLC framing
Transmit continous ”0” (1)
UART
7 Bit per character
8 Bit per character
No parity
Even parity
Odd parity
1 stop bit(1)
2 stop bit(1)
000*
001
010
011
100
00
01
00
01
10
0
1
0
0
0
0
1
0
0
HSHK is used to command the ST75C530/540 to begin the transmit handshake sequence
processing. The progress of the handshake is reported to the control processor.
Non parametric command.
33/84
ST75C530 - ST75C540
VII - COMMAND SET DESCRIPTION (continued)
IDT
Opcode:
0
Synopsis
Parameter
0
0
Parameter
Note :
Parameters
0
0
INIT
0
0
0
0
1
1
0
INIT forces the ST75C530/540to reset all parameters to their default conditions and restart
operations.
Non parametric command.
This command makes a software reset of the ST75C530/540 and so cannot have the regular handshake protocol. It
does not increment the COMACK, neither generate an Interrupt.
JSR
Call a Low Level Subroutine
18
0
Synopsis
1
Initialization
JSR
Opcode:
0
06
0
Synopsis
1
IDT ReturntheST75C530/540HardwareandSoftwarereleasenumber.SeeparagraphVIII.1.4.
Non parametric command.
INIT
Opcode:
IDT
Identify
14
0
0
1
1
0
0
0
JSR allows to execute a part of the ST75C530/540 firmware with a specific argument.
Field
C_ADDR_L
Byte
1
Pos.
7..0
Value
Definition
Low byte of the call address
C_ADDR_H
2
7..0
High byte of the call address
C_DATA_L
3
7..0
Low byte of the argument
C_DATA_H
4
7..0
High byte of the argument
This instruction can be used with SGS-THOMSON Microelectronics Application Laboratory Support for
special applications development or debugging needs. Contact your local representative.
34/84
ST75C530 - ST75C540
VII - COMMAND SET DESCRIPTION (continued)
MODC
Opcode:
0
Synopsis
0
1
0
0
0
0
1
MODC allows the modification of the parameters defined by the CONF command.
Parameters
Field
MODC_SDM
Byte
1
Pos.
0
MODC_DV21F
1
1
MODC_DDTMF
1
2
MODC_DTDT4
1
3
MODC_DTDT16
1
4
MODC_SH
1
6
MODC_FS
1
7
MODC_V22G (6)
2
1..0
MODC_FPT
2
3..2
MODC_NOTA (6)
2
4
Value
0
1
0
1
0
1
0
1
0
1
0*
1
0*
1
00*
01
10
00*
01
10
0*
1
Notes :
MODC
Modify Configuration
21
MODC_NOSA
(6)
2
6
MODC_NOQA
(6)
2
7
MODC_ADCFD
3
0..3
MODC_COD
3
5
MODC_LEC
4
0
MODC_AEC
4
1
MODC_FULLD
4
2
MODC_SOFTRx
4
3
MODC_AGC
4
4
MODC_SOFTTx
4
5
1.
2.
3.
4.
5.
6.
0*
1
0*
1
0000*
0001
0010
0011
1111
1110
1101
0111
Other
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Definition
Normal data mode
Short data mode (e.g. TVR) (5)
Normal V.21ch2 (1)
Disable V.21ch2 flag detector
Normal DTMF detector (1)
Disable DTMF detector
Normal secondary tone detector (1)
Disable secondary tone detector
Normal primary tone detector (1)
Disable primary tone detector
Normal training sequence
Short training sequence (2)
Secondary tone detector sampling frequency is 4.8kHz
Secondary tone detector sampling frequency is 9.6kHz
No guard tone
1800Hz guard tone (V.22bis/V.22)
550Hz guard tone (V.22bis/V.22)
No echo protection tone
Long echo protection tone (180ms) (4)
Short echo protection tone (30ms) (4)
Answer mode : generate answer tone for handshake
Originate mode : wait answer tone for handshake
Answer mode : do not generate answer
Originate mode : do not wait answer tone
Cut answer tone when receiving AA (V.32bis, V.32)
Continue answer tone when receiving AA.
Enable V.32bis/V.32 autoretrain on quality.
Disable V.32bis/V.32 autoretrain on quality.
Low bit rate decoder voice frame duration 30ms (nominal)
Low bit rate decoder voice frame duration 35ms (+16%)
Low bit rate decoder voice frame duration 40ms (+33%)
Low bit rate decoder voice frame duration 45ms (+50%)
Low bit rate decoder voice frame duration 25ms (-16%)
Low bit rate decoder voice frame duration 20ms (-33%)
Low bit rate decoder voice frame duration 15ms (-50%)
Low bit rate decoder pause
Reserved
Low bit rate coder disabled
Low bit rate coder enabled(3)
Line echo canceller enabled
Line echo canceller disabled
Audio echo canceller enabled
Audio echo canceller disabled(3)
Full duplex mode enabled
Half duplex mode enabled
Softclipping enabled on Rx
Softclipping disabled on Rx
AGC active
AGC frozen
Softclipping enabled on Tx
Softclipping disabled on Tx
In the modes where they are active.
Short train sequence must be preceded by at least one successful long train sequence at the same data rate. For
V.17 a successful long train at any data rate must preceded the short train.
Only coder or decoder can be enabled at the same time.
Only when sending V.17, V.33, V.29 or V.27ter.
French Minitel Application (TVR : Teletel Vitesse Rapide).
ST75C540 only
35/84
ST75C530 - ST75C540
VII - COMMAND SET DESCRIPTION (continued)
MR
Opcode:
0
Synopsis
0
0
Byte
Pos.
1
7..0
Low byte of the 16-bit address
MR_ADDR_H
2
7..0
High byte of the 16-bit address
0
1
Field
MRI_IADDR
Byte
1
Pos.
7..0
MRI
0
1
0
0
Value
0
Definition
Indirect Address
MRLO
Memory Read Low Word
0
1
0
1
0
0
1
MRLO allows the reading of the memory location which address coresponds to the previous
MR or MRI Absolute Adress minus 1. This command must be preceded by a MR or MRI
command. This command does not have any parameter. The double word reading is
executed by the MR or MRI previous command.
MW
Memory Write
12
0
36/84
Definition
29
MW
Parameters
0
MRI allows the reading of a 16-bit parameter. The parameter specifies an indirect address.
Refer to the “RAM Mapping Application Note” (delivered on request according to revision
number). The advantage to use MRI instead of MR is that the Indirect Address is constant
over the different release of the product.
0
Synopsis
Value
Memory Read Indirect
MRLO
Opcode:
0
28
Parameters
Synopsis
0
Field
0
Opcode:
0
MR_ADDR_L
MRI
Synopsis
1
MR allowsthereadingof a 16-bitparameter.The parameterspecifiestheparameteraddress.
Parameters
Opcode:
MR
Memory Read
10
0
0
1
0
0
1
0
MW allows the writing of a 16-bit parameter. The parameter specifies the address as well
as the value to be transferred.
Field
MW_ADDR_L
Byte
1
Pos.
7..0
Value
Definition
Low byte of the 16-bit address
MW_ADDR_H
2
7..0
High byte of the 16-bit address
MW_VALUE_L
3
7..0
Low byte of the 16-bit value
MW_VALUE_H
4
7..0
High byte of the 16-bit value
ST75C530 - ST75C540
VII - COMMAND SET DESCRIPTION (continued)
MWI
Opcode:
0
Synopsis
Parameters
0
1
Parameters
Pos.
7..0
MWI_IVALUE_L
2
7..0
Low byte of the 16-bit value
MWI_IVALUE_H
3
7..0
High byte of the 16-bit value
Parameters
1
Value
0
Definition
Indirect address
MWLO
Memory Write Low Word
2B
0
1
0
1
0
1
1
MWLO allows the writing of a 16-bit parameter at the address defined by the following MW
or MW Absolute Address minus 1. This command must be followed by a MW or MWI
command.The double word writing is executed by the MW or MWI following command.
Field
MWLO_VALUE_L
Byte
1
Pos.
7..0
MWLO_VALUE_H
2
7..0
Value
Definition
Low byte of the 16-bit value
High byte of the 16-bit value
RTRA
Retrain
02A
0
Synopsis
0
Byte
1
RTRA (ST75C540 only)
Opcode:
1
Field
MWI_IADDR
0
Synopsis
0
MWI allows the writing of a 16-bit parameter. Theparameters specifies an indirect address as well
asthe value to be transferred.Referto the “RAM MappingApplicationNote” (deliveredon request
accordingtorevisionnumber).TheadvantagetouseMWIinsteadofMWisthattheIndirectAddress
is constant over the differentrelease of the product.
MWLO
Opcode:
MWI
Memory Write Indirect
2A
0
0
0
0
1
0
1
RTRAis used to force the ST75C530/540to initiate a retrain sequence or a rate negotiation.
If MODC_NOQUA bit is set, the ST75C530/540 will initiate a transmission at the maximum
speed defined by the RTRA parameter, otherwise it will found the best reliable speed based
on the quality of the line (within the RTRA allowed speed).
Field
RTRA_NEG0
Byte
1
Pos.
0
Value
0
1
Definition
Retrain (V.22bis, V.32, V.32bis)
Ratr negotiation (V.32bis, V.22bis)
RTRA_SP0
1
7..4
xxx1
xx1x
x1xx
1xxx
1200bps
2400bps
4800bps
7200bps
RTRA_SP1
2
2..0
xx1
x1x
1xx
9600bps allowed (V.32bis, V.32)
12000bps allowed (V.32bis)
14400bps allowed (V.32bis)
allowed (V.22bis)
allowed (V.22bis)
allowed (V.32bis, V.32)
allowed (V.32bis)
37/84
ST75C530 - ST75C540
VII - COMMAND SET DESCRIPTION (continued)
SETGN
Opcode:
0
Synopsis
SETGN
Set Output Gain
02
0
0
0
0
0
1
0
SETGN is a command which sets the scaling factor of the transmit samples. It is used for
setting the output level or for setting the level of the tone generators. The gain value is given
in the form of a 2’s complement 16-bit value.
Parameter
Field
GAIN_L
GAIN_H
Byte
1
2
Pos.
7..0
7..0
Value
range FF*
range 7F*
Definition
Low byte of the 16-bit gain value
High byte of the 16-bit gain value
Example
Gain (dB)
0
-1
-2
-3
-4
Gain (Hex)
7FFF
7214
65AC
5A9D
50C3
Gain (dB)
-5
-6
-7
-8
-9
Gain (Hex)
47FA
4026
392C
32F5
2D6A
Gain (dB)
-10
-11
-12
-13
-14
Gain (Hex)
287A
2413
2026
1CA7
198A
The multiplication factor is : 10(-1/20) = 0.89125 for 1dB step.
SLEEP
Opcode:
SLEEP
Turn to Sleep Mode
03
0
0
0
0
0
0
1
1
Synopsis
SLEEP is used to force the ST75C530/540 to turn to low power mode.
Parameter
Non parametric command.
Note :
When receiving this command the ST75C530/540 will stop processing and so cannot have the regular handshake protocol.
It does not increment the COMACK, neither generate an Interrupt.
STOP
Opcode:
STOP
FAX Stop Transmitter
25
0
0
1
0
0
1
0
1
Synopsis
STOP is used, in FAX Modes, to force the ST75C530/540 to turn off the transmitter in
accordance with the corresponding ITU-T V.33/V.17/V.29/V.27recommendation.
Parameter
Non parametric command.
Note :
When receiving this command the ST75C530/540 will stop sending regular Data. This command must be preceded by a
XMIT Stop command. The ST75C530/540 will wait until all the transmit buffers are sent before starting the Stop sequence.
SYNC
Opcode:
26
0
Synopsis
Parameters
38/84
SYNC
FAX Synchronize the Receiver
0
1
0
0
1
1
0
SYNC is used, in FAX Modes, to force the ST75C530/540 to Start/Stop the receiver in
accordance with the corresponding ITU-T V.33/V.17/V.29/V.27recommendation.As soon as
the ST75C530/540 receives the SYNC Start command it sets its receiver to detect the FAX
synchronization signal.This command is the equivalent HSHK command for the receiver.
Field
RX_SYNC
Byte
1
Pos.
0
Value
0*
1
Definition
Stop receiver
Start receiver synchronization
ST75C530 - ST75C540
VII - COMMAND SET DESCRIPTION (continued)
TDRC
Opcode:
1A
0
Synopsis
TDRC
Tone Detector Read Coefficient
0
0
1
1
0
1
0
TDRC Read one Coefficient of the selected Tone Detector Cell.
Parameters
Field
TD_CELL
Byte
1
Pos.
4..0
Value
0..13
Definition
Tone detector cell number
TD_C_ADDR
2
7..0
0..B
10
20
30 (1)
40 (1)
Biquad coefficient
Energy coefficient
Static level
Energy coefficient for relative comparison
Gain for relative comparison
The command answer is : Low Byte of Coefficient followed by High Byte of Coefficient.
Note 1 :
Value 30 and 40 of byte 2 are available only for secondary tone detector.
TDRW
Opcode:
0
Synopsis
Parameters
TDRW
Tone Detector Read Wiring
1B
0
0
1
1
0
1
1
TDRW Read Wiring of the selected Tone Detector Cell.
Field
TD_CELL
Byte
1
Pos.
4..0
Value
0..13
Definition
Tone detector cell number
0
0
1
Other
Biquad and energy input
Comparator inputs
Reserved
For primary tone detector
TD_W_ADDR
2
The command answer is :
a) If TD_W_ADDR = 0 :
- First Byte is the Node Number of the Signal connected to Biquadratic Filter input.
- Second Byte is the Node Number of the Signal connected to the Energy estimator input.
b) if TD_W_ADDR = 1 :
- First Byte is the Node Number of the Signal connected to Comparator Negative input.
- Second Byte is the Node Number of the Signal connectedto the Comparator Positive input.
For secondary tone detector TD_W_ADDR is not defined.
- First byte is 00 if relative comparison is not mandatory,
First byte is 01 if relative comparison is mandatory.
- Second byte is for the configuration of the secondary tone detector :
C0 configuration 1+1 of secondary tone detectors,
E0 configuration 1+1+2,
F0 configuration 1+1+1.
39/84
ST75C530 - ST75C540
VII - COMMAND SET DESCRIPTION (continued)
TDWC
Opcode:
0
Synopsis
Parameters
Note 1 :
0
0
Field
TD_CELL
TD_C_ADDR
Byte
1
2
Pos.
4..0
7..0
TD_COEFL
TD_COEFH
3
4
7..0
7..0
Parameters
1
1
Value
0..13
0..B
10
20
30 (1)
(1)
40
0
Definition
Tone detector cell number
Biquad coefficient
Energy coefficient
Static level
Energy coefficient for relative comparison
Gain for relative comparison
Low byte of coefficient
High byte of coefficient
TDWW
Tone Detector Write Wiring
1D
0
0
1
1
1
TDWW Write Wiring of the selected Tone Detector Cell.
Field
TD_CELL
Byte
1
Pos.
4..0
Value
0..13
Definition
Tone detector cell number
Value
0
1
Other
Definition
Biquad and energy input
Comparator inputs
Reserved
For Primary Tone Detector
Field
TD_W_ADDR
Byte
2
Pos.
0
If TD_W_ADDR = 0 (Select Biquad and Energy Inputs)
Field
TD_W_ERN
TD_W_BIQ
Byte
3
4
Pos.
Value
0..3F
0..3F
Definition
Energy estimator signal input
Biquad filter signal input
If TD_W_ADDR = 1 (Select Comparator Inputs)
Field
TD_W_CN
TD_W_CP
Byte
3
4
Pos.
Value
0..3F
0..3F
Definition
Negative comparator signal input
Positive comparator signal input
Value
00
01
other
0
C0
E0
F0
other
Definition
Relative comparison not enable
Relative comparison enable
Reserved
Mandatory
1+1 configuration
1+1+2 configuration
1+1+1+1 configuration
Reserved
For Secondary Tone Detector
40/84
0
Value 30 and 40 of byte 2 are available only for secondary tone detector.
0
Synopsis
1
TDWC Write one Coefficient of the selected Tone Detector Cell.
TDWW
Opcode:
TDWC
Tone Detector Write Coefficient
1C
Field
TD_4DIFF
Byte
2
Pos.
7..0
TD_4_CONF
TD_4_CONF2
3
4
7..0
7..0
0
1
ST75C530 - ST75C540
VII - COMMAND SET DESCRIPTION (continued)
TDZ
Opcode:
0
Synopsis
0
Field
TD_CELL
Byte
1
TGEN
Parameters
1
1
1
1
Pos.
4..0
Value
0..13
0
Definition
Tone detector cell number
TGEN
Enable/Disable Tone Generators
0D
0
Synopsis
0
TDZ Clears all internal variables of one Tone detector cell including Filter local variables and
energy estimator. This command must be sent after changing coefficients of a cell to avoid
instability.
Parameters
Opcode:
TDZ
Tone Detector Clear Cell
1E
0
0
0
1
1
0
1
Enable or disable one of the four tone generator, define the output of the tone generator
either Line or Audio.
Field
TONE_0_ENA
Byte
1
Pos.
0
TONE_1_ENA
1
1
TONE_2_ENA
1
2
TONE_3_ENA
1
3
TONE_0_OUT
1
4
TONE_1_OUT
1
5
TONE_2_OUT
1
6
TONE_3_OUT
1
7
Value
0*
1
0*
1
0*
1
0*
1
0*
1
0*
1
0*
1
0*
1
Generator #0
Generator #0
Generator #1
Generator #1
Generator #2
Generator #2
Generator #3
Generator #3
Generator #0
Generator #0
Generator #1
Generator #1
Generator #2
Generator #2
Generator #3
Generator #3
Definition
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
output to line
output to audio
output to line
output to audio
output to line
output to audio
output to line
output to audio
41/84
ST75C530 - ST75C540
VII - COMMAND SET DESCRIPTION (continued)
TONE
Opcode:
0C
0
Synopsis
Parameters
0
0
Field
TONE_SELECT
Byte
1
Pos.
5..0
Value
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
TONE_OUT
1
7
0
1
Parameters
42/84
1
1
0
0
Definition
DTMF digit 0
DTMF digit 1
DTMF digit 2
DTMF digit 3
DTMF digit 4
DTMF digit 5
DTMF digit 6
DTMF digit 7
DTMF digit 8
DTMF digit 9
DTMF digit A
DTMF digit B
DTMF digit C
DTMF digit D
DTMF digit *
DTMF digit #
Answer tone 2100Hz
Tone 1650Hz
Tone 2225Hz
Tone 1300Hz
Tone 1100Hz
Output on line
Output on audio
XMIT
Start/stop Transmission
01
0
Synopsis
0
TONE programs the tone generator for the predifined tones. The tone generator #0 and
eventualy #1 are reprogrammed with this command. The tone generator #0 and eventualy
the #1 are enabled. Using a value not in the following table will disable tone generator #0
and #1.
XMIT
Opcode:
TONE
Predefined Tones
0
0
0
0
0
XMIT start or stop the transmission of the Transmit Data.
Field
TX_START
Byte
1
Pos.
0
Value
0*
1
Definition
Stop transmission
Start transmission
0
1
ST75C530 - ST75C540
VIII - STATUS DESCRIPTION
This appendix is dedicated to the ST75C530/540
reporting features. In the following sections the
command acknowledge process and the report
and status definitions are explained.
In the case of a memory reading command (CR,
TDRC, TDRW, IDT or MR) once the command
entered is executed,the reportarea is filled and the
acknowledge counter is incremented afterwards.
This insures that the controller will read the value
corresponding to its request.
Furthermore, the ST75C530/540 resets the value
of the COMSYS register and the interruption IT6
is raised.
VIII.1 - Command Acknowledge and Report
VIII.1.1 - Command Acknowledge Process
The ST75C530/540 features an acknowledge
process based on a counter COMACK. On poweron reset (or INIT command), this counter’s value is
set to 0. Each time a command is successfully
executed by the ST75C530/540, the acknowledge
counter COMACK is incremented. This allows a
precise monitoring of the command entered and
avoids command collision.
VIII.1.2 - Reports Specification
The report section of the Dual Port RAM is dedicated to memoryreading. In response to a CR, MR,
MRI, MRLO, TDRC, TDRW, IDT commands, the
value read is transferred to the report registers
COMREP[0..1].
Figure 16 : Command Acknowledge Process
BEGIN
COMSYS = 0
No
Yes
COMMAND EXIST
No
CLEAR
ANSWER
EXECUTE
COMMAND
COPY ANSWER
INTO
COMREP
SET SYSERR
ERR_IPRM
SET SYSERR
ERR_IOCD
INCREMENT
COMACK
ASSERT
INTERRUPT
IT0
ASSERT
INTERRUPT
IT0
CLEAR
COMSYS
ASSERT
INTERRUPT
IT6
75C53020.EPS
Yes
END
43/84
ST75C530 - ST75C540
VIII - STATUS DESCRIPTION (continued)
VIII.1.3 - CR Command
Issuing a CR command causes the ST75C530/540 to dump a specific memory location in complex mode.
This instruction is particularly useful for equalizer state analysis or for software eye-pattern display. The
report area has this meaning :
RP7
RP6
RP5
RP4
RP3
RP2
RP1
RP0
COMREP[0]
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
COMREP[1]
RP0..RP7 is the MSB part of the 16-bit value of the real part and IP0..IP7is the MSB part of the imaginary
part. The CR command insures that the real and imaginary part of the desired complex value are sampled
internally at the same time. The address given in the parameter field of CR is the address of the real part.
VIII.1.4 - MR/TDRC/TDRW/IDT/MRI/MRLO Commands
The report issued by the MR/TDRC/TDRW/IDT/MRI/MRLO commands follow the same rules as for CR.
The report meaning is :
D7
D6
D5
D4
D3
D2
D1
D0
COMREP[0]
D15
D14
D13
D12
D11
D10
D9
D8
COMREP[1]
D0..D15 is the 16-bit value requested by the command.
In the case of IDT,D15..D12 containsthe productidentification(3 for ST75C530,7 for ST75C5540), D11..D8
contains the hardware revision identification and D7..D0 contains the software revision identification.
VIII.2 - Modem Status
VIII.2.1 - Modem Status Description
The Status of ST75C530/540 is divided into 4 fields :
- The error status byte SYSERR that provides information about error. This status can trigger an IT0
interrupt,
- The general status byte STATUS[0] and STATUS[1] that contains all the modem signals. These status
bytes can trigger an IT4 interrupt,
- The quality status STAQUA, that contains the quality of the received transmission,
- The optional status bytes STAOP[0], STAOP[1], STAOP[2] and STAOP[3], that contains additional
information regarding the ST75C530/540 operating mode. This default information can be changed to
monitor any internal variables using the DOSR command.
All these informations are updated on a Baud basis :
Mode
V.32bis/V.32 (ST75C540 only)
Baud Rate
(2)
(Hz)
2400
V.22bis/V.22/Bell 212A (ST75C540 only)
2400
Tone
2400
Bell 103 (full duplex)
2400
V.21 (full duplex)
2400
V.23 (full duplex)
2400
V.27ter 2400bps
1200
V.27ter 4800bps
1600 (1)
V.29
2400
V.17/V.33
2400
V.21 channel 2
2400
HANDSET, CODER or DECODER Modes
1200
Notes : 1. In this mode the tone detectors outputs are update 800 times by second.
2. This baud rate defines also, the maximum command rate. Each baud time the ST75C530/540 looks at the COMSYS location
(Address $00) to see if a command have been sent by the host processor. If the content of this location is different from zero the
ST75C530/540 execute the command.
44/84
ST75C530 - ST75C540
VIII - STATUS DESCRIPTION (continued)
Starting at the adddress $08 the status area have the following format :
Add.
$08
Bit
Name
7
SYSERR ERR_RTK
6
5
4
-
-
ERR_IPRM
ERR_IOCD ERR_VOCO ERR_RX ERR_TX
STA_CPT0
STA_RING
STA_106
STA_AT
STA_CCITT
$09 STATUS0 STA_109F STA_CPT10 STA_CPT1
$0A STATUS1 STA_DTMF STA_FLAG STA_RNEG STA_HR
STA_CLR*
STA_RTRN*
$0B STAQUA
$0C
STAOP0
$0D
STAOP1
$0E
STAOP2
$0F
STAOP3
-
3
2
1
0
STA_107 STA_109
STA_VAD
STA-TIM
STA_H
Quality
Depend on operating mode (see below)
* ST75C540 only
VIII.2.2 - Error Status
The error status changes each time an error occurs. When the ST75C530/540 signals an error by setting
one of the SYSERR bit, it generates an interrupt IT0. These bits can only be cleared by the host controler
using the CSE command.
The meaning of the different bits of the SYSERR byte is discribed below :
SYSERR
Pos.
Meaning when set
ERR_TX
Field
0
Transmit buffer underflow. Loss of synchronisation between the host and ST75C530/540 transmit
data buffer managment.
ERR_RX
1
Receive buffer overflow. Loss of synchronisation between the host and ST75C530/540 receive
data buffer managment.
ERR_VOCO
2
Vocoder buffer underflow (Decoder) or overflow (Coder). Lost of synchronisation between the
Host and ST75C530/540 VOCODER Buffer management.
ERR_IOCD
3
Incorrect command
ERR_IPRM
4
Incorrect parameter for the command
ERR_RTK
7
Real time kernel error. ST75C530/540 not able to perform all its tasks within the baud period
(transmit or receive samples lost).
45/84
ST75C530 - ST75C540
VIII - STATUS DESCRIPTION (continued)
VIII.2.3 - Modem General Status
The modem general status word is composed of two bytes STATUS[0] and STATUS[1]. Any bit changecan
generate an IT4 interrupt. Using the DSIT command allows the selection of the corresponding bit that will
generate an interrupt each time they will change. The default pattern is $3F for STATUS[0] and $FF for
STATUS[1].
The different bits have the following meaning :
STATUS[0]
Field
Pos.
Meaning when set
STA_109
STA_VAD
0
In FAX MODEM and TONECID modes STA_109 : CCITT Circuit 109 (Carrier Detect). Indicates
that valid data are received.
In CODER and DECODER modes : VAD: Voice Activity Detected
STA_107
1
CCITT Circuit 107 (Data Set Ready). Valid only in FAX & DATA MODEM modes.
STA_106
2
CCITT Circuit 106 (Clear To Send). Indicates that the training sequence has been completed
and that any data in the Transmit Buffer will be transmitted. Valid only in FAX & DATA MODEM
modes.
STA_RING
3
Ring Detected. A valid ring signal is present at the Ring pin. Valid only in Tones modes. The
precise frequency can be read in the optional status byte STAOP2.
STA_CPT0
4
In TONE and TONECID modes STA_CPT0: Call progress tone detector #0. Low pass filter
650Hz.
STA_CPT1
5
In TONE and TONECID modes STA_CPT1: Call progress tone detector #1. High pass filter
600Hz.
STA_CPT10
6
In TONE and TONECID modes STA_CPT10: Signal in Filter #0 is higher than #1.
STA_109F
7
In FAX MODEM mode, V.22bis mode* and TONECID mode STA_109F: Fast Carrier Detect.
* ST75C540 only
STATUS[1]
Field
Pos.
Meaning
STA_H
0
Transmit synchronisation in progress. Valid only in FAX & DATA MODEM modes.
STA_TIM*
1
Handshake timeout. Valid only in Data Modem mode.
STA_CCITT
2
CCITT 2100Hz versus 2225Hz answer tone detect. Valid if STA_AT is set. Valid only in Tone
mode.
STA_AT
3
Answer tone (either 2100Hz or 2225Hz) detected. Valid only in Tone mode.
STA_HR
STA_RTRN*
4
STA_HR : Receive synchronisation in progress. Valid only in Fax Modem mode.
STA_RTRN : Remote retrain detec, valid only in V.32bis/V.32/V.22bis Data Modem modes.
STA_RENEG*
5
Remote rate negotiation detected, valid only in V.32bis/V.32/V.22bis Data Modem modes.
STA_FLAG
STA_CLR*
6
STA_FLAG : V.21 channel 2 flag detect. Valid only in FAX Modem mode and Tone mode.
STA_CLR : Remote clear down detected V.32bis/V.32 Data Modem modes.
STA_DTMF
7
DTMF digit detect. The digit itself is available in the optional status byte STAOP3.
* ST75C540 only
46/84
ST75C530 - ST75C540
VIII - STATUS DESCRIPTION (continued)
VIII.2.4 - Quality Status
The quality bytes STAQUAand STAQUAS monitor an evaluationof the line quality. They are updated once
per baud and their value ranges from 127 (perfect quality) to 0 (terrible quality). This value is automaticaly
adjusted according to the current receiving mode. Refer to the following chart to convert the value of
STAQUA into its Bit Error Rate equivalence. The time constant for STAQUA is 100ms. The slow quality
byte (available on STAOP1 in Fax and Data mode except FSK) STAQUAS gives the equivalent quality with
a 1 seconde time constant.
-2
BER
1e
-3
1e
-4
1e
-5
1e
-6
1e
-7
1e
-8
75C53021.EPS
STAQUA
1e
-9
1e
0
31
63
95
127
VIII.2.5 - Optional Status
According to the operating mode of the ST75C530/540 the optional status is displaying different informations.
The optional status are automatically reprogrammed after each CONF command with the address of the
variablesto monitor accordingwith theoperating mode selected (CONF_OPER).Afterthe CONF command
the user must overwrite this default programming by using the DOSR command. In order to change the
default set-up please refer to the “RAM Mapping application note” (delivered on request according to
revision number) to obtain the addresses of the DSP Internal variables.
VIII.2.5.1 - Default Optional Status in All modes Except MODEM
While in Tone mode the format of the STAOP word is as follows :
Optional Status Words
Add.
Name
Bit
7
6
5
4
3
2
1
0
$0C
STAOP0
TDT7
TDT6
TDT5
TDT4
TDT3
TDT2
TDT1
TDT0
$0D
STAOP1
TDT15
TDT14
TDT13
TDT12
TDT11
TDT10
TDT9
TDT8
$0E
STAOP2
$0F
STAOP3
RING_PERIOD (1)
TDT19
TDT18
TDT17
TDT16
DTMF_DIGIT (4)
Notes : 1. RING_PERIOD is valid when the Bit 3 of the STATUS0 (STA_RING goes high. This value is updated at eac h falling edge of the
RING Signal. The RING_PERIOD value must be multiplied by 2400 to obtain the Period in second.
2. TDTx (x in [0..15]) is the Output of the 16 Tone detectors x (sampling rate 7200Hz).
3. TDTy (y in [16..19] is the Output of the secondary Tone detectors (sampling rate 4800Hz or 9600Hz) with absolute comparison
or relative comparison.
4. DTMF_DIGIT is valid when the Bit 7 of STATUS1 (STA_DTMF) goes high. This value remains unchanged until a new DTMF
Digit is detected.
47/84
ST75C530 - ST75C540
VIII - STATUS DESCRIPTION (continued)
VIII.2.5.2 - Default Optional Status in Fax Mode
While in Fax Modem mode the format of the STAOP word is as follows :
Optional Status Words in MODEM Mode
Add.
Bit
Name
7
$0C
STAOP0
$0D
STAOP1
$0E
STAOP2
$0F
6
x
x
5
4
3
x
SPEED
2
1
0
(2)(5)
SPVAL (1)(5)
STAQUAS
PNSUCs
STAOP3
TDT19
PRDETs
TDT18
PNDETs
TDT17
SCR1s
PRs
TDT16
PNs
P2s
DTMF_DIGIT
P1s
(4)
Notes : 1. SPVAL is active in V.33 receiver only at the same time as the rising transition of the SCR1s signal. When SPVAL is set, it indicates
that the SPEED bits contain the Data speed information.
2. SPEED is valid in V.33 receiver only it can have 2 values, after the SCR1s signal goes high : 1000 for 14400bps and 0111 for
12000bps.
3. The STAOP2 Bit reflects the progression of the Synchronisation.
4. Only valid in V.21 Channel 2 Receive mode.
The STAOP2 Bits have the following meanings :
STAOP2 in Fax Modem Mode
Name
Position
P1s
0
Description
Unmodulated carrier sequence. Optional, used for echo protection.
P2s
1
Continuous 180° phase reversal sequence
PNs
2
Equalizer trainning sequence
PRs
3
V.33 and V.17 rate sequence
SCR1s
4
Continuous scrambled 1 sequence
PNDETs
5
Turned on after PN sequence detection
PRDETs
6
Turned on after PR sequence detection (V.33 and V.17 only)
PNSUCs
7
Turned on after succesfull training of the receive equalizer. When on at the end of the
synchronization, the transmition BER is statisticaly bellow 10ppm.
48/84
ST75C530 - ST75C540
VIII - STATUS DESCRIPTION (continued)
With the following timing :
P1
Transmit
T2
T1
P2
PN
R
SCR1
T3
T4
T5
T6
Data
STA_H
P1s
P2s
PNs
PRs
SCR1s
(6)
T7
Receive
STA_HR
T7
T8
T8
T8
T8
(7)
STA_109F
P2s
PNDETs
PNs
PRDETs
(1)
PNSUCs
(2) (8)
SCR1s
75C53022.EPS
STA_109
RxData
Mode
T1 (4)
T1p (5)
T2
T3
T4
T5
T6
T7
T8
V.17
192
30
22
107
1240
27
20
5
7
ms
V.17 short
192
30
22
107
16
0
20
5
7
ms
Unit
V.29
192
30
22
53
160
0
20
5
7
ms
V.29 short
192
30
22
41
26
0
8
5
7
ms
V.27 4800
192
30
22
31
670
0
5
5
7
ms
V.27 4800 short
192
30
22
9
36
0
5
5
7
ms
V.27 2400
192
30
22
42
895
0
7
6
7
ms
V.27 2400 short
192
30
22
12
48
0
7
6
7
ms
49/84
ST75C530 - ST75C540
VIII - STATUS DESCRIPTION (continued)
Data
SCR1
T11 min
T10
Transmit
STA_H
P1s
P2s
PNs
PRs
SCR1s
(6)
Receive
T12
T13
(3)
STA_HR
STA_109F
PNDETs (3)
PNs
PRDETs (3)
PNSUCs (3)
75C53023.EPS
STA_109
RxData
Mode
T10
T11
T12
T13
Unit
V.17
13
20
8
25
ms
V.17 short
13
20
8
25
ms
V.29
13
20
8
25
ms
V.29 short
13
20
8
25
ms
V.27 4800
20
30
8
25
ms
V.27 4800 short
20
30
8
25
ms
V.27 2400
27
40
8
25
ms
V.27 2400 short
27
40
8
25
ms
Notes : 1.
2.
3.
4.
5.
6.
7.
8.
In the case of V.29 or V.27, PRs and PRDETs bits are not active.
-5
PNSUCs indicates the quality of the Rx signal that will give a ber of approximation of 1e .
After sending the command SYNC0, all bits are reset.
When using long echo protection tone, otherwise 0.
When using short echo protection tone, otherwise 0.
STA-106 is set at the end of T6 and reset at the beginning of T10.
After sending the command SYNC1, this bit is set.
PNSUC is evaluated twice, first at SCR1 detection and further 256 baud (V.29, V.17, V.33 : 106ms ; V .27 4800bps : 160ms ;
V.27 2400bps : 212ms) after STA_109.
9.
For V.21 channel 2, timing for loss of STA_109 is 25ms and timing for detection of STA_109 is 7ms.
10. For V.21 channel 2 after a STOP command, STA_H is set to “1” during 13ms when the last HDLC flag is transmitted.
50/84
ST75C530 - ST75C540
VIII - STATUS DESCRIPTION (continued)
VIII.2.5.3 - Default Optional Status in DATA MODEM Mode (ST75C540 only)
While in Data Modem mode the format of the STAOP word is as follows :
Optional Status Words in MODEM Mode
Add.
Bit
Name
7
6
x
x
5
4
3
$0C
STAOP0
$0D
STAOP1
STAQUAS
$0E
STAOP2
HSHK_PHA
$0F
STAOP3
TDT19
TDT18
x
TDT17
SPEED
TDT16
2
1
(2)(5)
0
SPVAL (1)(5)
Not Used
Notes : 1. SPVALis active in V.33 receiver only at the same time as the rising transition of the SCR1s signal. When SPVAL is set, it
indicates that the SPEED bits contain the Data speed information.
2. SPEED is valid in V.32bis, V.32, V.22bis, V.22, Bell 212A and V.33 receiver only with the following meaning :
Bit 4
0
0
0
0
0
0
1
Bit 3
0
0
1
1
1
1
0
Bit 2
1
1
0
0
1
1
0
Other
Bit 1
0
1
0
1
0
1
0
Data Speed
1200bps
2400bps
4800bps
7200bps
9600bps
12000bps
14400bps
Reserved
3. The STAOP2 Bit reflects the progression of the Synchronisation.
4. Only valid in V.21 Channel 2 Receive mode.
5. SPVALis active in V.32bis/V.32/V.22bis/V.22 at the end of the training sequence and at least 8 baud before entering Data mode.
SPVALand SPEED are also updated with each retrain and rate negotiation.
6. The SPAOP1 bits reflect the progression of the synchronization in Data modes.
51/84
ST75C530 - ST75C540
VIII - STATUS DESCRIPTION (continued)
The STAOP2 Bits have the following meanings in Data Modem mode :
HSHK_PHA(R)
Handshake progression counter contains information about the progress of the
hadshake in V.32 and V.22bismodes. This 8-bit value is available in STAOP2 in modem
mode. It can be read to examine the progressio of the handshake and it contains normal
values and error values as below :
AUTOBAUD ORIG MODE
Event
HSHK_PHA Value
Wait Answer Tone
Wait End Answer Tone
Not Autobaud and Waiting
USC1
Autobaud Waiting AC or USC1
$01
$02
$03
$04
AUTOBAUD ANSW MODE
Event
HSHK_PHA Value
Waiting HSK Command
Generating Answer Tone
Generating Silence
$10
$11
$12
V.32 ORIG MODE
EVENT
HSHK_PHA Normal Value
HSHK_PHA Error Value
AC_DET
AC/CA DET
CA/AC DET
NO AC DET
S_DET
SB_DET
R1_DET
S_DET
SB_DET
R3_DET
E_DET
DATA_MODE
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
$30
$1
$2
$B for RTN, $C for RTN
$4
$5
$6
$7
$8
$9, $D no R5 det after RRN
$A
EVENT
HSHK_PHA Normal Value
HSHK_PHA Error Value
AA_DET
AA/CC DET
NO CC DET
S_DET
SB_DET2
SB_DET
R2_DET
E_DET
DATA_MODE
$40
$41
$42
$43
$44
$45
$46
$47
$50
$8 for RTN, $9 for RRN
$1
$2
$3
$4
$5
$6, $A if no R det after RRN
$7
V.32 ANSW MODE
V.22bis ORIG MODE
EVENT
HSHK_PHA Normal Value
HSHK
USC1_DET
SCR1_DET
S1_DET
DATA_MODE
$60
$61
$62
$63
$70
V.22bis ANSW MODE
52/84
EVENT
HSHK_PHA Normal Value
HSHK
SCR1_DET
S1_DET
DATA_MODE
$80
$82
$83
$90
ST75C530 - ST75C540
IX - TONE DETECTORS
IX.1 - Overview
The general purpose ST75C530/540 tone detectors block is a powerful module that covers a lot of
applications :
- call progress tone detection, fully programmable
for all countries,
- FAX, voice, data automatic detection,
- call waiting detection, while in vocoder or data
mode.
IX.2 - Description
The primary tone detector block is a set of 16
identical Cells. Each cell is composed of a Double
Biquadratic Filter, a Power estimator section, a
Static level and a Level comparator.
Each Biquadratic Filter, Power Estimator and Static
Level can be programmed using a complete set of
commands (TDRC, TDRW, TDWC, TDWW, TDZ).
The wiring between the different Cells can be defined by the user, using the associated command
allowing a wide range of applications.
The sampling frequency is 7200Hz, allowing detection of signals less than 3300Hz.The level of detection is programmable from -6dBm down to -51dBm.
The 16 Comparator Outputs give, on a baud basis,
the information into two 8 bits words TONEDET0
(for cells number 0 to 7) and TONEDET1 (for cells
number 8 to F). These TONEDET variables can be
accessed using a MRI command or, more easily,
monitored on a baud basis using the DOSR command.
The 16 primary tonedetectorsare initializedeach time
entering the tone mode. However the previous coefficient values could be kept using a MW command.
The secondary tone detector have been added to
the ST75C530/540. The filter structure is the same
as the primary tone detector.
The sampling rate is 4800Hz allowing detection of
signal less than 1800Hz by defaultprogramming or
with a MODC command, the sampling rate is
9600Hz allowing detection of signal less than
3300Hz. The level of detection is programmable
from -6dBm down to -51dBm. In order to increase
the reliability of the detection, using a TDWW command, 2 comparisonsare provided,one with a fixed
level (absolute) or with the receive signal (relative).
The 4 secondary tone detectors are initialiazed
each time entering the tone mode. However the
previous coefficient values could be kept using a
CONF command.
ThecommandTDRC, TDWC, TDWW, TDRW, TDZ
with the TD_CELL parameter of 0x10, 0x11, 0x12
or 0x13 can be used to program these filters.
IX.2.1 - Biquadratic Filters
Each Biquadratic Filter is a double regular section
that can perform any Transfer function with 4 Poles
and 4 Zeros.
This routine is run on a sample basis.
Figure 17 : Biquadratic IIR Filter
C0
C5
CB
C6
2
2
Z -1
Z -1
C1
C3
C7
Z -1
C2
Z -1
OUT
C9
Z -1
C4
C8
75C53024.EPS
IN
CA
The corresponding transfer function is :
CB + 2 ⋅ C9 ⋅ z−1 + 2 ⋅ CA ⋅ z−2 −1
Out
C5 + 2 ⋅ C3 ⋅ z−1 + 2 ⋅ C4 ⋅ z−2
⋅
C6
⋅
⋅z
= C0 ⋅
Input
1 − 2 ⋅ C1 ⋅ z−1 − 2 ⋅ C2 ⋅ z−2
1 − 2 ⋅ C7 ⋅ z−1 − 2 ⋅ C8 ⋅ z−2
Note :
All coefficients are coded on 16 bits 2’s complement in the range +1, -1 (Q15). To avoid the possibility of overflow the user must check
that the internal node must not be higher that 0.5 (in Q15 representation).
53/84
ST75C530 - ST75C540
IX - TONE DETECTORS (continued)
corresponding bit into the TONEDET[0..1] word; if
not it clear this bit.
IX.2.2 - Power Estimation
The Power estimation Cell is needed to measure
the amplitude of the different tones. It is run on a
sample basis.
IX.2.5 - Wiring
The user must specify the connection (wiring) between the input/outputof the Filter, the input/output
of the Power estimator, the output of the static
levels and the two inputs of the Comparators.
The output signals have an absolute address:
Figure 18 : Power Estimator
OUT
+
IN
ABS(.)
Z -1
P1
75C53025.EPS
Z -1
The corresponding transfer function is :
Out =
| Input| ⋅ z
−1
⋅
P1
1 − (1 − P1) ⋅ z
−1
IX.2.3 - Static Level
A single Threshold level is associated with each
Cell. It canbe use to comparethe output of a Power
Estimation with an Absolute Value.
IX.2.4 - Comparator
The Comparator computes, on a baud basis, the
differenceof the signal on its Positive and Negative
Inputs. If the result is Higher that zero it sets the
54/84
Node Address
Signal
Name
Address
Description
Ground
00
Signal always equal to 0000
RxSig
01
Receive signal from the
Analog front end
RxSig2
02
Receive signal multiplied by 2
RxSig4
03
Receive signal multiplied by 4
04..0F
Reserved
Filter[0..F]
10..1F
Biquadratic Filter Outputs
Power[0..F]
20..2F
Power Estimator Outputs
Level[0..F]
30..3F
Static Levels
The user will specify the inputs of the filters, Power
and Comparator. At leastone input must comefrom
the RxSig (node 01, 02 or 03). It is mandatory to
connect all unused cell inputs to the Ground signal
(node 00).
ST75C530 - ST75C540
IX - TONE DETECTORS (continued)
Figure 19 : Tone Detector Wiring Address (first half)
BIQUADRATIC
FILTER
#0
@10
POWER
#0
@20
@30
COMP.
#0
LEVEL #0
BIQUADRATIC
FILTER
#1
@11
POWER
#1
@21
@31
COMP.
#1
LEVEL #1
BIQUADRATIC
FILTER
#2
@12
POWER
#2
@22
@32
COMP.
#2
LEVEL #2
@00
BIQUADRATIC
FILTER
#3
@13
POWER
#3
D0
@23
D1
@33
COMP.
#3
D3
Rx SIGNAL
@02
2
D2
LEVEL #3
@01
BIQUADRATIC
FILTER
#4
@14
POWER
#4
D4
@24
@34
COMP.
#4
LEVEL #4
@03
D5
D6
D7
2
BIQUADRATIC
FILTER
#5
@15
POWER
#5
@25
@35
TONEDET0
COMP.
#5
LEVEL #5
BIQUADRATIC
FILTER
#6
@16
POWER
#6
@26
@36
COMP.
#6
LEVEL #6
BIQUADRATIC
FILTER
#7
@17
POWER
#7
@27
@37
COMP.
#7
75C53026.EPS
GROUND
LEVEL #7
55/84
ST75C530 - ST75C540
IX - TONE DETECTORS (continued)
Figure 20 : Tone Detector Wiring Address (second half)
BIQUADRATIC
FILTER
#8
@18
POWER
#8
LEVEL #8
BIQUADRATIC
FILTER
#9
@19
POWER
#9
LEVEL #9
BIQUADRATIC
FILTER
#A
@1A
POWER
#A
LEVEL #A
BIQUADRATIC
FILTER
#B
@1B
POWER
#B
LEVEL #B
@28
@38
COMP.
#8
@29
@39
COMP.
#9
@2A
@3A
COMP.
#A
D0
@2B
@3B
COMP.
#B
D1
D2
D3
BIQUADRATIC
FILTER
#C
@1C
POWER
#C
D4
@2C
@3C
COMP.
#C
LEVEL #C
D5
D6
D7
BIQUADRATIC
FILTER
#D
@1D
POWER
#D
@2D
@3D
TONEDET1
COMP.
#D
LEVEL #D
BIQUADRATIC
FILTER
#E
@1E
POWER
#E
@2E
@3E
COMP.
#E
LEVEL #E
@1F
POWER
#F
@2F
@3F
LEVEL #F
56/84
COMP.
#F
75C53027.EPS
BIQUADRATIC
FILTER
#F
ST75C530 - ST75C540
IX - TONE DETECTORS (continued)
Figure 21a : Secondary Tone Detector Configuration (2 tone detectors 1 + 1)
INPUT SIGNAL
FOURTH ORDER
IIR FILTER #16
POW ()
#16
COMPARATOR
#16
absolu
AND
TDT16
Relative
AND
TDT17
Relative
LEVEL #16
POW ()
#20
COMPARATOR
#16
GAIN
#16
OR
-TD4DIFF or
TDWW 1001 00C0
FOURTH ORDER
IIR FILTER #17
POW ()
#17
COMPARATOR
#17
absolu
LEVEL #17
COMPARATOR
#17
GAIN
#17
OR
75C53028.EPS
POW ()
#20
-TD4DIFF or
TDWW 1100 00C0
Figure 21b : Secondary Tone Detector Configuration (3 tone detectors 1 + 1 + 2)
FOURTH ORDER
IIR FILTER #16
INPUT SIGNAL
POW ()
#16
COMPARATOR
#16
absolu
AND
TDT16
Relative
AND
TDT17
Relative
AND
TDT18
Relative
LEVEL #16
POW ()
#20
COMPARATOR
#16
GAIN
#16
OR
-TD4DIFF or
TDWW 1001 00E0
FOURTH ORDER
IIR FILTER #17
POW ()
#17
COMPARATOR
#17
absolu
LEVEL #17
POW ()
#20
COMPARATOR
#17
GAIN
#17
OR
-TD4DIFF or
TDWW 1100 00E0
FOURTH ORDER
IIR FILTER #19
POW ()
#18
COMPARATOR
#18
absolu
LEVEL #18
POW ()
#20
GAIN
#18
COMPARATOR
#18
OR
75C53029.EPS
FOURTH ORDER
IIR FILTER #18
-TD4DIFF or
TDWW 1200 00E0
57/84
ST75C530 - ST75C540
IX - TONE DETECTORS (continued)
Figure 21c : Secondary Tone Detector Configuration (4 tone detectors 1 + 1 + 1 + 1)
INPUT SIGNAL
FOURTH ORDER
IIR FILTER #16
POW ()
#16
COMPARATOR
#16
absolu
AND
TDT16
Relative
AND
TDT17
Relative
AND
TDT18
Relative
AND
TDT19
Relative
LEVEL #16
POW ()
#20
COMPARATOR
#16
GAIN
#16
OR
-TD4DIFF or
TDWW 1001 00F0
FOURTH ORDER
IIR FILTER #17
POW ()
#17
COMPARATOR
#17
absolu
LEVEL #17
POW ()
#20
COMPARATOR
#17
GAIN
#17
OR
-TD4DIFF or
TDWW 1100 00F0
FOURTH ORDER
IIR FILTER #18
POW ()
#18
COMPARATOR
#18
absolu
LEVEL #18
POW ()
#20
COMPARATOR
#18
GAIN
#18
OR
-TD4DIFF or
TDWW 1201 00F0
POW ()
#19
COMPARATOR
#19
absolu
LEVEL #19
POW ()
#20
GAIN
#19
COMPARATOR
#19
OR
-TD4DIFF or
TDWW 1300 00F0
58/84
75C53030.EPS
FOURTH ORDER
IIR FILTER #19
ST75C530 - ST75C540
IX - TONE DETECTORS (continued)
IX.3 - Example
Hereunder is an example of programming a single
Tone detection (using Cell #3) and a complex differential tone detection (using Cell #4 and #5).
Bit 3 of the TONEDET variable will be triggered
each time the energy of that filtered signal is higher
than Static Level number 3.
Bit 4 of the TONEDET variable will be on each time
a receive signal has an energy higher than the
Static Level number 4. Bit 5 will be on only when
the Filtered (Filter section 4 and 5) received signal
higher than the energy of the wide-band signal
number 4 ; this prevents triggering on noise.
Figure 22 : Wiring Example
@00
GROUND
BIQUADRATIC
FILTER
#3
@13
POWER
#3
@23
@33
LEVEL #3
COMP.
#3
@01
Rx SIGNAL
@14
POWER
#4
@24
D3
@34
LEVEL #4
COMP.
#4
D5
@03
2
D4
BIQUADRATIC
FILTER
#5
@15
POWER
#5
@25
@35
LEVEL #5
Program Cell #3 :
TDWW
03
00
13
Connect Received signal to Filter and Filter to Energy.
TDWW
03
01
33
Connect Level to Comparator Neg Input and Energy to Pos Input.
Program Cell #4 and #5 :
TDWW
04
00
01
Connect Received Signal to Filter and Energy.
TDWW
04
01
34
Connect Level to Comparator Neg Input and Energy to Pos Input.
TDWW
05
00
15
Connect Filter#4 Output to Filter and Filter to Energy.
TDWW
05
01
24
TONEDET0
COMP.
#5
75C53031.EPS
@02
2
BIQUADRATIC
FILTER
#4
01
23
01
24
14
25
Connect Wide-band Energy to Neg Input and Energy to Pos Input.
59/84
ST75C530 - ST75C540
X - PARALLEL DATA EXCHANGE
X.1 - Overview
While transmiting (respectively receiving) data to
(from) the telephone line data are exchanged between the host and the ST75C530/540.
Two totaly independent channels are provived for
transmit and receive data. Even while using half
duplex modes of operation, the transmitted data
comes from the transmit buffers and the receive
data arrives in the receive buffers.
Two independent interrupts, IT2 (for transmit) and
IT3 (for receive) are available for synchronizing the
ST75C530/540 and the host. An additional IT0
interruptwill signal the errorsin the synchronization
mechanism.
The equivalent data flow is as follows (see Figure 20).
The ST75C530/540 has a buit-in HDLC capability.
This feature automatically performs HDLC framing/deframing, CRC generation/detection and “0”
insertion/deletion. The ST75C530/540 have also
UART capability, the format of data is selected by
the FORM command described bellow.
X.2 - Transmit Buffers
Two identical buffers are provided to exchangethe
dat a bet ween th e host in terface an d the
ST75C530/540. When the host is writing data into
a buffer, the ST75C530/540 is transmitting the
other one. After that, both the host and the
ST75C530/540switch to use the other buffer. This
mechanism, called “Double-Buffering”, ensures
that the host has the maximum time to fill one
buffer.
The DUAL Ram area associated with the transmit
buffers is as following table.
Name
DTTBS0
DTTBS0 [0]
DTTBS0 [1]
DTTBS0 [2]
DTTBS0 [3]
DTTBS0 [4]
DTTBS0 [5]
DTTBS0 [6]
DTTBS0 [7]
DTTBS1
DTTBS1 [0]
DTTBS1 [1]
DTTBS1 [2]
DTTBS1 [3]
DTTBS1 [4]
DTTBS1 [5]
DTTBS1 [6]
DTTBS1 [7]
Address
$2E
$2F
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
$3B
$3C
$3D
$3E
$3F
Description
Buffer 0 Status Byte
Buffer 0 Data Byte 0
Buffer 0 Data Byte 1
Buffer 0 Data Byte 2
Buffer 0 Data Byte 3
Buffer 0 Data Byte 4
Buffer 0 Data Byte 5
Buffer 0 Data Byte 6
Buffer 0 Data Byte 7
Buffer 1 Status Byte
Buffer 1 Data Byte 0
Buffer 1 Data Byte 1
Buffer 1 Data Byte 2
Buffer 1 Data Byte 3
Buffer 1 Data Byte 4
Buffer 1 Data Byte 5
Buffer 1 Data Byte 6
Buffer 1 Data Byte 7
Bit 0 (LSB) of the Buffer 0 Data Byte 0 is the first in
time to be transmited.
According to the Data Format, the Status byte of a
buffer has different meanings. However a value of
0 signals to the host that a buffer is empty. This
value is set by the ST75C530/540 each time it has
emptied the buffer. After having used one buffer,
the host must select the other buffer for the next
operation. The host must start with the Buffer 0 as
soon as the ST_106 signal goes on and BEFORE
the XMIT 1 command is sent.
A mechanism of interruption (IT2 for Transmit) is
associated with the data buffer managment. Each
time a buffer is emptied by the ST75C530/540 it
generates an interrupt.
Figure 23
IT2
HOST INTERFACE
Tx
Tx
BUFFERS
HDLC
UART
MODUL.
Telephone
Line
H
HDLC
UART
DEMOD.
Control
Data
IT3
60/84
75C53032.EPS
Rx
Rx
BUFFERS
ST75C530 - ST75C540
X - PARALLEL DATA EXCHANGE (continued)
X.3 - Receive Buffers
Symetrically two identical buffers are provided to
ex c h a n ge re ce iv e da t a b et we e n t h e
ST75C530/540 and the host processor. While the
ST75C530/540 is filling one of the buffers with the
receive bits, the host processor is reading the other
buffer. As soon as the host has emptied a buffer it
frees it by writing 0 in the buffer status byte.
The DUAL Ram area associated with the receive
buffers is as following table.
Name
Address
Description
DTRBS0
$1C
Buffer 0 Status Byte
DTRBS0 [0]
$1D
Buffer 0 Data Byte 0
DTRBS0 [1]
$1E
Buffer 0 Data Byte 1
DTRBS0 [2]
$1F
Buffer 0 Data Byte 2
DTRBS0 [3]
$20
Buffer 0 Data Byte 3
DTRBS0 [4]
$21
Buffer 0 Data Byte 4
DTRBS0 [5]
$22
Buffer 0 Data Byte 5
DTRBS0 [6]
$23
Buffer 0 Data Byte 6
DTRBS0 [7]
$24
Buffer 0 Data Byte 7
DTRBS1
$25
Buffer 1 Status Byte
DTRBS1 [0]
$26
Buffer 1 Data Byte 0
DTRBS1 [1]
$27
Buffer 1 Data Byte 1
DTRBS1 [2]
$28
Buffer 1 Data Byte 2
DTRBS1 [3]
$29
Buffer 1 Data Byte 3
DTRBS1 [4]
$2A
Buffer 1 Data Byte 4
DTRBS1 [5]
$2B
Buffer 1 Data Byte 5
DTRBS1 [6]
$2C
Buffer 1 Data Byte 6
DTRBS1 [7]
$2D
Buffer 1 Data Byte 7
The Bit 0 (LSB) of the Buffer 0 Data Byte 0 is the
first received bit in time (the oldest).
According to the Data Format, the Status byte of a
buffer has different meaning. However a value of 0
signals to the ST75C530/540that a buffer is empty.
This value is set by the Host each time it has
emptied the buffer. After having used one buffer,
the host must select the other buffer for the next
operation. The Host must start with the Buffer 0 as
soon as the STA_109 signal goes.
A mechanism of interruption (IT3 for Receive) is
associated with the Data Buffer managment. Each
time a buffer is filled by the ST75C530/540 it generates an interrupt.
X.4 - Interruption
Two Interrupt signals are provided in order to synchronize the Data Buffer Exchanges. IT2 is associated with the Transmit Buffer mechanism and IT3
with the Receive Buffer mechanism.
In order to enable these interrupts, the Host processor must set the bit 2 (for IT2) and the bit 3 (for
IT3) of the ITMASK Register to 1. It must also set
the Bit 7 of the ITMASK register to 1 in order to
globally enable all the selected sources of interruption.
When an Interrupt occurs (low level on SINTR pin)
the user must read the ITSRCR Register to determine the source of the interrupt, either IT2 for Tx (if
the bit 2 is 1) or IT3 for Rx (if the bit 3 is 1).
Once the Interrupt has been serviced, the host
must acknowledge it by writing a $00 value into the
register ITRES2 for IT2, or ITRES3 for IT3.
These registers have the following address :
Name
ITRES2
ITRES3
ITMASK
ITSRCR
Address
$42
$43
$4F
$50
Type
Write only
Write only
Read/Write
Read Only
Description
Clear IT2
Clear IT3
Interrupt Mask
Interrupt Source
Notes : 1. The ST75C530/540 does not check that the interrupt has
been acknowledged.
2. Even if the Host does not use the interruption, the
ST75C530/540 will set the bit 2 (for IT2) and/or bit 3 (for
IT3) of the ITSRCR.
3. The ST75C530/540 uses only the Data Buffer Status
Bytes to detectOverrun or Underrun Error. These errors
are reported into the SYSERR byte, and could generate
an interrupt IT0.
The equivalent schematic is : see Figure 21.
The interrupt mechanism assumes that the Host
processor uses a Level sensitive interrupt (active
low). The Flow chart of the Host interrupt service
routine looks generaly like Figure 22.
X.5 - Data Format
Different Formats of Data can be Transmitted/Received to/from the Telephone Line.
These Formats can be selected when entering the
Data Mode by using the FORM command.
The Format of the Data can be changed,on the fly
in the Data Mode during the same communication,
by sendinga different FORM commandat anytime.
Note that for Full Duplex operation the Data Format is the same for the transmitter and the receiver.
61/84
ST75C530 - ST75C540
X - PARALLEL DATA EXCHANGE (continued)
Figure 24
ITRES 2
(write only)
R
Q
S
(Tx buffer emptied)
ITRES 3
(write only)
From
ST75C540
DSP
R
Q
S
(Rx buffer filled)
ITSRCR
(read only)
6
5
4
3
2
1
0
6
5
4
3
2
1
0
ITMASK
(read write)
7
75C53033.EPS
SINTR
Figure 25
IT
READ ITSRCR
MASK UNWANTED BITS
Yes
=0
Check only the Interrupt sources
that we want to manage under Interrupt
RETURN
If all sources served return from interrupt
BIT 2 = 1
Yes
No
BIT 3 = 1
No
(Other Interrupts)
62/84
Yes
EXECUTE IT_TRANSMIT
Execute Tx Buffer
Management
WRITE 00 INTO ITRES2
Reset IT2
EXECUTE IT_RECEIVE
Execute Rx Buffer
Management
WRITE 00 INTO ITRES3
Reset IT3
75C53034.EPS
No
ST75C530 - ST75C540
X - PARALLEL DATA EXCHANGE (continued)
X.6 - FORM Command
The FORM command allows the selection of the
Data Format. The Parameter syntax is as follows :
Field
X_SYNC
Byte Pos. Value
Definition
1
2..0 000* Synchronous format
001 T ransmit continuous
“1” (1)
010 HDLC framming
011 T ransmit continuous
”0” (1)
100 UART
X_ANBIT
2
1..0
00
7 Bit per character
01
8 Bit per character
X_APAR
2
3..2
00
No parity
01
Even parity
10
Odd parity
X_ASTOP
2
5
0
1 stop bit(1)
1
2 stop bit(1)
Note : 1. Transmit only
X.6.1 - Synchronous Mode
The synchronous mode is the default mode, if no
FORM command is used.
The transmitter reads the bits in the DUAL Ram
Buffer DTTBFx (starting with the Bit 0 of Byte 0 of
Buffer 0) and send them over the Telephone line.
The Buffer Status Byte DTTBSx contains the number of Data Bytes to transmit.
The Receiver write the received bits coming from the
Telephone line and write them into the DUAL Ram
Buffer DTRBFx (startingwith theBit 0 of the Byte 0 of
theBuffer0).TheBufferStatusByte DTRBSx contains
the number of Data Bytes received (generaly 8).
The time betweeneach IT2 interrupts(or IT3) is equal
to 64-bit if the number of Data Bytes is set to 8. The
Host has the full 64 bits time to serve the interrupt :
Bit Rate (bps)
14400
12000
9600
7200
4800
2400
1200
300
75
Interrupt Time (ms)
4.4
5.3
6.6
8.8
13.3
26.6
53.3
213.3
853.3
X.6.2 - HDLC Mode
The HDLC Format can be used for T.30 or ECM
implementations
X.6.2.1 - HDLC Transmit
TheHDLC Transmitter performsthe following tasks :
- Flag generation (7E) while in inter-frame.
- Flag generation (7E) at the begining of a frame.
- Zero insertion (after 5 consecutive “1”).
- CRC16 computation.
- CRC16 transmission at the end of a frame.
- Flag generation (7E) at the end of a frame.
- Abort frame.
- Programmable number of Starting flags.
- Programmable number of Inter frame flags.
- Programmable number of Ending flags.
The Buffer Status Byte DTTBSx defines the frame
type, and the number of Data Bytes to transmit.
X.6.2.2 - HDLC Receive
The HDLC Receiver performs the following tasks :
- Flag recognition.
- Opening flag recognition.
- Zero deletion.
- CRC16 computation.
- CRC16 check ; error CRC16 detection.
- Closing flag recognition.
- Abort frame detection.
- Received CRC.
The BufferStatusByte DTRBSx containsthe frame
type, the number of Data Bytes and the error report
if any. The errors detected are :
- CRC16 Error : Wrong CRC received.
- Non byte-alligned frame : The number of Data bits
betweenthe beginingoftheframe andtheendofthe
frame (after “zero” deletion)is not a byte- multiple.
- Aborted frame : More that 6 consecutive “1” received.
X.6.3 - UART Mode
In the UART mode the buffers contains only one
Character to transmit or received. The worse case
of interruptrate isobtained with the lower character
bit length (7bit of data, no parity and 1 stop bit) and
is provided in the following table.
Bit Rate (bps)
14400
12000
9600
7200
4800
2400
1200
300
75
Interrupt Time (ms)
0.41
0.41
0.82
1.25
1.64
3.75
7.5
30
120
X.6.3.1 - UART Transmit
TheUART Transmitter performsthe following tasks :
- Start bit generation.
- Parity Computation.
- Stop Bit generation.
- Break generation.
X.6.3.2 - UART Receive
The UART Receiver performs the following tasks :
- Start bit recognition.
- Parity Checking.
- Stop bit Checking.
- Break detection.
63/84
ST75C530 - ST75C540
XI - TRANSMITTING DATA IN PARALLEL MODE
XI.1 - Description
XI.1.1 - XMIT Command
The XMIT Command works like a CTS signal for
the Parallel Data process.
When XMIT is off, the ST75C530/540 transmits
continuous “1”. When on the ST75C530/540transmits Data in accordance with the FORM command
and starts to manage the Data Buffer.
This command can be sent at any time, while in
Data Mode (see Table below).
transmission, to stop sending the carrier on the
telephone line.
Prior to the STOP command the user must have
stop the parallel transmition with a XMIT off command.
When the current data buffer will be totaly transmitted, and that no more buffers will be available, that
is to said both DTTBF0 and DTTBF1 will be $00
(equivalent to an Underrun condition).
XI.1.4 - Timing
Here are regular sequences to stop properly the
transmition (see Figure 27).
XI.1.2 - FORM Command
The FORM Command can be sent at any time to
redefine the current format. The effect will take
place only when XMIT is on.
Here is a formal example showing the relationship
between XMIT, and FORM Commands (see Figure 26).
Field
Byte Pos. Value
TX_START 1
0
0*
1
XI.1.3 - STOP Command
The STOP command is used, at the end of the
**
Definition
(Off) Send
continuous “1” (**).
( O n ) Se n d D a ta
according with the
Format defined in the
FORM command.
The XMITOff command takes effect only when the two Transmit
buffers are empty : DTTBF0 and DTTBF1 equal to $00.
Figure 26
STA_106
DATA
TRANSMITTED
1
1
0
1
0
$7E
FORM 3
XMIT 1
XMIT 0
75C53035.EPS
COMMANDS :
XMIT 1
FORM 2
XMIT 0
Figure 27
Case # 1 Synchronous Format
STA_106
Feed Last Buffer
XMIT 0
STOP
DATA
TRANSMITTED
(ignored until here)
Last Buffer
1
Case # 2 HDLC Format
STA_106
Feed Last Buffer
XMIT 0
STOP
DATA
TRANSMITTED
(ignored until here)
Last Buffer
CRC16
$7E
1
Case # 3 UART Format
XMIT 0
STOP
DATA
TRANSMITTED
64/84
(ignored until here)
Last Buffer
1
75C53036.EPS
STA_106
ST75C530 - ST75C540
XI - TRANSMITTING DATA IN PARALLEL MODE (continued)
FSK Standard
V.21
Bell 103
V.23 Originate
V.23 Answer
Note 1 :
Establish a V.29 transmition and send the very first
Buffer (see Figure 29).
Figure 28
Nominal Transmit Bit Rate (Hz) (1)
300
300
75
1200
T he accur acy of the B i t cl ock is given by t he
ST75C530/540 oscillator, and must better than 100ppm.
XI.2 - Modem Flow Chart
When Data Mode, each time the ST75C530/540
need a bit to transmit it executes the following
routine (see Figure 28). Where x starts with the
value 0 and toggle thereafter between 1 and 0.
XI.3 - Host Flow Chart
Here after are Flowcharts to :
- Establish a V.29 transmission
- Send Synchronous continuous “$AA, $55, $AA,
$55, ...” sequence.The managmentof the Buffers
are done under Interrupt.
- Stop properly the transmition.
BEGIN
READ BIT IN
INTERNAL BUFFER
INTERNAL BUFFER
EMPTY
No
Yes
RETURN
SELECT NEXT DUAL
RAM BUFFER X
DTTBSx = 0
Yes
No
SIGNAL ERROR
INTO ERR_TX
MOVE DTTBFx DATA
TO INTERNAL BUFFER
RAISE IT0 INTERRUPT
CLEAR DTTBSx
RAISE IT2 INTERRUPT
SELECT DUAL
RAM BUFFER x = 0
RETURN
RETURN
75C53037.EPS
XI.1.5 - FSK Full Duplex Mode
In FSK Full duplex Mode the parallel mode assumes that the Bit time duration is the nominal Bit
rate.
Each bit element from the Transmit buffer is maintained during the full bit time.
The Nominal bit clock is defined as follows :
Figure 29
CONF 0F 08 00 01
Select V.29 9600bps
Subroutine :
FILL FIRST BUFFER
HSHK
Start V.29 sequence
WRITE AA, 55 ...
INTO DTTBF [0..7]
FORM 00 (opt)
Format synchronous
FILL FIRST BUFFER
Fill the first buffer # 0
WRITE 08 INTO DTTBFS0
SELECT NEXT BUFFER
IBUF = 1
STA_106 = 1
No
Wait until end
of training
Tx_COMPLETED = FALSE
Yes
Start to transmit
the first buffer
ENABLE IT2
ITMASK = 0 x 84
75C53038.EPS
XMIT 1
RET
65/84
ST75C530 - ST75C540
XI - TRANSMITTING DATA IN PARALLEL MODE (continued)
DTTBSx buffer. An abort frame is transmitted in
place of the regular Buffer.
- This condition cannot append in UART mode.
When an underflow condition occur the host must
restart the whole parallel initialization, as explained
above.
These flowcharts show two CPU variables labeled
IBUF and Tx_Completed, they are necessary for
the understanding of the mechanism, but there is
different manners to implement it. These two variables have the following meanning :
- IBUF : Thisis thenumberof the DUALRAM Buffer
currently in use by the Host processor. It starts
with 0 and then alternate 1, 0, 1, 0, ...
- Tx_Completed : This is a Flag to dialog with the
interrupt process in order to stop properly the
transmition.
The other Buffers are sent under interrupt control
(refer to the interrupt flow chart, Figure 30).
To stop properly the transmition, without loss of
Data (see Figure 31).
Figure 31
Stop sending parallel
data (delayed)
XMIT 00
STOP
Stop signal
Tx_COMPLETED = TRUE
Semaphore with interrupt
No
Wait until last buffer is
transmitted and CCITT
stop sequence completed
EXECUTE_IT_TRANSMIT
STA_106 = 1
Yes
Tx_COMPLETED ?
Yes
No
(1)
Yes
WRITE AA, 55, ...
INTO DTTBF1
WRITE AA, 55, ...
INTO DTTBF0
WRITE 08 INTO DTTBS1
WRITE 08 INTO DTTBS0
IBUF = 0
IBUF = 1
RETURN
XI.4 - Error Detection
Error occurs when the ST75C530/540 need some
bitsfrom the transmitbuffer DTTBSx and this buffer
is empty. This condition is called “Underflow”.
This error is signaled in the bit ERR_TX of the
SYSERR byte, and generates an interrupt IT0. To
clear the error a CSE 01 command must be issued.
An Underflow contition occurs when :
- In synchronous mode: the host processor “forgets” to feed the current DTTBSx buffer.
- In HDLC mode: when, while inside a frame, the
host processor “forgets” to feed the current
66/84
XI.5.2 - Status Word Format
The Transmit Status Bytes DTTBS0 or DTTBS1
have the same following meaning(see table below).
75C53039.EPS
(1)
XI.5 - Synchronous Mode
XI.5.1 - Description
In synchronousmode the ST75C530/540transmits
the bits contained in the DUAL RAM Buffer without
any modification. It starts with the Bit 0 of the
DTTBF0[0] byte.
No
IBUF = 1
DTTBSx in Synchronous Mode
Field
Pos. Value
BUFF_LENG 3 .. 0
0
1
2
..
8
Other
Other
7 .. 4
0
Definition
Buffer empty.
1 Byte to transmit
(DTTBFx[0]).
2 Bytes to transmit
(DTTBFx[0] and
DTTBFx[1]).
..
8 Bytes to transmit
(DTTBFx[0 .. 7]).
Not allowed.
Reserved, must be 0.
This status byte must be written by the Host, after
filing the corresponding data buffer DTTBFx[0..7]
with the right number of data bytes to transmit.
This status byte is cleared by the ST75C530/540,
just before generating the IT2 interrupt.
75C53040.EPS
Figure 30
ST75C530 - ST75C540
XI - TRANSMITTING DATA IN PARALLEL MODE (continued)
XI.6 - HDLC Mode
XI.6.1 - Description
will be transmitted, the ST75C530/540 will send
8 consecutive “1” and wait for the next buffer.
In HDLC mode the ST75C530/540 transmits the
data bytes contained into the DUAL Ram buffer
packed inside an HDLC frame. The mechanism is
as follows :
- While the Host has no frame to transmit, that is:
a s lo ng a s DTTBSx e qu a ls $ 0 0, t he
ST75C530/540 transmits the HDLC Flag $7E.
- When the Host wants to send some data, it feeds
the buffer with some data bytes to transmit (between 1 and 8) and set the BUFF_SFRM bit in
t he DTTBSx status buffer. At that time the
ST75C530/540 start sending data contained in
the Buffer, computin the CRC and performing
“zero intertion” if needed.
- When the host wants to send additional data
(within the same frame) it feeds the buffers just
like in synchronous mode. If an Underflow condition occurs, the ST75C530/540 will abort the
frame by sending 8 consecutive “1”, and the Host
must restart the whole parallel initialization.
- When the host wants to close a frame, it set the
BUFF_EFRM bit in the DTTBSx status buffer. At
that time the ST75C530/540 will send the contents of the buffer, then send the CRC and an
HDLC closing flag $7E.
- If the Host, wants to abort a frame (while sending
a frame)it setthe BUFF_FRAB bit in the DTTBSx
status buffer.At thattime, as soonas the last buffer
XI.6.2 - Status Word Format
DTTBSx in HDLC Mode
Field
Pos. Value
Definition
BUFF_LENG 3 .. 0
0
Buffer empty.
1
1 Byte to transmit
(DTTBFx[0]).
2
2 Bytes to transmit
(DTTBFx[0] and
DTTBFx[1]).
..
..
8
8 Bytes to transmit
(DTTBFx[0 .. 7] ).
other Not allowed.
BUFF_SFRM
4
0
Data stream.
1
Start of frame : the buffer
is a beginning of frame.
BUFF_EFRM
5
0
Data stream.
1
End of frame : the buffer
will be followed by the
transmission of the CRC
and closing flag.
BUFF_FRAB
6
0
Data stream.
1
Abort frame :
8 consecutive “1” will be
transmitted (whatever
BUFF_LENG is).
Other
7
0
Reserved, must be 0.
Notes : 1. A buffer can have BUFF_SFRM and BUFF_EFRM set
in the same DTTBSx byte, this means that the frame
transmitted is short (between 1 and 8 Bytes long).
2. An ending frame (with BUFF_EFRM set) must have at
least ONE byte of data to transmit.
XI.6.3 - Single Short Frame (see Figure 32)
Figure 32
TRANSMITTED
$7E
DATA
D0
CRC $7E D1 CRC
$7E
D2
CRC $7E D3 CRC $7E
BUFF_FRAB
BUFF_SFRM
BUFF_EFRM
(BUFF_DATA)
0
6
2
D0
D1
0
8
D2
0
5
0
75C53041.EPS
BUFF_LENG
D3
67/84
ST75C530 - ST75C540
XI - TRANSMITTING DATA IN PARALLEL MODE (continued)
XI.6.4 - Long Frame
Figure 33
TRANSMITTED $7E
DATA
D0
D1
D2
D3
5
8
8
4
D0
D1
D2
D3
D0
D1
D2
5
8
8
x
D0
D1
D2
x
D0
D1
D2
5
8
8
D0
D1
D2
CRC
$7E
BUFF_FRAB
BUFF_SFRM
BUFF_EFRM
0
(BUFF_DATA)
0
75C53042.EPS
BUFF_LENG
XI.6.5 - Abort Frame
Figure 34
TRANSMITTED $7E
DATA
$7E
ABORT
D3
D4
D5
6
8
8
D3
D4
D5
BUFF_FRAB
BUFF_SFRM
BUFF_LENG
0
(BUFF_DATA)
0
75C53043.EPS
BUFF_EFRM
XI.6.6 - Abort Due to Underflow
Figure 35
TRANSMITTED $7E
DATA
ABORT
$7E
D3
D4
D5
6
8
8
D3
D4
D5
BUFF_FRAB
BUFF_SFRM
BUFF_LENG
(BUFF_DATA)
0
0
(1)
ERR_TX
(3)
(2)
Where : 1. The Underflow condition appears when the ST75C530/540 needs, inside a frame, some bytes to transmit and that the
corresponding buffer is empty.
2. The ERR_TX bit is cleared with a CSE 01 Command.
3. After an Underflow condition restart the initialization of the parallel mode and use the buffer number 0.
68/84
75C53044.EPS
BUFF_EFRM
ST75C530 - ST75C540
XI - TRANSMITTING DATA IN PARALLEL MODE (continued)
XI.6.7 - HDLC Special Timming
Figure 36
XMIT 0
XMIT 1
_NHFBF
DATA TRANSMITTED
_NHFCF
7E..7E 7E
Time to fill the Buffer 0
(Otherwise Extra
Flags Added)
DATA
Time
to fill the
Buffer 1
IT
Tx
STOP
IT
Tx
_NHFST
CRC 7E..7E 7E
Time
to fill the
Buffer 0
Time to fill the
Buffer 1(Otherwise
Extra Flags Added)
IT
Tx
A set of global variables allows the programmation
of the number of flags (7E) generated by the
ST75C530/540 :
- _NHFBF : Number of flags before the first frame.
- _NHFCF : Number of flags between frames.
- _NHFST : Number of flags after the last frame.
The default value for all these variables is 0, the
programming range is from 0 to 7FFF (32767).
These varaibales must be modified with a MW or
MWI command (see Figure 36).
XI.7 - UART Mode Description
In UART mode the ST75C530/540 transmits the
data Character contained into the DUAL Ram
buffe. The mechanism is as follows :
- While the Host has no character to transmit, that
i s: as lo n g a s DTTBSx equals $ 00, the
ST75C530/540 transmits continuous “1”.
- When the Host wants to send a chacarter,it feeds
the buffer with the character to transmit.
- The ST75C530/540 start to send a stop bit (“0”)
then the charactercontainedin the Buffer,computing the parity. It send the parity bit, if needed, and
the stop bits (1 or 2 according with the FORM
CRC 7E 7E..7E
DATA
Time
to fill the
Buffer 0
IT
Tx
75C53045.EPS
FORM 2
IT
Tx
command).
- If the user wants to send a break signal, he has
to set the BUFF_UBRK bit within the corresponding Status Word (DTTBSx). A break signal is
defined as a totaly null character with all stop bits
duration maintained to “0” (e.g: if format is 7 bit,
even parity and 2 stop bit, break is a ”0” durring
10 bit). Multiple continuous breaks (“0” continuous signal) can be send by using consecutive
buffers with BUFF_UBRK set to 1.
XI.7.1 - Status Word Format
DTTBSx in UART Mode
Field
Pos. Value
BUFF_LENG 3 .. 0
0
1
other
Definition
Buffer empty.
1 character to transmit
(DTTBFx[0]).
Not allowed.
BUFF_UBRK
6
0
1
Normal character.
Break signal : a complete
“0” character with all stop
bits equal to ”0”.
Other
7
0
Reserved, must be 0.
69/84
ST75C530 - ST75C540
XII - RECEIVING IN PARALLEL MODE
Figure 37
75C53046.EPS
DEMODULATED
SIGNAL
SAMPLE TIME
RECEIVE BIT
0
0
1
XII.1 - Description
When the STA_109 (CD) signal goes on, the
ST75C530/540 will write received data into the
DUAL RAM buffer DTRBS0 at first.
XII.1.1 - Initialization
The host processor must enable the IT3 receive
interrupt first.
Then it must empty the two DTRBS0 and DTRBS1
registers by writting $00 at these locations.
As soon as the first IT3 interrupt appears, the host
must proceed with the DTRBS0 buffer.
XII.1.2 - Loss of Carrier
Eac h t ime a lo ss of ca rrier ap pe ars the
ST75C530/540 stops updating the Data buffer. If
the carrier reappers the host must proceed again
with the initialisation sequence.
XII.1.3 - FSK Synchronization
The FSK Full Duplex demodulator uses an algorithm based on the transitions of the received signal. The synchronization mechanism is adjusted
with each signal transiton in order to sample the
demod ulated signal at the middle of the bit
(see Figure 37).
0
0
1
0
0
1
1
XII.3 - Host Flow Chart
Hereafter are flowcharts to :
- Establish a V.29 reception.
- Receive synchronous data. This task is performed under interrupt.
- Handle properly some temporary loss of carrier.
Figure 38
BEGIN
WRITE BIT IN
INTERNAL BUFFER
INTERNAL BUFFER
FULL
No
Yes
RETURN
SELECT NEXT DUAL
RAM BUFFER X
DTRBSx = 0
No
Yes
MOVE DATA FROM INTERNAL
BUFFER TO DTRBFx
SIGNAL ERROR
INTO ERR_Rx
RAISE IT0 INTERRUPT
70/84
WRITE DTRBSx
RAISE IT3 INTERRUPT
SELECT DUAL
RAM BUFFER x = 0
RETURN
RETURN
75C53047.EPS
XII.2 - Modem Flow Chart
When in parallel data mode, each time the
ST75C530/540 has receive some bit of data it
executes the following routine (see Figure 38).
Where x start with the value 0 and toggle between
1 and 0.
ST75C530 - ST75C540
XII - RECEIVING IN PARALLEL MODE (continued)
Establish the reception (see Figure 39).
Figure 39
CONF 0F 08 00 01
Subroutine :
Select V.29 9600bps
CLEAR FIRST BUFFER
SYNC1
Arm V.29 receiver
WRITE 00 INTO DTRBFS0
WRITE 00 INTO DTRBFS1
CLEAR FIRST BUFFER
FORM 00 (opt)
Clear the first
buffers #0 and #1
SELECT NEXT BUFFER
IBUF = 0
Format synchronous
ENABLE IT3
ITMASK = 0 x 88
STA_109 = 1
No
Wait until V.29
carrier detected
RET
Yes
No
In case of lost of carrier
while in data mode
75C53048.EPS
STA_109 = 0
Yes
XII.4 - Error Detection
Error occurs when the ST75C530/540 has received some bits and that the buffer DTRBSx is not
empty, this condition is called “Overflow”.
This error is signaled in the bit ERR_RX of the
SYSERR byte, and generates an interrupt IT0. To
clear the error a CSE 02 command must be issued.
An Overflow condition occurs when :
- In synchronous mode: the host processor “forgets” to empty the current DTRBSx buffer.
- In HDLC mode: when, while inside a frame, the
host processors “forgets” to empty the current
DTRBSx buffer.
- In UART mode, this cannot happen.
When an Overflow condition occurs the host must
restart the whole parallel initialisation.
Figure 40
EXECUTE_IT_RECEIVE
No
IBUF = 1
(1)
Yes
(1)
READ DTRBS1
EXTRACT BUFF_LENG
READ DTRBS0
EXTRACT BUFF_LENG
BUFF_LENG TIMES (2)
BUFF_LENGTIMES (2)
READ DTRBF1 DATA
READ DTRBF0 DATA
WRITE 00 INTO DTRBS1
WRITE 00 INTO DTRBS0
IBUF = 0
IBUF = 1
75C53049.EPS
These flowcharts show one CPU variable labeled
IBUF which is necessary for the understanding of
the mechanism, but there are different manners to
implement it.
- IBUF : thisis the number of the DUAL RAM buffer
currently in use by the Host processor. It starts wit
0 an then alternates 1, 0, 1, 0, ...
The received bits are read by an interrupt routine
(See Figure 40).
RETURN
Notes : 1. At that step the host can check that the corresponding
DTRBSx buffer is full (different from $00), otherwise it is
an error.
2. This means read BUFF_LENG bytes, inside the Receive
buffer DTRBFx starting from location DTRBFx[0] to
DTRBFx[BUFF_LENG - 1]. In synchronous mode, the
BUFF_LENG isalways 8 bytes, except when a STA_109
lost appears in the middle of the buffer.
71/84
ST75C530 - ST75C540
XII - RECEIVING IN PARALLEL MODE (continued)
XII.5 - Synchronous Mode
XII.5.1 - Description
In synchronous mode the ST75C530/540 writes
the received bit into the DUAL RAM Buffer without
any modification. It starts with the Bit 0 of the
DTRBF0[0] byte.
XII.5.2 - Status Word Format
ThereceiveStatus Byte DTRBS0 or DTRBS1 have
the same following meaning (See Table below).
The BUFF_LENG is always 8 except when a lost
of carrier (STA_109 going to 0) happens.
This status byte is set by the ST75C530/540, just
before generating the IT3 interrupt.
XII.6 - HDLC Mode
XII.6.1 - Description
In HDLC mode the ST75C530/540 extracts from
the received HDLC frame the Data information
only. It reports, trough the DUAL Ram buffer, only
data information and frame validity. The mechanism is as follows :
- As long as the ST75C530/540 receives continuous HDLC Flag $7E, nothing happens. Note that
the ST75C530/540 allows zero sharing between
adjacent flags.
- When the ST75C530/540 receives some data, it
removes inserted “zero” if needed, and starts to
compute the CRC. As soon as its internal buffer
is full, the ST75C530/540writes the receiveddata
i n t o t he DTRBFx b u f f er a nd se t s t h e
BUFF_SFRM inside the DTRBSx status byte.
- Wh e n r ec e iv in g ad d it ion a l d a t a, t h e
ST75C530/540 feeds the buffer just like in synchronous mode.
- When the ST75C530/540 receives a closing flag
(which can be shared with the following opening
flag) it compares the received CRC with its internal computation. It writes the contents of the
received last data into the DTRBFx buffer, sets
the BUFF_EFRM bit and reports any frame error
in the DTRBSx register via the BUFF_ERRS bits.
Reported errors are :
• CRC error (lowest priority): the received CRC
is not equal to the computed CRC. Some bits,
72/84
inside the frame, are erroneous.
• Non Byte-Aligned frame (middle priority): the
received data bit count (after deletion of the
“zero inserted”), between the opening and the
closing flag, is not a multiple of 8.
• Aborted frame (highest priority): the frame was
aborted with at least 7 consecutive “1”
- An abort frame can be also detected, while in the
inter frame mode, if instead of receiving $7E flag,
the ST75C530/540receive more than 7 consecutive “1”. In this case only one Aborted frame is
signaled, event if the ”1” condition is maintained.
DTRBSx in Synchronous Mode
Field
Pos. Value
Definition
Buffer empty.
BUFF_LENG 3 .. 0
0
1
1 Byte received
(DTRBFx[0]).
2
2 Bytes received
(DTRBFx[0] and
DTRBFx[1]).
..
..
8
8 Bytes received
(DTRBFx[0 .. 7]).
Other Not used.
Other
7 .. 4
0
Not used.
XII.6.2 - Status Word Format
DTRBSx in HDLC Mode
Field
Pos. Value
Definition
BUFF_LENG 3 .. 0
0
Buffer empty.
1
1 Byte received
(DTRBFx[0]).
2
2 Bytes received
(DTRBFx[0] and
DTRBFx[1]).
..
..
8
8 Bytes received
(DTRBFx[0 .. 7]).
other Not allowed.
BUFF_ERRS 5 .. 4 0 0
No error.
01
CRC error.
10
Non Byte-Aligned frame.
11
Aborted frame.
BUFF_SFRM
6
0
Data stream.
1
Start of frame : the buffer
is a beginning of frame.
BUFF_EFRM
7
0
Data stream.
1
End of frame : the buffer
is a closing frame.
ST75C530 - ST75C540
XII - RECEIVING IN PARALLEL MODE (continued)
XII.6.3 - Single Short frame
Figure 41
RECEIVED
DATA
$7E
D0
CRC $7E D1 CRC
$7E
D2
CRC $7E D3 CRC $7E
BUFF_ERRS
BUFF_SFRM
BUFF_EFRM
0
6
(BUFF_DATA)
0
2
D0
0
8
D1
75C53050.EPS
BUFF_LENG
D2
XII.6.4 - Long Frame
Figure 42
RECEIVED
DATA
$7E
D0
D1
D2
D3 CRC
$7E
(1)
BUFF_ERRS
BUFF_SFRM
BUFF_EFRM
(BUFF_DATA)
8
8
D0
D1
5
8
D2
0
75C53051.EPS
0
BUFF_LENG
D3
Note : 1. If error occurs during the reception, it is signaled in this last buffer.
XII.6.5 - Aborted Frame
Figure 43
RECEIVED
DATA
$7E
D0
D1
D2 ABORT
BUFF_ERRS
$7E
D4
D3
D5
11
BUFF_SFRM
BUFF_EFRM
(BUFF_DATA )
8
8
x
D0
D1
x
0
8
75C53052.EPS
BUFF_LENG
D3
73/84
ST75C530 - ST75C540
XII - RECEIVING IN PARALLEL MODE (continued)
XII.7 - UART Mode
XII.7.1 - Description
In UART mode the ST75C530/540extracts from the
received Characters the Data information only. It reports, troughthe DUAL Ram buffer,onlydatainformation charactervalidity. The mechanism is as follows :
- As long as the ST75C530/540 receives continuous “1” nothing happens.
- When the ST75C530/540 receives the start bit
(“0”) it starts to compute the parity. As soon as the
number of data bit (defined by the FORM command) is received, the ST75C530/540writes the
received character into the DTRBFx buffer and
update the receive Status word DTRBSx.
- The Reported errors are :
• Parity error (lowest priority): the receivedparity
is not equal to the computed parity. Some bits,
inside the character, are erroneous.
• Stop bit error (middle priority): the bit after the
parity was not a stop bit (“1”). Note that if the
two stop bit format was selected, only the first
stop bit will be checked.
• Break Detection (highest priority): the characteris
a breaksignal as definedin the transmit section.If
the duration of the break is longerthan one character, only one break bufferwill be reported.
XI.7.2 - Status Word Format
DTRBSx in UART Mode
Field
Pos.
Value
Definition
BUFF_LENG
3 .. 0
0
1
Other
Buffer empty.
1 character received
(DTRBFx[0]).
Not allowed.
00
01
10
11
No error.
Parity error
Stop bit error
Break signal detected
BUFF_ERRS
5..4
XIII - VOCODER DATA EXCHANGE
XIII.1 - Overview
The ST75C530/540 can receive (or transmit)
coded voice from (to) the telephone line or the
audio interface. The receiving mode is the CODER
mode while the transmit is the DECODER mode.
Two formats of Voice compression are provided: Low
bit rate and ADPCM. In all the formats and speed the
managementof the CodedVoice is exactly the same.
In any format a frame of all data equal to zero will
be synthesised (DECODER) as a frame of silence.
XIII.2 - Vocoder Buffer
A buffer area is reserved in the DUAL ram to
exchange Voice between the ST75C530/540 and
74/84
the Host processor. Thisareaisusedeitherforrecording (CODER) or playing back (DECODER) the voice
signal.
The DUAL Ram area associated with the VOCODER is as follows :
Name
VOCSTA
VOCDATA
VOCCORR
Address
$1C
$1D..$2E
$2F..$30
Description
Vocoder Buffer Status
Vocoder Buffer Data
Vocoder Buffer Corrector
The IT1 interrupt signalis dedicatedto the Vocoder
Buffer Management.
XIII.3 - Transmit (DECODER)
This mode is entered with the CONF DECODER
command.
If the ADPCM or Low bit rate without error correction mode (CONF_ERCOR = 0) are selected, the
user needs to feed the vocoder buffer with 18 bytes
of voice data, then set the VOCSTA byte with a
value different from zero.
In the low bit rate with error mode (CONF_ERCOR
= 1), the user needsto feed the vocoder buffer with
20 bytes of voice data, then set the VOCSTA byte
with a value different from zero.
Once the ST75C530/540 have read the buffer, it
clears the VOCSTAbyte and raise the IT1 interrupt.
The IT1 interrupt rate is as follows :
Mode
Interrupt
Time (ms)
Number of
Voice Samples
in the Buffer
(8kHz sampling)
ADPCM 32Kpbs
4.5
36
ADPCM 24Kpbs
6
48
ADPCM 16Kpbs
9
72
Low Bit Rate Nominal
(with and without
error correction)
30
240
Low Bit Rate
Depends on
Depends on
Fast/Slow Playback speed 15 to 45 speed 120 to 360
Low Bit Rate Pause
0
-
A silence can be generatedby writing zero to all the
VOCDATA bytes (an d VOCCORR b ytes if
CONF_ERCOR = 1). The duration of the silence
will be the same as the other frames of signal.
As the buffer contains always a complete number
of samples representing the same duration, it is
easy to randomly advance forward/backward in a
message.
If the user does not feed the Buffer within the
Interrupt time, the ST75C530/540 will signal this
error by rising the ERR_VOCO in theSYSERRbyte
and rising the IT0 Interrupt. In this case the previous frame will be re-transmited.
ST75C530 - ST75C540
XIII - VOCODER DATA EXCHANGE (continued)
XIII.4 - Receive (CODER)
This function can be entered either by :
- The CONF CODER Command.This corresponds
to the “Normal Answering Machine” function.
- The MODC Command with MODC_COD = 1, in
the HANDSET Mode. This corresponds, in the
HANDSET mode to the “Conversation Recording” function. This reduced sub-mode does not
allow ADPCM format and does not perform VAD
(Voice Activity Detector).
Once this function is selected, the ST75C530/540
starts to code the voice signal, writes one frame of
compressed voice into the VOCDATA bytes (if the
low bit rate mode is selected, computes always the
Corrector bytes and writes them in the VOCCORR
bytes)then writes the VOCSTAbyte and generates
the IT1 interrupt.
The IT1 interrupt rate is as follows :
Mode
ADPCM 32Kpbs
ADPCM 24Kpbs
ADPCM 16Kpbs
Low Bit Rate (with and
without error correction)
Interrupt
Time
(ms)
4.5
6
9
30
Number of Voice
Samples
in the Buffer
(8kHz sampling)
36
48
72
240
Note that the VOCCORR are always computed,
whatever the value of CONF_ERCOR.
The format of the VOCSTA byte is as follows :
Format
Low Bit
Rate
ADPCM
Field
VOC
_VAD
VOC
_NUM
VOC
_VAD
VOC
_NUM
VOCSTAT
Pos. Value
Definition
7
0
VAD Unvoiced Signal.
1
VAD Voice Signal.
4..0 10100 (20 decimal) Number
of VOCDATA Bytes
7
0
VAD Unvoiced Signal.
1
VAD Voice Signal.
4..0 10010 (18 decimal) Number
of VOCDATA Bytes
Note that in “Conversation recording” the VOCSTA
byte is always $14.
The user must read the VOCDATA (and optionally
the VOCCORR) bytes and clear the VOCSTA byte
(writing $00).
If the user does not clear the VOCSTA byte within
the interrupt time, the ST75C530/540 will signal
this error by rising the ERR_VOCO in the SYSERR
byte and rising the IT0 Interrupt. In this case the
current frame is lost.
If the CONF_SUPSIL bit is 1 in the CONF CODER
command, the interrupts IT1 appears only when
the VAD has detected a voiced signal.
75/84
ST75C530 - ST75C540
XIV - TRANSPARENT MODE DATA EXCHANGE
The mode uses the DPR locations to exchange
samples between the host and the AFE’s. To allow
maximum interrupt latency, the DSP uses internal
buffers to store samples and updates the DPR
buffers when internal buffers are ready. The DPR
buffers are bidirectional, thus doubling the effective
DPR capacity.
The transfer mechanism is depicted below :
1. At baud rate (every 4 samples at 9.6kHz), the
DSP transfers 4 samples from the Modem AFE
to the internal receive buffer, after sending them
through a high-passfilter with a transferfunction
H(z) = (z-1)/ (z-0.875) used to remove all DC
components from the signal, and transfers
4 samplesfrom the Internal transmit bufferto the
Modem AFE. This comes from the currently
implemented internal scheduling. The same
operation is performed for the voice AFE.
2. After 3 bauds, the internal receive buffer is full
(the internal transmit buffer is also empty), the
DPR buffer is copied to the internal transmit
buffer, then the internal receive buffer is copied
into the DPR.
3. A host interrupt is generated : during servicing,
the host reads the DPR sample buffer then
writes it with new transmitted samples.
XIV.1 - Sample buffers
The mode uses the DPR locations to exchange
samples between the host and the AFE’s ; since no
data transfer (HDLC, UART) occurs in this mode,
76/84
the full 0x10 .. 0x3F DPR locations are available.
The Modem sample buffer (MODEMDPR) uses
locations 0x10 to 0x27 (24 bytes) to exchange
12 MAFE samples. The audio sample buffer
(AUDIODPR) uses locations 0x28 to 0x3F to exchange 12 VAFE samples. Samples are represented in 16-bit linear data format, byte order is
little-Endian(Intel-like, LSByteat low address),and
consecutive locations correspond to consecutive
samples in time. Example : locations (0x10, 0x11)
correspond to the first sample (LSB, MSB) received from the line AFE.
XIV.2 - Interrupts
The DSP signal events to the host using the interrupt mailbox (ITREST[0..6], ITMASK, ITSRCR).
IT2 is set by the DSP whenever the DPR buffers
are ready. This interrupt source can be masked
through ITMASK, and acknowledged using
ITSRCR[0..6]. The host interrupt service routine
should read received samples from the DPR, write
transmitted samples to the DPR, then acknowledge by clearing the IT2 flag. The interrupt latency
is approximately equal to the interrupt period, i.e.
T = 1/800 = 1.25ms. Overrun and underrun conditions may occur if the host interrupt latency exceeds the previous value. Since this situation is
unrecoverable, no specific action is taken. Nevertheless, for debug purposes the user can detect
this condition by probing the interrupt line (SINTR),
and trigger on a pulse width greater than the maximum allowed latency.
ST75C530 - ST75C540
XV - DEFAULT CALL PROGRESS TONE DETECTORS
Figure 44 : Call Progress Tone Detector Band 1
dB
0
no detection
detection
-10
dB
no detection
detection
-8
step = 10Hz
reference level = 0dB
-20
-16
-24
-40
-32
f (Hz)
-50
0
200
400
600
800
1000
75C53053.EPS
-30
step = 100Hz
reference level = 0dB
f (Hz)
-40
0
720
1440
2160
2880
3600
75C53054.EPS
0
Figure 45 : Call Progress Tone Detector Band 2
XVI - DEFAULT ANSWER TONE DETECTORS
Figure 46 : 2100Hz Answer Tone Detector
dB
0
step = 10Hz
reference level = 0dB
-10
-10
-20
-20
-30
-30
-50
2000
2040
2080
no detection
detection
step = 10Hz
reference level = 0dB
-40
no detection
detection
f (Hz)
2120
2160
2200
75C53055.EPS
-40
dB
f (Hz)
-50
200
320
440
560
680
800
77/84
75C53056.EPS
0
Figure 47 : 440Hz Tone Detector
75C53057.EPS
RxA
MIC3
MIC2
MIC1
0VA
V CM
R4 1.2kΩ
R3 1.2kΩ
R2 1.2kΩ
R1 1.2kΩ
C20 (1)
2.2nF
C19 (1)
2.2nF
C18 (1)
2.2nF
C17 (1)
2.2nF
C9 (1)
100nF
C7 (1)
100nF
C4
2.2µF
C8
4.7µF
C5 (1)
100nF
C6
2.2µF
C2
2.2µF
C10 (1)
100nF
C16 (1)
100nF
VCC
C11
4.7µF
MIC1
MIC2
8
9
20 DGND1
19 DVDD6
18 DGND6
17 EYEY
16 EYEX
15 TxA1
14 TxA2
13 AGNDM
12 AVDDM
11 RxA
10 MIC3
AGNDRA
VCM
6
7
VREFP
VREFN
4
5
AGNDTA
3
ST75C530
ST75C540
EXTALL
GIO15
GIO16
SA1
GIO17
SA0
TEST0
SD5
RESET
SD4
SPK3N
SD3
SPK3P
SD2
SPK2N
SD1
SPK2P
SD0
AVDDA
DVDD1
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
SD6
SPK1P
XTALL
SD7
SPK1N
DV DD5
DGND2
2
XPLL
SR/W
1
GIO14
SA2
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DGND5
DD2
DV
C3 (1)
100nF
CLKOUT
SDS
C1
2.2µF
GIO13
SA3
+5VA
GIO12
SA4
AGNDM
GIO11
SA5
78/84
SA6
AGNDRA
C14 (1)
100nF
SCS 41
SINTR 42
INT/MOT 43
RGND 44
RELAY0 45
RELAY1 46
RING 47
GIO00 48
GIO01 49
DGND3 50
DVDD3 51
GIO02 52
GIO03 53
GIO04 54
GIO05 55
GIO06 56
GIO07 57
DGND4 58
DVDD4 59
GIO10 60
C12 (1)
100nF
VCC
C13 (1)
100nF
C15
10µF
ST75C530 - ST75C540
XVII - ELECTRICAL SCHEMATICS
Figure 48
ST75C530 - ST75C540
XVIII - PCB DESIGN GUIDELINES
Performances of the FAX modem depends on the
ST75C530/540 intrinsic performances and on the
proper PC board layout.
All aspects of the proper engineering practices, for
PC board design, are beyond the scope of this
paragraph.
We recommend the following points :
- in a 4-layer PC board : Separated digital ground
and analog ground, connected together at one
point, as close as possible to the ST75C530/540,
- in a 2-layer PC board : Provide a ground grid in all
spacearoundandundercomponentsonbothsides
of the band and connect to avoid small islands,
- both AGNDR and AGNDT must be connected
with very low impedance to a single point, (see
Chapter I.6, Power Supply),
- the four 2.2nF capacitors connected to the RxA
and MIC1, MIC2, MIC3 Pins must be as close as
possible to them,
- thetwo100nFcapacitorsconnectedtotheVREFP and
VREFN pins must be as close as possible to them,
- analog and digital supplies must be connected
together,at a single point, as close as possibleto
the chip.
XIX - APPENDIX A : MODES OF OPERATION
Figure 49 : Tone Mode (TONE)
TxA1
ATT_TX
15
4 TONES
GENERATOR
DAC
MUTE
Line
TxA2
11
16 TONE
DETECTORS
DUAL
RAM
INTERFACE
HYBRID
14
DTMF
DETECTOR
DG
ADC
4 TONE
DETECTORS
ATT_LOC
V.21 FLAG
DETECTOR
RxA
MUTE
[0..-30]dB
Step 3dB
ATT_SPK
1
2
SPK1
76
DAC
RING
DETECTOR
MUTE
SPK3
77
78
MUTE
79
9
Addition
of Signals
Automatic
Gain
DG
MIC2
8
75C53058.EPS
Programmable
Attenuation
ADC
SPK2
MIC1
10 MIC3
Figure 50 : Tone Mode with Caller ID (TONECID)
TxA1
ATT_TX
4 TONES
GENERATOR
15
DAC
MUTE
11
DG
ADC
4 TONE
DETECTORS
ATT_LOC
V.21 FLAG
DETECTOR
UART
Line
TxA2
6 TONE
DETECTORS
DUAL
RAM
INTERFACE
HYBRID
14
DTMF
DETECTOR
RxA
MUTE
[0..-30]dB
Step 3dB
ATT_SPK
V.23
DEMODULATOR
1
2
SPK1
76
DAC
MUTE
SPK3
77
78
MUTE
79
9
Programmable
Attenuation
Addition
of Signals
DG
Automatic
Gain
ADC
8
SPK2
MIC2
75C53059.EPS
RING
DETECTOR
MIC1
10 MIC3
79/84
ST75C530 - ST75C540
XIX - APPENDIX A : MODES OF OPERATION (continued)
Figure 51 : Fax Modem Mode (MODEM)
TxA1
ATT_TX
HDLC
Tx
15
FAX
TRANSMITTER
DAC
MUTE
14
HYBRID
Line
HYBRID
Line
TxA2
DUAL
RAM
INTERFACE
SD[0..7]
HANDSHAKE
AND STATUS
REPORT
HDLC
Rx
11
DG
ADC
RxA
FAX
RECEIVER
MUTE
[0..-30]dB
Step 3dB
4 TONE
DETECTORS
SINTR 42
1
2
SPK1
76
DAC
V.21 FLAG
DETECTOR
MUTE
SPK3
77
ATT_LOC
78
MUTE
79
9
Programmable
Attenuation
Addition
of Signals
DG
ADC
Automatic
Gain
8
SPK2
MIC2
75C53060.EPS
DTMF
DETECTOR
(V.21ch2 only)
MIC1
10 MIC3
Figure 52 : Data Modem Mode (Full Duplex Modem) (ST75C540 only)
UART
HDLC
Tx
TxA1
ATT_TX
MODEM
TRANSMITTER
15
DAC
MUTE
14
TxA2
DUAL
RAM
INTERFACE
SD[0..7]
HANDSHAKE
AND STATUS
REPORT
UART
HDLC
Rx
ECHO
CANCELLER
11
ADC
RxA
MUTE
[0..-30]dB
Step 3dB
MODEM
RECEIVER
SINTR 42
1
2
SPK1
76
DAC
MUTE
SPK3
77
ATT_LOC
78
MUTE
9
Programmable
Attenuation
80/84
Addition
of Signals
DG
Automatic
Gain
ADC
8
SPK2
MIC2
MIC1
10 MIC3
75C53061.EPS
79
ST75C530 - ST75C540
XIX - APPENDIX A : MODES OF OPERATION (continued)
Figure 53 : Decoder Mode (DECODER)
TxA1
ATT_TX
15
DAC
DECODER
MUTE
14
4 TONE
GENERATORS
HYBRID
Line
HYBRID
Line
TxA2
LINE ECHO
CANCELLER
11
ADC
4 TONE
DETECTORS
DUAL
RAM
INTERFACE
RxA
DG
MUTE
[0..-30]dB
Step 3dB
ATT_LOC
DTMF
DETECTOR
RING
DETECTOR
1
2
SPK1
76
DAC
MUTE
SPK3
77
78
MUTE
9
Programmable
Attenuation
Addition
of Signals
ADC
Automatic
Gain
DG
8
SPK2
MIC2
75C53062.EPS
79
MIC1
10 MIC3
Figure 54 : Coder Mode (CODER)
TxA1
4 TONE
GENERATORS
CODER
15
DAC
MUTE
14
AGC
TxA2
ATT_SEL
11
VOICE
ACTIVITY
DETECTOR
DUAL
RAM
INTERFACE
DTMF
DETECTOR
ADC
RxA
MUTE
[0..-30]dB
Step 3dB
DG
4 TONE
DETECTORS
1
2
SPK1
76
DAC
RING
DETECTOR
MUTE
SPK3
77
ATT_LOC
78
MUTE
9
Programmable
Attenuation
Addition
of Signals
DG
Automatic
Gain
ADC
ATT_MIC
8
SPK2
MIC2
75C53063.EPS
79
MIC1
10 MIC3
81/84
ST75C530 - ST75C540
XIX - APPENDIX A : MODES OF OPERATION (continued)
Figure 55 : Room Monitoring Mode (ROOM)
TxA1
15
DAC
MUTE
14
ATT_TX
HYBRID
Line
HYBRID
Line
TxA2
LINE ECHO
CANCELLER
11
ADC
DUAL
RAM
INTERFACE
DTMF
DETECTOR
RxA
DG
MUTE
[0..-30]dB
Step 3dB
4 TONE
DETECTORS
1
2
SPK1
76
DAC
Programmable
Attenuation
MUTE
Addition
of Signals
SPK3
77
78
MUTE
Automatic
Gain
79
9
ADC
AGC
8
ATT_MIC
SPK2
MIC2
75C53064.EPS
DG
MIC1
10 MIC3
Figure 56 : Telephone Mode (HANDSET)
4 TONE *
GENERATOR
TxA1
ATT_TX
15
DAC
MUTE
14
TxA2
11
ADC
DUAL
RAM
INTERFACE
RxA
CODER
MUTE
[0..-30]dB
Step 3dB
AGC
1
2
SPK1
76
* default is 2.
RING
DETECTOR
DG
SPK3
77
78
MUTE
79
9
ADC
ATT_MIC
82/84
MUTE
8
SPK2
MIC2
MIC1
10 MIC3
75C53065.EPS
4 TONE *
DETECTORS
HALF/FULL DUPLEX
SPEAKER-PHONE
ALGORITHMS
DAC
AGC
ST75C530 - ST75C540
XIX - APPENDIX A : MODES OF OPERATION (continued)
Figure 57 : TransparentMode
ATT_MODTX
ATT_TX
ATT_MODRX
TxA1
15
4 TONE
GENERATORS
DAC
MUTE
HYBRID
14
Line
DUAL RAM
INTERFACE
TxA2
DTMF
DETECTOR
11
DC- (*)
BLOCK
DG
ADC
6 PRIMARY
TONE
DETECTORS
4 SECONDARY
TONE
DETECTORS
RxA
MUTE
[0..-30]dB
Step 3dB
ATT_SEL
1
2
SPK1
76
MUTE
ATT_LOC
SPK3
77
78
ATT_AUDTX
79
ATT_SPK
ATT_AUDRX
(*)
H(z) =
Addition
of Signals
9
ATT_MIC
DC- (*)
BLOCKA
Programmable
Attenuation
MUTE
DG
Automatic
Gain
ADC
8
SPK2
MIC2
MIC1
10 MIC3
75C53066.EPS
DAC
z-1
z - 0.875
83/84
ST75C530 - ST75C540
XX - PACKAGE MECHANICAL DATA
80 PINS - FULL THIN PLASTIC QUAD FLAT PACK (TQFP)
A
A2
e
80
A1
61
0,10 mm
.004 inch
60
20
41
SEATING PLANE
E3
E1
E
B
1
c
Dimensions
A
A1
A2
B
C
D
D1
D3
e
E
E1
E3
L
L1
K
Min.
0.05
1.35
0.22
0.09
0.45
Millimeters
Typ.
1.40
0.32
16.00
14.00
12.35
0.65
16.00
14.00
12.35
0.60
1.00
Max.
1.60
0.15
1.45
0.38
0.20
0.75
PM-1S.EPS
K
0,25 mm
.010 inch
GAGE PLANE
Min.
0.002
0.053
0.010
0.004
0.020
Inches
Typ.
0.055
0.012
0.630
0.551
0.486
0.026
0.630
0.551
0.486
0.024
0.039
Max.
0.063
0.006
0.057
0.014
0.008
0.030
0o (Min.), 7o (Max.)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical comp onents in lifesupport devicesor systems
without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
 1999 STMicroelectronics - All Rights Reserved
2
2
Purchase of I C Components of STMicroelectronics, conveys a license under the Philips I C Patent.
2
Rights to use these components in a I C system, is granted provided that the system conforms to
2
the I C Standard Specifications as defined by Philips.
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84/84
1S.TBL
40
L1
D3
D1
D
L
21