STP12NK30Z N-CHANNEL 300V - 0.36Ω - 9A - TO-220 Zener-Protected SuperMESH™Power MOSFET TYPE STP12NK30Z ■ ■ ■ ■ ■ ■ ■ VDSS RDS(on) ID (1) Pw (1) 300 V < 0.4 Ω 9A 90 W TYPICAL RDS(on) = 0.36 Ω EXTREMELY HIGH dv/dt CAPABILITY IMPROVED ESD CAPABILITY 100% AVALANCHE RATED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY DESCRIPTION The SuperMESH™ series is obtained through an extreme optimization of ST’s well established stripbased PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. 3 1 2 TO-220 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS LIGHTING ■ IDEAL FOR OFF-LINE POWER SUPPLIES, ADAPTORS AND PFC ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ ORDERING INFORMATION SALES TYPE MARKING PACKAGE PACKAGING STP12NK30Z P12NK30Z TO-220 TUBE December 2002 1/8 STP12NK30Z ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID IDM (1) PTOT VESD(G-S) dv/dt (2) Tstg Tj Parameter Value Unit Drain-source Voltage (VGS = 0) 300 V Drain-gate Voltage (RGS = 20 kΩ) 300 V Gate- source Voltage ± 30 V Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C 9 5.6 A A Drain Current (pulsed) 36 A Total Dissipation at TC = 25°C 90 W Derating Factor 0.72 W/°C Gate source ESD(HBM-C=100pF, R=1.5KΩ) 3000 V/ns 4.5 V/ns –55 to 150 °C Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature THERMAL DATA Rthj-case Thermal Resistance Junction-case Max 1.38 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W 300 °C Tl Maximum Lead Temperature For Soldering Purpose Note: 1. Pulse width limited by safe operating area 2. ISD< 9A, di/dt<300A/µs, VDD<V(BR)DSS, TJ<TJMAX AVALANCHE CHARACTERISTICS Symbol Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) Max Value Unit 9 A 155 mJ GATE-SOURCE ZENER DIODE Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs=± 1mA (Open Drain) Min. 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 2/8 STP12NK30Z ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol Parameter Test Conditions Min. Typ. Max. Drain-source Breakdown Voltage ID = 1 mA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C 1 50 µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20V ±10 µA VGS(th) Gate Threshold Voltage VDS = VGS, ID = 50µA RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 4.5 A V(BR)DSS 300 Unit 3 V 3.75 4.5 V 0.36 0.4 Ω Typ. Max. Unit DYNAMIC Symbol gfs (1) Ciss Coss Crss Coss eq. (3) RG Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions Min. VDS = 10 V, ID = 4.5 A VDS = 25V, f = 1 MHz, VGS = 0 5.4 S 670 125 28 pF pF pF Equivalent Output Capacitance VGS = 0V, VDS = 0V to 440 V 70 pF Gate Input Resistance f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain 3.6 Ω SWITCHING Symbol Parameter Test Conditions td(on) tr td(off) tf Turn-on Delay Time Rise time Turn-off Delay Time Fall Time VDD = 150 V, ID = 4.5 A RG = 4.7Ω VGS = 10 V (Resistive Load see, Figure 3) Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 240V, ID = 9 A, VGS = 10V Min. Typ. Max. 16 20 36 10 Unit ns ns ns ns 25 5.5 13.4 35 nC nC nC Typ. Max. Unit 9 36 A A 1.6 V SOURCE DRAIN DIODE Symbol Parameter Test Conditions ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 9 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 9 A, di/dt = 100A/µs VDD = 40V, Tj = 150°C (see test circuit, Figure 5) trr Qrr IRRM Min. 165 0.9 11.2 ns µC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 3/8 STP12NK30Z Safe Operating Area For TO-220 Thermal Impedance For TO-220 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance 4/8 STP12NK30Z Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized BVDSS vs Temperature 5/8 STP12NK30Z Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STP12NK30Z TO-220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 D1 0.107 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 L2 16.4 0.645 13.0 14.0 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 D1 C D A E L4 H2 G G1 F1 L2 F2 F Dia. L5 L9 L7 L6 L4 P011C 7/8 STP12NK30Z Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 8/8