STW52NK25Z N-CHANNEL 250V - 0.033Ω - 52A TO-247 Zener-Protected SuperMESH™ MOSFET Figure 1: Package Table 1: General Features TYPE VDSS RDS(on) ID Pw STW52NK25Z 250 V < 0.045 Ω 52 A 300 W ■ ■ ■ ■ ■ ■ TYPICAL RDS(on) = 0.033 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY DESCRIPTION The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. 3 2 1 TO-247 Figure 2: Internal Schematic Diagram APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING DC CHOPPERs ■ IDEAL FOR OFF-LINE POWER SUPPLIES, ADAPTORS AND PFC Table 2: Order Codes SALES TYPE MARKING PACKAGE PACKAGING STW52NK25Z W52NK25Z TO-247 TUBE Rev. 2 November 2004 1/10 STW52NK25Z Table 3: Absolute Maximum ratings Symbol VDS VDGR VGS Parameter Drain-source Voltage (VGS = 0) Value Unit 250 V Drain-gate Voltage (RGS = 20 kΩ) 250 V Gate- source Voltage ± 30 V ID Drain Current (continuous) at TC = 25°C 52 A ID Drain Current (continuous) at TC = 100°C 32.76 A 208 A IDM () PTOT VESD(G-S) dv/dt (1) Tj Tstg Drain Current (pulsed) Total Dissipation at TC = 25°C 300 W Derating Factor 2.38 W/°C Gate source ESD(HBM-C=100pF, R=1.5KΩ) 6000 V Peak Diode Recovery voltage slope Operating Junction Temperature Storage Temperature 4.5 V/ns -55 to 150 °C () Pulse width limited by safe operating area (1) ISD ≤52A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. Table 4: Thermal Data Rthj-case Thermal Resistance Junction-case Max 0.42 °C/W Rthj-amb Tl Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 30 300 °C/W °C Max Value Unit Table 5: Avalanche Characteristics Symbol Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 52 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 500 mJ Table 6: GATE-SOURCE ZENER DIODE Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs=± 1mA (Open Drain) Min. 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 2/10 STW52NK25Z ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 7: On/Off Symbol Parameter Test Conditions Min. Typ. Max. 250 Unit Drain-source Breakdown Voltage ID = 1 mA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C 1 50 µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20V ±10 µA VGS(th) Gate Threshold Voltage VDS = VGS, ID = 150 µA 3.75 4.5 V RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 26 A 0.033 0.045 Ω Typ. Max. Unit V(BR)DSS 3 V Table 8: Dynamic Symbol gfs (1) Ciss Coss Crss Coss eq. (3) Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions Min. VDS = 15 V, ID = 26 A VDS = 25V, f = 1 MHz, VGS = 0 25 S 4850 855 222 pF pF pF Equivalent Output Capacitance VGS = 0V, VDS = 0V to 200 V 720 pF td(on) tr td(off) tf Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time VDD = 125V, ID = 26 A RG = 4.7Ω VGS = 10 V (see Figure 17) 40 75 115 55 ns ns ns ns Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 200 V, ID = 52 A, VGS = 10V 160 32 87 nC nC nC Table 9: Source Drain Diode Symbol Parameter ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 52 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 52 A, di/dt = 100A/µs VDD = 100 V, Tj = 25°C (see Figure 18) 285 0.285 2 ns µC A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 52 A, di/dt = 100A/µs VDD = 100 V, Tj = 150°C (see Figure 18) 336 0.37 2.2 ns µC A trr Qrr IRRM trr Qrr IRRM Test Conditions Min. Typ. Max. Unit 52 208 A A 1.6 V Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 3/10 STW52NK25Z Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics Figure 5: Transconductance Figure 8: Static Drain-source On Resistance 4/10 STW52NK25Z Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized On Resistance vs Temperature Figure 11: Source-Drain Diode Forward Characteristics Figure 14: Normalized BVdss vs Temperature 5/10 STW52NK25Z Figure 15: Avalanche Energy vs Starting Tj 6/10 STW52NK25Z Figure 16: Unclamped Inductive Load Test Circuit Figure 19: Unclamped Inductive Wafeform Figure 17: Switching Times Test Circuit For Resistive Load Figure 20: Gate Charge Test Circuit Figure 18: Test Circuit For Inductive Load Switching and Diode Recovery Times 7/10 STW52NK25Z TO-247 MECHANICAL DATA DIM. mm. MIN. MAX. MIN. A 4.85 5.15 0.19 0.20 A1 2.20 2.60 0.086 0.102 b 1.0 1.40 0.039 0.055 b1 2.0 2.40 0.079 0.094 TYP. MAX. b2 3.0 3.40 0.118 0.134 c 0.40 0.80 0.015 0.03 D 19.85 20.15 0.781 0.793 E 15.45 15.75 0.608 e 5.45 0.620 0.214 L 14.20 14.80 0.560 0.582 L1 3.70 4.30 0.14 0.17 L2 18.50 0.728 øP 3.55 3.65 0.140 0.143 øR 4.50 5.50 0.177 0.216 S 8/10 TYP inch 5.50 0.216 STW52NK25Z Table 10: Revision History Date Revision 29-Oct-2004 22-Nov-2004 1 2 Description of Changes First Relase Final datasheet 9/10 STW52NK25Z Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 10/10