STY60NM60 N-CHANNEL 600V - 0.050Ω - 60A Max247 Zener-Protected MDmesh™Power MOSFET TYPE STY60NM60 VDSS RDS(on) ID 600V < 0.055Ω 60 A TYPICAL RDS(on) = 0.050Ω HIGH dv/dt AND AVALANCHE CAPABILITIES IMPROVED ESD CAPABILITY LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL INDUSTRY’S LOWEST ON-RESISTANCE DESCRIPTION The MDmesh™ is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company’s proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition’s products. 2 3 1 Max247 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS The MDmesh™ family is very suitable for increasing power density of high voltage converters allowing system miniaturization and higher efficiencies. ORDERING INFORMATION SALES TYPE MARKING PACKAGE PACKAGING STY60NM60 Y60NM60 Max247 TUBE July 2003 1/8 STY60NM60 ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS Parameter Value Unit Drain-source Voltage (VGS = 0) 600 V Drain-gate Voltage (RGS = 20 kΩ) 600 V Gate- source Voltage ±30 V ID Drain Current (continuous) at TC = 25°C 60 A ID Drain Current (continuous) at TC = 100°C 37.8 A Drain Current (pulsed) 240 A Total Dissipation at TC = 25°C 560 W 6 KV 4.5 W/°C IDM () PTOT VESD(G-S) Gate source ESD(HBM-C=100pF, R=15KΩ) Derating Factor dv/dt (1) Tstg Tj Peak Diode Recovery voltage slope Storage Temperature 15 V/ns –65 to 150 °C 150 °C Max. Operating Junction Temperature (•)Pulse width limited by safe operating area (1) ISD ≤60A, di/dt ≤400 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. THERMAL DATA Rthj-case Thermal Resistance Junction-case Max Rthj-amb Thermal Resistance Junction-ambient Max Tl 0.22 °C/W Maximum Lead Temperature For Soldering Purpose 30 °C/W 300 °C AVALANCHE CHARACTERISTICS Symbol Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Parameter 30 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 35 V) 1.4 J GATE-SOURCE ZENER DIODE Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs=± 1mA (Open Drain) Min. 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 2/8 STY60NM60 ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol Parameter Test Conditions Min. Typ. Max. Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 10 µA VDS = Max Rating, TC = 125°C 100 µA Gate-body Leakage Current (VDS = 0) VGS = ± 20V ±10 µA VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 4 5 V RDS(on) Static Drain-source On Resistance VGS = 10 V, ID = 30 A 0.050 0.055 Ω Typ. Max. Unit V(BR)DSS IDSS IGSS 600 Unit 3 V DYNAMIC Symbol gfs (1) Ciss Coss Crss RG Parameter Test Conditions Forward Transconductance VDS = ID(on) x RDS(on)max, ID = 30 A Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25 V, f = 1 MHz, VGS = 0 Gate Input Resistance f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain Min. 35 S 7300 2000 40 pF pF pF 1.8 Ω SWITCHING ON Symbol Parameter Test Conditions td(on) tr Turn-on Delay Time Rise Time VDD = 300 V, ID = 30 A RG = 4.7Ω VGS = 10 V (see test circuit, Figure 3) Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 470 V, ID = 60 A, VGS = 10 V Min. Typ. Max. 55 95 Unit ns ns 178 44.5 95 266 nC nC nC Typ. Max. Unit SWITCHING OFF Symbol tr(Voff) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Conditions Min. VDD = 400 V, ID = 60 A, RG = 4.7Ω, VGS = 10 V (see test circuit, Figure 5) 130 76 105 ns ns ns SOURCE DRAIN DIODE Symbol Parameter ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 60 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 60 A, di/dt = 100 A/µs, VDD = 30 V, Tj = 150°C (see test circuit, Figure 5) trr Qrr IRRM Test Conditions Min. Typ. 600 14 48 Max. Unit 60 240 A A 1.5 V ns µC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3/8 STY60NM60 Safe Operating Area Thermal Impedance Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance 4/8 STY60NM60 Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Threshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized BVDSS vs Temperature 5/8 STY60NM60 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STY60NM60 Max247 MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. A 4.70 5.30 A1 2.20 2.60 b 1.00 1.40 b1 2.00 2.40 b2 3.00 3.40 c 0.40 0.80 D 19.70 20.30 e 5.35 5.55 E 15.30 15.90 L 14.20 15.20 L1 3.70 4.30 MIN. TYP. MAX. P025Q 7/8 STY60NM60 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 8/8