STV9410 CRT AND LCD SEMI-GRAPHIC DISPLAY PROCESSOR . .. . . . . . . . . . CMOS SINGLE CHIP CRT AND LCD DISPLAY PROCESSOR BUILT IN 6 KBYTE RAM 25 ROWS OR MORE OF 40 CHARACTERS CRT MODE : - ANALOG Y LUMINANCE OUTPUT OF 4BIT DAC - R,G,B DIGITAL COLOR OUTPUTS - FAST BLANKING OUTPUT FOR VIDEO SWITCH COMMAND - SYNCHRONIZATION INPUT AND OUTPUT - MASTER AND SLAVE SYNCHRONIZATION MODES LCD MODE : - 8 GREY LEVELS - 4 BIT DATA WITH CLOCK OUTPUT - 3 OUTPUTS FOR LCD DRIVERS SYNCHRONIZATION - CONTRAST ANALOG COMMAND WITH DAC OUTPUT 128 ALPHANUMERIC CODES AND 128 SEMI-GRAPHIC CODES IN INTERNAL ROM PARALLEL ATTRIBUTES THANKS TO 2 BYTE CODES 128 ALPHANUMERIC AND 96 SEMIGRAPHIC USER DEFINABLE CODES DOWN-LOADABLE IN RAM 3-WIRE ASYNCHRONOUS SERIAL MCU INTERFACE SQUARE WAVE OR LOGICAL PROGRAMMABLE OUTPUT FULLY PROGRAMMABLE WITH 7 16-BIT CONTROL REGISTERS 24-PIN SO OR 20-PIN DIP PACKAGES DESCRIPTION STV9410 controller is a VLSI CMOS Display Processor. Time base generator, display control & refresh logic, interface for transparent MCU memory access, ROM character sets, memory to store display data & page codes and control registers are gathered on a single chip component packed in a short 20 DIP or SO plastic package. April 1996 Using its 3-wire serial interface, working in both read and write mode to program 7 control registers and to access internal RAM, STV9410 is a highly flexible processor. The STV9410 provides the user an easy to use and cost effective solution to display alphanumeric and semigraphic Informationon CRT and LCD screens. DIP20 (Plastic Package) ORDER CODE : STV9410P SO24 (Plastic Micropackage) ORDER CODE : STV9410D 1/25 STV9410 PIN CONNECTIONS SO24 CRT LCD XTO 1 20 VDD VDD XTI 2 19 SYNC IN CKD CKO 3 18 VSYNC FRAME POR 4 17 C SYNC LOAD NCS 5 16 - DF SDA 6 15 I D0 SCK 7 14 B D1 VREF 8 13 G D3 VSSA 9 12 R D2 VSS 10 11 Y VEE CRT LCD RESERVED 1 24 - RESERVED XTO 2 23 VDD V DD XTI 3 22 SYNC IN CKD CKO 4 21 VSYNC FRAME POR 5 20 C SYNC LOAD NCS 6 19 - DF SDA 7 18 I D0 D1 SCK 8 17 B V REF 9 16 G D3 V SSA 10 15 R D2 V SS 11 14 Y V EE RESERVED 12 13 - RESERVED 9410-01.EPS - 9410-02.EPS DIP20 PIN DESCRIPTION Symbol Pin no DIP20 SO24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 I/O Description XTO XTI CKO POR NCS SDA SCK VREF VSSA VSS Y R G B I C SYNC VSYNC SYNC IN VDD - 2/25 O I O O I I/O I I S S O O O O O O O O I/O S - Reserved Crystal oscillator output Crystal oscillator or clock input Clock output Programmable output port Serial interface selection Serial data input/output Serial interface clock input Reset input and ref supply of Y DAC Ref ground of Y DAC Ground Reserved Reserved Luminance output Red output Green output Blue output Fast blanking output Reserved Composite synchro output Vertical synchro output Synchro input +5v power supply Reserved 9410-01.TBL CRT MODE STV9410 PIN DESCRIPTION (continued) o Pin n Symbol DIP20 SO24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 I/O Description LCD MODE O I O O I I/O I I S S O O O O O O O O I/O S - Reserved Crystal oscillator output Crystal oscillator or clock input Clock output Programmable output port Serial interface selection Serial data input/output Serial interface clock input Reset input and ref supply of contrast adjustment Ref ground of contrast adjustment Ground Reserved Reserved Constrast adjustment D2 Data output D3 Data output D1 Data output D0 Data output LCD polarity output Load output (line) Frame output Data Clock +5v power supply Reserved 9410-02.TBL XTO XTI CKO POR NCS SDA SCK VREF VSSA VSS VEE D2 D3 D1 D0 DF LOAD FRAME CKD VDD - BLOCK DIAGRAM XTI XTO CKO VDD PO R VREF S TV9410 CLOCK GENE RATOR CONTROL P ROCES SING DISPLAY LOGIC TIME BASE DAC LCD MODE R, G, B C S YNC VSYNC I Y D2, D3 , D1 LOAD FRAME D0 VEE DF CKD (SYNC IN) MCU INTERFACE NCS SDA SCK 6K BYTE RAM VS S 9410-03.EPS S YNC IN CRT MODE VS SA 3/25 STV9410 ABSOLUTE MAXIMUM RATINGS Parameter Value Unit V VDD* Supply Voltage -0.3, +7.0 VIN* Input Voltage -0.3, +7.0 Toper Operating Temperature Tstg Storage Temperature Ptot Power Dissipation V 0, +70 o -40, +125 o C C 300 mW 9410-03.TBL Symbol * with respect to VSS ELECTRICAL CHARACTERISTICS (VDD = 5V, VSS = 0V, Ta = 0 to + 70oC, fxtal = 8 to 10MHz, unless otherwise specified) Symbol Min Typ Max Unit VDD Supply voltage Parameter 4.75 5.0 5.25 V IDD Supply current * - - 50 mA 0 - 0.8 V INPUTS NCS, SDA, SCK, SYNC IN, XTI VIL Input low voltage VIH Input high voltage (except XTI) IIL Input leakage current (except XTI) (0 < VIN < VDD) CIN Input capacitance (except XTI) 2 - VDD V -10 - +10 µA - 10 - pF 1.5 - VDD V VREF Vrh Voltage reference of DAC Vrst Reset level on VREF RIN VREF to VSSA internal resistance VSSA Reference level of DAC 0 - 0.4 V 0.4 - 1.0 kΩ 0 - VDD V 0 - 0.4 V 0.8 VDD - VDD V OUTPUTS SDA, CSYNC, VSYNC, R, G, B, I, SYNC IN, DF, XTO, CKO, POR VOL Output low voltage (IOL = 1.6mA) VOH Output high voltage (IOH = - 0.1mA ) Y LI Integral linearity - - 0.25 V LD Differential linearity - - 0.1 V ZOUT Output impedance - - 0.5 kΩ Propagation time at VOUT 90% of V FINAL, C L=20pF, IOUT=0, VREF=5V, VSSA=0V - - 80 ns Tp * no load on outputs 4/25 9410-04.TBL Output voltage (VREF=5V, VSSA=0, IOUT=0) STV9410 TIMINGS (VDD = 5V ±5%, VSS = 0V, Ta = 0 to + 70oC, fxtal = 8 to 10MHz, VIL = 0.8V, VIH = 2V, VOL = 0.4V, VOH = 2.4V, CL = 50pF, unless otherwise specified) Symbol Parameter Min Typ Max Unit SERIAL INTERFACE NCS, SCK, SDA (Figure 1) Tcsl NCS low to SCK falling edge 0 ns Tsch SCK pulse width high 80 ns Tscl SCK pulse width low 80 fSCK Serial Clock Frequency ns 4 Tsds Set up time of SDA on SCK rising edge 20 Tsdh Hold time of SDA after SCK rising edge 20 Tsdv Access time in read mode Tsdx Hold data in read mode Tsdz Serial interface disable time Tread Delay before Valid Data MHz ns ns 50 ns 0 ns 50 ns 2 µs OSCILLATOR INPUT (XTI) (Figure 1) Twh Clock high level 30 ns T wl Clock low level 30 ns Fclk Clock frequency 8 Reset Low level pulse 2 10 MHz RESET (VREF) Tres µs OUTPUT SIGNALS SDA, CSYNC, VSYNC, R, G, B, I, SYNC IN, DF, XTO, CKO, POR (Figure 2) Tph,Tpl Propagation time Tskew Skew between R, G, B, I signals CL = 30 pF CL = 100 pF 50 100 ns ns 30 ns o (VDD = 5V ±5%, VSS = 0V, Ta = 0 to + 70 C, fxtal = 8 to 10MHz, VOL = 0.2VDD, VOH = 0.8VDD, CL = 100pF, unless otherwise specified) tCYC CKD Shift Clock Period tCH tCL 4 x Pxtal ns CKD Clock High 150 ns CKD Clock Low 150 ns tWLD Load Pulse Width 150 ns ns tSU Data Set-up Time 150 tDH Data Hold Time 150 tDF DF Delay from Load tSUF Frame Set-up before Load ns 100 150 ns ns 5/25 9410-05.TBL LCD INTERFACE D0, D1, D2, D3, CKD, LOAD, DF, FRAME (Figure 3) STV9410 Figure 1 : Microcontroller Interface Timings NCS t csl t read t sch SCK SDA t scl t sdh A8 A9 A6 t sdx t sdv A7 D0 WRITE D1 D6 READ t sdz D7 9410-04.EPS t sds Figure 2 : Output Signals Delay versus Clock t wh t wl XTI t pl t ph OUTPUT 9410-05.EPS t skew OUTPUT Figure 3 : LCD Interface Timings t CH t CL t CLD CKD t CYC t WLD LOAD t SU t DH D0, D1 D2, D3 t DF DF FRAME 6/25 9410-06.EPS t SUF STV9410 2. FUNCTIONAL DESCRIPTION STV9410 display processor operation is controlled by a host microcomputer via a 3-wire serial bus. It is fully programmable through seven internal read/write registers and performs all the display functions either for CRT screen or LCD passive matrix by generating pixels from data stored in its internal memory. In addition, the host microcomputer can have straightforward accesses to the on-chip 6 Kbytes RAM, even during the display operation. The following functions are integrated in the STV9410 : - Crystal oscillator, - Programmable timing generator, - Microcomputer 3-wire serial interface, - ROM character generatorincluding 128 alphanumeric and 128 semigraphic character sets, - 6 Kbytes on chip RAM to store character codes, user definable character sets, and any host microcomputer data, and in CRT mode : - Y output driven by a 4-bit DAC, - Programmable master or slave synchro modes, - R, G, B, I outputs, in LCD mode : - LCD interface for passive multiplexed matrix, - 7 grey levels plus black. 2.1 SERIAL INTERFACE This 3-wire serial interface can be used with any microcomputer. Data transfer is supported by hardware peripherals like SPI or UART and can be emulated with standard I/O port using software routine ( see application note ). NCS input enablestransfer on high to low transition and transfer stays enabled as long as NCS input remains at logical low level. NCS input disables transfer as soon as low to high transition occurs, whatever transfer state is, and transfer remains disabled as long as NCS input remains at logical high level. SCK input receives serial clock; it must be high at the beginning of the transfer; data is sampled on rising edge of SCK. SDA input (in write mode) receives data which must be stable at least tsds before and at least tsdh after SCK rising edge. In read mode, SDA receives address and read command (R/W bit) and then it switches from input state to output state to send data (see Data transfer and Application Note). Data Transfer in Write Mode The host MCU writes data into STV9410 registers or memory. The MCU sends first MSB address with R/W bit clear, it sends secondly LSB address followed by data byte(s). STV9410, then, internally increments received address, ready to store a second data byte if needed, and so on, as long as NCS remains low (see Figure 4). LSB are sent first. Data Transfer in Read Mode The host MCU reads data from STV9410 registers or memory. The MCU sends first MSB address with R/W bit set, it sends secondly LSB address, then SDA pin switches from input state to output state and provides data byte(s) at SCK MCU clock rate. Notice that a minimum delay is needed before sending the first SCK rising edge to sample the first data bit (at least 2µs). After each data byte STV9410 internally increments address and it sends next data at SCK frequency. SDA remains in output state as long as NCS remains low (see Figure 5). Address auto-incrementation allows host MCU to use 8, 16, 32-bit data words to optimize transfer rate. LSB are sent first. SCK max speed is 4MHz. 7/25 STV9410 Figure 4 : Serial Interface Write Mode NCS SCK SDA A8 A9 A10 A11 A12 A13 W A0 A1 A2 A3 @ MSB A4 A5 A6 A7 D0 D1 @ LSB D2 D3 D4 D5 D4 D5 Data byte 1 NCS SCK D6 D7 D0 D1 D2 D3 data byte n - 1 D4 D5 D6 D7 9410-07.EPS SDA D5 data byte n Figure 5 : Serial Interface Read Mode NCS 2µs min. SCK SDA A8 A9 A10 A11 A12 A13 R A0 A1 A2 @ MSB A3 A4 A5 A6 A7 D0 @ LSB D1 D2 D3 Data byte 1 INPUT OUTPUT SDA Pin NCS SCK D5 D6 D7 data byte n - 1 D0 D1 D2 D3 8/25 D5 D6 D7 data byte n OUTPUT SDA Pin D4 INPUT 9410-08.EPS SDA STV9410 2.2. ADDRESSING SPACE STV9410 registers, RAM and ROM are mapped in a 12 kbytes addressing space. The mapping is the following : HSYN 2FF5 SU7 SU6 SU5 SU4 SU3 SU2 SU1 SU0 2FF4 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 SU (7:0) : Synchro rising edge position SD (7:0) : Synchro falling edge position 0000 h Display memory DRCS Descriptor tables User memory 6144 RAM bytes 17FF h 1800 h POR Empty Area 1FFF h 2000 h VOE - - - - - TE PV 2FF6 N7 N6 N5 N4 N3 N2 N1 N0 P8 P7 P6 VOE TE PV N (7:0) 1280 slices ROM G0 24FF h 2500 h 2FF7 1280 slices ROM G1 2CFF h 2D00 h 2FF9 - P12 P11 P10 P9 2FF8 - G12 G11 G10 - DISP Internal Registers 2FFB IMG GMG RMG BMG 2FFF h 2FFA 2.2.1 Register Set VERT LCD ILC 2FF0 F7 : : : : : : : F6 C/H V/P VSE HSE F5 A12 A11 A10 P (12:6) : Address of first descriptor of page to display G (12:10) : User definable graphic character set address A (12:10) : User definable alphanumeric character set address Empty Area 2FEF h 2FF0 h LCD ILC C/H V/P VSE HSE F (8:0) Video output enable Timer enable Port value Square wave period ADDR Empty Area 27FF h 2800 h 2FF1 : : : : F4 F3 F2 - F8 F1 F0 LCD/CRT mode Interlaced/non-interlaced Composite/horizontal synchro Vertical synchro/real time port Vertical synchro enable Horizontal synchro enable Number of scan line per frame - - - - - 2FF2 - - L5 L4 L3 - HIC BR3 BR2 BR1 BR0 IMG, GMG, : Margin value of I, G, R, B outputs RMG, BMG HIC : High contrast, forces black and white on outputs FLE : flashing enable CCE : Conceal enable IN1, IN0 : Fast blanking mode BR (3:0) : Luminosity adjustment on Y output 2FFD CEN CBL CUL 2FFC MG2 MG1 MG0 L2 IN2 - CURS HORI 2FF3 FLE CCE IN1 - L1 CEN CBL CUL C (12:1) C8 : : : : C7 Cursor Cursor Cursor Cursor C6 C5 C12 C11 C10 C9 C4 C1 C3 C2 enable blinking underlining address L0 MG (2:0) : Margin duration L (5:0) : Line duration 9/25 STV9410 2.2.2 Descriptor UNIFORM 0 LSB RTP FFB I C (2:0) SL (7:0) RTP FFB - I C2 C1 C0 SL7 SL6 SL5 SL4 SL3 SL2 SL1 SL0 : : : : : Real time port Field flyback Fast blanking Strip color (G, R, B) Number of scan line of the strip 0000h Descriptor (Table 1) 64b (for page 0) 0040h Descriptor (Table 2) 64b (for page 0) 0080h Page 0 Row 1 CHARACTER MSB 1 LSB C8 RTP DE ZY C (12:1) : : : : 80b Code 0 to 39 RTP DE C7 C6 ZY C12 C11 C10 C9 C5 C4 C1 C3 C2 Real time port Display enable Vertical zoom Address of first character to display 00A8h Page 0 Row 2 80b Code 0 to 39 ~ ~ 07D8h ~ ~ 80b Code 0 to 39 0800h Descriptor (Table 1) 64b (for page 1) Descriptor (Table 2) CHARACTER NUMBER 64b (for page 1) Page 1 Row 1 LSB (EVEN) 0 IV DW DH FL FC2 FC1 FC0 CHARACTER NUMBER : lower than 80h in ROM from 80h to FFh in RAM IV : Inverted video DW : Double width DH : Double height FL : Flashing FC (2:0) : Foreground color (G, R, B) Page 1 Row 2 1 BC2 BC1 BC0 FL ~ ~ ~ ~ Page 1 Row 24 1000h Alphanum Character 0 10b Alphanum Character 1 10b ~ ~ 10b Page 0 Row 0 4b Free 1400h 10b LSB (EVEN) 1 EOL IF, IB UL CC BC (2:0) HG FC (2:0) 10/25 : : : : : : : 10b Graphic Character 1 1 EOL IF IB UL ~ ~ CC ~ ~ ~ ~ Graphic Character 93 BC2 BC1 BC0 HG FC2 FC1 FC0 End of line Fast blanking foreground/background Underline Conceal Background color (G, R, B) Hold graphic Foreground color (G, R, B) 1 Kbyte 80b Code 0 to 39 Graphic Character 0 1 ~ ~ ~ ~ Alphanum Character 93 FC2 FC1 FC0 CONTROL 1 ~ ~ 80b Code 0 to 39 CHARACTER NUMBER : lower than 80h in ROM from 80h to DFh in RAM BC (2:0) : Background color (G, R, B) FL : Flashing FC (2:0) : Foreground color (G, R, B) MSB (ODD) 2 Kbyte 80b Code 0 to 39 CHARACTER NUMBER LSB (EVEN) 80b Code 0 to 39 GRAPHIC MSB (ODD) ~ ~ Page 0 Row 24 2.2.3 Code Format ALPHANUM MSB (ODD) 2 Kbyte Page 1 Row 0 10b 1 Kbyte 80b Code 0 to 39 Free 17FFh 4b 9410-09.EPS MSB 2.2.4 Example of RAM Maping STV9410 2.3.1 Time Base Registers 2.3 CLOCK AND TIMING GENERATOR The whole timing is derived from XTI input frequency which can be an external generator or a crystal signal thanks to XTO/XTI oscillator.This clock is also pixel frequency which can be chosen between 8MHz to 10MHz (pxlck). This clock is available on CKO pin. It should be use for the MCU, saving a crystal in the application. Vertical Time Base and Configuration Register (VERT) Internal address : 2FF1-2FF0 h RESET value :01-36 h (@ = RESET default configuration) 2FF1 h LCD ILC @ 0 0 C/H V/P VSE HSE 0 0 0 0 0 F8 1 2FF0 h @ F5 1 F1 1 F0 0 The active area of a video line is 320 pixels periods long (40 characters of 8 pixels wide). Number of lines per frame, margin width, line duration, leading and trailing edges of horizontal synchronizationare fully programmable in CRT mode using VERT, HORI, HSYN registers. LCD A RESET, can be applied to STV9410 by pulling low VREF pin ( ≤ 0.4V). V/P On RESET, default values are forced into configuration registers and video outputs are at low level. ILC C/H VSE HSE F (8:0) All unused bit of registers are always read as ”0”. F7 0 F6 0 F4 1 F3 0 F2 1 : 1 LCD mode 0 CRT mode @ : 1 Interlaced scanning 0 non-interlaced scanning @ : 1 CSYNC is composite synchro 0 CSYNC is horizontal synchro @ : 1 VSYNC is vertical synchro 0 VSYNC is RTP bit of current descriptor @ : 1 enable vertical synchro with SYNC IN 0 disable @ : 1 enable horizontal synchro with SYNC IN 0 disable @ : scan line number per frame (@ 312) 2FF1 LCD ILC X X C/H X 2FF0 V/P VSE HSE X X X Nb of S can LS B Lines HEXA - F8 F7 F6 F5 F4 F3 F2 F1 F0 F(0:8) + 2 - 0 0 0 0 0 0 0 0 0 Not allowed - 0 0 0 0 0 0 0 0 1 3 01 0 0 0 0 0 1 1 1 0 16 0E 0 0 0 1 1 1 1 1 0 64 3E 0 0 1 1 0 0 0 1 0 100 62 0 0 1 1 1 0 1 1 0 120 76 0 1 1 1 0 1 1 1 0 240 EE 0 1 1 1 1 1 0 0 0 250 F8 0 262 04 05 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 263 1 0 0 1 1 0 1 0 0 310 34 1 0 0 1 1 0 1 1 0 312 36 1 0 0 1 1 0 1 1 1 313 37 1 0 0 1 1 1 1 1 0 320 3E 1 1 1 0 1 1 1 1 0 480 DE 1 1 1 1 1 1 1 1 0 512 FE 1 1 1 1 1 1 1 1 1 513 FF 9410-10.EPS Figure 6 : Vert Register Scan Lines Programmation F[8:0] = Scan Line Number - 2 11/25 STV9410 Margin and Horizontal Time Base Register (HORI) Internal address : 2FF3-2FF2 h RESET value :03-3F h (@ = RESET default configuration) 2FF3 @ 0 0 0 0 0 2FF2 @ 0 0 L5 1 L4 1 L3 1 Horizontal Synchronization Register (HSYN) Internal address : 2FF5-2FF4 h RESET value :E6-DC h (@ = RESET default configuration) MG2 MG1 MG0 0 1 1 L2 1 L1 1 L0 1 2FF5 @ SU7 SU6 SU5 SU4 SU3 SU2 SU1 SU0 1 1 1 0 0 1 1 0 2FF4 @ SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 1 1 0 1 0 1 0 0 MG(2:0) : Left and right margin duration (@ = 4µs) MarginDuration MG = −1 8 pxlck SU(7:0) : SYNC rising edge position (@ = 57.75µs) Rise Edge Position SU = −1 2 pxlck L(5:0) SD(7:0) : SYNC falling edge position (@= 53.25µs) FallingEdge Position SD = −1 2 pxlck : Line duration (@= 64µs) Line Duration L= −1 8 pxlck Figure 7 : HSYN Register Synchro Pulse Programmation Qz = 8MHz Active area Register Value Duration Duration (µs) (nber of char.) 64µs 64 1µs 1 1µs 1 FIXED 40µs 40 RESULT 21µs 21 HORI (L = 3F) FIXED HORI (MG = 0) HSYN (SU = B7) 46µs 46 HSYN (SD = BF) 48µs 48 HSYN PULSE Positive Pulse HSYN (SU = BF) 48µs 48 HSYN (SD = B7) 46µs 46 HSYN PULSE 12/25 Negative Pulse 9410-11.EPS REG STV9410 Figure 8 : Horizontal Synchronization Timing DESIGNATION TIMING DIAGRAM COMMENTS Crystal = 8MHz pxlck = 125ns 0 = origin PIXEL CLOCK START 0 Start Margin Active Area (320 pixels) Margin End of line 0 Y OUTPUT DAC output START 8pxlck Fixed ”HORT” MSB REG = (MG +1) x 8 x pxlck ”HORT” LSB REG = (L +1) x 8 x pxlck ”HSYN” LSB REG = (SD + 1) x 2 x pxlck = (SU + 1) x 2 x pxlck 9410-12.EPS ”HSYN” MSB REG HSYN PULSE Video Validation and Port Register (PORT) Internal address : 2FF7-2FF6 h RESET value :00-00 h (@ = RESET default configuration) mode (CRT or LCD), be fulfiled : - SU ≠ SD SU + 1 SD + 1 < L and <L 4 2FF7 @ VOE 0 0 0 0 0 0 TE 0 PV 0 2FF6 @ N7 0 N6 0 N5 0 N4 0 N3 0 N2 0 N1 0 N0 0 VOE TE PV N(7:0) : Video Output Enable 1 enable synchro & video outputs 0 disable synchro & video outputs @ (@ Output Y, CSYNC, VSYNC, R, G, B, I, POR, and DF are grounded, Input SYNC IN is high impedance) : Timer Enable 1 POR provides a square wave signal with a period of 16 x N(7:0) x pxlck 0 POR output is PV bit @ : Port Value POR output value if TE=0 (@=0) : Square wave period on POR if TE=1 (@=0) BEWARE The programmation of VERT, HORI, HSYN registers must be consistent. To get a proper work of the controller, the following conditions must, in any 4 - 2(MG + 1) + 40 ≤ L Line period is : - PL = [L(5:0) + 1] x 8 pxlck - In LCD, MG(2:0) can be 0, then minimum Line Period is PL (min.) = 43 x 8 pxlck Frame period is : - PF = [F(8:0) + 2] x PL - In LCD, using a 240 lines matrix, F(8:0) = 238, then minimum frame is : PF (min.) = 240 x 43 x 8 pxclk Pixel period is : - Pxclk = PFrame [ F(8:0) + 2 ] [ L(5:0) + 1 ] x 8 - I n LCD, u sing a 240 line s matrix, an d MG(2:0) = 0, Pxclk = PFrame 240 x 43 x 8 Interlaced mode conditions : SU + 1 SD + 1 and <L 4 4 SU + 1 SD + 1 and > (MG + 1) + 42 4 4 13/25 STV9410 2.3.2. CRT Mode In CRT mode, the Vsync signal appears at the first two lines of the first strip of the descriptor list. It is recommended to provide an uniform blanked (with FFB bit) strip as first descriptor. The scan line number of this strip have to be equal or higher than scan line number of the vertical blanking Interval. Master Mode This mode is selected by writing VSE and HSE bit of VERT register with logical value ”0”. Non-interlaced mode is selected by writing ILC bit of VERT register with logical value ”0”. Horizontal or composite synchronization signal is output on CSYNC pin, Vertical synchronization signal is output on VSYNC pin. Signal waveforms are described in Figure 9. Interlaced mode is selected by writing ILC bit of VERT register with logical value ”1”. Even frame is identical to non-interlaced frame. VSYNC PULSE is low during second half of last line of previous Odd frame and during the two first lines of current Even frame. Odd frame is one scan line more than Even frame. VSYNC PULSE is low during the two first lines and up to first half of the third line of current Odd frame. Half line corresponds to 17th character position. Signals waveforms are described in Figure 10. Slave Mode This mode is activated by writing VSE and/or HSE bit of VERT register with logical value ”1”. Then SYNC IN input signal is sampled according to procedure described below. Vertical Synchronization SYNC IN signal may be either a vertical synchronization or a composite synchronization. It is sampled on first pixel of each scan line active area. As soon as SYNC IN signal low level is detected, vertical time base counter F(8:0) of VERT register is reset without any modification of other time base registers. Horizontal Synchronization SYNC IN is sampled one pxlck before and one pxlck after internal horizontal pulse transition. If falling edge is not found, one pixel period is added to internal line duration. Using a line frequency locked clock applied on XTI, internal scan line becomes phase locked after few scan line periods at programmed value (see Figure 11). 2.3.3 LCD Mode LCD mode only works as a master mode with 320 pixels per line. Internal algorithm allows 8 grey levels on passive LCD matrix. Number of scan line is programmable. In order to get maximum refresh frequency of display, margin and line duration must be reduced to miminum. Interlaced mode and external synchronization are not allowed. The 1st line of the first descriptor in the description list correspond to the first line of the LCD display. Y output provides a programmable voltage usable to adjust contrast of LCD display. To reduce supply current consumption, when Y output is unused, VSSA must not be connectedto ground, and VREF pin works as a reset pin. Notice that SYNC IN Pin provides (CKD) data clock signal. 2.4 POR OUTPUT POR is a standard I/O pin programmable at logical level ”1” or ”0”. It can also provide a programmable square wave signal of period P = 16 x N(7:0) x pxlck (0 ≤ N ≤ 255). It can drive a capacitive buzzer (see application diagram at page 22). RESET value of PORT is ”0”. Figure 9 : ODD and EVEN Synchronization Pulses in Non-interlaced Mode DESIGNATION TIMING DIAGRAM COMMENTS Horizontal Synchro H SYNC PULSE Composite Synchro C SYNC PULSE Vertical Synchro ”VERT” LSB REG LINE NUMBER * Internal logic adds one more line 14/25 FN - 1 FN N N+1 FN + 1* N +2 F0 F1 F2 F3 1 2 3 4 Programmed value of F (8 : 0) is N Frame number of lines is N + 2 9410-13.EPS VSYNC PULSE STV9410 Figure 10 : Interlaced Mode Synchronization Pulses DESIGNATION H SYNC PULSE COMMENTS Horizontal Synchro C SYNC PULSE Composite Synchro ”VERT” LSB REG TIMING DIAGRAM FN - 1 FN FN + 1 F0 F1 F2 F3 Programmed value of F (8 : 0) is N N N+1 N +2 1 2 3 4 EVEN frame number of lines is N + 2 LINE NUMBER Previous Picture Current Picture EVEN Frame ODD Frame V SYNC PULSE Vertical Synchro ODD Frame H SYNC PULSE Horizontal Synchro C SYNC PULSE FN FN + 1 FN + 2 F0 F1 F2 F3 Programmed value of F (8 : 0) is N N+ 1 N+ 2 N +3 1 2 3 4 ODD frame number of lines is N + 3 ”VERT” LSB REG LINE NUMBER Current Picture Picture number of lines is 2N + 5 EVEN Frame ODD Frame Vertical Synchro EVEN Frame V SYNC PULSE Start Margin Active Area Margin End of line ZONE 1 2 3 4 15 16 17 18 38 39 40 Characters Position H SYNC PULSE Horizontal Synchro LINE 3 ODD FRAME Composite Synchro LINE N + 3 ODD FRAME 9410-14.EPS CHAR NUMBER Composite Synchro 15/25 STV9410 Figure 11 : Synchronization on SYNC IN External Signal VERTICAL SYNCHRONIZATION DESIGNATION COMMENTS TIMING DIAGRAM Sampling Clock PIXEL CLOCK Margin Margin Active Area Y OUTPUT H Pulse H Pulse Sampling on first pixel of active area SYNC IN VERTICAL PULSE F (8 : 0 ) Fx F0 S S = 0 clear F (8 : 0) only HORIZONTAL SYNCHRONIZATION COMMENTS TIMING DIAGRAM Sampling Clock PIXEL CLOCK INTERNAL H SYNC DURATION = L (5 : 0) Sampling window for H Synchro EXTERNAL H SYNC UNLOCKED EXTERNAL H SYNC LOCKED 3. INTERNAL REGISTER DESCRIPTION STV9410 is programmable with 7 registers of 16 bit each. These registers can also be programmed in byte mode. Not significant bit must be cleared in order to be compatible with next generation products. 3.1 TIME BASE REGISTERS Registers VERT, HORI, HSYN and PORT are described in chapter 2.3 3.2 ADDRESS REGISTER ( ADDR ) Internal address : 2FF9-2FF8 h 16/25 L = L+ 1 Line Duration Increase + 1 L= L Good Line Duration 9410-15.EPS DESIGNATION RESET value :00-00 h (@ = RESET default configuration) 2FF9 h @ 0 P12 P11 P10 0 0 0 P9 0 2FF8 h @ 0 G12 G11 G10 0 0 0 0 P8 0 P7 0 P6 0 A12 A11 A10 0 0 0 P(12:6) : Page first descriptor address, P(5:0)=0 @ G(12:10) : Graphic character set MSB address, G(9:0)=0 @ A(12:10) : Alphanumeric character set MSB address, A(9:0)=0 @ NB : as addresses are in RAM area, address bit 13 is reset to ”0” STV9410 Figure 12 : ADDR Register and Descriptor List Address 2FF9 ADDR REGISTER - P12 P11 P10 P9 2FF8 P8 P7 P6 - G12 G11 G10 - A12 A11 A10 Used for RAM character sets 0 PROG VALUE 1 0 0 0 2 REAL ADDRESS 1 PROG VALUE 0 0 PROG VALUE 0 0 0 1 0 1 1 1 0 0 0 1 0 2 0 0 0 1 0 0 0 0 0 0 0 (0800h) 0 0 0 (15C0h) 0 0 0 (0A40h) - 0 0 0 - 9 0 - - 7 1 0 - 0 5 REAL ADDRESS 0 9410-16.EPS REAL ADDRESS 64 bytes blocks 3.3 DISPLAY REGISTER (DISP) BR(3:0) : This value is combined with pixel value to drive Y DAC in CRT mode : Y= 4xG + 2xR + B + BR(2:0) + 3x(R or G or B) (logical or) R, G, B, I, Y, = 0 during line flyback. Internal address : 2FFB-2FFAh RESET value :00-00 h (@ = RESET default configuration) 2FFB IMG GMG RMG BMG @ 0 0 0 0 2FFA FLE CCE @ 0 0 IMG, GMG, RMG, BMG HIC IN1 0 0 0 0 HIC 0 IN0 BR3 BR2 BR1 BR0 0 0 0 0 0 : M a rg in v a lu e o f I, G , R, B o u tp ut s and background color and insertion default attribute of next alphanumeric character. In case of graphic characters only I is default attribute. : Forces alphanumeric characters background black (R, G, B = 0), and foreground white (R, G, B = 1) for maximum contrast, 0 = disable @ FLE : Flashing enable, 0 = disable @ CCE : Conceal enable, 0 = disable @ IN1,IN0 : Insertion attribute mode selection. Mode selects value of I output during active area of scan line in CRT mode; I output value (during margin) is programmed with DISP register; during uniform strip I output value is set according to strip descriptor. During active time slot : 0 0 : I output gets value of current code I attribute (margin attribute or control character attribute ) @ 0 1 : I is set (”1”) 1 0 : I output gets value of current code I attribute if I=0 R,G,B are reset to ”0” 0 1 : Reserved mode Black level is output with R, G, B = ”0”. White level is output with R, G, B = ”1”. During frame flyback, R, G, B, I, Y provides signal according to uniform strip descriptor FFB bit state (see chapter 4.2.1) During LCD mode BR(3:0) drives continuously Y DAC. Notice that only bit 0 to 2 of BR are used in CRT mode. 3.4. CURSOR REGISTER (CURS) Internal address : 2FFD-2FFC h RESET value : 00-00 h (@= RESET default configuration) 2FFD @ 2FFC @ CEN CBL CUL 0 0 0 C8 0 C7 0 C6 0 0 C5 0 C12 C11 C10 0 0 0 C9 0 C4 0 C1 0 C3 0 C2 0 CEN CBL : Cursor enable, 0 = disable @ : 0 cursor blinking off, character blinking attribute unchanged @ 1 cursor blinking on, blinking is mixed with character blinking attribute. Blinking frequency is around 1Hz and duty cycle 50% CUL : 0 character underline attribut is complemented on cursor position @ 1 character color is complemented on cursor position C(12:1) : Cursor address (not a screen position) 17/25 STV9410 - vertical synchro - border lines Parameters : - number of scan lines - color - Character strip Characters and attributes are defined by a succession of codes stored in memory; thanks to the character code, a memory address is calculated and used to get the character pattern. Parameters : - address of the first code - size, display enable 4. DISPLAY CONTROL 4.1 SCREEN DESCRIPTION A screen is composed of successive scan lines gathered in one or several strips. Each strip is defined by a descriptor stored in memory. A list of descriptors allows screen composition, different screens can be defined in memory (see application note and Figures 13, 14.). Two kinds of strip are available : - Uniform color strip Applications : - vertical front and back porch DESCRIPTOR LIST 1460 0A02 F8AA 20AB 48AB A8AA D0BA 1402 1906 1903 1907 CONTENTS U0* U1 R0* R1 R2 R18 R19 U2 U3 U4 U5 SCAN LINES 20 10 10 10 10 10 10 20 25 25 25 SUM 20 30 40 50 60 220 230 250 275 300 325 VERT REGISTER 242 Scan Lines (00F0h) COMMENTS U2 Strip is cut (red uniform strip) VERT REGISTER 312 Scan Lines (0136h) COMMENTS U2 (red), U3 (yellow), U4 (cyan) and part of U5 (white) uniform strip are displayed * U0 is uniform strip number 0, R0 is character strip number 0 9410-17.EPS Figure 13 : Programmation of Number of Scan Lines - Vertical Register VERT (2FF0/2FF1) and Descriptor List Figure 14 : Relation between Screen Location/Descriptor Pointer/RAM Page Codes Address of the list ADDR REGISTER * Identical to row 2 OTHER UNIF 0 TOP UNIFORM STRIP 25th ROW CODES ROW 0 1st CHARACTER ROW OTHER ROW 1 2nd CHARACTER ROW 1st ROW CODES ROW 2 3rd CHARACTER ROW ROW 22 23th CHARACTER ROW 2nd ROW CODES 18/25 OTHER ROW 2 24th CHARACTER ROW * 23th ROW CODES ROW 24 25th CHARACTER ROW OTHER UNIF 1 BOTTOM UNIFORM STRIP RAM PAGE CODES LOCATION RAM DESCRIPTOR LIST SCREEN 9410-18.EPS 3rd ROW CODES STV9410 4.2. STRIP DESCRIPTOR FFB : Field Flyback 0 R, G, B, I and Y outputs are defined by corresponding bit of DISP for margin and C(2:0) and I for active area 1 R, G, B, I and Y outputs are cleared during Field Flyback, whatever other parameters are. I : 0 Fast Blanking Disable 1 Fast Blanking Enable C(2:0) : G, R, B, value during the active area of the strip (320 pixels) SL(7:0) : Number of scan lines of the strip, minimal value is 1. Each strip is defined by 2 bytes. During the vertical retrace, an internal descriptor address counter is initialised with the value P(12:0) of ADDR register; on the trailing edge of vertical synchro, the first strip descriptor is loaded into the display controller; if it is an uniform strip, selected color is displayed during the corresponding number of scan lines; if it is a character strip, left margin followed by text, followed by right margin are displayed during 10 scan lines ; the next descriptor is then read, and the same process is repeated until the last scan line. This information being given by the vertical timing generator. 4.2.2. Character Strip 1 RTP DE ZY C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 RTP : Real Time Port RTP bit value is output on VSYNC when V/P bit of VERT register ”0”, along the complete duration of the strip line, during the whole strip. DE : Display Enable 0 display off, the strip is displayed with margin attributes IMG, GMG, RMG, BMG bit of DISP register, 1 display on, the strip works as selected. ZY : Vertical Zoom 0 normal display mode 1 all scan line are doubled, providing a vertical zoom effect C(12:1) : Address of the first code to display 4.2.1 Uniform Strip 0 RTP FFB - I C2 C1 C0 SL7 SL6 SL5 SL4 SL3 SL2 SL1 SL0 RTP : Real Time Port RTP bit value is output on VSYNC when V/P bit of VERT register is ”0”, along the complete duration of the strip scan line. Not used in LCD mode. Figure 15 : Character Strip Descriptor - First Character Address Selection MSB 1 RTP DE ZY C12 C11 C10 1 EFFECTIVE ADDRESS C9 C8 C7 C6 5 C5 C4 C3 C2 C1 C0 0 0 F BINARY ADDRESS - - - - 1 0 1 0 1 1 1 1 1 0 0 0 BINARY DESCRIP. 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 0 A PROG VALUE F 0 EFFECTIVE ADDRESS BINARY ADDRESS - - BINARY DESCRIP. 1 1 PROG VALUE A E 8 9 - - 0 1 1 0 0 1 4 7 0 0 1 0 0 0 1 0 B 2 1 1 1 0 1 1 1 0 0 1 0 1 0 9 9410-19.EPS DESCRIPTOR LSB 19/25 STV9410 5. CHARACTER CODE FORMAT ODD 1 Each character is defined with a two bytes code; the first is at an even address, the second is at the following odd address. Some attributes are parallel, other keep the last explicit value. STV9410 uses 3 different types of codes. EVEN 1 5.1 ALPHANUMERIC CHARACTERS (256 patterns) The background color is not defined by the code; it takes the same value as the previous character or it has the value of the margin color at the beginning of each row. The character pattern lies in ROM if CHARACTER NUMBER is lower than 80h, (ALPHANUMERIC CHARACTER SET is shown in TABLE 3),else it is User Defined Character in RAM (DRCS). ODD EVEN CHARACTER NUMBER 0 IV DW DH FL FC2 FC1 FC0 CHARACTER : ROM or RAM character set code NUMBER IV : Inverted video if set. DW : Double character width if set, code must be repeated for the right part of the character. DH : Double character height if set, code must be repeated for the bottom part of the character. The first DH attribute encountered in a vertical column is always interpreted as a top part. FL : Flashing, inverted phase if IV is set. FC(2:0) : Foreground color (Green, Red, Blue). 5.2. GRAPHIC CHARACTERS (224 patterns) IV, DW, DH, UL take the value ”0” CHARACTER NUMBER must be lower than E0h. The character pattern lies in ROM if CHARACTER NUMBER is lower than 80h, (STANDARD MOSAIC character set is shown in Table 4), else it is an User Defined Character in RAM (DRCS). ODD EVEN CHARACTER NUMBER 1 CHARACTER NUMBER BC(2:0) FL FC(2:0) BC2 BC1 BC0 FL FC2 FC1 FC0 : ROM or RAM character set code : Background color (Green, Red, Blue). : Flashing. : Foreground color (Green, Red, Blue). 5.3. CONTROL CHARACTERS (32 codes) These characters are displayed as foreground color spaces if HG bit is clear. They can change some attributes applying to themselves and to the following string. 20/25 1 1 EOL IF IB UL CC BC2 BC1 BC0 HG FC2 FC1 FC0 EOL : End Of Line 0 normal control code 1 space are displayed until the end of the row, allowing memory space saving IF,IB : Insert foreground, Insert background attribute. 0 fast blanking disable 1 fast blanking enable UL : Underlined 0 disable 1 enable CC : Conceal Character 0 disable 1 enable, character is diplayed as a space. BC(2:0) : Default background color of next character(s) HG : Hold Graphics 0 disable, the control character is displayed as a uniform space character with foreground color fixed by FC(2:0) 1 enable, the control character pattern takes the last mosaic value encountered in the row, if any, or is a space. FC(2:0) : G, R, B foreground value of the control character At the beginning of each row, those attributes take default values : - EOL, UL, CC, HG = 0 - IF = 1 - IB = IMG (Margin insert attribute) - BC(2:0) = GMG, RMG, BMG (Margin color). Notice that following characters code is reserved for futur use. ODD 1 1 1 1 X X X 1 EVEN 1 X X X X X X X 6. CHARACTER GENERATORS Each pixel is defined with one bit, 1 refers to foreground color, and 0 to background color. PX7 PX6 PX5 PX4 PX3 PX2 PX1 PX0 PX7 is the leftmost pixel. Character slice address : Each character generator contains a succession of patterns arranged as a number of horizontal slices : - Slice addr = (Set addr) + Char Number x 10 + (slice number) - Char Number is the number of the character in the set; using DRCS in RAM, the calling code of the character is the number of the character in the set plus 80h. - Set addr is defined in ADDR register, in RAM for DRCS (see section 3.2), and is2000h for ALPHANUMERIC ROM, and 2800h for STANDARD MOSAIC ROM. STV9410 Table 3 : Go AlphanumericCharacter Set 40 Character/Row STV9410 C3 C2 C1 C0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 9410-20.EPS C6 C5 C4 21/25 STV9410 Table 4 : G1 Semigraphic Character Set 22/25 C3 C2 C1 C0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 SEPARATEDSEMI-GRAPHIC 0 0 0 0 0 0 1 1 0 1 0 1 MOSAIC SEMI-GRAPHIC 1 1 1 0 0 1 0 0 1 1 1 1 9410-21.EPS C6 C5 C4 STV9410 TYPICAL APPLICATIONS CRT APPLICATION DIAGRAM C S YNC S CANNING VSYNC SYNC IN VREF VDD XTI R, G, B 47pF Y XTO CRT S TV9410 47pF POR I NCS BUZZER SCK VSS A SDA VS S 9410-22.EPS CK0 MCU LCD APPLICATION DIAGRAM VRE F VDD XTI VEE LOAD FRAME D0 ... D3 CKD DF 47pF XTO 47pF P OR S TV9410 SCK BUZZER SDA VS SA NCS VSS 320 x 2 50 LCD MATRIX 9410-23.EPS CK0 MCU 23/25 STV9410 PM-DIP20.EPS PACKAGE MECHANICAL DATA 20 PINS - PLASTIC DIP a1 B b b1 D E e e3 F I L Z 24/25 Min. 0.254 1.39 Millimeters Typ. Max. 1.65 0.45 0.25 Min. 0.010 0.055 Inches Typ. Max. 0.065 0.018 0.010 25.4 8.5 2.54 22.86 1.000 0.335 0.100 0.900 7.1 3.93 3.3 0.280 0.155 0.130 1.34 0.053 DIP20.TBL Dimensions STV9410 PACKAGE MECHANICAL DATA 24 PINS - PLASTIC MICROPACKAGE 0.10mm B e A A2 h x 45? A1 K A1 L .004 C H Seating Plane D 13 1 12 PM-SO24.EPS E 24 SO24 A A1 A2 B C D E e H h K L Min. 2.35 0.1 Millimeters Typ. 0.33 0.23 15.20 7.40 Max. 2.65 0.30 2.55 0.51 0.32 15.60 7.60 Min. 0.093 0.004 0.013 0.009 0.598 0.291 1.27 10.0 0.25 0.40 Inches Typ. Max. 0.104 0.012 0.100 0.020 0.013 0614 0.299 0.050 10.65 0.394 0.75 0.010 0o (Min.), 8o (Max.) 1.27 0.016 0.419 0.030 SO24.TBL Dimensions 0.050 Information furnished is believed to be accurate and reliable. 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