STMICROELECTRONICS EF9345

EF9345
HMOS2 SINGLE CHIP SEMI-GRAPHIC
DISPLAY PROCESSOR
.
.
.
.
..
.
.
.
SINGLE CHIP LOW-COST COLOR CRT
CONTROLLER
TV STANDARD COMPATIBLE (50Hz or 60Hz)
2 SCREEN FORMATS :
- 25 (or 21) ROWS OF 40 CHARACTERS
- 25 (or 21) ROWS OF 80 CHARACTERS
ON-CHIP 128 ALPHANUMERIC AND 128
SEMI-GRAPHIC CHARACTER GENERATOR
TWO STANDARD OPTIONS AVAILABLE FOR
ALPHANUMERIC SETS (EF9345-R003 IS NO
MORE AVAILABLE)
EASY EXTENSION OF USER DEFINED ALPHANUMERIC OR SEMI-GRAPHIC SETS
(> 1 K CHARACTERS)
40 CHARACTERS/ROW ATTRIBUTES : FOREGROUND AND BACKGROUND COLOR, DOUBLE HEIGHT, DOUBLE WIDTH, BLINKING,
REVERSE, UNDERLINING, CONCEAL, INSERT, ACCENTUATION OF LOWER CASE
CHARACTERS
80 CHARACTERS/ROW ATTRIBUTES : UNDERLINING, BLINKING, REVERSE, COLOR
SELECT
PROGRAMMABLE ROLL-UP, ROLL-DOWN
AND CURSOR DISPLAY
ON-CHIP R, G, B, I VIDEO SHIFT REGISTERS
EASY SYNCHRONIZATION WITH EXTERNAL VIDEO-SOURCE : ON-CHIP PHASE
COMPARATOR
ADDRESS/DATA MULTIPLEXED BUS DIRECTLY COMPATIBLE WITH STANDARD MICROCOMPUTERS SUCH AS 6801, 6301,
8048, 8051, ST9
ADDRESSING SPACE : 16K x 8 OF GENERAL PURPOSE PRIVATE MEMORY
EASY OF USE OF ANY LOW-COST MEMORY COMPONENTS : ROM, SRAM, DRAM
DESCRIPTION
The EF9345, new advanced color CRT controller,
in conjunction with an additional standard memory
package allow full implementation of the complete
display control unit of a color or monochrome lowcost termainl, thus significantly reducing IC cost
and PCB space.
March 1995
DIP40
(Plastic Package)
ORDER CODE : EF9345P
PIN CONNECTIONS
V SS
1
40
ADM0
OE
2
39
ADM1
WE
3
38
ADM2
ASM
4
37
ADM3
HVS/HS
5
36
ADM4
PC/VS
6
35
ADM5
B
7
34
ADM6
G
8
33
ADM7
R
9
32
AM8
I
10
31
AM9
HP
11
30
AM10
CLK
12
29
AM11
SYNC IN
13
28
AM12
AS
14
27
AM13
DS
15
26
CS
R/W
16
25
AD7
AD0
17
24
AD6
AD1
18
23
AD5
AD2
19
22
AD4
V CC
20
21
AD3
9345-01.EPS
.
..
.
1/38
EF9345
PIN DESCRIPTION (All the input/output pins are TTL compatible)
Name
Pin
Type
Pin N°
Function
Description
MICROPROCESSOR INTERFACE
AD(0:7)
I/O
17-29
21-25
Multiplexed
Address/Data
Bus
AS
I
14
Address
Strobe
The falling edge of this control signal latches the address on the
AD(0:7) lines, the state of the Data Strobe (DS) and Chip Select (CS)
into the chip.
These 8 bidirectional pins provide communication with the
microprocessor system bus.
DS
I
15
Data Strobe
When this input is strobed high by AS, the output buffers are selected
while DS is low for a read cycle (R/W = 1).
In write cycle, data present on AD(0:7) lines are strobed by R/W low
(see timing diagram 2).
When this input is strobed low by AS, R/W gives the direction of data
transfer on AD(0:7) bus. DS high strobes the data to be written during
a write cycle (R/W = 0) or enables the output buffers during a read
cycle (R/W = 1). (see timing diagram 1).
R/W
I
16
Read/Write
This input determines whether the Internal registers get written or
read. A write is active low (”O”).
CS
I
26
Chip Select
The EF9345 is selected when this input is strobed low by AS.
MEMORY INTERFACE
ADM(0:7)
I/O
40-43
Multiplexed
Address/Data
Bus
Lower 8 bits of memory address appear on the bus when ASM is
high. It then becomes the data bus when ASM is low.
AM(8:13)
O
32-27
Memory
Address Bus
These 6 pins provide the high order bits of the memory address.
OE
O
2
Output Enable
When low, this output selects the memory data output buffers.
This output determines whether the memory gets read or written. A
write is active low (”0”).
WE
O
3
Write Enable
ASM
O
4
Memory
Address
Strobe
CLK
I
12
Clock Input
VSS
S
1
Power Supply
Ground.
VCC
S
20
Power Supply
+5V
This signal cycles continuously. Address can be latched on its falling
edge.
OTHER PINS
External TTL clock Input (nominal value : 12MHz, duty cycle : 50%).
VIDEO INTERFACE
R
G
B
O
O
O
7
8
9
Red
Green
Blue
I
O
10
Insert
HVS/HS
O
5
Sync. Out
PC/VS
O
6
Phase
Comparator /
Vertical Sync
SYNC IN
I
13
Synchro In
This input allows vertical and/or horizontal synchronizing the EF9345
on an external signal. It must be grounded if not used.
HP
O
11
Video Clock
This output delivers a 4MHz clock phased with the R, G, B, I signals.
2/38
These outputs deliver the video signal. They are low during the
vertical and horizontal blanking intervals.
This active high output allows to insert R : G: B : in an external video
signal for captioning purposes, for example. It can also be used as a
general purpose attribute or color.
This output delivers either the composite synchro (bit TGS4 = 1) or the
horizontal synchro signal (bit TGS4 = 0)
9345-01.TBL
When TGS4 = 1, this signal is the phase comparator output.
When TGS4 = 0, this output delivers the vertical synchro signal.
EF9345
BLOCK DIAGRAM
+5V
CMD
STA
ROW BUFFER 120 x 8
AD(0:7)
9
R
8
G
7
B
10
I
11
HP
8
ROM
15
8
R/W
16
CS
16
ATTRIBUTE
LOGIC
R2
8
R3
MPU ACCESS
R4
R3
R5
R3
R6
R3
R7
R3
ROR
R3
DOR
R3
MAT
PAT
TSG
R3
TRANSCODER
RFSH
R3
HVS/HS
6
PC/VS
13
TIMING
ADDRESS UNIT
5
SYNC. IN
GENERATOR
R3
EF9345
6
8
AM(8:13)
ADM(0:7)
4
2
3
12
ASM
OE
WE
CLK
9345-02.EPS
DS
R1
14
DATA BUS
AS
3/38
EF9345
ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Unit
VCC*
Supply Voltage
-0.3, 7.0
V
Vin*
Input Voltage
-0.3, 7.0
V
TA
Operating Temperature
Tstg
Storage Temperature
PDm
Maximum Power Dissipation
0, +70
o
-55, +150
o
C
C
0.75
W
9345-02.TBL
Symbol
* With respect to Vss.
Stresses above those hereby listed may cause permanent damage to the device. The ratings are stress ones only and functional operation of
the device at these or any conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect reliability. Standard MOS circuits handling procedure should be used to avoid possible damage
to the device.
Symbol
Supply Voltage
VIL
Input Low Voltage
VIH
IIN
4/38
Parameter
VCC
Input High Voltage :
CLK
Other Inputs
Min.
Typ.
Max.
Unit
4.75
5
5.25
V
-0.3
0.8
V
2.2
2
VCC
VCC
V
10
µA
Input Leakage Current
VOH
Output High Voltage (Iloa d = -500µA)
2.4
V
VOL
Output Low Voltage : Iload = 4mA ; AD(0:7), ADM(0:7), AM(8:13)
Iload = 1mA ; Other Outputs
0.4
0.4
V
PD
Power Dissipation
CIN
Input Capacitance
15
pF
ITSI
Three State (Off State) Input Current
10
µA
250
mW
9345-03.TBL
ELECTRICAL CHARACTERISTICS
VCC = 5.0V ±5%, VSS = 0V, TA = 0 to +70°C, unless otherwise specified.
EF9345
MEMORY INTERFACE
VCC = 5.0V ±5%, TA = 0 to + 70°C
Clock : fin = 12MHz ; Duty Cycle 40 to 60% ; tr, tf < 5ns
Reference Levels : VIL = 0.8V and VIH = 2V, VOL = 0.4V and VOH = 2.4V
Ident. N°
tELEL
1
Memory Cycle Time
Parameter
Min.
tD
2
Output Delay Time from CLK Rising Edge (ASM, OE, WE)
tEHEL
3
ASM High Pule Width
tELDV
4
Memory Access Time from ASM Low
Typ.
Max.
500
Unit
ns
60
120
ns
ns
290
ns
80
ns
tDA
5
Output Delay Time from CLK Rising Edge (ADM(0:7), AM(8:13))
tAVEL
6
Address Setup Time to ASM
30
ns
tELAX
7
Address Hold Time from ASM
55
ns
tCLAZ
8
Address Off Time
tGHDX
9
Memory Hold Time
tOZ
10
Data Off Time from OE
80
10
ns
ns
60
150
ns
tGLDV
11
Memory OE Access Time
tQVWL
12
Data Setup Time (Write Cycle)
tWHQX
13
Data Hold Time (Write Cycle)
30
ns
tWLWH
14
WE Pulse Width
110
ns
30
Table 1
VDD
Symbol
AM(8:13)
ADM(0:7)
AD(0:7)
Other
Outputs
C
100pF
50pF
RL
1kΩ
3.3kΩ
R
4.7kΩ
4.7kΩ
RL
Test
Point
MMD7000
or equivalent
R
9345-03.EPS
CL
9345-05.TBL
Figure 1 : Test Load
ns
ns
9345-04.TBL
Symbol
Figure 2 : Memory Interface Timing Diagram
T
1
CLK
2
3
2
4
ASM
8
5
ADM (0:7)
6
5
7
5
D IN
READ ADDRESS
6
7
D OUT
WRITE ADDRESS
AM (8:14)
2
9
2
11
2
10
2
12
13
9345-04.EPS
OE
14
WE
5/38
EF9345
MICROPROCESSOR INTERFACE
EF9345 is motel compatible. It automatically selects the processor type by using AS input latch to
state of the DS input.
No external logic is needed to adapt bus control
signals from most of the common multiplexed bus
microprocessors.
EF9345
6801
INTEL Family
Timing 1
Timing 2
AS
AS
ALE
DS
DS, E, φ 2
RD
R/W
R/W
WR
MICROPROCESSOR INTERFACE TIMING AD(0:7), AS, DS, R/W, CS
VCC = 5.0V ±5%, TA = 0 to + 70°C, CL = 100pF on AD(0:7)
Reference Levels : VIL = 0.8V and VIH = 2V on All Inputs ; VOL = 0.4V and VOH on all Outputs.
Symbol
Ident. N°
tCYC
1
Memory Cycle Time
Min.
400
Typ.
Max.
Unit
ns
tASD
2
DS Low to AS High (Timing 1)
DS High or R/W High to AS High (Timing 2)
30
ns
tASED
3
AS Low to High (Timing 1)
AS Low to DS Low or R/W Low (Timing 2)
30
ns
tPWEH
4
Write Pulse Width
200
ns
tPWASH
5
AS Pulse Width
100
ns
tRWS
6
R/W to DS Setup Time (Timing 1)
100
ns
tRWH
7
R/W to DS Hold Time (Timing 1)
10
ns
tASL
8
Address and CS Setup Time
20
ns
tAHL
9
Address and CS Hold Time
20
ns
tDSW
10
Data Setup Time (Write Cycle)
100
ns
tDHW
11
Data Hold Time (Write Cycle)
10
tDDR
12
Data Access Time from DS (Read Cycle)
tDHR
13
DS Inactive to High Impedance State Time (Read Cycle)
tACC
14
Address to Data Valid Access Time
ns
10
150
ns
80
ns
300
ns
9345-06.TBL
Parameter
Figure 3 : Microprocessor Interface Timing Diagram 1 (6801 Type)
2
1
3
2
DS
ASM
5
7
6
R/W
CS
8
10
9
WRITE CYCLE
AD (0:7)
11
ADDRESS
INPUT DATA
8
READ CYCLE
AD (0:7)
6/38
12
13
OUTPUT
DATA
ADDRESS
14
9345-05.EPS
9
EF9345
Figure 4 : Microprocessor Interface Timing Diagram 2 (INTEL Type) - Read Cycle
1
ALE
(Pin AS)
5
2
RD
(Pin DS)
3
2
WR
(Pin R/W)
12
CS
8
13
9
D OUT
ADDRESS
9345-06.EPS
AD(0:7)
14
Figure 5 : Microprocessor Interface Timing Diagram 2 (INTEL Type) - Write Cycle
1
ALE
(Pin AS)
5
2
RD
(Pin DS)
2
3
4
WR
(Pin R/W)
CS
AD(0:7)
9
ADDRESS
10
11
9345-07.EPS
8
D IN
7/38
EF9345
VIDEO INTERFACE R, G, B, I, HP, HVS/HS, PC/VS
VCC = 5.0V ±5%, TA = 0 to + 70°C, CLK Duty Cycle = 50%, CL = 50pF
Reference Levels : VIL = 0.8V and VIH = 2.2V on CLK Inputs. VOL = 0.4V and VOH = 2.4V on all Outputs.
Parameter
Min.
tSU
Setup Time R, G, B, I to HP
10
tHO
Hold Time R, G, B, I from HP
50
tD
Output Delay from CLK Edge
Typ.
Max.
Unit
ns
ns
60
ns
tPWCH
CLK High Pulse Width
30
ns
tPWCL
CLK Low Pulse Width
30
ns
9345-07.TBL
Symbol
Figure 6
CLK
tD
tD
R, G, B, I,
40 char/row
tD
t HO
HP
t SU
tD
tD
R, G, B, I,
80 char/row
tD
HVS/HS
PC/VS
INPUT CLK
t PWCH
CLK
9345-08.EPS
t PWCL
8/38
9345-09.EPS
Odd Frame
VS (TGS4 = 0)
Even Frame
Odd Frame
HVS (TGS4 = 1)
Even Frame
INTERLACED
VS (TGS4 = 0)
TGS0 = 1
TGS0 = 0
HVS (TGS4 = 1)
NON INTERLACED
2 lines
2.5 lines
VOL
VOH
VER TICAL SYNCHRO
R, G, B, I
HVS
HORIZONTAL SYNCHRO
Blanking 25 Lines
25 Lines
10µs
9.96µs
40 char/row
80 char/row
H Blanking
4.5µs
40µs
362.5 lines (TGS0 = 1)
Page 250 Lines
210 Lines
362 lines (TGS0 = 1)
312.5 lines (TGS0 = 0)
Bulk
Even frame 1/2 pulse
40µs
312 lines (TGS0 = 0)
Margin 16 Lines
10 Lines
6µs
6µs
Margin
32µs
Odd frame 1/2 pulse
64µs
Margin
18 Lines
14 Lines
6µs
6µs
Margin
4.5µs
Blanking 3 Lines
3 Lines
2.04µs
2µs
H Blanking
EF9345
Figure 7 : Vertical and Horizontal Synchronization Outputs (CLK = 12MHz)
9/38
EF9345
FUNCTIONAL DESCRIPTION
The EF9345 is a low cost, semigraphic, CRT controller.
It is optimized for use with a low cost, monochrome
or color TV type CRT (64ms per line, 50 or 60Hz
refresh frequency).
The EF9345 displays up to 25 rows of 40 characters or 25 rows of 80 characters.
The on-chip character generator provides a 128
standard, 5 x 7, character set and standard semigraphic sets.
More use definable (8 x 10) alphanumeric or semigraphic sets may be mapped in the 16 K x 8 private
memory addressing space.
These user definable sets are available only in 40
characters per row format.
Microprocessor Interface
The EF9345 provides an 8-bit, adress/data multiplexed microprocessor interface.
It is directly compatible with popular (6801, 8048,
8051, 8035, ...) microprocessors.
Registers
The microprocessor directly accesses 8 registers :
- R0 : Command/status register.
- R1, R2, R3 : Data registers.
- R4, R5, R6, R7 : Each of these register pairs
points into the private memory.
Through these registers, the microprocessor indirectly accesses the private memory and 5 more
registers :
- ROR, DOR : Base address of displayed page
memory and used external character generators.
- PAT, MAT, TGS : Used to select the page attributes and format, and to program the timing generator option.
Private Memory
The user may partition the 16 K x 8 private memory
addressing space between :
- Page of character codes (2 K x 8 or 3 K x 8),
- External character generators,
- General purpose user area.
Many types of memory components are suitable :
- ROM, DRAM or SRAM,
- 2 K x 8, 8 K x 8, 16 K x 4 organizations,
- Modest 500ns cycle time and 250ns access time
is required.
10/38
40 Characters per Row : Character Code
Formats and Attributes
Once the 40 characters per row format has been
selected, one character code format out of three
must be chosen :
- 24-bit fixed format :
All the attributes are provided in parallel.
- 8/24-bit compressed format :
All the attributes are latched.
- 16-bit fixed format :
Some parallel attributes, other are latched.
Character attributes provided :
- Background and foreground color (3 bits each),
- Double height, double width,
- Blinking,
- Reverse,
- Underlining,
- Conceal,
- Insert,
- Accentuation of lower case characters,
- 3 x 100 user definable character generator in
memory,
- 8 x 100 semi-graphic quadrichrome characters.
80 Characters per Row Format : Character
Code Format and Attributes
Two character code formats are provided :
- Long (12 bits) with 4 parallel attributes :
• Blinking,
• Underlining,
• Reverse,
• Color select.
- Short (8 bits) : no attributes.
Timing Generator
The whole timing is derived from a 12MHz main
clock input.
The RGB outputs are shifted at 8MHz for the 40
character/row format and at 12MHz for the 80
character/row.
Besides, the user may select :
- 50Hz or 60Hz vertical sync. frequency,
- Interlaced or not,
- Separated or composite vertical and horizontal
sync. ouputs.
Furthermore, a composite sync. input allows, when
it is required :
- An on-chip vertical resynchronization,
- An on-chip crude horizontal resynchronization,
- An off-chip high performance horizontal resynchronization by use of a simple external VCXO
controlled by the on-chip phase comparator.
EF9345
MEMORY ORGANIZATION
Logical And Physical Addressing
The physical 16-Kbyte addressingspace is logicaly
partitioned by EF9345 into 40-byte buffers (Figure 8). More precisely, a logical address is given by
an X, Y, Z triplet where :
- X = (0 to 39) points to a byte inside a buffer,
- Y = (0, 1 ; 8 to 31) points to a buffer inside a
1 Kbyte blocks,
- Z = (0 to 15) points to a block.
Obviously, 1 K = 210 = 1024 cannot be exactly
divided by 40. Consequently, any block holds 25
full buffers and a 24-byte remainder. Provided that
the physical memory is a multiple of 2 Kbytes, the
remainders are paired in such a way as to make
available :
- A full buffer (Y = 1) in each even block,
- A partial buffer (Y = 1 ; X = 32 to 39) in each odd
block.
Pointers
Each X, Y and Z component of a logical address is
binary encoded and packed in two 8-bits registers.
Such a register pair is a pointer (Figure 9). EF9345
contains two pointers :
- R4, R5 : auxiliary pointer,
- R6, R7 : main pointer.
R5 and R7 have the same format. Each one holds
an X component and the two LSB’s of a Z component. This packing induces a partitioning of Z in 4
districts of 4 blocks each.
R5, R7 points to a block number in a district. R4
and R6 have a slightly different format : Each one
holds a Y component and the LSB of the district
number. But R6 holds both district MSB
Figure 11 gives the logical to physical address
transcoding scheme performed on chip.
Figure 8 : Memory Row Buffer
Figure 9 : Pointer Auto Incrementation
X
8
X
32
39
8
32 39
Y = (0, 1 ; 8 to 31)
DISTRICT
d1
0
1
8
d’1
d0
4
3
2
1
0
R6
MAIN
POINTER
X = 0 to 39
BLOCK 0
(1Kbyte)
31
0
1
8
b0
b1
5
4
_
_
d’0
4
3
2
1
0
R7
0
R4
Y’ = (0, 1 ; 8 to 31)
3
2
1
BLOCK 1
Y
AUXILIARY
POINTER
X’ = 0 to 39
31
0
1
8
b’0
b’1
5
4
3
2
1
0
R5
BLOCK 2
Z = (0 to 15)
31
0
1
8
3
Y
0
2=0
4=0
6=0
BLOCK 3
1
3= 1
5= 1
7= 1
39
0
B
1
8
DISTRICT
1
D
0
31
0
9
2
9
1
X
31
Y
10 0
B
2
2
3
DISTRICT
Y incrementation
Modulo 24
Z incrementation/
decrementation
Modulo 4 on the
block number only
9345-11.EPS
80-BYTE ROW BUFFER
Notes : - Row buffers lay indide a district
- At two or three successive block addresses (modulo 4)
- First block address is even
9345-10.EPS
120-BYTE ROW BUFFER
X incrementation
Modulo 40
11/38
EF9345
Data Structure in Memory
Consequently, a page should not cross a district
boundary. General purpose memory area may be
used but should respect the buffer of row buffer
structure. See Figure 9 for pointer incrementation
implied by these data structures.
A page is a data structure displayable on the
screen up to 25 rows of characters. According to
the character code format, each row on the screen
is associated with 2 (or 3) 40-byte buffers. This set
of 2 (or 3) buffers constitutes a row buffer (Figure 8). The buffers belonging to a row buffer must
meet the following requirements :
- They have the same Y address,
- They have the same district number,
- They lie at 2 (or 3) successive (modulo 4) block
addresses in their common district.
Consequently, a row buffer is defined by its first
buffer address and its format.
Memory Time Sharing (See Figure 10)
The memory interface provides a 500 ns cycle time.
That is to say a 2 Mbyte/s memory bandwith. This
bandwith is shared between :
- Reading a row buffer from memory to load the
internalrow buffer(up to 120 bytes once each row),
- Reading user defined characters slices from memory (1 byte each µs),
- Indirect microprocessor read or write operation,
- Refresh cycles to allow DRAM use, with no overhead.
A fixed allocation scheme implements the sharing.
During these lines, no microprocessor access is
provided for 104µs ; this hold too when no user
defined character slices are addressed.
A page is a set of successive row buffers :
- With the same format,
- With the same district number,
- With the same block address of first buffer. This
block address must be even,
- Lying at successive (modulo 24) Y addresses.
Figure 10 : Memory Cycle Allocation
40µs
Notes : 1.
2.
3.
250/210
ACTIVE
SCAN
LINES
ACTIVE
DISPLAY
TIME
ONE ROW = 10 SCAN LINES
µP
MEMORY CYCLE
LD
LD
RFSH
µP
DUM : dummy cycle
µP : indirect access to memory
RFSH : refresh cycle
UDS : slice read cycle
LD : read cycle to load the internal row buffer
INACTIVE LINE
DUM
µP
LAST ROW LINE
UDS
LD
FIRST ROW LINE
UDS
LD
OTHER ROW LINE
UDS
µP
RFSH
µP
RFSH
1µs
1µs
40µs
24µs
9345-12.EPS
312/362
SCAN
LINES
24µs
Dummy cycles are read cycles at dummy addresses.
RFSH cycles are read cycles performed by an 8-bit auto-incrementing counter. Low order address byte ADM(0:7) cycles
through its 256 states in less than 1ms.
The microprocessor may indirectly access the memory once every µs, except during the first and the last line of a row, when
the internal buffer must be reloaded.
Figure 11 : Logical to Physical Address Transcoding Performed On-chip
Z (0 to 15)
D
LOGICAL
ADDRESS
3
Y (0, 1 ; 8 to 31)
X (0 to 39)
B
2
1
0
4
3
2
1
0
5
4
3
2
1
0
2
1
0
PHYSICAL
ADDRESS
12/38
13
12
11
10
9
8
7
6
5
4
3
9345-13.EPS
TRANSCODING
EF9345
Table 2
Physical Address AM(3:10)
X and Y
Condition
Y≥8
10
9
8
7
6
5
4
3
X5 = 0
b0
Y4
Y3
Y2
Y1
Y0
X4
X3
X5 = 1
b0
0
0
Y2
Y1
Y0
Y4
Y3
Y0 = 0
Y<8
Y0 = 1
b0
0
0
X5
X4
X3
0
0
b0 = 0
X3
0
0
I
X5
X4
0
0
b0 = 1
I
0
0
I
X5
X4
0
0
SCREEN FORMAT AND ATTRIBUTES
The screen format and attributes are programmed
through 5 indirectly accessible registers : ROR,
TGS, PAT, MAT and DOR. IND command allows
accessing these registers. TGS is also used to
select the timing generator options (see Table 3).
Row and Character Code Format
PAT7 ; TGS(6:7)
Two row formats and 5 character code formats are
available but cannot be mixed in a given screen.
DOR register interpretation is completely row format dependentand is discussed in the correspondnig 40 char/row and 80 char/row section.
Screen Partition - Page Pointer ROR
(See Table 3)
The screen is partitioned into 3 areas :
- The margin,
- The service row,
- The bulk of remaining rows.
MAT(0:3) declares the color of the margin and the
value IM of its insert attribute.
ROR register points to the page to be displayed and
gives the 3 MSB’s of the Z address : Z0 = 0
implicitly ; the page block address must be even.
YOR gives the first row buffers to be displayed at
the top of the bulk area. The next row buffers to be
displayed are fetched sequentiallyby incrementing
the Y address (modulo 24). This address never
gets out of the origin block. Incrementation of YOR
by the microprocessor yields a roll up.
Service Row : TGS5 - PAT0
The service row is displayed for 10 TV lines on top
of the screen and does not roll. Following TGS5, it
is fetched from the origin block at either Y = 0 or Y
= 1. The Y = 1 is a partial row buffer. It can be used
only with variable 40 char./row and an 8 byte
attribute file. The service row may be disabled by
PAT0 = 0 ; it is the displayed as a margin extension.
BULK : TGS0 ; PAT(1:2) ; MAT7
It is displayed after the service row for 200 or 240
TV lines according to TGS0. Each row buffer is
usually displayed for 10 TV lines. However,
MAT7 = 1 doubles this figure. Then every character
appears in double height (double height characters
are quadrupled).
PAT1 = 0 and/or PAT2 = 0 disables respectively the
upper 120 lines and/or the lower 80/120 lines of the
bulk.
When disabled, the corresponding TV lines are
displayed as a margin extension.
Cursor MAT(4:6)
To be displayed with the cursor attributes, a character must be pointed by the main pointer (R6, R7)
and MAT6 must be set. The cursor attributes are
given by MAT(4:5) :
- Complementation : the R, G and B of each pixel
is logically negated.
R, G, B → R, G, B
- Underline : the underline attribute of this character is negated.
- Flash : the character is periodically displayed
with, then without, its cursor attributes (50% /
50% ; ≈1Hz).
Flash Enable (PAT6) - Conceal Enable (PAT3)
Any character flashing attribute is a ”don’t care”
when PAT6 = 0. When PAT6=1, a character flashes
if its flashing attribute is set. It is then periodically
displayed as a space (50% / 50% ; 0.5Hz).
PAT3 is a ”don’t care” for 80 char./row formats.
When any 40 char./row format is in use :
- If PAT3 = 0 the conceal attribute of any character
is a don’t care
- If PAT3 = 1, the conceal attribute of each character is interpreted : a concealed character appears
as a space on the screen.
13/38
EF9345
During retrace, margin and extended margin periods, the I output pin delivers the value of the insert
margin attribute.
I = IM = MAT4
During active line period, the I output state is controlled by the Insert Mode and i, the insert attribute
of each character. The I output pin may have
several uses (see Figure 12) :
- As a margin/active area signal in the active area
mark mode.
- As a character per character marker signal in the
character mark mode.
- As a video mixing signal in the two remaining
modes, provided that the EF9345 has been vertically and horizontally synchronized with an external video source : the I pin allows mixing RGB
outputs (I = 1) and the external video signal
(I = 0). This mixing can be achieve by switching
or Oring. It may occur for the complete character
window (Boxing Mode) or only for the foreground
pixels (Inlay Mode).
Table 3 : Video Outputs During Active Periods
Char. Level
Insert Mode
i
Pixels
Active Area Mark
Character Mark
Boxing
Inlay
Notes :
1.
2.
14/38
(1)
Outputs
I
R, G, B
(2)
–
1
X
0
–
0
X
1
–
1
X
0
–
0
BLACK
1
–
1
X
0
–
0
BLACK
1
BACKGND
0
BLACK
FOREGND
1
X
Pixel type :
– : Dont’t care.
FOREGRND = A foreground pixel is :
- Any pixel of a quadrichrome cha racter,
- A pixel of a bichrome character ge nerated from a ”1” in the
character generator cell.
RGB outputs :
X : Not affected.
BLACK : Forced to low level.
Timing Generator Options : TGS(0:4)
TGS(0:1) select the number of lines per frame :
TGS1
0
0
1
1
TGS0
0
1
0
1
LINES
312
262
312.5
262.5
NON INTERLACED
INTERLACED
The composite incoming SYNC IN signal is separated into 2 internals signals :
- Vertical Synchronization In (VSI),
- Horizontal Synchronization In (HSI).
TGS3 enable VSI to reset the internal line count.
SYNC IN input is sampled at the beginning of the
active area of each line. When the sample transits
from 1 to 0, the line count is reset at the end of the
current line.
TGS2 enables HSI to control an internal digital
phase lock loop. HSI and on-chip generated HS
Out are considered as in phase if their leading
edges match at ±1 clock period.
When they are out of phase, the line period is
lengthened by 1 clock period (≈80ns).
TGS4 controls the SYNC OUT pins configuration :
TGS4
1
0
HVS / HS
Composite Sync
H Sync Out
PC / VS
PC
V Sync Out
PC is the output of the on-chip phase comparator.
An external VCXO allows a smoother horizontal
phase lock than the internal scheme.
Figure 12
PC
SYNC IN
D
Q
D
Q
HS
HVS/HS
CLK
VS
÷6
9345-14.EPS
Insert Modes : PAT(4:5)
EF9345
Table 3 : Screen Format
MEMORY
0
MARGIN
BLOCK ORIGIN
(even)
39
0
1 TGS5
8
SERVICE ROW
Y ORIGIN
Y ORIGIN + 1
BULK
YOR
YOR +1
31
Service
Row
7
6
5
Z3
Z1
Z2
4
3
2
1
0
ROR (r = 7)
YOR
Origin row address
YOR = (8 to 31)
YOR
+23
YOR +1
Block origin (even)
Service row select
(Y = 1/0)
YOR +2
7
6
5
4
3
2
1
0
TGS (r = 1)
525/625 lines
Char Code
40 CHAR LONG
40 CHAR VAR
40 CHAR SHORT
80 CHAR LONG
80 CHAR SHORT
PAT7 TGS7 TGS6
0
0
1
0
0
0
0
0
1
1
Interlaced
Horizontal resync enable
0
1
0
1
0
Vertical resync enable
Sync out pins configuration
1 : composite sync
+ phase comparator
0 : V sync + H sync
7
6
5
4
3
2
1
0
PAT (r = 3)
Service row enable
INLAY
BOXING
CHARACTER MARK
ACTIVE AREA MARK
PAT5 PAT4
0
0
1
1
Upper bulk enable
0
1
0
1
Lower bulk enable
Conceal enable
Flash enable
7
Cursor Display mode
FIXED COMPLEMENTED
FLASH COMPLEMENTED
FIXED UNDERLINED
FLASH UNDERLINED
MAT5 MAT4
0
1
0
1
Note : PROGRAMMING BIT VALUE
1 = True, 0 = False
0
0
1
1
6
5
4
3
2
1
0
iM
BM
GM
RM
MAT (r = 2)
Margin color
Margin insert
9345-15.EPS
Insert Mode
Cursor display enable
Double height
15/38
EF9345
40 CHAR/ROW CHARACTER CODES
To display pages in 40 character per row format,
one out of three character code formats must be
selected :
- Fixed long (24 bits) code : all parallel attributes.
- Fixed short (16 bits) code : mix of parallel and
latched attributes.
- Variable (8/24 bits) code : all latched attributes.
Fixed short and variable codes are translated into
fixed long codes by EF9345 during the internal row
buffer loading process. The choice of the character
code format is obviously a display flexibility/memory size trade off, left up to the user.
Fixed Long Codes
This is the basic 40 char./row code. Each 8 pixels
x 10 lines character window, on the screen is
associated with a 3-byte code in memory, namely
the C, B and A bytes (Figure 13). A row on the
screen is associated with a 120 byte row buffer in
memory.
3-BYTE Code Structure
1. C7 is a don’t care. Up to 128 characters may
be addressed in each set. Each user definable
set holds only 100 characters : C byte value
ranges from 00 to 03 and 20 to 7F (hexa).
2. B(4:7) give the type and set number of the
character.
3. All the bichrome characters have the same
attributes except that alphanumerics may be
underlined,semi-graphics cannot.Accentuated
alphanumerics allow orthogonal accentuating
of any one of the 32 lower case ROM characters
with any of 8 accents (see Figure 27).
4. Bichrome and quadrichrome characters use
two different coloring schemes.
For bichrome characters, character code byte A
defines a two color set by giving directly two color
values (Figure 14). The negative attribute exchanges the two values. Each bit of slice byte
selects one color value out of two.
The ”A” byte in a quadrichrome character code
defines an ordered 4 color set (Figure 15). When
more than 4 bits are set, higher ranking bits are
ignored. When less than 4 bits are set, the color set
is completed with implicit ”white” value. The slice
byte is shifted 2 bits at once at half the dot frequency (≈4MHz).
Each bit pair designates one color out of the 4 color
sets.
Quadrichrome characters allow displaying up to 4
different colors (instead of 2) in any 8 x 10 window
at the penalty of an halved horizontal resolution.
By programming the R attribute in byte B, one may
chose to keep the full vertical resolution (1 slice per
line) or to halve it (each slice is repeated twice). In
any case, it is possible to change the color set freely
from window to window and to mix freely all the
character types. So, fairly complex pictures may be
displayed at low memory cost.
Handling Long Codes
The KRF command allows an easy X, Y random
access or an X sequential access to/from the microprocessor from/to a memory row buffer (Figure 16).
Figure 13 : 40 Char/Row Fixed Long Codes
Bichrome Code
7
6
5
4
3
2
Quadrichrome Code
1
0
7
6
1
1
5
4
3
2
1
0
k
R
i
C BYTE
N
B1
G1
R1
F
m
B0
H
G0
i
R0
B BYTE
Insert
Insert
Double height
Low resolution
Conceal
Double width
Subset index
(low resolution only)
Type and set
Set number
A BYTE
Background color C 0
Flash (blink)
Foreground color C1
Negative (reverse video)
16/38
4 COLOR PALETTE
9345-16.EPS
L
EF9345
Figure 13 (Continued)
7
Number of Character
per Set
Set
Name
6
5
4
C(0:6)
0
1
1
1
0
128 Standard Mosaïcs
32 Strokes
G11
128 Alphanumerics
G0
0
0
U
N
D
E
R
L
I
N
E
0
1
0
1
ALPHA
G21
100 Semi-Graphic UDS
G’10
1
1
100 Semi-Graphic UDS
G’11
8 Sets of 100
X
X
Q0
to
Q7
1
B
I
C
H
R
O
M
E
G20
0
0
1
Accentuated Lower Case Alpha
G’0
0
Cell
Location
SEMI-GR
100 Alpha UDS
0
1
G10
Set
Type
Quadrichrome Character
ON-CHIP
ROM
EXTERNAL
MEMORY
SEMI-GR.
9345-08.TBL
Type and Set
Code : B(4:7)
Quadrichrome
Note : Programming bit value : 1 = True ; 0 = False.
Figure 14 : Coloring with Bichrome Characters
G
R
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Color Value
Black
Red
Green
Yellow
Blue
Magenta
Cyan
White
7
6
5
4
3
2
1
0
N
B1
G1
R1
F
B0
G0
R0
3
3
N=1
Exchanges values
C0
C1
SHIFTED SLICE BYTE
(LSB first)
Foreground
color
7
6
5
4
3
2
1
0
0
1
0
1
0
0
1
0
Background
3 color
3
MUX
Foreground
3
Pixel color
R, G, B
17/38
9345-17.EPS
B
CHARACTER
CODE A BYTE
EF9345
Figure 15 : Coloring with Quadrichrome Characters
CHARACTER
CODE A BYTE
7
6
5
4
3
2
1
0
0
1
0
1
1
0
1
0
ORDERED
COLOR
COLOR VALUES
SET
_
Black
Red
Green
Yellow
Blue
Magenta
Cyan
White
7
6
5
4
3
2
1
0
0
1
C0
_
C1
C2
_
C3
_
C3
C1
C2
3
3
Color set
C0
3
3
2
MUX (1 out of 4)
3
C1 (yellow)
9345-18.EPS
SLICE BYTE SHIFTING :
2 bits at once at half the pixel frequency
Figure 16 : Fixed Long Codes in Memory 120 Byte Row Buffer
X
KRF COMMAND
R1
R2
R3
C
B
A
R4
R5
R6
R7
D, Y
B, X
0
D district
number
C
B (even)
B
B+1
A
B+2
9345-19.EPS
Y
39
18/38
EF9345
Variable Codes
In many cases, successive characters on screen
belong to the same character set and have the
same attributes. Variable codes achieve memory
saving by storing B and A bytes only when it is
required by exploiting the C7 bit.
C7 = 1 This is a long 3-byte code.
Character set and attribute values are
completely redefined by B and A bytes.
C7 = 0 This is a short 1-byte code.
Character set and attributes value are
identical to the previous code.
A further saving comes from the fact that an accentuated alphabetic character is, more often than not,
followed by a not accentuatedalphabetic character.
So, G20 or G21 sets are processed as one-shot
escape with return to G0. For normal operation,
variable codes should obey the following rules :
- The first character code of any row (X = 0) should
be long.
- A character code may be short when it has the
same attributes as the previous character code
and belongs to the same set.
However :
- Any code belonging to G20 or G21 must be long
and must be repeated if the character is double
width,
- A code belonging to G0 following a G20 or G21
code may be short.
Handling the Variable Codes
During the display process, a row of variable code
should be laid in an 80/120 byte row buffer. The
first buffer holds the C bytes. The second buffer
holds the B, A file providing up to 20 long codes per
row (Figure 18). In the exceptional case when this
is not enough, the second buffer overflows in the
third one. Every code may then be long. Variable
codes can almost always achieve a memory saving
over long fixed codes and can never be worse.
The KRV command gives a very easy sequential
access to/from a row buffer from/to the microprocessor. This command automatically updates the C
byte and B, A file pointers (the last one when C7 is
set).
Figure 17 : Expansion/Compression Move
X
EXP and CMP
COMMANDS
-
R4
R5
R6
R7
ZW, YW
BF, XF
D, Y
B, X
0
39
B
DW
BW (even)
YW
EXPANDED
CODE
A
BW + 1
D
C
B (even)
Y
VARIABLE
CODE
BA
B + 1 = BF
9345-20.EPS
R1
R2
R3
XF
19/38
EF9345
Random access to a variable code is obviously not
as easy. The EXP, KRE and CMP commands are
designed to facilitate this task (figure 17).
Fixed Short Codes
These fixed 16 bits codes achieve memory saving
by anotherway. They may be easier to handlethan
variable codes. The penalty is in lesser display
capabilities :
- Accentuated character sets are no longer available : accentuated characters must be individually provided by the character generators.
- G’11 and quadrichrome sets cannot be reached.
- Some attributes are latched and can be changed
only while displaying a space (delimitor code).
The EXP command translates a full row of variable
codes into a row of expanded codes. Expanded
codes are generally not displayable by very similar
to the long codes.
KRE gives a random access to an expanded code
and makes it appear as a regular long code.
The CMP command translates a full row of expanded code into a row of variabble codes and
minimizes the file size in the process.
These commands use a buffer pair as working
area.
The KRG command allows an easy access from/to
an 80-byte row buffer in memory to/from the microprocessor (Figure 19). Figure 20 gives the fixed
short to fixed long translation process which occurs
for each row - while loading the internal row buffer
before display.
Figure 18 : Variable Codes in memory
Figure 19 : Fixed Short Codes in Memory 80
X
R1
R2
R3
C
B
A
R4
R5
R6
R7
BF, XF
D, Y
B, X
0
39
D district
number
X
KRG COMMAND
Y
39
District
BA
B + 1 = BF
XF :
file pointer
R1
R2
R3
A*
B*
W
R4
R5
R6
R7
D, Y
B, X
A*
B (even)
B*
B+1
Y
B+2
9345-21.EPS
Overflow
buffer
20/38
0
B (even)
9345-22.EPS
KRV COMMAND
1
1
SEMIGRAPHIC
DEL
9345-23.EPS
1
5
X
X
X
0
0
#00
#00
1
0
ALPHA
0
0
6
X
0
7
X
X
X
X
X
4
B*
3
X
X
X
X
X
2
U
X
X
X
X
X
i
X
X
X
X
X
1
m
X
X
X
X
X
0
C0
C0
1
1
L
0
N
C0
1
L
C0
5
6
N
1
0
7
FIXED SHORT CODE
4
H
H
A*
C1
F
C1
C1
C1
F
F
C1
F
1
C1
2
F
3
0
:
:
:
:
0
X
X
X
X
X
0
X
X
X
X
X
Don’t care
Conceal
Flash
Insert
0
#00
0
m
F
i
X
X
X
#00
1
0
X
C
0
X
X
X
X
X
N
U
X
DEL
0
X
X
X
X
X
:
:
:
:
0
X
X
X
X
X
0
0
1
1
0
1
1
0
Negative
Underline
Character code
Deliminator
0
0
0
0
0
1
1
0
0
0
0
0
U
L
U
0
0
0
L
0
0
U
L
H
C0
C1
0
m
:
:
:
:
m
m
i
i
i
i
i
i
1
0
N
0
0
N
Double width
Double height
Background color
Foreground color
0
0
H
0
m
m
H
m
FIXED LONG CODE
B
C1
C1
C1
C1
C1
C1
A
Latched
attribute
0
F
F
F
F
F
C0
C0
C0
C0
C0
C0
TRANSLATION PROCESS
The translation process operates through 3 elementary operations :
- Field-to-field : a character code or an attribute value (i.e : C0, flashing) is directly loaded from short to long code.
- Field-to-constant the decoding of a short code forces the value of the equivalent long code attribute. For example, semigraphic short character forces normal size (H = 0, L = 0) attributes.
- Latched attributes : at the beginning of each row, these attributes are reset (no underline, not concealed, no insert, black background). Then, they keep their current value until modified by either a field to constant operation.
SEMIGRAPHIC
ALPHA
Note :
M
E
M
O
R
Y
R
O
M
Negative
space
G’10
G’0
G10
G0
SET
EF9345
Figure 20 : Fixed Short Code to Fixed Long Code Translation
21/38
EF9345
USED DEFINED CHARACTER GENERATOR IN MEMORY : DOR REGISTER
With 40 char / row, the elementary window dimensions on the screen are 10 slices x 8 pixels. Thus,
a character cell holds 10 bytes in memory and 4
character cells are packed in one 40-byte buffer
(Figure 21). However, 5 bytes of a low resolution
quadrichrome cell are enough to fill up to window.
In this case, 8 character cells can be packed in one
40-byte buffer.
Figure 21 : Packing UDS Cells in Memory
~
~
Character set base address
and
Character set number
~
~
0
39
Z block address
0
8
9
ONE
1K BYTE
BLOCK
4 CHARACTER CELLS
C6 C5 C4 C3 C2 C1 C0
Y
Slice number
(0 to 9)
31
5
~
~
~
~
MEMORY
PIXELS
4
3
2
1
0
NT
X
A CHARACTER SET LAYS IN ONE BLOCK
(up to 100 characters per set)
0 1 2 3 4 5 6 7
SLICE
NUMBER
(0 to 9)
NT
0
1
2
3
4
5
6
7
8
9
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
ONE SLICE
ONE BYTE
SLICES ARE SHIFTTED LSB FIRST
Character code C byte
(0 to 3 ; 32 to 127)
C6 C5 C4 C3 C2 C1 C0
k
TWO SLICES
ONE BYTE (repeated)
5
+
2
1
0
NT
NT*
5
4
3
2
1
0
X
A SPECIAL CASE : LOW RESOLUTION QUADRICHROME CELL (R = 1)
(up to 200 characters per set)
22/38
NT* = 5k +NT
k = Subset index
9345-24.EPS
SLICE
NUMBER
(0 to 4)
NT
0
0
1
1
2
2
3
3
4
4
EF9345
- Assign a character number to each character
belonging to this set, character numbers range
from 0 to 3 and 32 to 127.
The cells of one given character set should be layed
in one block.
Up to 100 character cells may be addressed in
each set (or 200 for low resolution quadrichrome
only). The location in memory, where to fetch the
sets in use, are declared by DOR register (Figure 22). For each type of set, it gives the MSB(s)
of the Z block address. EF9345 reads the Z LSB(s)
in the B byte of the (equivalent) long code. As usual,
the character code is read in the C byte. NT is
derived from the TV line rank in the row and the
double height status.
• It is binary coded into 7 bits C(0:6) - C(0:6)
will be loaded later on into a C byte character code in order to display the character.
- A pointer to a character slice in memory is then
manufactured from :
• The character number C(0:6)
• The slice number NT(0:3)
• The block number assigned to the set
Z(0:3)
Loading User Defined Character Set
Before loading a character set into RAM, the user
must :
- Assign a name to the set :
• G’0, G’10 or G’11 for bichrome characters.
• From Q0 to Q7 for quadrichrome characters.
Figure 23 shows how to proceed with the auxiliary
pointer and the OCT command.
Note : The main pointer may be also used. When
sequentially accessing slices of a given
character, auto incrementation is helpless.
Figure 22 : UDS Fetch to Display
~
MEMORY
~
DOR G’0 (alpha UDS)
G’0
1 Kbyte
~
~
DOR G’1
(semi-grap hic UDS)
G’10
Even block
G’11
Odd block
7
6
5
4
3
2
1
0
Z3
Z3
Z2
Z1
Z3
Z2
Z1
Z0
DOR Q DOR G’1
DOR register
DOR G’0
2 Kbytes
~
~
DOR Q
(quadrichr ome)
7
6
5
4
3
2
1
0
1
X
X
X
X
X
X
X
CHARACTER LONG
CODE B BYTE
Q0
Q1
8 Kbytes
~
Q7
~
~
UDS Set
#
Z Address
B7 B6 B5
Z3
Z2
Z1
Z0
G’0
1
0
0
DOR3
DOR2
DOR1
DOR0
G’11
1
0
1
DOR6
DOR5
DOR4
B4
Q0 - Q7
1
1
X
DOR7
B5
B3
B4
9345-25.EPS
~
23/38
EF9345
Figure 23 : Accessing a Character Slice in Memory Using OCT Command with Auxiliary Pointer
R1 SLICE
R2
R3
R4
Z0
R6
Z1
NT
C1 C0
Y
X
Z3
9345-26.EPS
R5
Z2 C6 C5 C4 C3 C2
R7
On-Chip Character Generator
- G0 set is common to 40 and 80 char./row modes
(Figure 24 and Figure 34).
- G10 is the standard mosaïc set for videotex (Figure 25).
- G11, G20 and G21 cannot be reached from the
16-bit short fixed codes (Figure 26 and Figure 27).
Displaying the Attributes
1. For normal operation, a double height and/or
double width character must be repeated in
memory in two successive Y and/or X
positions. The user may otherwise freely mix
any character size.
24/38
2. The attributes are logically processed in the
following order :
- Underline or underline cursor : foreground
forced on the last slice (NT = 9).
- Flash : background periodically forced on the
whole window (0.5Hz). The phase depends on
the negative attribute.
- Conceal : background forced permanently on
the whole window. A concealed character
neither blinks nor is underlined.
- Negative : exchange the background and
foreground color values when set.
- Coloring.
- Complemented cursor mode.
- Insert : black color forced when required.
3. Basic pixel shift frequency : fCLK x 2/3 = 8MHz.
EF9345
Figure 24 : G0 Alphanumeric Character Set in 40 Character/Row Mode
C3
C2
C1
C0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
9345-27.EPS
C6
C5
C4
25/38
EF9345
Figure 25 : G10 Semigraphic Character Set
26/38
C3
C2
C1
C0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
SEPARATED SEMI-GRAPHIC
0
0
0
0
0
0
1
1
0
1
0
1
1
0
0
MOSAIC SEMI-GRAPHIC
1
1
1
0
1
1
1
0
1
9345-28.EPS
C6
C5
C4
EF9345
C3
C2
C1
C0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
C5
0
0
C4
0
1
9345-29.EPS
Figure 26 : G11 Stroke Set
27/38
EF9345
Figure 27 : G20 and G21 Accentued Character Sets
0
0
0
1
1
0
1
1
C3
C2
C1
C0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Example :
7
6
5
4
3
2
1
0
Byte C
X
0
1
0
0
0
0
1
Byte B
0
1
0
0
X
X
X
X
Byte A
X
X
X
X
X
X
X
X
X = bits defined by user
28/38
C4
B5
0
1
9345-30.EPS
C6
C5
EF9345
80 CHAR/ROW CHARACTER CODES
To display pages in 80 character per row format,
one of two character code formats must be selected :
- Long (12 bits) code : 4 parallel attributes and large
on-chip 1024 semigraphic character set,
- Short (8 bits) code : no attribute, no semigraphic
set.
Short Codes
They are derived from the long code by giving a 0
implicit value to each bit of the A nibble : positive,
not underlined, not flashing.
Packing the Codes in Memory
Long codes are paired. A pair is packed in a 3-byte
word. Therefore, the 80 codes of a row fill a 120byte row buffer (Figure 29). The left most position
on the screen is even. Its corresponding C byte is
at the beginningof the first buffer. The next position
on the screen is odd. Its corresponding C byte is at
the beginning of the second buffer. Both nibbles
are packed in the third buffer. With short codes, the
same scheme yields 80-byte row buffers.
Both formats address the on-chip G0 set (128
characters 6 x 10). None allows UDS addressing.
Long Codes
Each 6 pixels x 10 lines character window on the
screen is associated with a 12-bit code in memory,
namely a C byte and an attribute nibble A (Figure 18). C7 bit designates the set.
- Alphanumeric set : C7 = 0
C(0:6) designates one out of 128 alphanumeric
characters in the G0 on-chip set. This set is
common to the 40 char/row format, with the 2 right
most columns truncated (see Figure 34).
A(0:3) gives 4 parallel attributes.
- Mosaïc set : C7 = 1
A(1:3) and C(0:6) address a dedicated mosaïc
character. Each of these address bits controls the
foreground/background status of a 3 pixels x 2
lines sub-window : foreground when the bit is set.
Access to the Codes in Memory
KRL command transfers 12 bits from/to the R1 and
R3 registers to/from memory. The read modify
write operation, necessary to write the A nibble in
memory, is automatically performed provided that
the A nibble is repeated in the R3 register (Figure 30). Dedicated auto-incrementationis also performed when required.
KRC command does a similar job for the short
codes (Figure 31).
A very simple scheme allows the microprocessor
to transcode an horizontal screen location into a
pointer (Figure 32). The joint use of this scheme
with the dedicated command alleviates all the
packing/unpacking troubles.
A0 provides a color select attribute.
Figure 28 : 80 Char/Row Character Code
7
6
5
4
3
2
1
0
3
2
1
0
7
6
5
4
3
2
1
0
3
2
1
0
0
X
X
X
X
X
X
X
N
F
U
D
1
X
X
X
X
X
X
X
X
X
X
D
ALPHANUMERIC CHAR CODE
N = Negative
F = Flash
U = Underline
D = Color set
128 ALPHANUMERICS
In G0 set.
A
C
A
MOSAIC CHAR CODE
0
1
2
3
4
5
6
7
8
9
3 pels
3 pels
C0
C1
C2
C3
C4
C5
C6
A1
A2
A3
DEDICATED
MOSAIC SET
9345-31.EPS
C
29/38
EF9345
Figure 29 : 80 Char/Row Character Code Packing
6
5
4
3
2
1
0
7
6
5
4
3
2
1
C
0
B (even)
PACKING 2 CODES
IN 3 BYTES
IN MEMORY
C
B +1
A
A
EVEN POSITION
ODD POSITION
B +2
9345-32.EPS
7
Figure 30 : KRL Command : Sequential Access to Long Codes
KRL Command
R1
R2
R3
C
A
R4
R5
R6
R7
D, Y
B, X
D district
number
Y
A
B
even
Even
position
B +1
odd
Odd
position
B +2
R3
7
6
5
4
3
2
1
0
N
F
U
D
N
F
U
D
The A nibble should be respected
30/38
9345-33.EPS
X
EF9345
Displaying the Attributes - DOR Register
with a background color same as the margin
color. The foreground color is selected in DOR
register by the D attribute.
- Negative : when the character is negative, background and foreground colors are exchanged. In
complemented CURSOR position, these colors
are complemented.
- Insert : the D attribute selects one insert value in
DOR register. This attribute is then processed up
to the current insertion mode (see screen format
and attribute insert section.
Short code and mosaïc characters are not flashing,
not underlined and ”positive”.
The attributesare processedin the following order :
- Underline or underlined cursor : foreground is
forced on the last slice (NT = 9).
- Flash : background is periodically (0.5Hz - 50%)
forced on all the window. The phase depends on
the negative attribute.
- Color select : a ”positive” character is displayed
Figure 31 : KRC Command : Sequential Access to Short Codes
KRC Command
R1
R2
R3
C
-
R4
R5
R6
R7
D, Y
B, X
D district
number
B (even)
Y
9345-34.EPS
B + 1 (odd)
X
Figure 32 : Transcoding an Horizontal Screen Location into a R7 Pointer
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Rotate right
b0 b1 X5 X4 X3 X2 X1 X0
CHARACTER POSITION (0 to 79)
9345-35.EPS
b1 X5 X4 X3 X2 X1 X0 b0
X = (0 to 39)
Block parity
Figure 33
MAT
6
5
4
3
2
1
I1
B1 G1 R1
I0
B0 G0 R0
C1
C0
D=1
D=0
X
X
0
BM G M R M
D
N
0
0
1
1
0
1
0
1
Background Foreground
Color
Color
CM
C0
CM
C1
C0
CM
C1
CM
i
i0
i0
i1
i1
9345-36.EPS
DOR
7
CM
The pixel shift frequency is fCLK (12MHz)
31/38
EF9345
Figure 34 : G0 Alphanumeric Character Set in 80 Character/Row Mode
32/38
C3
C2
C1
C0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
9345-37.EPS
C7
C6
C5
C4
EF9345
MICROPROCESSOR ACCESS COMMANDS
A microprocessor bus cycle may transfer one byte
from/to the microprocessor to/from a directly addressable register. These registers provide an indirect access :
- To/from 5 on-chip indirect registers : ROR, DOR,
MAT, PAT and TGS.
- To/from the private memory.
Due to address/datamultiplexing, a bus cycle is a
2 phase process (see Timing diagram 1 or Timing
diagram 2).
EF9345 is selected when the following condition is
met : ASN = 2(Hexa) and LCS = 0.
Therefore, EF9345 is mapped in the hexadecimal
microprocessor addressing space form XX20 to
XX2F, where XX is up to the user. Xhen EF9345 is
not selected, its AD bus pins float and no register
can be modified.
Figure 35
Address Phase
The falling edge of AS latches to AD(0:7) bus state
and CS signal into the temporary A address register
(Figure 36).
- A(0:2) = i :
This register index designates one out of 8 direct
access registers Ri.
- A3 = XQR :
This is the execution request bit.
- A(4:7) = ASN :
This is the Auto-Selection Nibble
- A8 = LCS :
This is the latched value of CS input pin.
8
7
6
5
4
3
2
1
0
ADDRESS
REGISTER
(temporary)
Index register
Execution request (XOR)
Auto select nibble
(compared to 0010)
9345-38.EPS
LCS (latched CS)
Figure 36 : Direct Access Registers
7
6
5
4
3
2
1
0
7
R1
7
R3
5
4
3
CODE
DATA
REGISTERS
R2
6
6
5
2
1
R5
B’
Y’
AUXILIARY
POINTER
X’
COMMAND
REGISTER
(write only)
PAR
4
3
2
1
0
D’
R4
0
R0
0
0
STATUS
REGISTER
(read only)
V sync status
R17
R7
B
LXa (X’ = 39)
Y
X
MAIN
POINTER
LXm (X = 39)
9345-39.EPS
D
R6
Alarm
Busy
33/38
EF9345
Data Phase - Registers
When EF9345 isselected and while AS input is low,
the Ri register is accessed.
R0 designates a write-only COMMAND register or
a read-only STATUS register.
R1 to R7 hold the arguments of a command. They
are read/write registers.
R1, R2, R3 are used to transfer the data.
R4, R5 hold the Auxiliary Pointer (AP).
R6, R7 hold the Main Pointer (MP).
(see memory organization ; pinter section for
pointer structure).
p:
Pointer select
1 : auxiliary pointer
0 : main pointer
Source, destination select
01 : source : MP ; destination : AP
10 : source : AP ; destination : MP
Stop condition
01 : stop at end of buffer
10 : no stop.
s, s :
a, a :
Status Register
This is a read-only, direct access register.
S7 : BUSY BUSY is set at the beginningof any
command execution. It is reset at
completion.
LXm or LXa is set when resS6 : AI
pectively the main pointer or the
auxiliary pointer holds X = 39
S5
LXm
before a possible incrementation.
The alarm bit S6 is set when LXm
S4 : LXa
or LXa is set and an incrementation
is performed after access.
S3 :
Gives the MSB value of R1.
S2 :
Gives the vertical synchronization
signal state.
This is maskable by the VRM
command.
S1 = S0 = 0 Not used.
S3 to S6 are reset at the beginning of any command.
Command Register
This register holds a 4-bit command type and 4 bits
of orthogonal parameters (see command table).
Type
There are 4 groups of command :
The IND command which gives access to on-chip
resources,
The fixed format character code transfer commands,
The variable character code handling commands,
The general purpose commands.
Parameters
R/W : Direction
1 : to DATA registers (R1, R2, R3)
0 : from DATA registers.
r:
Internal resource index (see figure 27).
l:
Auto-incrementation
1 : with post auto-incrementation
0 : without auto-incrementation
The COMMAND TABLE shows every command
able to set, each of these status bits, after completion.
Figure 37 : Indirect On-Chip Resource Access
7
6
5
4
3
1
0
0
0
R/W
R1
R2
R3
X
-
R4
R5
-
R6
R7
-
2
1
r
0
IND
COMMAND
r
Register
0
1
2
3
4
5
6
7
ROM*
TGS
MAT
PAT
DOR
ROR
NT
R6
34/38
... B6 C6 C5 C4 C3 C2
R7 B4 B5
3
2
1
0
C1
C0
9345-40.EPS
* A slice in 400 only can be read from the internal
character generator.
The slice address must be initialized in R6, R7.
EF9345
IND Command (See Figure 37)
This command transfers one byte between R1 and
an internal resource. The r parameter designates
one on-chip indirect register.
KRF transfers 24 bits.
KRG transfers 16 bits
KRL transfers 12 bits.
KRC transfers 8 bits.
Code packing, pointer and data structures are explained in the corresponding character code section.
When auto-incrementation is enabled, MP is automatically updated after access so as to point to the
next location. This location corresponds to the next
right position on screen. When last position (X = 39)
is accessed, LXm is set. When last position is
accessed with auto-incrementation, alarm is also
set. MP is then pointing back at the beginning of
the row : there is no automatic Y incrementation.
Variable Code Handling Commands :
KRV EXP, CMP, KRE
An overview on these commands is given in ”handling the variable codes” (40 char./row section).
KRV uses R5 to point the attribute file. LXa is set
when this file is full (the last attribute pair has been
accessed).
EXP and CMP use MP and R5 in the same way as
KRV. Furthermore, R4 points to a working double
buffer. Thse two commands process a whole row
buffer and stop either at the end of the row buffer
or when the file overflows. In the last case, the
alarm bit is set.
KRE uses MP to point to a buffer and R4 to point
to a working double buffer. R5 is unused. In other
respects, KRE is identical to KRL.
For these commands, R4(5:7) hold the LSB’s block
dress of the working buffer W.
Figure 38
7
6
5
Z0
Z1
Z2
ZW
Fixed Format Character Code Access :
KRF, KRG, KRL, KRC
Each of these commands is dedicated to transfer
one complete character code between DATA registers and memory. MP is exclusively used.
4
3
2
Y
1
0
R4
YW
ZW3 is given by bit 6 of R6
9345-41.EPS
Notes on Command Execution
1. The execution of any command starts at the
trailing edge of DS when (and only when) :
- EF9345 has been selected,
- XQR has been set,
at the previous AS falling edge.
This scheme allows loading a command and its
argument in any order. For instance, a command,
once loaded,may be re-executed with new or partly
new arguments.
2. At power on, the busy state is undeterminated.
It is recommanded to load first a dummy
command with XQR = 1 before any effective
command.
3. While Busy is set, the current command is
under execution. Register access is then
restricted.
Register access with XQR = 0
- Read STATUS is effective.
- Write COMMAND or any other register access
are ineffective.
That is to say, the microprocessor reads undetermined values and may not modify a register.
Register access with XQR = 1
- Read STATUS or write COMMAND are effective,
- Access to other registers is ineffective.
However, the previous command is aborted and
the new command execution launched (with an
initial state undetermined for registers and memory
locations handled by the aborted command).
4. Execution suspension
The execution of any command (except VRM,
VSM) is suspended during the last and first TV line
of an active row. This is because the memory bus
cannot be allocated for microprocessor access during this 104 µs period.
This holds too for internal resource access because
on-chip data transfer uses internal data memory
bus.
35/38
EF9345
General Purpose Access to a Byte OCT
This command uses either MP or AP pointer.
When MP is in use, an overflow yields to a Y
incrementation.
parameter a = 0, the process never stops until
aborted. In this case, main pointer overflow yields
to a Y incrementation in MP. So, a whole block or
page may be initialized.
Move Buffer Commands : MVB, MVD, MVT
These are memory to memory commands which
use R1 as working register.
MVB transfers a byte from source to destination,
post-increments the 2 pointersand iterates until the
stop condition is met. MVD and MVT are similar but
work respectively with 2 byte word and 3 byte word.
That is to say, MVB works on buffers, MVD on
double buffers and MVT on triple buffers. If the
parameter a = 1, the process stops when either
source or destination buffer end is reached. If the
Miscellaneous Commands : INY, VRM and
VSM
INY command increments Y in MP.
VRM and VSM respectively reset and set a vertical
synchronization status mask. When the mask is
set, status bit S2 remains at 0. When the mask is
reset, status S2 follows the vertical sync. state : it
is reset for 2 TV lines per frame and stays at 1
during the remaining period. It becomes readable
by the microprocessor form the status register.
After power on, the mask state is undetermined.
Type
Indirect
40 Characters
40 Characters
80 Characters
80 Characters
- 24 bits
- 16 bits
- 8 bits
- 12 bits
Memo
IND
KRF
KRG
KRC
KRL
7
1
0
0
0
0
Code
6 5
0 0
0 0
0 0
1 0
1 0
4
0
0
0
0
1
Parameter
3
2 1
R/W
r
R/W 0 0
R/W 0 1
R/W 0 0
R/W 0 0
0
I
I
I
I
40 Characters Variable
KRV
0
0
1
0
R/W
0
0
I
Expansion
Compression
Expanded Characters
Byte
Move Buffer
Move Double Buffer
Move Triple Buffer
EXP
CMP
KRE
OCT
MVB
MVD
MVT
0
0
0
0
1
1
1
1
1
0
0
1
1
1
1
1
0
1
0
1
1
0
1
1
1
1
0
1
0
0
R/W
R/W
s
s
s
0
0
0
p
s
s
s
0
0
0
0
a
a
a
0
0
I
I
a
a
a
Clear Page (4) - 24 Bits
CLF
0
0
0
0
0
1
0
1
Clear Page (4) - 16 bits
CLG
0
0
0
0
0
1
1
1
Vertical Sync Mask Set
VSM
Vertical Sync Mask Reset VRM
Increment Y
INY
No Operation
NOP
1
1
1
1
0
0
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
1
1
0
1
P
s, s
:
:
Status
Arguments
Execution Time (1)
AI LX m LXa R17 R1 R2 R3 R4 R5 R6 R7
Write
Read
0
0
0
0 D MP
2
3.5
X
X
0
0 C B A
MP
4
7.5
X
X
0
0 A* B* W MP
5.5
7.5
X
X
0
0 C MP
9
9.5
X
X
0
0 C - A
MP
12.5
11.5
3.5 +
X
X
X
X C B A
- XF MP (2) 3 + 3 + j
6 *j
X
0
X
0 C B A PW XF MP
(3) < 247
X
0
X
0 C B A PW XF MP
(3) < 402
X
X
0
0 C B A PW MP
4
7.5
X
X
X
0 D AP
MP
4
4.5
0
0
0
0 W AP
MP
(2) 2 + 4. n
0
0
0
0 W AP
MP
(2) 2 + 8. n
0
0
0
0 W AP
MP (2) 2 + 12. n < 4700
X
X
0
0 C B A
MP
(1 K code)
< 5800
X
X
0
0 A* B* W MP
(1 K code)
0
0
0
0
- - 1
- - 1
0
0
0
0
- Y 2
- - 1
-
Pointer select
1 : auxiliary pointer
0 : main pointer
-
:
Not affected
W
:
Used as working register
Source, destination
01 : source = MP ;
destination = AP
10 : source = AP ;
destination = MP
PW
:
(Z, YW)
Working buffer
X
:
Set or Reset
XF
:
X File
a, a
:
Stop condition
01 : stop at end of buffer
10 : no stop
I
:
Pointer incrementation
D
:
Data
r
:
Indirect register number
MP
:
Main pointer
AP
:
Auxiliary pointer
36/38
(1) Unit :
12 clock periods (≈ 1µs)
without possible suspension.
(2) n
:
total number of word ≤ 40 ;
j = 1 for long code,
j = 0 for short codes.
(3)
:
Worst case (20 long codes +
20 short codes).
(4)
:
These commands repeats KRF
or KRG with Y incrementation
when X overflows. When the
last position is reached in a
row. Y is incremented and the
process starts again on the
next row.
9345-09.TBL
Table 4 : Command
EF9345
Figure 39 : Interface with EF6801
PORT C
Figure 40 : Minimum Application with 2K x 8
Memory
One page memory terminal in 16-bit fixed format or
24-bit compressed format.
AD(0:7)
D0-D7
AS
E
DS
EF6801
74LS
373
ADM(0:7)
A0-A7
EF9345
CS
ASM
SC2
R/W
IOS
CS
9345-42.EPS
AM(8:10)
Figure 41 : Typical Application with 8K x 8 Dynamic or Pseudoi-static RAM
Multipage terminal with possibility of multiple user
definable character sets.
EF9345
RAM
2K x 8
ET2128
A8-A10
OE
OE
WE
WE
9345-43.EPS
SC1
Figure 42 : Maximum Application with 16K x 8
Memory
Multipage terminal with user definable character
sets and buffer areas.
D4-D7
ADDRESS MUX
2 x 74LS157
D0-D3
ADM(0:7)
D0-D7
AM(8:13)
OE
OE
WE
WE
EF9345
Q
D
Q
CK
CK
CAS
DRAM
16K x 4
RAS
CLK
OE
G
WE
W
9345-45.EPS
EF9345
A8-A12
D
1/2 74LS74
AM(8:12)
CE
ASM
RAM
8K x 8
1/2 74LS74
ASM
A0-A7
9345-44.EPS
ADM(0:7)
A0-A7
12MHz CLOCK
37/38
EF9345
I
L
a1
PACKAGE MECHANICAL DATA
40 PINS - PLASTIC DIP
b1
b
e
b2
E
e3
D
21
1
20
a1
b
b1
b2
D
E
e
e3
F
i
L
Min.
Millimeters
Typ.
0.63
0.45
0.23
Max.
Min.
0.31
0.009
1.27
Max.
0.012
0.050
52.58
16.68
15.2
Inches
Typ.
0.025
0.018
2.070
0.657
0.598
2.54
48.26
0.100
1.900
14.1
4.445
3.3
0.555
0.175
0.130
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility
for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result
from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without noti ce. This publication supersedes and replaces all
information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life
support devices or systems without express written approval of SGS-THOMSON Microelectronics.
 1995 SGS-THOMSON Microelectronics - All Rights Reserved
Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips
I2C Patent. Rights to use these components in a I2C system, is granted provided that the system confo rms to
the I2C Standard Specifications as defined by Philips.
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco
The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
38/38
DIP40.TBL
Dimensions
PM-DIP40.EPS
F
40