TDA7309 DIGITAL CONTROLLED STEREO AUDIO PROCESSOR WITH LOUDNESS INPUT MULTIPLEXER: 3 STEREO INPUTS RECORD OUTPUT FUNCTION LOUDNESS FUNCTION VOLUME CONTROL IN 1dB STEPS INDEPENDENT LEFT AND RIGHT VOLUME CONTROL SOFT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL I2C BUS DIP20 DESCRIPTION The TDA7309 is a control processor with independent left and right volume control for quality audio applications. Selectable external loudness and soft mute functions are provided. Control is accomplished by serial I2C bus microprocessor interface. The AC signal setting is obtained by resistor net- SO20 ORDERING NUMBER: TDA7309 TDA7309D works and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and Low DC stepping are obtained. BLOCK DIAGRAM 100nF Recout(L) 1 3x 2.2µF LOUD(L) 19 17 18 LEFT INPUTS VOLUME + LOUDNESS 20 2 OUT LEFT MUTE INPUT SELECTOR 6 4 3x 2.2µF SERIAL BUS DECODER + LATCHES 5 14 8 DIGGND SDA SCL BUS ADDR 13 RIGHT INPUTS VOLUME + LOUDNESS 11 SOFT MUTE TDA7309 SUPPLY 3 CSM 9 OUT RIGHT MUTE 16 VS 7 15 AGND CREF 10 Recout(R) D93AU045A 22µF September 1997 12 LOUD(R) 100nF 1/12 TDA7309 PIN CONNECTION (Top View) RecoutL 1 20 IN3L OUTL 2 19 LOUDL CSM 3 18 IN2L SDA 4 17 IN1L SCL 5 16 VS DGND 6 15 CREF GND 7 14 IN1R ADD 8 13 IN2R OUTR 9 12 LOUDR 10 11 IN3R RecoutR D94AU058A ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Operating Supply Voltage VS Tamb Operating Ambient Temperature Tstg Storage Temperature Range Unit 10.5 V –40 to 85 °C –55 to +150 °C QUICK REFERENCE DATA Symbol Parameter Test Condition VS Operating Supply Voltage Min. Typ. 6 Unit 10 V VCL Max. Input Signal Handling THD Total Harmonic Distortion 2 Vrms S/N Signal to Noise Ratio 106 dB Sc Channel Separation f = 1KHz 100 dB V = 1Vrms, f = 1KHz 0.01 Volume Control 1.0dB step –95 0.1 0 % dB Soft Mute Attenuation 60 dB Direct Mute Attenuation 100 dB TEST CIRCUIT IN1L IN2L IN3L RecoutL IN1R IN2R IN3R RecoutR 17 3 CSM 18 20 2 OUTL 1 16 VS 15 CREF 7 AGND 9 OUTR 8 ADD TDA7309 14 13 11 10 19 LL 12 LR 5 4 6 SCL SDA DIGGND D94AU057A 2/12 Max. TDA7309 THERMAL DATA Symbol Rth j-pins Parameter Thermal resistance Junction to Pins SO20 150 DIP20 100 Unit °C/W ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Tamb = 25°C, VS = 9V, RL = 10KΩ, RG = 50Ω, all controls flat (G = 0), f = 1KHz unless otherwise specified.) Symbol Parameter Test Condition Min. Typ. Max. Unit 5 (*) 10 10 60 9 7 85 V mA dB 35 80 50 90 65 KΩ dB SUPPLY VS IS SVR Supply Voltage Supply Current Ripple Rejection INPUT SELECTORS RI Sin Input Resistance Input Separation VOLUME CONTROL C RANGE AVMAX ASTEP EA Control Range Max. Attenuation Step resolution Attenuation Set Error ET VDC Tracking Error DC Steps Amute Output Mute Attenuation AV = 0 to -24dB AV = -24 to -56dB 87 0.5 -1.2 -3 adjacent attenuation steps from 0dB to AV max. 80 92 92 1 0 0.5 100 95 1.5 1.2 2 2 3 5 dB dB dB dB dB dB mV mV dB SOFT MUTE Td Delay Time C smute = 22nF 0 to –20dB Fast Mode Slow Mode 1 20 ms ms 2.6 Vrms KΩ Ω V AUDIO OUTPUTS VCLIP RL R out VDC Clipping Level Output Load Resistance Output Impedance DC Voltage Level d = 0.3% Output Noise BW = 20-20KHz, flat output muted all gains = 0dB A curve all gains = 0dB AV = 0 to –24dB AV = -24 to –56dB all gains = 0dB; VO = 1Vrms 2 2 100 200 3.8 300 GENERAL e NO Et Total Tracking Error S/N d SC Signal to Noise Ratio Distortion Channel Separation 95 80 2.5 5 3 0 0 106 0.01 100 15 1 2 0.1 µV µV µV dB dB dB % dB BUS INPUTS V IL VIH IIN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge 1 Vin = 0.4V IO = 1.6mA 3 -5 0.4 +5 0.8 V V µA V (*) Hedevice work until 5V but no guarantee about SVR 3/12 TDA7309 Figure 1: Noise vs. volume setting. Figure 2: SVRR vs. frequency. Figure 3: THD vs. frequency Figure 4: THD vs. RLOAD. Figure 5: Channel separation vs. frequency. Figure 6: Output clip level vs. Supply Voltage. 4/12 TDA7309 Figure 7: Quiescent current vs. supply voltage. Figure 8: Loudnessvs. Volume Attenuation. Figure 9: Loudnes vs. Frequency (CLOUD = 100nF) vs. Volume Figure 10: Loudness vs. External Capacitors 5/12 TDA7309 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7313 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 11, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig. 12 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Figure 11: Data Validity on the I2CBUS Figure 12: Timing Diagram of I2CBUS Figure 13: Acknowledge on the I2CBUS 6/12 Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 13). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. TDA7309 SDA, SCL I2CBUS TIMING Symbol Parameter Min. Typ. Max. Unit 400 kHz fSCL SCL clock frequency tBUF Bus free time between a STOP and START condition 1.3 µs Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs 0.6 µs 0.300 µs tHD:STA 0 tSU:STA Set-up time for a repeated START condition tHD:DA Data hold time tSU:DAT Data set-up time 100 tR Rise time of both SDA and SCL signals 20 300 ns (*) tF Fall time of both SDA and SCL signals 20 300 ns (*) Set-up time for STOP condition 0.6 tSU:STO ns µs All values referred to VIH min. and VIL max. levels (*) Must be guaranteed by the I2C BUS master. Definition of timing on the I2C-bus SDA tBUF tR tF tHIGH tHD;STA tSP tSU;STO SCL t LOW P S tHD;STA tHD;DAT tF tSU;STA tSU;DAT Sr D95AU314 P P = STOP S = START 7/12 TDA7309 address (the 8th bit of the byte must be 0). The TDA7309 must always acknowledge at the end of each transmitted byte. A sequence of data (N-bytes + acknowledge) A stop condition (P) SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte, containing the TDA7309 TDA7309 ADDRESS first byte MSB S 0 0 1 1 0 LSB 0 A MSB LSB 0 ACK DATA MSB LSB DATA ACK ACK P Data Transferred (N-bytes + Acknowledge) ACK = Acknowledge S = Start P = Stop MAX CLOCK SPEED 100kbits/s SOFTWARE SPECIFICATION Chip address MSB LSB 0 0 1 1 0 0 1 0 pin address open 0 0 1 1 0 0 0 0 pin address close to ground FUNCTION CODES MSB F6 F5 F4 F3 F2 F1 LSB VOLUME 0 X X X X X X X MUTE/LOUD 1 0 0 X X X X X INPUTS 1 0 1 X X X X X CHANNEL 1 1 0 X X X X X F4 F3 F2 F1 LSB X X X 0 0 X X X 0 1 LEFT X X X 1 0 BOTH X X X 1 1 BOTH CHANNEL ABILITATION CODES MSB F6 F5 1 1 0 Power on reset condition 1 1 1 1 1 1 1 0 8/12 FUNCTION channel RIGHT TDA7309 VOLUME CODES MSB F6 F5 F4 F3 F2 F1 LSB 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 0 FUNCTION step 1dB 0 -7dB step 8dB 0 0 0 0 0dB 0 0 0 1 -8dB 0 0 1 0 -16dB 0 0 1 1 -24dB 0 1 0 0 -32dB 0 1 0 1 -40dB 0 1 1 0 -48dB 0 1 1 1 -56dB 1 0 0 0 -64dB 1 0 0 1 -72dB 1 0 1 0 -80dB 1 0 1 1 -88dB 1 1 X X MUTE F4 F3 MUTE LOUDNESS CODES MSB F6 F5 1 0 0 F2 F1 LSB FUNCTION mute/loud X 0 0 slow soft mute on X 0 1 fast soft mute on 1 soft mute off 1 LOUD OFF X 0 0 loud on (10dB) X 1 0 loud on (20dB) F4 F3 F2 F1 LSB FUNCTION X X X 0 0 MUTE X X X 0 1 IN2 X X X 1 0 IN3 X X X 1 1 IN1 INPUT MULTIPLEXER CODES MSB F6 F5 1 0 1 inputs Purchase of I2C Components of SGS-THOMSON Microlectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. 9/12 TDA7309 SO20 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. TYP. 2.65 0.1 MAX. 0.104 0.3 a2 0.004 0.012 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 0.020 c1 45 (typ.) D 12.6 13.0 0.496 0.512 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.4 7.6 0.291 0.299 L 0.5 1.27 0.020 0.050 M S 10/12 MIN. 0.75 0.030 8 (max.) TDA7309 DIP20 PACKAGE MECHANICAL DATA mm DIM. MIN. a1 0.254 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L Z 3.3 0.130 1.34 0.053 11/12 TDA7309 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGSTHOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1997 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 12/12