pt2259 thd

PT2259
Volume Controller IC
DESCRIPTION
FEATURES
PT2259 is an 8-pin 2-channel volume controller which
utilizes CMOS technology and incorporates the I2C
interface control. The controller features an attenuation
range of 0 to -79dB, low noise output, a high degree of
stereo separation and requires only a small number of
external components. PT2259 is an essential
component for modern audio visual systems.
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APPLICATIONS
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Attenuation range: 0 to -79dB in 1dB steps
Operating voltage: 4 to 10V
Low power consumption
Low signal noise: S/N > 100dB (A-weighting)
Stereo separation > 100dB
Requires few external components
2-channel volume individual adjust
Available in 8 Pins DIP or SOP
Audio/visual surround sound systems
Car audio systems
Mini-compo systems
Computer multi-media speakers
Other audio applications
BLOCK DIAGRAM
Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT2259
APPLICATION CIRCUIT
IMPROVE VDD NOISES REJECTION
LIN
C1
10uF
C2
10uF
1 LIN
LOUT
C3
10uF
LIN
C1
10uF
RIN 8
2 LOUT
3 VSS
RIN
1 LIN
C4
10uF
ROUT 7
ROUT
LOUT
R1
VDD 6
4 SDA
C6
0.1uF
C5
100uF
SCL 5
PT2259
C3
10uF
VDD
C2
10uF
RIN
C4
10uF
ROUT
RIN 8
2 LOUT
ROUT 7
3 VSS
VDD 6
4 SDA
SCL 5
VREG
100
C5
100uF
PT2259
VDD
C6
0.1uF
MCU
MCU
ADD a RC filter on the VDD path
Use a regulated supply
IMPROVE INPUT ESD HANDLING CAPABILITY
BAV99
P T2259
VDD
P T2259
VDD
IN
AUDIO IN
10uF
2K
IN
AUDIO IN
33K
10uF
2K
33K
VREF
VREF
ADD a Resistor on the input path
V1.5
ADD a protection diode on the input path
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July, 2011
PT2259
ORDERING INFORMATION
Valid Part Number
PT2259
PT2259-S
Package Type
8 Pins, DIP, 300mil
8 Pins, SOP, 150mil
Top Code
PT2259
PT2259-S
PIN CONFIGURATION
PIN DESCRIPTION
V1.5
Pin Name
I/O
LIN
I
LOUT
O
VSS
SDA
SCL
VDD
I
I
-
ROUT
O
RIN
I
Description
Left Channel Input
(capacitor coupled to input port)
Left Channel Output
(capacitor coupled to output port)
Ground
I2C Data Input
I2C Clock Input
Power Supply
Right Channel Output
(capacitor coupled to input port)
Right Input Channel
(capacitor coupled to output port)
3
Pin No.
1
2
3
4
5
6
7
8
July, 2011
PT2259
FUNCTIONAL DESCRIPTION
I2C BUS INTERFACE
In PT2259 the DATA and CLK make up the bus interface through which data is transmitted to and from the
microprocessor.
DATA VALIDITY
Data on the DATA line is considered valid and stable only when the CLK signal is in the “high” state. In addition, the “high”
and “low” states of the DATA line can change only when the CLK signal is in the “low” state. Please refer to the diagram
below:
START AND STOP CONDITIONS
A start condition is activated when:
1. the CLK signal is set to “high”, and
2. the DATA signal shifts from “high” to “low”
A stop condition is activated when:
1. the CLK signal is set to “high”, and
2. the DATA signal shifts from “low” to “high”
Please refer to the timing diagram below:
V1.5
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July, 2011
PT2259
BYTE FORMAT
Every byte transmitted to the DATA line consists of 8 bits and each byte must be followed by an “acknowledge” bit. The
MSB is transmitted first.
ACKNOWLEDGE SIGNAL
During the ninth clock pulse, the microprocessor puts a resistive “high” level on the DATA line. If the peripheral audio
processor (PT2259) acknowledges, it will pull the DATA line from a “high” state to a “low” state during this acknowledge
clock phase so that the DATA line is in a stable “low” state during this clock pulse. Please refer to the diagram below.
The audio processor that has been address (PT2259) must generate an “acknowledge” signal after receiving each byte
or the DATA line will remain at the “high” level during the ninth clock pulse.
TRANSMISSION WITHOUT ACKNOWLEDGE
If you do not wish the audio processor (PT2259) to detect the “acknowledge” signal, a simpler microprocessor
transmission method can be used: after PT2259 has received a byte wait for one clock pulse and do not acknowledge it.
If this approach is used, however, there is a greater chance for faulty operations to occur and noise immunity will be
decreased.
I2C START TIME
When PT2259 is powered on, a short period must elapse before voltage becomes stable. After the power is turned on,
PT2259 must wait at least 200ms before it is able to send an I2C control signal otherwise control efficacy and normal
operation will be comprised. Please refer to the diagram below:
V1.5
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July, 2011
PT2259
INTERFACE PROTOCOL
The interface protocol consists of the following:
1.
2.
3.
4.
a start condition
the PT2259 address byte followed by an “acknowledge” signal
a data sequence (n-bytes and an “acknowledge” signal)
a stop condition
Please refer to the following diagram:
PT2259 Address
START
MSB
1
0
0
First Address
0
1
0
LSB
MSB
0
ACK
0
LSB
DATA
MSB
ACK
LSB
ACK
DATA
STOP
Data Transmitted (N + Bytes + Acknowledge)
Notes:
1. ACK= Acknowledge
2. Max Clock Speed = 100K BITS/S
SOFTWARE SPECIFICATIONS
PT2259 address is shown below
MSB
LSB
1
V1.5
0
0
0
6
1
0
0
0
July, 2011
PT2259
DATA BYTES DESCRIPTION
FUNCTION BITS
MSB
1
1
1
1
0
0
1
0
1
1
0
0
0
0
1
1
0
1
1
1
1
1
1
1
1
0
0
1
0
1
1
1
A3
0
A3
0
A3
0
0
0
A2
B2
A2
B2
A2
B2
0
1
A1
B1
A1
B1
A1
B1
0
C1
LSB
A0
B0
A0
B0
A0
B0
0
C0
Function
2-channel, -1dB/step
2-channel, -10dB/step
Left channel, -1dB/step
Left channel, -10dB/step
Right channel, -1dB/step
Right channel, -10dB/step
Clear register
Mute select
ATTENUATION UNIT BITS
A3
0
0
0
0
0
0
0
0
1
1
A2/B2
0
0
0
0
1
1
1
1
0
0
A1/B1
0
0
1
1
0
0
1
1
0
0
A0/B0
0
1
0
1
0
1
0
1
0
1
Attenuation (dB)
0/0
-1/-10
-2/-20
-3/-30
-4/-40
-5/-50
-6/-60
-7/-70
-8/
-9/
MUTE FUNCTION BITS
C1
0
0
1
1
V1.5
C0
0
1
0
1
Function
Mute OFF
Right channel mute ON
Left channel mute ON
Left and right channel mute ON
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July, 2011
PT2259
PT2259 I2C CODE SEQUENCE
User must following I2C code sequence describe in this section in order to ensure proper operation under various
operation voltage. If any register doesn’t given an initial value, or code sequence is not following the instruction, the
PT2259 is possible out of control. Please refer to the following instruction.
1st, clear the volume register
Start 0x88
0xF0
Stop
0x88: PT2259 chip address
0xF0: Clear register
2nd, give all register an initial value
Start 0x88
0xF0 0x74
0xE2
0xD0
Stop
0x88: PT2259 chip address
0xF0: Clear register
0x74: All channels mute off
0xE2: 2-channels -20dB
0xD0: 2-channels -0dB
(1dB code must follow a 10dB code and not be interrupted)
3rd, follow the code sequence 2nd to setting functions.
Start 0x88
0xF0 0x74
0xE2
0xD0
Stop
Set volume to -20dB, all channels mute off
Start 0x88
0xF0 0x74
0xE1
0xD9
Stop
Set volume to -19dB, all channels mute off
Start 0x88
0xF0 0x77
0xE1
0xD9
Stop
Set volume to -19dB, all channels muted
Start 0x88
0xF0 0x74
0x31
0x29
Stop
Set R-CH volume=-19dB, all mute=off
WARNING! THESE TRANSMISSION METHODS ARE PROHIBITED.
Missing clear register code(0xF0) after chip address(0x88).
Start
0x88
0xE2
Stop
Only a 10dB attenuation value:
Start
0x88
0xF0 0xE4
-40dB
Stop
Only a 1dB attenuation value:
Start
0x88
0xF0 0xD2
-2dB
Stop
Other code occupied in between the 10dB and 1dB code.
Start
0x88 0xF0
0xD2
0x22
0xE4
-2dB
R-CH -2dB
-40dB
V1.5
8
Stop
July, 2011
PT2259
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Operating Temperature
Storage Temperature
Input Voltage
Symbol
Vcc
Topr
Tstg
Vi
Rating
12
-40 ~ +85
-65 ~ +150
-0.3 ~ Vcc + 0.3
Unit
V
°C
°C
V
ELECTRICAL CHARACTERISTICS
(Conditions: Vcc=9V, Vi=1Vrms, f=1KHz, Temp=27°C)
Parameter
Operating Voltage
Operating Current
Symbol
Vcc
Icc
Volume Attenuation Range
ARANGE
Attenuation Step
Attenuation Step Gain Error
Interchannel Attenuation Gain Error
ASTEP
GERR
CERR
Maximum Output Voltage
Vomax
Total Harmonic Distortion
THD
Noise Output
NO
Signal-to-Noise Ratio
SNR
Channel Separation
CS
Mute
MUTE
Frequency Response
Input Impedance
Output Impedance
Minimum Load Resistance
FR
Rin
Rout
Rload
Testing Conditions
Vcc=9V, Vi=0V
Minimum attenuation
Maximum attenuation
Vcc=9V, freq=1KHz, Volume Att.=0dB,
Rload=50KΩ, THD<1%
f=1KHz,
Vout=2Vrms
Volume Att.=0dB,
A-weight Rload=50KΩ Vout=200mVrms
Vin=GND, Mute=OFF,
Volume Att.=0dB, A-weighted
No-weighted
Vin=1Vrms,
Att.=0dB
A-weighted
Vin=2.5Vrms, freq.=1KHz,
Volume Att.=0dB
Vin=2.5Vrms, freq.=1KHz,
Volume Att.=0dB, A-weighted
Vin=1Vrms, Volume Att.=-10dB
f=1KHz
f=1KHz, Vout=100mVrms
VDD=9V, Vo=2Vrms, THD<1%
Min.
4
-
Typ.
9
2.5
0
-79
1
0.5
0.5
Max.
10
3
-
Unit
V
mA
2.0
2.3
2.5
Vrms
-
0.07
0.09
-
0.003
0.005
%
-
2
3
μVrms
95
110
100
120
103
125
dB
100
120
125
dB
90
95
97
dB
6
1
33
6
-
1.3
-
MHz
KΩ
Ω
KΩ
dB
dB
dB
dB
I2C BUS SECTION ELECTRICAL CHARACTERISTICS
Symbol
VIH
VIL
V1.5
Parameter
Bus High Input Level
Bus Low Input Level
Condition
-
9
Min.
3.5
-
Typ.
-
Max.
0.8
Unit
V
V
July, 2011
PT2259
PT2259 THD - FAST FOURIER TRANSFORM (FFT) ANALYSIS 1
(Conditions: Rload=10K, Volume Att=0dB, Vcc=9V, Output Level=1Vrms)
+0
-20
-40
-60
dB
-80
-100
-120
-140
-160
20
50
100
200
500
1k
2k
5k
10k
Hz
PT2259 THD - FAST FOURIER TRANSFORM (FFT) ANALYSIS 2
(Conditions: Rload=10K, Volume Att=0dB, Vcc=9V, Output Level=200mVrms )
+0
-20
-40
-60
dB
-80
-100
-120
-140
-160
20
50
100
200
500
1k
2k
5k
10k
Hz
V1.5
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July, 2011
PT2259
PT2259 NOISE FLOOR - FAST FOURIER TRANSFORM (FFT)
ANALYSIS 3
(Conditions: Rload=10K, Volume Att=0dB, Vcc=9V, Vin=GND)
+0
-20
-40
-60
dB
-80
-100
-120
-140
-160
20
50
100
200
500
1k
2k
5k
10k
Hz
PT2259 THD VS. OUTPUT LEVEL
(Conditions: Rload=10K, Volume Att=0dB, Vcc=9V, f=1KHz, A-weighted)
20
5
1
%
0.1
0.01
0.001
1m
2m
5m
10m
20m
50m
100m
200m
500m
1
2
4
Vrms
V1.5
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July, 2011
PT2259
PT2259 THD VS. FREQUENCY RESPONSE AT VARIOUS OUTPUT
LEVELS
(Conditions: Rload=10K, Volume Att=0dB, No-weighted)
Vout=2.5Vrms
1
%
Vout=1Vrms
0.1
0.01
Vout=200mVrms
0.001
20
50
100
200
500
1k
2k
5k
10k
2k
5k
10k
20k
Hz
Note: from top to bottom: Vout = 2.5Vrms, 1Vrms = 200mVrms
PT2259 INTERCHANNEL CROSSTALK
(Conditions: Rload=10K, Volume Att=0dB)
+0
-50
dB
-100
-150
20
50
100
200
500
1k
20k
Hz
V1.5
12
July, 2011
PT2259
PACKAGING INFORMATION
8-PIN, DIP, 300 MIL
Symbol
A
A1
A2
b
c
e
D
E
E1
L
Min.
0.50
3.10
0.38
0.21
9.10
7.62
6.25
2.92
Dimensions (MM)
Nom.
3.30
2.54 BSC
9.20
7.87
6.35
3.30
Max.
4.80
3.50
0.55
0.35
9.30
8.25
6.45
3.81
Note: Refer to JEDEC MS-001 BA
V1.5
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July, 2011
PT2259
8-PIN, SOP, 150MIL
Symbol
Note: Refer to JEDEC MS-012 AA
V1.5
A
A1
A2
b
c
e
D
E
E1
L
θ
Dimensions (MM)
Nom.
1.60
0.15
1.40
1.27 BSC
4.90
6.00
3.90
0.60
-
Min.
1.35
0.08
1.20
0.33
0.17
4.70
5.80
3.70
0.38
0°
14
Max.
1.77
0.28
1.65
0.51
0.26
5.10
6.20
4.10
1.27
8°
July, 2011
PT2259
IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and to discontinue any product without notice at any time.
PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No
circuit patent licenses are implied.
Princeton Technology Corp.
2F, 233-1, Baociao Road,
Sindian, Taipei 23145, Taiwan
Tel: 886-2-66296288
Fax: 886-2-29174598
http://www.princeton.com.tw
V1.5
15
July, 2011