W.A.R.P.2.0 8-BIT FUZZY CO-PROCESSOR PRELIMINARY DATA Digital Fuzzy Co-processor 8-bit I/O High Speed Rules Processing 4 Input, 2 Output, 32 Rules in 33.1µs Up to 256 Rules (4 Antecedents,1 Consequent) Up to 8 Input Configurable Variables Up to 16 Membership Functions for an Input Variable Antecedent Membership Functions with Triangular and Trapezoidal Shape Up to 4 Output Variables PLCC68 Up to 256 Membership Functions for all Consequents Singleton Consequent Membership Functions Defuzzification on chip Figure 1. Logic Diagram. Maximum Clock Frequency 40MHz A/D Start Convertion Pulse presettable Direct Interface to all popular microprocessor MCLK VSS VDD WAIT 8 12 I0-I7 O0-O11 3 Handshaking Signal Polarity presettable 2 SIS0-SIS2 Operates ”STAND ALONE” (without µP) if desired Standard +5V Supply Voltage Software Tools and Emulators Availability LASTIN OC0-OC1 W.A.R. P. DS OE 2.0 AUTO RD ENDOFL Pin number: 52 68-lead Plastic Leaded Chip Carrier package. READY ERR OFL PRESET BUSY Figure 2. Simplified Block Diagram. 8 Input Port with HANDSHAKE 8 ALPHA CALCULATOR INFERENCE UNIT DEFUZZIFIER Ouput Port with HANDSHAKE INTERNAL BUS ANTECE DENT MEMORY P ROGRAM & CONSE QUENT MEMORY P ROGRAMMABLEA/D OUTPUT PULSE March 1996 This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without no tice. 1/28 W.A.R.P.2.0 nc nc I7 I6 I5 I4 I3 I2 VSS I1 I0 WAIT SIS0 SIS1 SIS2 nc nc Figure 3. Pin Connections 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 W.A.R.P. 2.0 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 VSS VDD MCLK PRESET OFL AUTO LASTIN OE RD TEST DS ENDOFL ERR BUSY READY VSS VDD nc nc nc VDD VSS O0 O1 O2 O3 O4 O5 O6 VDD VSS nc nc nc nc nc nc VSS VDD OC1 OC0 O11 O10 O9 O8 O7 VSS VDD nc nc nc 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Note: nc = Not Connected. GENERAL DESCRIPTION W.A.R.P.2.0 is a member of the W.A.R.P. family of fuzzy microprocessors, completely developed and produced by SGS-THOMSON Microelectronics using the high performance, reliable HCMOS4T (O.7µm) process. W.A.R.P.2.0 can be used both as a Fuzzy Co-processor or as a stand-alone microcontroller. In the former case, it can work together with standard micros which shall perform normal control tasks while W.A.R.P.2.0 will be indipendentlyresponsible for all the fuzzy related computing. W.A.R.P.2.0 core includes the fuzzifier (ALPHA calculator), the inference unit, and the defuzzifier. The I/O capabilities demanded by microprocessor applications are fulfilled by W.A.R.P.2.0 with 8 Input and 4 Output lines which can be supported by handshaking signals. The capability of preset the polarity of the handshaking signals simplifies the interface with the host processor. An internal Start Conversion pulse is provided to allow simple use for waveform generation which can be directly applied to drive an A/D converter. The output 3-STATE buffer can be temporarily frozen in order to synchronize W.A.R.P.2.0 with slower devices. 2/28 Running W.A.R.P.2.0 involves a downloading phase and an On-Line phase. The downloading phase allows the setting of the processor, in terms of I/O number, universe of discourse, Membership Functions (MFs) and rules. During this phase W.A.R.P.2.0 prepares its internal memories for the On-Line elaboration phase and loads the microcode in its program memory. This microcode, which drives the On-Line phase, is generated by the Compiler (see FUZZYSTUDIO 2.0 User Manual). After that W.A.R.P.2.0 is ready to run (On-Line phase) processing inputs and producing the related outputs according to the configuration loaded in the downloading phase. It is also possible to provide the processor with inputs in any order by specifying their identification numbers. Two basic memories are available in W.A.R.P.2.0 : the Antecedent Memory (AM) and the Program/Consequent Memory (PCM). The antecedent MFs, portrayed by a resolution of 28 elements, are stored in the AM (256 bytes). W.A.R.P.2.0 exploits a SGS-THOMSON patented strategy to store the MFs in the AM. The information about Rules and Consequent MFs are stored in the PCM (1.4 Kbyte). FUZZYSTUDIO 2.0 is a powerful development environment consisting of board and software allows an easy configuration and use of W.A.R.P.2.0. W.A.R.P.2.0 Table 1. Pin Description Pin Assignment Name Pins Type Function 11,26,31,40,48,57 VDD - Power Supply 1,10,25,30,39,47,56 19 12 VSS TEST MCLK I I Ground Testing (It must be connected to VSS) Master Clock (up to 40 MHz) 13 PRESET I Preset 15 AUTO I Auto/Manual-Boot 65 SIS0 I Auto-Boot Speed (Ext. Memory Support AccessTime) / Input Selection bit 0 64 SIS1 I Auto-Boot Speed (Ext. Memory Support Access Time) / Input Selection bit 1 63 SIS2 I Auto-Boot Speed (Ext. Memory Support Access Time) / Input Selection bit 2 67 68 2 I0 I1 I2 I I I Data Input bit 0 Data Input bit 1 Data Input bit 2 3 I3 I Data Input bit 3 4 I4 I Data Input bit 4 5 6 7 I5 I6 I7 I I I Data Input bit 5 Data Input bit 6 Data Input bit 7 14 OFL I Off-Line/On-Line Switch 18 RD I Handshaking Read Ready 16 17 66 LASTIN OE WAIT I I I Last Input (Start Elaboration) bit Output Enable/3-STATE bit Temporary Output Processing Stop 24 READY O Handshaking Output Signal 21 ENDOFL O Offline Phase (external memory downloading) End 23 20 22 BUSY DS ERR O O O Elaboration Phase Indicator Data Strobe (Output Ready Signal) Error Flag 33 OC0 O Output Identifier bit 0 32 OC1 O Output Identifier bit 1 55 54 O0 O1 O O External Memory Address/Defuzzified Output bit 0 External Memory Address/Defuzzified Output bit 1 53 52 O2 O3 O O External Memory Address/Defuzzified Output bit 2 External Memory Address/Defuzzified Output bit 3 51 O4 O External Memory Address/Defuzzified Output bit 4 50 49 38 O5 O6 O7 O O O External Memory Address/Defuzzified Output bit 5 External Memory Address/Defuzzified Output bit 6 External Memory Address/Defuzzified Output bit 7 37 O8 O External Memory Address bit 8 / Next Input Progressive Number bit 0 36 O9 O External Memory Address bit 9 / Next Input Progressive Number bit 1 35 O10 O External Memory Address bit 10 / Next Input Progressive Number bit 2 34 O11 O External Memory Address bit 11 / Start Conversion for the external A/D 3/28 W.A.R.P.2.0 PIN DESCRIPTION Signals READY, RD, WAIT, DS, BUSY, LASTIN and O11 ( external A/D Start Conversion) have programmable polarity, see table 6 for default values. VDD, VSS. Power is supplied to W.A.R.P. using these pins. VDD is the power connection and VSS is the ground connection; multi-connections are necessary. MCLK. Master Clock (Input): This is the input master clock whose frequency can reach up to 40MHz (MAX). During the Off-Line phase with AUTO High, the MCLK is internally divided to utilize boot memories working with a slower frequency.The access speed is presettable by means of SIS0-SIS2 pins. PRESET. Preset (Input, active Low) : This is the restart pin of W.A.R.P.. It is possible to restart the work during the computation (On-Line phase) or before the writing of internal memories (Off-Line phase). In both cases it must be put Low at least for a clock period. After PRESET Low the processor remains in the reset status 3 MCLK pulses. AUTO. Auto-Boot: (Input, active High): During the Off-Line phase AUTO High enables the automatic boot of W.A.R.P.2.0 whereas AUTO Low validates the manual downloading. The manual boot has to be performed using the handshaking signals RD/READY. During the On-Line phase AUTO High disables the generation of the Start A/D conversion (O11) signal. SIS0-SIS2. Speed & Input Selection (Inputs): During the Off-Line phase with AUTO High (Auto-Boot) SIS bus allows to choose the speed of downloading from the external memory which contains the startup configuration of W.A.R.P.2.0. In that case (AutoBoot) MCLK is internally divided to provide a slower sinchronization signal which is automatically used as RD for the reading of the external memory. Table 2 shows how to preset the frequency of this synchronization signal. During the On-Line phase in Slave mode (see Register Bench description, Tab.5) SIS bus allows to provide W.A.R.P.2.0 with inputs in any order by specifying their identification number. The input and its identification number (SIS0-SIS2) will be acquired at the next active RD so they must be already stable when RD is given. Table 2. Downloading Speed SIS0 SIS1 SIS2 Internal Synchronization Signal Frequency Low High Low Low Low Low MCLK/32 MCLK/16 4/28 I0-I7. Input bus (Input): During the Off-Line phase these 8 data input pins accept addresses and data from the external boot memory containing W.A.R.P.2.0 configuration. This start-up memory (which can be a ZERO-POWER, the host processor memory, an EPROM, a Flash, the PC Memory, etc.) contains the fuzzy project built by means of FUZZYSTUDIO 2.0. In On-Linemode this bus carries the input variables according to the prefixed order. OFL. Offline (Input, active High): When this pin is High, the chip is enabled to load data in the internal RAMs (Off-Line phase). It must be Low when the fuzzy controller is waiting for input values and during the processing phase (On-Line phase). When OFL changes its status the processor remains presetted for 3 clock pulses. LASTIN. Last Input (Input, default active High): During the On-Line phase in slave mode (see Register Bench description, table 5) LASTIN High indicates no other inputs have to be provided so W.A.R.P.2.0 can start the processing phase. W.A.R.P.2.0 inputs are those in the input interface so if some variables do not need to be acquired again (because they change slower than others) they remain stored and no extra time is required to acquire them again. OE. Output Enable (Input, active Low): OE Low enables O0-011output bus or (if High) put it in 3-STATE. WAIT. Wait (Input, default active High): This pin High stops the output processing. When WAIT is enabled W.A.R.P.2.0 finishes to compute the current output variable but it does not give it on the output bus until WAIT becomes Low. This signal allows to synchronize W.A.R.P.2.0 with slower devices. RD. Read (Input, default active High): Both in Off-Line and in On-Line mode RD indicates data are ready to be acquired from the input bus I0-I7. READY. Ready (Output, default active High): Both in Off-Line and in On-Line mode RD indicates data have been acquired from the input bus I0-I7 and are now stored in W.A.R.P.2.0 internal registers. ENDOFL. End of Off-Line phase (Output, active High): This pin indicates the end of the downloading phase (Off-Line) so the content of the boot memory is already stored in W.A.R.P.2.0 internal memories. After ENDOFL is active the user can put OFL Low so the On-Line phase can start. BUSY. Busy Signal (Output, default active High): When the elaboration phase is running this pin is active. When W.A.R.P.2.0 finishes to compute the last output variable, it puts BUSY Low and waits for new inputs. W.A.R.P.2.0 DS. Data Strobe (Output, default active High): The strobe pin enables the user to utilize the output. When this pin is High it indicates that a new output variable has been calculated and it is ready on the output bus (O0-O7). This signal synchronizes the external devices and in particular the interfaces with the controlled processes (On-Line mode). ERR. Error (Output, active Low): When this pin is active, W.A.R.P.2.0 has incurred in an internal error condition. OC0-OC1. Output Counter (Output): This 2 bit output bus provides the output variables with a progressive number during the On-Line phase. As a consequence it is possible to know to which variable correspond the data that are on the output data bus (O0-O7). The dimension of OC bus is connected with the maximum number of output variables (4). O0-O11. Output Bus (Output): In the Off-Line phase these pins provide the addresses (12 bit) for its internal memories and send those addresses to the external memory support where data to load are located. These addresses sent on O0-O11 bus allow to identify the data that have to be loaded in W.A.R.P.2.0 internal memories. In the On-Line phase O0-O7 carrie out the output values. When the DS is High, one output variable can be read by external devices. The resolution of output variables is 256 points (8 bit). If there is more than one output, the output variables are calculated one by one and they are provided in the sequence stabilized during the editing phase (see FUZZYSTUDIO 2.0 User Manual). In On-Line mode O8-O10 provide the progressive number of the next variable to be acquired. These pins can be used to select the next input to provide on I0-I7 bus. Still in on-line mode O11 allows to provide a presettable signal which can be used as Start-Conversion for an A/D converter after (about 400 ns) OFL or BUSY fall. 5/28 W.A.R.P.2.0 FUNCTIONAL DESCRIPTION W.A.R.P.2.0 works in two mode depending on the OFL control signal level (see table 3) : Off-line MODE (OFL High) On-line MODE (OFL Low) OFF-LINE MODE All W.A.R.P. memories are loaded during the OffLine phase. The membership functions are written inside their related memories and the process control rules are loaded inside the PCM. The addresses of the words to be written in the memories, are internally generated while the addresses of the external memory locations to be read are directly provided by W.A.R.P.2.0 by means of O0-O11 output pins. Data must be loaded 8 bit a time in the data bus and can be read from an external non volatile memory or loaded by an host processor. The Off-Line phase can be performed automatically (see figure 4) or manually (see figure 5). When the auto-boot is chosen (AUTO = High) it is possible to configure the reading access time of the external memory. The auto-boot end is indicated by the ENDOFL signal. The downloading phase requires: F*NWordsDatabase clock pulses, where F is 16 or 32 (see table 2). NWordsDatabase is the number of words stored in the boot-memory (see register bench description, table 5). When the manual-boot is chosen (AUTO = Low) data have to be provided by using the handshaking signals (RD/READY). In this way it is possible to update only a portion of the database or change the processor configuration. The time required from the manual boot depends on the efficiency of the communication handled with the handshaking signals. Figure 4. Off-Line phase: Auto-Boot Auto-Boot Enable AUTO=HIGH AUTO OFL H Off-line Phase Enable OFL=HIGH H I0-I7 BOOT MEMORY External Memory Access Time SETTING SIS0-SIS2=LowLow... O0-O11 W.A.R.P.2.0 SIS0-SIS2 ENDOFL Downloading From External Memory OFFLINE PHASE ENDS ENDOFL=HIGH Figure 5. Off-Line Phase: Slave Downloading Manual-Boot Enable AUTO=LOW AUTO L OFL H I0-I7 Off-line Phase Enable OFL=HIGH Downloading with Handshaking Signals RD/READY 6/28 BOOT MEMORY OFFLINE PHASE ENDS O0-O11 W.A.R.P.2.0 RD READY W.A.R.P.2.0 ON-LINE MODE In On-line mode (see figure 7) W.A.R.P.2.0 is enabled to elaborate input values and calculate outputs according to the fuzzy rules stored into the microprogram. W.A.R.P.2.0 reads the input values one a time in the input data bus using the RD/READY signals. If the processor is working in SLAVE mode (see register bench description in table 5) the user has to provide the inputs with their identificationnumbers (by means of SIS0-SIS2), so it is possible to provide inputs in any order. In SLAVE mode it is a ls o po ssib le to f orce W.A.R.P.2.0 to start the elaboration phase (by means of LASTIN) without providing all inputs, for instance when input variables change with different speed. In this case the outputs that have not be provided in this cycle, but sampled in the previous ones, are recovered from the internal buffers. When all inputs are given or a LASTIN signal is given, the elaboration phase starts. The elaboration phase is divided in two main parts. During the first one the input values are read and the corresponding ALPHA values (activation levels) are calculated. In the second part the computation of the fuzzy rules and the defuzzification are implemented. W.A.R.P.2.0 acquires each input in 8 clock pulses (min). Since the acquisition phase is performed by the user by means of the handshaking signals, 8 clock pulses per input are referred to the most efficient case. In figure 6 are shown the perform- Figure 6. W.A.R.P.2.0 performances Num b e r of Clock Pu ls e s 8.0 00 6.0 00 4.0 00 2.0 00 0 0 64 1 28 Num b e r of Ru le s 192 256 Numbe r of Inputs = 8 ances in case of 8 inputs. If you are using less inputs you have to subtract 8 clock pulses for each of them. The elaboration time for rule requires 32 clock pulses. For instance if W.A.R.P.2.0 is working at a frequency of 40 MHz (25ns period) with 8 inputs and 128 rules globally (for all outputs) the time required to provide all outputs is 4000clkp*25ns = 100µs. Figure 7. On-Line phase O n-line Ph a se Ma ster (”MASTER” s e t in th e regi ster ben ch) On-line Ph a se Sl ave (”SLAVE” set in the register be nc h) CHIP PRESET CHIP PRESET O n-line Ph a se Ena ble O FL=LOW O n-line Ph a se Ena ble O FL=LOW Input s Acquisition with Hands ha king Sign als (RD/READY) Acquisition with Hands haking by s p ecifying which inputs is on the input bu s by m e an s of SIS0-SIS 2 En d of Acquisition Ph a se S tart Elaboration Pha se Elaboration P h a se Last Input h as b een give n LASTIN=HIGH O utputs Gen eration DS=HIGH End of Acquisition Ph as e S tart Elabora tion Pha se Elabora tion P h ase Outputs Ge n eration DS=HIGH 7/28 W.A.R.P.2.0 Table 3. Operating Modes (1) Mode PRESET OFL AUTO OE I0-I7 Off-Line Slave VIH VIH VIL X Data In Off-Line Autoboot VIH VIH VIH VIH Data In On-Line Master(2) VIH VIL X (2) VIH Data In X Data Out Next Input On-Line (3) Slave VIH VIL X (2) VIH Data In Input Selection Data Out X Output Disable VIH X X VIL X X X X X X X X X Reset(4) RD SIS0-SIS2 O0-O7 O8-O10 X X X Clock Rate Selection Code O11 OC0-OC1 X X X External Memory Addresses X (2) (2) Hi-Z VOL VOL Output Selection Output Selection X VOL VOL Notes: 1. This table uses default active handshaking signal polarity (see table 6), X = don’t care. 2. If AUTO is High pulse in O11 is absent. 3. LASTIN and WAIT pulses are optional. 4. Same operation is obtained when positive and negative OFL transactions occour. INTERNAL STRUCTURE The block diagram shown in figure 2 describes the structure of W.A.R.P.2.0 (a more detailed block diagram is shown in fig. 11). Input Port. This internal block performs the input data routing. Data are read one byte a time from the input data bus, internally stored, and sent to the ALPHA calculator following the rules loaded in the Program Memory. Input data resolution is 8 bit. The cycle starts when all inputs or a LASTIN High have been provided and continues until BUSY is active or a PRESET signal is given. When BUSY becomes inactive a new acquisition phase can start. Alpha Calculator. This block calculates the intersection (ALPHA weight) between an Antecedent Membership Function and the corresponding crisp input (see figure 8). Inference Unit. Thanks to the Theta Operator, the Inference Unit generates the THETA weights which are used to manipulate the consequent MFs. This is a calculation of the maximum and/or minimum performed on ALPHA values according to the logical connectives of fuzzy rules. It is possible to utilize the AND/OR connectives and to directly exploit ALPHA weights or the negated values. The number of THETA weights depends on the number of rules. The rules can have at maximum four ALPHA weights (however they are connected).Two or more 8/28 rules can be only joined with the OR connective. Inference Unit structure is shown in figure 9. Defuzzifier. It generates the output crisp values implementing the consequent part of the rules. In this method consequentMFs are multiplied by a weight value Ω (OMEGA), which is calculated on the basis of antecedent MFs and logical operators. The processing of fuzzy rules produces, for each output variable, a resulting membership function. Each MF related to the processed output variable is firstly modified by a rule weight. Output value (Y) is deduced from the centroids (Xi) and the modified MFs (Ωi ) by using the formula: n ∑ Y = Ωi ∗ Xi 1 n ∑ Ωi 1 n = number of MFs of the Output Variable. Xi =absciss of the MFi centroid. Ωi =membership degree of the output MFi. Two parallel blocks calculate the numerator and denominator values to implement the centroids formula. A final division block calculates the output values (see figure 10). W.A.R.P.2.0 Output Port. This block provides the output data supported by handshaking signals. Ouput data resolution is 8 bit. An output ready on the bus O0-O7 is indicated by a DS pulse and by its identification number (OC0OC1). WAIT active temporarily stops the elaboration phase allowing the synchronization with slower devices. Programmable A/D output pulse. This block allows to program the width of the pulse provided on O11 (only in On-Line mode) that can be used as a Start Conversion for an external A/D. The width of this pulse can be configured by means of the related register (see register bench description) following the table 4. Table 4. Start Conversion Pulse (O11) Width Setting. Start conversion Pulse Register Low, Low, Low Low, Low, High Pulse Width (TCLK = MCLK Period) 128xTCLK 256xTCLK Low, High, Low 2040xT CLK Low, High, High 4080xT CLK High, Low, Low High, Low, High 8160xT CLK 16320xT CLK High, High, Low High, High, High 32000xT CLK 65520xT CLK 9/28 W.A.R.P.2.0 Figure 8. ALPHA Calculator Structure IN P U T AN T E C E D E N T M F 8 12 8 12 C O M P A R AT O R M U X M U X M U X S u b t ra c t o r M u lt ip li e r M AX TR U T H LE V E L A d d e r C O M P A R ATO R M U X 4 α Figure 9. Inference Unit Structure 4 A LP H A 1 R e g is t e r A LP H A 2 4 R e g is t e r A LP H A 4 3 A LP H A 4 4 R e g is t e r R e g is te r M A X /M IN M A X /M IN S e le c t o r M IC R O CODE M A X /M IN T H E TA 4 M A X /M IN R e g is t e r O M EG A 4 Figure 10. Defuzzifier Structure. X i O ME G A 4 8 M u ltip lie r P R O G R AM M E MO R Y Ad d e r Ad d e r D ivid e r 8 O U T P UT 10/28 W.A.R.P.2.0 Figure 11. Detailed Block Diagram L F O Y Y D A B U S E N D O R E CO 0C 1 O 0 O 1O 2O 3O 4 O 5O 6O 7 O 1 1 O 0 9 O 8 O R S E RD 1 Q O D C O U N T E R R C O U N T E R C O M P 2 1 P 2 1 MU X R U N T E O C 2 PR 1 2 1 2 1 8 K C L D E RS O A O F R D U MO B L WO N T F L 4 D E F U Z 0 1 4 M IP C 2 I U N I T N F 6 M A D T D M 4 A T 4 2 T U 3 T U 2 N T R T U 1 O L O G I T U 0 C 7 6T I T 5I 4T I T 3I 2T I T 1I 0T I T I O CL 4 Q 4 4 Q Q D D D D T U 0 T U 1 T U 2 T U 3 6 1 M Q IT A IN T W UX α 4 C A L C U L A T O R MU X D IT A IN T R IN T W 2 3 0 2 Q 8 6 16 32 K K / / C L C L 6 6 M D A UX M MU X 6 D 2 3 6 D 3 8 8 8 8 8 8 8 8 3 E R S T O GMNI C H F RR BE E L K N I T CR 2 M A D T K C L MU X Q Q 0 Q 1 2 4 4 M PC 4 4 8 PR 8 8 1 T I 0 T I Q D 8 2 T I Q Q P R D PR 8 3 T I Q PR D 4 6 M P I C 8 4 T I 8 5 T I Q PR D 8 6 T I Q PR D D 8 7 T I PR D C O U N T E R Q Q PR PR PR D D Q Q 0 Q 1 2 1 D 0D D 2 N I T R 8 UX O F ML I N P U T R E G I S T E Q R S T R D D T RS S S V MU X O F N O I S TS IS SIS 0SIU 1ST 2 A L A Q R D S T T E I0 I1 I2 I3 I4 I5 I6 L S S V O F L I7 D E TD V ES PR S S V T L KIA W M C O 11/28 W.A.R.P.2.0 possible to have up to 16 MFs for each input. If W.A.R.P.2.0 has been configured to accept up to 8 inputs it is possible to have up to 8 MFs for each input. Each MF of the AM contains 3 (or 2) bit indicating to which input variable the MF is correlated. MEMORY There are three memories in W.A.R.P.2.0, the Antecedent Memory (AM), The Program/Consequent Memory (PCM) and the Register Bench (RB). The AM is divided in 4 spaces, each having a maximum of 64 bytes. It is also possible to divide the AM in 8 parts, each having a maximum of 32 bytes. It is possible to configure the AM in the following modes (see fig. 12): a) up to 4 inputs, each with 16 Antecedent MFs (MAX); b) up to 8 inputs, each with 8 Antecedent MFs (MAX); Each word (4 byte) of the AM contains the data of a single MF related to an input. If W.A.R.P.2.0 has been configured to accept up to 4 inputs it is The PCM is composed by 256 words (see fig. 13). Each row (word) is related to a single rule and contains 36 bit of microcode and 8 bit indicating the consequent MF (crisp) related to this rule. The RB contains data for the configuration of the processor that can be set by software. It is possible to fix: the number of inputs, the number of outputs, the address of the last word to load from the external memory, the number of MF per input, the width of the start A/D conversion pulse, the handshaking signals polarity and the functioning mode of the processor (Master/Slave). Figure 12. Antecedent Memory Spaces. 64 64 Memb er ship Functions related to INPUT 4 MFs relate d to INPUT7 48 MFs relate d to INPUT6 Memb er ship Functions related to INPUT 3 MFs relate d to INPUT5 32 MFs relate d to INPUT4 Memb er ship Functions related to INPUT 2 MFs relate d to INPUT3 16 16 MFs relate d to INPUT2 Memb er ship Functions related to INPUT 1 8 0 0 MFs relate d to INPUT8 0 MFs relate d to INPUT1 8 0 Figure 13. Program/Consequent Memory and Register Bench. 25 6 Microco de Cons e que nt MFs rela te d to RULE 256 4 Hands haking signal s polarity 3 2 2 12/28 1 Microco de Cons e que nt MFs rela te d to RULE 2 1 0 Microco de Cons e que nt MFs rela te d to RULE 1 0 Numb e r of Inputs -1 Num be r of Outputs - 1 Antece dent Me mory Configuration A/D Sta rt Conve r sion Pulse width On-Line phase Ma ste r/Slav e Numbe r of Words to lo ad from the ex ternal Me mory W.A.R.P.2.0 Table 5. Register Bench Description. Register Name Resolution Function Handshaking Signal Polarity (ONLY during the On-Line Phase) 8 0 active Low, 1 active High (default) bit 0 READY bit 1 RD bit 2 WAIT bit 3 DS bit 4 BUSY bit 5 LASTIN bit 6 not connected bit 7 START CONVERSION Number of Inputs - 1 Number of Outputs - 1 3 2 000-111 = 1 to 8 Inputs 00 - 11 = 1 to 4 Outputs Antecedent Memory Configuration 1 A/D Conversion Pulse Width 3 On-Line Phase Master/Slave 1 0 = Slave Functioning 1 = Master Functioning Number of Words to load from the External Memory 12 0000000000000-100110000100 from 0 to 2436 words to read 0 = 8 Inputs, 8 MFs per Input 1 = 4 Inputs, 16 MFs per Input see table 4 Note: These Registers are configurable by means of the FUZZYSTUDIO 2.0. Table 6. Default Active Handshaking Signal Polarity READY RD WAIT DS BUSY LASTIN START C ONVERSION (O11) High High High High High High High Note: Default polarities are used in the following timing diagrams 13/28 W.A.R.P.2.0 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VDD Supply Voltage -0.5 to 7 V IDD Supply Current 50 mA +24 -12 0 to +70 mA mA °C IOL IOH TOPT Output Sink Peak Current Output Source Peak Current Operating Temperature Note: Stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. Table 7. Recommended Operation Conditions (1) Symbol Min Typ Max Unit VDD VI Supply Voltage Input Voltage 4.75 0 5.0 5.25 VDD V V VO tIR (2) Ouput Voltage Input Rise Time 0 VDD 40 V ns 40 ns tIF (2) Parameter Input Fall Time Notes: 1. Operating Condition: VDD=5V±5%-T A=0 °C to 70 °C, unless otherwise specified. 2. See fig. 22. DC ELECTRICAL CHARACTERISTICS VDD = 5V±5% TA = 0 to +70 °C unless otherwise specified. Symbol Parameter VIL Low Level Input Voltage VIH VOL VOH High Level Input Voltage Low Level Output Voltage High Level Output Voltage VT+ Schmitt trig. +ve Threshold see fig. 14 0.8 V VT- Schmitt trig. - ve Threshold see fig. 14 2.0 V (1) Low Level Leakage Input Current High Level Leakage Input Current VI=VSS VI=VDD(3) (3) -1 +4 (2) Low Level Input Current VI=VSS (2) IIH High Level Input Current VI=VDD IOL Tri-State Output Leakage Current IIL IIH(1) IIL Notes: 1. All inputs with the except of OE and TEST. 2. Only OE and TEST inputs. 3. IOH = -400µA, IOL = +16mA, T = +25°C. 14/28 Condition Min Typ Max V 0.4 V V V 2.0 2.4 0.2 3.4 Unit 0.8 -2 nA nA (3) 100 nA (3) 160 µA ±10 µA VO=VSS or VDD W.A.R.P.2.0 Figure 14. TTL-level input Schmitt trigger characteristic. 5 4 V = 5V DD TA = 25°C 3 V0 (V) (TYPICAL) 2 1 0 0.5 0.8 1.0 1.5 2.0 2.5 V (V) I Figure 15. Input Pin Equivalent Circuit (1) Pull Down Figure 16. Input Pin Equivalent Circuit (2) VDD VDD DEVICE INPUT RS V IN R PD VSS V DEVICE INPUT RS V IN 0 VSS Note: 1. Only OE and TEST pins. 0 CIN CIN VS S V VS S VS S Note: 1. All input pins except for OE and TEST. 15/28 W.A.R.P.2.0 Figure 17. Equivalent Tristate Output Circuit (1) Figure 18. Equivalent Output Circuit (1) CONTROL SIGNAL DEVICE O UTPUT DEVICE OUTPUT COUT C OUT VS S VSS Note: 1. Only O0-O11 pins. Note: 1. All output pins except for O0-O11. Table 8. Equivalent Circuit Parameters Symbol Parameters Test Conditions Max Unit C IN Input Capacitance VI = 0V f = 1.0 MHz 15 pF COUT Output Capacitance VO = 0V f = 1.0 MHz 15 pF RS Stray Resistor RPD Pull Down Resistor Typ VI = 2V, VDD = 5V VI = 0.8V, VDD = 5V Figure 19. AC Test Circuit (1) VDD Min 20 Ohm 16K 13.6K Ohm Figure 20. AC Test Circuit (1) VDD DEVICE O UTPUT R L2 D EVICE O UTPUT VDD D.U.T. D.U.T. R L1 CL INCLUDING PR O BE CA PACITANC E RL CL VSS VS S Note: 1. Only O0-O11pins. 16/28 Note: 1. All output pins except for O0-O11. INCLUDING PRO BE CAPACITANCE W.A.R.P.2.0 AC ELECTRICAL CHARACTERISTICS VDD = 5V±5% TA = 0 to +70 °C unless otherwise specified. Figure 22. Input/Output Rise & Fall Times Figure 21. Data Input Timing tCLL tCLH INPUT 90% VDD 5 0% VSS tC P tIF 3.2V 90% 90% 5 0% OUTPUT 10% 10% VSS tS ET Clock 0V tIR VDD Data tHLD VDD 5 0% 5V 90% 10% 10% tOR 0.1V tOF VSS Table 9. Timing Parameters Test Conditions Symbol Parameters Min Typ tCLH tCLL Clock High Clock Low tSET Setup 15 ns tHLD tOR tOF Hold Output Rise Output Fall 15 3 3 ns ns ns 10 15 see fig.22 see fig.22 Max Unit ns ns Test Conditions MCLK frequency = 40MHz, T = +25°C. 17/28 W.A.R.P.2.0 OFF-LINE SLAVE DOWNLOADING PHASE TIMING AUTO OFL INP 0 I0-I7 INP 1 INP 2 INP N RD READY T T 1 T 2 T T 3 T T 3 2 2 2 Table 10. Off-Line Slave Timing Parameters Symbol T1 T2 T3 Mode Off-Line Slave Off-Line Slave Parameter OFL High to first RD High RD High to READY High Off-Line Slave READY Low to RD High Min Typ Max Unit Clock Pulses Clock Pulses 3 4 Clock Pulses 3 Figure 23. Off-Line Slave Typical Application 8 A9-A16 ADDRESS BUS MCLK AS OE ADDRESS DECODE OFL READY AUTO HIGH RD/WR 8 micro 18/28 DS W.A.R.P. 2.0 BUSY I0-I7 8 READY AD0-AD7 PRESET RD DATA BUS W.A.R.P.2.0 OFF-LINE AUTO-BOOT PHASE TIMING AUTO OFL INP 0 I0-I7 ADDR 0 O0-O11 INP 1 INP N ADDR 1 ADDR N READY ENDOFL T 1 T 2 T T 3 3 Table 11. Off-Line Auto-Boot Timing Parameters Symbol Mode Parameter T1 Off-Line Auto-Boot OFL High to Address Valid Off-Line Auto-Boot Off-Line Auto-Boot Address Valid to Input Sampling Address Valid to next Address Valid T2 T3 (1) Min Typ Max Unit Clock Pulses 3 8 16 32 Clock Pulses Clock Pulses Note: 1. see Table 2. Figure 24. Off-Line Auto-Boot typical Application MCLK OFL HIGH AUTO LOW OE HIGH PRE SET READY ENDOFL 8 I0-I7 OE DATA OUT W.A.R.P. 2.0 ADDRESS INPUT MEMORY se e table 2 SIS0-SIS 2 O0-O11 12 19/28 W.A.R.P.2.0 ON-LINE SLAVE PHASE TIMING OFL I0-I7 INP 0 INP 1 SIS0-SIS2 ADDR 0 ADDR 1 INP N-1 ADDR N-1 INP N ADDR N LASTIN T RD 1 READY T WAIT 2 T 3 T BUSY T T 4 DS 6 T 5 T T 8 O0-O7 OUT 0 7 T 8 OUT 1 9 OUT N-1 OUT N Table 12. On-Line Slave Timing Parameters Symbol T1 T2 T3 T4 T5 (1) T6 T7 T8 T9 Mode Parameter On-Line Slave On-Line Slave On-Line Slave OFL Low to first RD High RD High to READY High READY High to next RD High On-Line Slave On-Line Slave On-Line Slave Last RD High to BUSY High BUSY High to first Output Ready Elaboration Time On-Line Slave On-Line Slave On-Line Slave Wait Low to next Output Valid Min Typ Max 3 2 5 Clock Pulses Clock Pulses Clock Pulses 10 64 see fig.6 32 DS Pulse Width 5 LAST DS Pulse Width 1 Unit Clock Pulses Clock Pulses Clock Pulses Clock Pulses Clock Pulses Clock Pulses Note 1. T7 depends on the number of rules related to the current output variable. Each output variable needs at least two rules and each rule requires 32 clock pulses. 20/28 W.A.R.P.2.0 ON-LINE SLAVE TYPICAL APPLICATION 8 ADDRESS BUS A9-A16 MCLK AS OE ADDRESS DECODE OFL AUTO HIGH PRESET RD/WR READY RD W.A.R.P. 2.0 DS micro WAIT OE 3 DATA REGISTER 3 LASTIN 8 SIS0-SIS2 8 O0-O7 I0-I7 BUSY READY AD0-AD7 DATA BUS 21/28 W.A.R.P.2.0 ON-LINE MASTER PHASE TIMING OFL INP 0 I0-I7 INP 1 INP N RD READY T T 4 5 WAIT T BUSY 9 T T 6 DS 8 T T 10 T 10 11 T 3 T 7 OUT 0 O0-O10 OUT 1 OUT N-1 OUT N O11 OC0-OC1 ADDR 0 T ADDR 1 ADDR N-1 ADDR N T 1 2 T 3 Table 13. On-Line Master Timing Parameters Symbol Mode Parameter T1 On-Line Master OFL Low to first RD High On-Line Master On-Line Master RD High to READY High OFL/BUSY Low to O11 Pulse T4 On-Line Master RD High to next RD High 10 Clock Pulses T5 On-Line Master READY High to BUSY High 1 Clock Pulses (1) On-Line Master BUSY High to first Output Ready 64 Clock Pulses T7(1) On-Line Master DS High to next DS High 64 Clock Pulses T8 On-Line Master WAIT Low to next Output Valid On-Line Master On-Line Master Elaboration Time see fig.6 DS Pulse Width 5 LAST DS Pulse Width 1 T2 T3 T6 T9 T10 T11 On-Line Master Min Typ Max Unit Clock Pulses 3 Clock Pulses Clock Pulses 2 10 32 Clock Pulses Clock Pulses Clock Pulses Clock Pulses Note 1. It depends on the number of rules related to the current output variable. Each output variable needs at least two rules and each rule requires 32 clock pulses. 22/28 W.A.R.P.2.0 ON-LINE MASTER TYPICAL APPLICATION MCLK OFL CS ANALOG INPUTS INPUT S ELECT RD LOW AUTO LOW OE HIGH PR ES ET 8 DATA OUT READY ENDOFL I0-I7 W.A.R.P. 2.0 INT MULTIPLE A/D CONVERTER OC0-OC1 3 CS RD DS O0-O11 ANALOG OUTPUTS DATA IN 8 12 WR 2 OUT SELECT MULTIPLE D/A CONVERTER 23/28 W.A.R.P.2.0 PROGRAMMING TOOLS Figure 25. FUZZYSTUDIO 2.0 Block Diagram HIGH LEVEL SUPPORT TOOLS BASIC TOOLS AFM SUPPORT TOOLS IMPORTER Adaptive Fuzzy Modeller EMULATORS ANSI C EDITORS MATLAB EXPORTER COMPILER BOARD MANAGER RS232 FUZZYSTUDIOADB2.0 Application Development Board DEBUGGER W.A.R.P. FUZZYSTUDIO2.0 FUZZYSTUDIO 2.0 SGS-THOMSON has developed a software tools to support the use of W.A.R.P.2.0 allowing easy configurating and loading of the memories and functional simulations. It has been designed in order to be used with the following hardware/software requirements: 80386 (or higher) processor VGA / SVGA screen Windows Version 3.0 or Higher The constituting blocks are: Editors it is a tool to define the fuzzy controller with a User-Friendly Interface. It is composed by: – Variables Editor: to define the I/O variables, and to draw relatedmembership functions. – Rule Editor (to define the base of knowledge) Compiler it generates the code to be loaded in W.A.R.P.2.0 memories according to the data defined through the editor. It also generates the data base for Debugger, Exporter and Simulator. 24/28 Debugger it allows the user to examine step-by-step the fuzzy computation for a defined application. It also allows to check the results of the entire control process by using a list of patterns stored into a file. Exporter it generatesfiles to be imported in different environments in order to develop W.A.R.P.2.0 based simulations exploiting user-developed models. It addresses the following environments: Standard C: the exporter generates C functions that can be recalled by an user program MATLAB: the exporter generates a ’.M’ file that can be used to perform simulations in MATLAB environments Importer It allows to use a fuzzy project edited by a development system of a different hardware device, i.e. W.A.R.P.3 family, or by the AFM. Board Manager It allows the W.A.R.P.2.0 and ZEROPOWER programming, board testing and project debugging directly on the silicon. W.A.R.P.2.0 FUZZYSTUDIO ADB2.0 DESCRIPTION The board has been designed to be connected to the RS232 port of an IBM PC 386 (or higher), but it can also work stand alone. It can manage up to 8 digital inputs and 4 digital outputs. Inputs and outputs are provided at TTL compatible level. The board allows the user to charge the rules and the membership functions (see FUZZYSTUDIO 2.0 User Manual) into the W.A.R.P.2.0 memories. The clock generator frequency on board is 8 MHz. An automatic trigger is used to synchronize W.A.R.P.2.0 with the external environment (working connected with a PC). When the board is used deconnected from a PC all the fuzzy data (membership functions and rules) are stored in a ZEROPOWER SRAM. Figure 26. FUZZYSTUDIO ADB2.0 Board Layout Tab. 14 Ordering Information Order Code STFLSTUDIO2/KIT Device STFLWARP20/PL Development Tools FUZZYSTUDIO ADB2.0 W.A.R.P.2.0 W.A.R.P.2.0 programmer ZEROPOWER programmer RS-232 communication handler Internal Clock SW Tools Variables and Rules Editor W.A.R.P.2.0 Compiler/Debugger Exporter for ANSI C and MATLAB Importer from AFM 25/28 W.A.R.P.2.0 Adaptive Fuzzy Modeller Adaptive Fuzzy Modeller (AFM) is a tool that easily allows to obtain a model of a system based on Fuzzy Logic data structure, starting from the sampling of a process/function expressed in terms of Input\Output values pairs (patterns). Its primary capability is the automatic generation of a database containing the inference rules and the parameters describing the membership functions. The generated Fuzzy Logic knowledge base represents an optimized approximation of the process/function provided as input. The AFM has the capability to translate its project files to FUZZYSTUDIO project files, MATLAB and C code, in order to use this environment as a support for simulation and control . The block diagram illustrates the AFMdesign flow. SUPPORTED TARGETS The supported environment are: - W.A.R.P. 1.1 using FUZZYSTUDIO 1.0 - W.A.R.P.2.0 using FUZZYSTUDIO 2.0 - MATLAB - C Language - Fu.L.L. (Fuzzy Logic Language). SYSTEM REQUIREMENTS MS-DOS version 3.1or higher Microsoft Windows 3.0 or compatible later version 486, PENTIUM compatible processor chip 8 MBytes RAM (16 Mbytes recommended) Hard Disk with at least 1MBytes free space Figure 27. AFM Design Flow pattern file rules minimizer Learning Phases Fuzzy Logic knowledge base exporter to processor Rules extractor MFs tuning Simulation and Manual Tuning W.A.R.P. 1.1 W.A.R.P. 2.0 ANSI C MATLAB Table 15. Ordering Information Order Code Description Support ed Target STFLWARP11/PG STFLWARP11/PL WTA-FAMfor Building Rules STFLAFM10/SW STFLWARP20/PL BACK-FAM for Building MFs ANSI C MATLAB 26/28 Functionalities System Requirement Rules Minimizer MS-DOS 3.1or higher Step-by-Step Simulation Windows 3.0 or later Simulation from File 486, PENTIUM compatible Local Tuning 8 MB RAM W.A.R.P.2.0 PACKAGE DIMENSIONS Dim. mm A B 24.13 24.33 0.950 D 4.20 5.08 0.165 d1 d2 E Typ. inches Min. 25.02 Max. 25.27 Min. 0.985 2.54 0.56 22.61 1.27 F G 0.38 M M1 1.27 1.14 Max. 0.995 0.958 0.200 0.100 0.022 23.62 e Typ. 0.890 0.930 0.050 0.015 0.10 0.004 0.050 0.044 Figure 28. W.A.R.P.2.0 PLCC68 Package Table 16. Ordering Information Part Number Maximum Frequency Supply Voltage Temperature Range Package STFLWARP20/PL 40 MHz 5±5% 0 °C to 70 °C PLCC68 27/28 W.A.R.P.2.0 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized foruse as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved FUZZYSTUDIO is a trademark of SGS-THOMSON Microelectronics MS-DOS, Microsoft and Microsoft Windows are registered trademarks of Microsoft Corporation. MATLAB is a registered trademark of Mathworks Inc. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 28/28