78P7200L
E3/DS3/STS-1
Transceiver
®
TDK SEMICONDUCTOR CORP.
March 2001
FEATURES
DESCRIPTION
The 78P7200L is a line interface transceiver IC for
E3, DS3, STS-1, North America T3 and ATM
applications. It includes clock recovery and
transmitter pulse shaping functions for applications
using 75-ohm coaxial cable at distances up to 1100
feet. These applications include DSLAMs, T3/E3
digital multiplexers, SONET Add/Drop multiplexers,
PDH equipment, DS3 to Fiber optic and microwave
modems and ATM WAN access for routers and
switches.
•
•
•
•
•
The receiver recovers clock and positive data and
negative data from an AMI signal. It can compensate
for over 12dB of cable and 6dB of flat loss. The
transmitter generates a signal that meets the
standard pulse shape requirements.
•
•
•
The 78P7200L is pin and functionally compatible to
the 78P7200. It adds loop-back and clock polarity
selection.
•
•
•
•
The 78P7200L is manufactured in an advanced
BICMOS process and operates at both 5V and
3.3 V power supply voltages. It consumes less than
95 mA of supply current.
Single chip transmit and receive interface for
E3, DS3 and STS-1 applications.
Interface to 75 ohm coaxial cable over 1100
feet at speeds up to 51.84 Mbps.
Compliant with ANSI T1.102-1993, Telcordia
GR-499-CORE and GR-253-CORE, ITU-T
G.703 and G.823 for jitter tolerance.
Compliant with ATM FORUM af-phy-0034 (E3
public UNI) and af-phy-0054 (DS3 public UNI).
Easily Interfaced to ATM framer ICs such as
PMC 7345 , 7346 QJET and 7321.
Unique clock recovery requires no reference
clock or crystal oscillator.
Receive DS3-high signal
Includes diagnostic loop-back for AMI and digital
signals.
Pin compatible to 78P7200 and 78P2241 (28lead PLCC).
28-lead PLCC and 48-lead TQFP packages
3.3 or 5 V operation, ICC<95mA
Input circuit works either Transformer or
Capacitor coupled
BLOCK DIAGRAM
LPBK
TPOS
TNEG
TCLK
RPOS
RNEG
RCLK
LBO
Binary
to
AMI
AMI
to
Binary
TXEN
LOUTP
LOUTN
PULSE
SHAPER
Data
Slicer
Adaptive
Equalizer
Clock
Recovery
LF
Biasing
LPBK
RFO
Signal
Detector
LOS
LINP
LINN
78P7200L
E3/DS3/STS-1
Transceiver
RECEIVER
The receiver input can be either transformer-coupled
or capacitor coupled to the AMI signal.
In
applications where the highest performance and
isolation is required, a 1:1 transformer is used on the
receiver path. In the applications, where isolation is
provided elsewhere in the circuit, an AC coupling
can be used. The inputs to the IC are internally
referenced to Vcc. Since the input impedance of the
78P7200L is high, the AMI line must be terminated
to 75Ω. The input signal of the 78P7200L must be
limited to a maximum of three consecutive zeros
using a coding scheme such as B3ZS or HDB3.
FUNCTIONAL DESCRIPTION
The 78P7200L is a single chip line interface IC
designed to work with a 51.84 Mbit/s STS-1, 44.736
Mbit/s DS3 or 34.368 Mbit/s E3 signal. The receiver
recovers clock, positive data and negative data from
an Alternate Mark Inversion (AMI) signal. The AMI
line input signal should be B3ZS or HDB3 coded.
The transmitter accepts clock, positive, and negative
data and converts them into an AMI signal to drive a
75Ω coaxial cable. The shape of the transmitted
signal though any cable length of 0 to 450 feet complies
with the published templates of ANSI T1.102-1993,
Telcordia TR-NWT-000499 and GR-253-CORE, ITU-T
G.703. The 78P7200L is designed to work with B3ZS
or HDB3 coded signals. The B3ZS or HDB3 encoding
and decoding functions can be included in the framer
ICs. The 78P7200L is designed to easily connect to
popular ATM framer ICs such as PMC 7345 (SUNIPDH), PMC 7346 (QJET) and 7321.
The AMI signal first enters an equalizer and AGC
gain stage. The equalizer is designed to overcome
intersymbol interference caused by long cables.
Because the equalizer is adaptive, the circuit will work
with all square shaped signals such as DS3 high or 34
Mbit/s E3. The variable gain differential amplifier
maintains a constant voltage level output regardless
of the input voltage level. The gain of the amplifier is
adjusted by detecting the peak of the signal and
comparing it to a fixed reference.
OPERATION SPEED
Internal bias generators that are adjusted by the value of
the RFO set the 78P7200L PLL center frequency and
Transmitter amplitude for the different standards. The E#
pin controls the equalizer response and the transmitter
pulse shape and amplitude. The following table shows
the proper settings.
STANDARD
E3
DS3
STS-1
RFO VALUE,
KΩ
6.81
5.23
4.53
Outputs of the data comparators are connected to
the clock recovery circuits. The clock recovery
system employs a phase locked loop with an
auxiliary frequency-sensitive acquisition loop. This
system permits the loop to independently lock to the
frequency and phase of the incoming data stream
without the need for an external, high precision
tuned circuits or reference clock signal.
E# PIN SETTING
Low
High
Float
The jitter tolerance of the 78P7200L meets the
requirements of Telcordia GR-499-CORE for
Category I equipment for DS3 rates and exceeds the
requirements of ITU-T G.823 for E3 rates.
2
78P7200L
E3/DS3/STS-1
Transceiver
LOOP-BACK MODES:
The following loop-back modes allow for the
diagnostic test of the PC board. This function is
controlled by the LPBK pin.
FUNCTIONAL DESCRIPTION (continued)
LOSS OF SIGNAL
Should the input signal fall below a minimum value,
the loss of signal indication, LOS goes low.
TRANSMITTER
The transmitter accepts logic level clock (TCLK),
positive data (TPOS) and negative data (TNEG)
signals and generates current pulses on the LOUT+
and LOUT- pins. When properly connected to a
center-tapped 1:2 transformer, an AMI pulse is
generated which can drive a 75Ω coaxial cable.
PIN 40/TQFP
PIN 28/PLCC
LPBK
When the recommended transformer is used and the
E# pin is set high, the transmitted pulse shape at the
end of the 75Ω terminated cable of 0 to 450 feet will
fit the DS3 template in ANSI T1.102-1993 and
Telcordia GR-499-CORE standard documents.
RCLK/TCLK POLARITY REVERSAL:
To simplify the interface with framer circuitry, RCLK
and TCLK can be inverted with the ICKP pin.
TCLK
Low
Normal
Normal
Float
Invert
Invert
High
Normal
Invert
Local loop-back (LLB)
Float
Remote loop-back (RLB)
High
Normal Operation
When LPBK is low, the 78P7200L enters Local
loopback. In this mode, the LOUT+/- transmit signals
are internally routed to the receiver input circuit. The
incoming line receiver AMI signal on LIN+/- is
ignored. With the transmitter still tied to the cable,
this test mode can indicate a short circuit on the
transmitter external components or other problem in
the transmit path.
For E3 applications, the transmitted pulse for a short
cable meets the requirements of ITU-T G.703. The
E# pin is to be pulled low.
RCLK
Low
LOCAL LOOP-BACK:
For STS-1 applications, the transmitted pulse for a
short cable meets the requirements of TelcordiaGR253-CORE. The E# pin should be allowed to float.
PIN 10
LOOP-BACK
REMOTE LOOP-BACK:
When LPBK pin is allowed to float, the 78P7200L
enters remote loopback mode. The RPOS/RNEG
and RCLK pins are internally tied to the
TPOS/TNEG and TCLK so the same AMI signal that
is received by the framer is transmitted back to the
far end where a bit continuity test can be performed.
ICKP
LINE BUILD-OUT:
The Line Build-Out function controls the amplitude in
DS3 and STS-1 mode. The selection of LBO
depends on the amount of cable the transmitter is
connected to. When used with less than 225 ft of
cable the LBO pin should be pulled high. With 225ft
or more cable the LBO pin should be low.
3
78P7200L
E3/DS3/STS-1
Transceiver
PIN DESCRIPTION: THE 28-PIN PLCC IS COMPATIBLE WITH 78P7200 AND 78P2241
NAME
PIN
TQFP
42
44
33
35
PIN
PLCC
1
3
23
25
TYPE
34
24
O
LOS
39
27
O
LOUT+
LOUTTCLK
9
11
18
9
11
16
O
TPOS/
TNRZ
16
14
I
TNEG
17
15
I
Transmit Negative Data: A logic one on this pin generates
a negative AMI pulse on the coax. This pin should not be
high at the same time that TPOS/TNRZ is high.
LBO
13
12
I
E#
15
13
I3
TXEN
22
18
I
ICKP
10
10
I3
LPBK
40
28
I3
VCC
5,6,20,
21,37,38
27, 28
7,17,26
P
Line Build-Out, Transmitter: Logic low used with 225ft or
more of cable is used on transmit path. Logic high used
with less than 225ft of cable.
DS3, E3 and STS-1 Select: Set low for E# applications.
Set high for DS3, allow to float for STS-1 operation.
Formerly OPT! on the 78P7200.
Transmitter Enable: When high, enables transmitter.
When low, tri-states transmitter drivers, LOUT±. This pin
was called OPT@ on 78P7200.
Invert Clock Polarity: When low, the polarities of RCLK and
TCLK are the same as those on the 78P7200. When set
high, the polarity of TCLK is inverted. When allowed to float,
the polarities of both RCLK and TCLK are inverted.
Loop-back Select: When high, neither loop-back is
activated.
When allowed to float RPOS, RNEG and RCLK are
looped back onto TPOS, TNEG and TCLK. When low,
LOUT± is looped back onto LIN±.
Power Supply.
LIN+
LINRCLK
RPOS/
RNRZ
RNEG
N/C
20, 21
I
O
O
I
DESCRIPTION
Line Input: Differential AMI inputs to the chip. Should be
transformer coupled and terminated at 75-ohm resistor.
Receive Clock: Recovered receive clock.
Receive Positive Data / NRZ Data: This pin indicates
reception of a positive AMI pulse on the coax cable.
Receive Negative Data: This pin indicates reception of a
negative AMI pulse on the coax.
Loss of Signal: logic low indicates that receiver signal
(LIN±) is below the threshold level
RPOS and RNEG are forced low when LOS=0.
Line Out: Differential AMI Output. Requires a 2:1 center
tapped transformer and 301Ω resistor.
Transmitter Clock Input: This signal is used to latch the
TPOS/TNRZ and TNEG signals into the 78P7200L.
Transmit Positive Data / Transmit NRZ: A logic one on this
pin generates a positive AMI pulse on the coax. This pin
should not be high at the same time that TNEG is high.
No Connect
4
78P7200L
E3/DS3/STS-1
Transceiver
PIN DESCRIPTION: THE 28-PIN PLCC IS COMPATIBLE WITH 78P7200 AND 78P2241(continued)
NAME
PIN
PLCC
2, 4, 6, 8,
22
TYPE
P
Ground. Connecting all ground pins to a common ground
plane is recommended.
RFO
PIN
TQFP
1, 3, 4, 7, 8,
12, 14, 19, 23,
24, 25, 29, 30,
31, 32, 36, 41,
43, 45, 46, 47,
48
2
5
-
LF1
26
19
-
A resistor to GND sets the operational speed of the chip.
RFO= 5.23K for DS3, RFO=6.81K for E3 and
RFO=4.53K for STS-1.
Receiver PLL filter capacitor.
GND
DESCRIPTION
Note 1: Pin type: I-input; I3-three level logic input; O-output; P-power supply. Advanced Data sheet pin
assignment and functions are subject to change.
5
78P7200L
E3/DS3/STS-1
Transceiver
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation beyond these maximums rating may permanently damage the device.
PARAMETER
RATING
Positive supply, VCC
6V
Storage temperature
-65 to 150
Ambient operating temperature
-40 to +85 °C
Output Pin Voltage (LOUT+, LOUT-)
VCC -2 to VCC +2 V
Input Pin Voltage (LIN+, LIN-)
Input pin voltage, all other pins
VCC+0.3 to GND-0.3 V
DC CHARACTERISTICS: Ta = -40°° to +85°°C; positive supply voltage = 5V ±0.5V or 3.3V±
±0.3V
PARAMETER
PIN TYPE
CONDITION
MIN
TYP
MAX
UNIT
110
mA
Supply current ICC
Transmit and receive all
ones, VCC=5V or 3.3V
70
Supply current ICC
transmitter disabled,
TXEN=0
35
VIL
I
VIH
I
2.0
IIL, IIH
I
-10
VIL3
I3
ZIM3
I3
VIH3
I3
VCC-0.5
IIL3, IIH3
I3
-100
VOL
O
IOL=-0.1mA
VOH
O
IOL=+0.1mA
mA
0.8
Input Floating
8
VCC-0.5
6
V
V
10
+10
uA
0.5
V
20
kΩ
V
+100
uA
0.5
V
V
78P7200L
E3/DS3/STS-1
Transceiver
E3 – receiver (RFO = 6.81kΩ
Ω, E# is set low), receiver is transformer-coupled.
PARAMETER
CONDITION
MIN
Peak Differential Input
Amplitude, LIN+, LIN-
See Note 2
104
Bit Error Ratio in the
presence of an Interfering
Signal at Receive Input
Interfering signal power 20dB below
E3 signal power. Both are PRBS23
23
(2 -1) patterns.
RCLK rise/fall time TRCT
TYP
MAX
UNIT
1200
mVpk
4
ns
-9
10
2
RCLK period, TRCF
29.10
RCLK clock duty cycle
45
RCLK pulse width TRC
55
14.55
RPOS/RNEG data setup
time TRDPS
CL=15 pF
7
RPOS/RNEG data hold
time TRDPH
CL=15 pF
7
Note 2: 104 mVpk equals 950 mVpk at the source with 1100 feet of cable (13.2dB loss).
7
ns
%
ns
ns
78P7200L
E3/DS3/STS-1
Transceiver
DS3/STS-1 RECEIVER (RFO = 5.23KΩ
Ω FOR DS3 AND 4.53KΩ
Ω FOR STS-1, E# PIN IS SET HIGH OR
ALLOWED TO FLOAT), INPUT IS TRANSFORMER COUPLED
PARAMETER
CONDITION
Peak Differential Input
Amplitude, LIN+ and LIN(see Note 3)
Peak Differential Input
Amplitude, LIN+ and LIN-
Signal at DSX is 360-850mVP (see
Note 4)
DS3 HIGH (see Note 5)
Bit Error Ratio in the presence
of an Interfering Signal (IS) at
LIN+,LIN-
IS is a sinusoidal tone, 22.368 MHz
for DS3 or 25.92MHz for STS-1. Data
15
is a PRBS15 (2 -1) pattern. IS power
is 10dB below data signal power.
Cl=25pf
DS3
STS-1
DS3
STS-1
CL=15 pF
7
ns
CL=15 pF
7
ns
RCLK rise/fall time TRCT
RCLK period
TRCF
RCLK pulse width
TRC
RPOS/RNEG data setup time
TRDPS
RPOS/RNEG data hold time
TRPDH
MIN
TYP
MAX
UNIT
90
850
mVP
90
1200
mVP
10-9
5
22.35
19.29
12.24
9.65
ns
ns
ns
Note 3: Signal source should meet DS3 template of ANSI-T102.1993 Figure 4 and STS-1 template of ANSIT102.1993 Figure 5, Loss characteristics of the WE728A or RG 59B cable should be better than Figure C2 of
ANSI-T102.1993.
Note 4: Receiver can handle up to 450 feet of cable loss (5.5dB) from the DSX cross-connect.
Note 5: Case where test signal is fed directly into receiver with fast rise times violates DS3 template and normal
maximum. Interfering signal performance is not guaranteed in the presence of DS3 High at the input..
8
78P7200L
E3/DS3/STS-1
Transceiver
TIMING DIAGRAM: RECEIVE WAVEFORMS (E3/DS3/STS-1)
RECEIVE LINE
INPUT (REF)
LIN+/LINTRCF
TRC
TRCT
TRCT
RCLK
ICKP=LOW or HIGH
RCLK
ICKP=FLOAT
TRDPS
TRDPH
RPOS
TRDNS
TRDNH
TRDN
RNEG
9
78P7200L
E3/DS3/STS-1
Transceiver
RECEIVER JITTER TOLERANCE
E3 and DS3 jitter tolerance specifications are in ITU-T G.823 and G.824. The test condition can be found in ITU-T
O.171. The E3 specification is the tighter of the two for frequencies greater than 20 kHz. Receive jitter tolerance is
not tested during production test.
100
10
E3
1
DS3
0.1
0.01
1.E-05
1.E-03
1.E-01
1.E+01 1.E+03 1.E+05 1.E+07
PARAMETER
CONDITION
MIN
Receiver Jitter Tolerance
12µHz to 2.78 Hz
18
10Hz to 600Hz
5
20 kHz to 800 kHz
0.15
10
NOM
MAX
UNIT
UI
78P7200L
E3/DS3/STS-1
Transceiver
RECEIVER JITTER TRANSFER FUNCTION
The receiver clock recovery loop filter characteristics are such that the receiver has the following transfer function.
The corner frequency of the PLL is approximately 50 kHz. Receiver jitter transfer function is not tested during
production test.
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
1.E+01
1.E+02
1.E+03
PARAMETER
CONDITION
Receiver Jitter transfer function
below 59.6 kHz
1.E+04
MIN
Jitter transfer function roll-off
1.E+05
NOM
20
11
1.E+06
MAX
UNIT
0.1
dB
dB per decade
78P7200L
E3/DS3/STS-1
Transceiver
E3 – TRANSMITTER (RFO = 6.81KΩ
Ω, E# = LOW)
PARAMETER
CONDITION (SEE TIMING DIAGRAM)
MIN
TYP
MAX
UNIT
Transmitter amplitude
LOUT+ and LOUT-
900
1000
1100
mVP
Transmitter Amplitude Mismatch
Ratio of amplitudes of positive
and negative pulses measured at
pulse centers
0.95
1.05
Transmitter width mismatch
TTPL/TTHL
Ratio of widths of positive and
negative pulses measured at
pulse half amplitude
0.95
1.05
Transmitter Pulse width TTPL,
TTPN
LOUT+ and LOUT-
Transmitter clock duty cycle,
TTC/TTCF
Transmitter clock period
14.55
40
ns
60
%
TTCF
29.10
ns
Transmitter clock pulse width , TTC
14.55
ns
Transmitter clock transition time,
Rising and falling CPTT/CNTT
0.8
Data setup time
TTDRS
2.5
ns
Data hold time
TTDHS
2.5
ns
12
3
5
ns
78P7200L
E3/DS3/STS-1
Transceiver
DS3/STS-1 TRANSMITTER (E#
E# = High)
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Transmitter Amplitude
LOUT+ and LOUT-
650
800
850
mVP
Transmitter Amplitude Mismatch
Ratio of amplitudes of positive
and negative pulses measured at
pulse peaks.
0.9
1.1
Transmitter power
DS3 only - All ones, 3kHz
bandwidth
-1.8
+5.7
dBm
DS3 only - All ones, 3kHz
bandwidth
-21.8
-14.3
dBm
40
60
%
At 22.368 MHz
Transmitter power
At 44.736 MHz
Transmitter clock duty cycle,
TTC/TTCF
Transmitter clock period
TTCF
DS3
22.35
ns
STS-1
19.29
ns
Transmitter clock period
TTCF
Data setup time
TTPDS
2.5
ns
Data hold time
TTPDH
2.5
ns
Transmitter clock transition time,
Rising and falling TTCPT,TTCNT
0.8
13
2
4
ns
78P7200L
E3/DS3/STS-1
Transceiver
TIMINGING DIAGRAM: TRANSMITTER WAVEFORMS (E3/DS3/STS-1)
TTCF
TCLK
ICKP=HIGH or
FLOAT
TTC
TTCPT
TTCNT
TCLK
ICKP=LOW
TTPDH
TTPDS
TPOS
TTNDS
TTNDH
TTPL
VP
0.5 VP
0.5 VN
VN
TTNL
14
78P7200L
E3/DS3/STS-1
Transceiver
E3 TRANSMIT TEMPLATE
17 ns
0.2
0.1
1.0
8.65 ns
0.1
0.2
14.55 ns
0.5
12.1 ns
24.5 ns
0.1
0.1
0
0.1
0.1
0.2
29.1 ns
15
78P7200L
E3/DS3/STS-1
Transceiver
DS3 TRANSMIT PULSE TEMPLATE
1.2
1
Normalized Amplitude
0.8
0.6
0.4
0.2
0
-0.2
-1
-0.5
0
0.5
1
Time, Unit Intervals
TIME AXIS RANGE (UI)
NORMALIZED AMPLITUDE EQUATION
UPPER CURVE
-0.85 < T < -0.68
0.03
-0.68 < T < 0.36
0.03 + 0.5{1+sin[(pi/2)(1+T/0.34)]}
0.36 < T < 1.4
0.08+0.407 e-1.84(T-0.36)
LOWER CURVE
-0.85 < T < -0.36
-0.03
-.0.36 < T < 0.36
-0.03 + 0.5{1+sin[(pi/2)(1 + T/0.18)]}
0.36 < T < 1.4
-0.03
16
1.5
78P7200L
E3/DS3/STS-1
Transceiver
STS-1 TRANSMIT PULSE TEMPLATE
1.2
1
Normalized Amplitude
0.8
0.6
0.4
0.2
0
-0.2
-1
-0.5
0
0.5
1
Time, Unit Intervals
STS-1 (Transmit template specs)
TIME AXIS RANGE (T)
NORMALIZED AMPLITUDE EQUATION (A)
UPPER CURVE
-0.85 < T < -0.68
0.03
-0.68 < T < 0.26
0.03 + 0.5{1+sin[(pi/2)(1+T/0.34)]}
0.26 < T < 1.4
0.1+0.61 e-2.4(T-0.26)
LOWER CURVE
-0.85 < T < -0.38
-0.03
-0.38 < T < 0.36
-0.03 + 0.5{1+sin[(pi/2)(1 + T/0.18)]}
0.36 < T < 1.4
-0.03
17
1.5
78P7200L
E3/DS3/STS-1
Transceiver
TRANSMITTER OUTPUT JITTER
The transmit jitter specification ensures compliance with ITU-T G.823 and G.824, and ANSI T1.102-1993 for all
supported rates. Transmit output jitter is not tested during production test.
Jitter
Detector
Measured Jitter
Amplitude
20dB/decade
Transmitter
Output
10Hz
PARAMETER
CONDITION
Transmitter Output Jitter
10 Hz to 800 kHz
800kHz
MIN
18
NOM
MAX
UNIT
0.1
UI
78P7200L
E3/DS3/STS-1
Transceiver
E3/DS3/STS-1 EXAMPLE CIRCUIT
Note 6: Pin names in ( ) denote pin names from 78P7200. Pin numbers refer to 28 PLCC package. Default
settings used to simulate 78P7200.
Note 7: Resistors on TCLK, TNEG, TPOS are optional but recommended. Clock pulse shapes at the inputs to the
78P7200L are dependent on board layout and will dictate the need for such added resistors.
Note 8. Adding a series Ferrite Bead on VCC pins may be required for some pc board layout.
EXTERNAL COMPONENTS (COMMON TO E3/DS3/STS-1)
COMPONENT
Receiver Termination Resistor
Receiver Transformer Turns Ratio
Transmitter Termination Resistor
Transmitter Transformer Turns Ratio
TOLERANCE
VALUE
UNIT
RTR
1%
75
Ω
TR
3%
1:1
---
RTT
1%
301
Ω
TT
3%
1:2ct
---
EXTERNAL COMPONENTS (DEPENDANT ON SPEED, NOMINAL VALUE)
COMPONENT
TOLERANCE
STS-1
DS3
E3
UNIT
Loop Filter Capacitor
CLF
10%
0.047
0.047
0.047
µF
Bias Resistor
RFO
1%
4.53
5.23
6.81
kΩ
Note 9: Advanced Data sheet pin assignment, functions and external component values are subject to change.
19
78P7200L
E3/DS3/STS-1
Transceiver
78P7200L REPLACEMENT FOR EXISTING 78P7200 DESIGNS
COMPONENT VARIATION FOR EXISTING 78P7200 DESIGNS
INPUT FILTER
COMPONENT
78P7200
78P7200L
R1,R2
SHORT (0Ω)
NOT INSTALLED
NOT INSTALLED
NOT INSTALLED
NOT INSTALLED
NOT INSTALLED
1:1
75Ω
CPD
75Ω
82p
6.8u
0.47u
1000p
0.01
1:2
422Ω
0.22u
RLF2
100kΩ
RLF1
CLF1
RTT
6.04kΩ
0.22u
DS3
CTT
E3
DS3
LVCC
E3
4.7uH
C2
L2
L1
C1
C3
T1
RTR
PLL FILTER
TRANSMITTER
POWER SUPPLY
20
SHORT (0Ω)
NOT INSTALLED
NOT INSTALLED
0.047u
301Ω
301Ω
604Ω
5-15pF
3pF
301Ω
NOT INSTALLED
NOT INSTALLED
SHORT (0Ω) or Ferrite
Bead
78P7200L
E3/DS3/STS-1
Transceiver
PACKAGE PIN DESIGNATIONS
(Top View)
GND
LIN+
LPBK
3
2
1
28 27 26
VCC
LIN-
4
LOS
GND
CAUTION: Use handling procedures necessary for
a static sensitive component.
RFO
5
25
RPOS
GND
6
24
RNEG
VCC
7
23
RCLK
GND
8
22
GND
LOUT+
9
21
N/ C
ICKP
10
20
N/ C
LOUT-
11
19
LF1
TXEN
VCC
TCLK
TNEG
RNAZ
E#
LBO
12 13 14 15 16 17 18
28-Pin PLCC
(Not drop-in compatible to 78P7200)
21
78P7200L
E3/DS3/STS-1
Transceiver
PACKAGE PIN DESIGNATIONS
(Top View)
LIN+
GND
LPBK
42
41
40
VCC
GND
43
37
LIN44
LOS
GND
45
VCC
GND
46
38
GND
47
39
GND
48
CAUTION: Use handling procedures necessary for
a static sensitive component.
GND
1
36
GND
RFO
2
35
RPOS
GND
3
34
RNEG
GND
4
33
RCLK
VCC
5
32
GND
VCC
6
31
GND
GND
7
30
GND
GND
8
29
GND
LOUT+
20
21
22
23
24
TXEN
GND
GND
GND
VCC
19
VCC
18
TCLK
17
TNEG
GND
16
LF1
25
TPOS
26
12
15
11
GND
14
LOUT-
E#
N/C
GND
N/C
27
13
28
10
LBO
9
ICKP
48-PIN TQFP
(Not drop-in compatible to 78P7200)
22
78P7200L
E3/DS3/STS-1
Transceiver
MECHANICAL DRAWING
28-Pin PLCC
0.495 (12.573)
0.075 (1.905)
0.485 (12.319)
PIN NO. 1 IDENT.
0.065 (1.651)
0.165 (4.191)
0.180 (4.572)
0.495 (12.573)
0.456 (11.650)
0.485 (12.319)
0.450 (11.430)
0.050 (1.270)
0.045 (1.140)
0.016 (0.406)
0.020 (0.508)
0.390 (9.906)
0.430 (10.922)
0.456 (11.650)
0.450 (11.430)
23
0.020 (0.508)
78P7200L
E3/DS3/STS-1
Transceiver
MECHANICAL DRAWING
48-Pin TQFP
8.7 (0.343)
9.3 (0.366)
8.7 (0.343)
9.3 (0.366)
INDEX
1
6.8 (0.267)
7.2 (0.283)
1.40 (0.055)
1.60 (0.063)
0.0 (0)
0.20 (0.008)
0.2 (0.008) Typ.
0.60 (0.024) Typ.
0.50 (0.0197) Typ.
ORDERING INFORMATION
PART DESCRIPTION
ORDER NUMBER
PACKAGE MARK
28-pin PLCC
78P7200L-IH
78P7200L-IH
48-pin TQFP
78P7200L-IGT
78P7200L-IGT
Advanced Information: Indicates a product is either in prototype testing or undergoing design evaluation prior to full production release.
Specifications are based on design goals or preliminary evaluation and are not guaranteed. Small quantities are usually available and TDK
Semiconductor Corporation should be consulted for current information.
No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks
or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK
Semiconductor Corporation, and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the
reader is cautioned to verify that the data sheet is current before placing orders.
TDK Semiconductor Corp., 2642 Michelle Dr., Tustin, CA 92780, (714) 508-8800, FAX (714) 508-8877 www.tdksemiconductor.com
03/06/01 - rev. C
2001 TDK Semiconductor Corporation
24