Features • • • • • • • • • • 850–930 MHz Output Frequency Rx Current: 14.5 mA Low Sleep Mode Current: 1 uA DSSS Processing and BPSK Modulation/Demodulation Battery Voltage Monitoring Circuitry 4 mW (6 dBm) Min. Transmit Power @ Vdd = 1.8V Serial Peripheral Interface (SPI) Control Power Supply Voltage Operating Range: 1.8V to 3.6V Low External Component Count 48QFN Package AT86RF210 Z-Link™ Transceiver Applications • • • • • • Low Band IEEE 802.15.4/ZigBee™-based Systems Industrial, Commercial, Home Lighting Control, Security, and HVAC Inventory Management Health Monitoring Wireless PC Peripherals such as Mouse, Keyboard, and Joystick Consumer Electronics Remote Controls and Toys Description The Atmel AT86RF210 Z-Link ™ Transceiver is a fully integated, low-cost ZigBee™ transceiver capable of transmitting and receiving BPSK modulated digital data over a frequency range of 868 MHz and 902–928 MHz using a minimum number of external components. It combines excellent RF performance with low cost, small size and low current consumption. The AT86RF210 includes a crystal stabilized Fractional-N synthesizer, BPSK transmitter and receiver, and full Direct Sequence Spread Spectrum Signal (DSSS) processing, including spreading and despreading. The device is fully compatable with IEEE 802.15.4 and ZigBee standards. It includes internal voltage regulation and battery monitoring circuitry and requires a minimum number of external support components. 868/902–928 MHz Direct Sequence Spread Spectrum BPSK Transceiver Preliminary Figure 1. Block Diagram Low Noise I/Q Mixer Amp X Rx In IF Amp Polyphase Filter Demodulator Sw Out Ant In T/R Switch Synthesizer Despreader Data Out Sw In Tx Out Modulator Spreader Power Amp SPI Bus SDO SDI SCLK SEL Data In 5033AS–WIRE–10/03 Figure 1. Functional Block Diagram LNAOUT GND VDDA VDDD VSSA Reg Filter VSSD RSSI TEST RXD Lim/PPF DC DIST Despreader CCA IQ-Limiter Strip 1.2 MHz SUB LNA LNAIN Image Reject Filter P P F M U X 1 LNAVSS 1.200 MHz P P F M U X 2 BPSK Demod START bandwidth Control RSWOUT VSS /2 with Buffers TR SW ANT PPF AUTOCAL Circuit VDD DBLR TXD Low Voltage Detect NC POR VSS DC DIST/BG/PTAT with main BandGAP FSK TUNE LOGIC TSWIN VSS PA PA OUT /N-M Fine Atten VSS PA Regulator SDMOD VCO Fcx2 BPSKO OK MOD Tune Word FROM TXD Cap Array Charge Pump Spreader PAREG VCOREG VCO NC NC VCO VCO CPVCO CPOUT VSS TUNE CHP_RDY S T A T U S PRGM DIV Coarse Lock/Lock Detect Phase Detector XTALGND Mode Logic RESET_ RX TX CLK Clock Distribution SEL Serial Configruation Register Xstal Osc XTAL1 XTAL2 SCL SDO SDI Table 1. Absolute Maximum Ratings* Storage Temperature ..............................................−65 to +150 Maximum Input Voltage...........................................VDD + 0.5V Maximum Operating Voltage (VDD ) ................................... 4,5 *NOTE: Stresses beyond those listed in this table may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Operating Conditions Symbol Parameter Min TAMB Operating temperature −40 VSUPPLY Voltage supply range 1.8 HUMIDITY Humidity 10 Note: 2 Typ 2.7 Max Unit 85 °C 3.6 V 90 % Unit operation is guaranteed by design when operating within these ranges. AT86RF210 5033AS–WIRE–10/03 AT86RF210 Table 3. DC Characteristics Symbol Parameter IDDRX Supply current, receive mode IDDTX Min Typ Max Unit 14.5 mA Supply current, transmit mode VDD = 3.3V 60 mA IDDSleep Supply current, sleep mode 1 uA VPOR Power-on reset voltage 1.5 V VIH Digital input voltage high VIL Digital input voltage low VOH Digital output voltage high VOL Digital output voltage low 0.7*VDD V 0.3*VDD 0.7*VDD V V 0.3*VDD V Max Unit 930 MHz Table 4. Receiver AC Characteristics Symbol Parameter Min Typ FLO Local oscillator operating range, external inductor 850 ZRF Port impedance antenna input 50 Ohm Rx Sens Sensitivity, PER = 1% 40 kB/s, BW = 600 kHz BPSK modulation −95 dBm Rx NF Receiver noise figure 6.0 dB Rx P1dB Receiver input 1dB compression point LNA gain max setting −40 dBm Rx IP3 Input IP3 −30 dBm Rx LO Leakage Receiver LO leakage (all possible paths) −80 dBm Pin Maximum input signal; LNA gain min setting EDthresh Default energy detection threshold (programmable) Ttx/rx Turnaround time, transmit to receive 100 usec Trx/tx Turnaround time, receive to transmit 100 usec RJAMadj Receiver relative jamming resistance adjacent channel (desired signal = −89 dBm) 0 dB RJAMalt Receiver relative jamming resistance alternate channel (desired signal = −89 dBm) 30 dB IFCF IF center frequency 1.2 MHz IFBW IF bandwidth 600 KHz Imreg IF image rejection −35 dB RX IFS/N RX IF SNR (600 KHz BW) Min input signal = −100 dBm 10 dB Rx DR Receiver max data rate 40 Kb/s RSSI GN RSSI Gain 1.0 uA/dB RSSI RG RSSI RANGE −20 −84 −105 dBm dBm −30 dBm 3 5033AS–WIRE–10/03 Table 5. Transmitter AC Characteristics Symbol Parameter Tx Pout Transmitter output power: Vdd = 1.8V Vdd = 3.6V Min Typ Max Unit dBm 6 12 Rsym Tx symbol rate 915 MHz band 40 Kbit/s Rsym Tx symbol rate 868 MHz band 20 Kbit/s EVM Transmit error vector magnitude measured over 1000 chips 35% PSD Transmit power spectral density 915 MHz band; |f–fc| >1.2 MHz (absolute measured in 100 KHz resolution BW) −20 Tx Pvar Transmitter power variation over temperature 3 dB Tx/Rx Z Antenna switch impedance 50 Ohm Tx spur Transmit spurious within ±2 MHz −25 dBc Tx spur Transmit spurious beyond ±2 MHz −35 dBc Tx Pcon Transmitter power control resolution Tx Pran Transmitter power control range Tx lvt Transmitter low-voltage threshold 1.8 1.9 Volt Tx lvpo Transmitter low-voltage output power 0.25 0.50 mwatt Tx tot Transmitter turn-on time 90% full power 10 usec Tx tofft Transmitter turn-off time less than 10% of output power 10 usec 0.25 0.75 25 dBm dB dB Table 6. Synthesizer AC Characteristics Symbol Parameter Min F LO Carrier frequency 850 LOPN LO phase noise (integrated 10 Hz–100 KHz rms) Fpull Typ Max Unit 930 MHz 6 deg Crystal oscillator frequency pulling @ 25°C 20 ppm Lopno Local oscillator phase noise 2.0 MHz offset from LO −95 dBc TXtal Crystal oscillator settling time 150 usec TSynth Phase locked loop settling time Synthres Synthesizer tuning resolution 100 500 usec Hz . Table 7. Serial Configuration Register* Symbol Parameter TRISE CMOS input rise time 20 nsec TFALL CMOS input fall time 20 nsec TCLKS CLK setup time 4 Min 25 Typ Max Unit nsec AT86RF210 5033AS–WIRE–10/03 AT86RF210 Table 7. Serial Configuration Register* (Continued) Symbol Parameter TCLKH CLK hold time 25 nsec TCLKW CLK pulse width 50 nsec TSDIS SDI setup time 25 nsec TSDIH SDI hold time 25 nsec TSDOD Note: Min Typ SDO delay time Max Unit 25 nsec *Rise and fall time is measured 10%–90%. Delay, setup, and hold times are measured 50%–50% Table 8. Low Battery Detector Characteristics Symbol Parameter Min Lvbat 0 Low voltage battery detector threshold voltage mode 0 (5 bit resolution) 1.5 Typ Max Unit 3.5 Volt Table 9. Preliminary PIN Description QFN48 PIN Num Type Startup Cond SUB 1 V_I/O GND LNARFIN 2 RF_I NA Low-noise amplifier RF input LNAVSS 3 RF_I/O NA Analog ground for the LNA RSWOUT 4 RF_I/O NA Transmit-receive switch out. Signal from ANT is routed through the TR switch to the LNA input. VSS 5 RF_I/O NA Transmit-receive switch isolation ground 1. ANT 6 RF_I/O NA Antenna RF input/output. Nominal impedance 50Ω, part of T/R switch. Routes signal to the LNA or from the PA. VSS 7 RF_I/O NA Transmit-receive switch isolation ground 2. TSWIN 8 RF_I/O NA Transmit-receive switch input. Signal from PA comes into TR switch and is routed to ANT. PAOUT 9 RF_I/O NA PA signal routed into the T/R switch from the PA. VSS 10 VDDA 11 V_I NA Secondary analog power supply input. Set in proximity to power amplifier circuits. PAREG 12 A_O NA PA regulator output. Settable current source output for charging a large external capacitor during battery operation. VCOVDD 13 V_I NA VCO power supply input VCOREG 14 V_I NA External filter cap for the VCO regulator No Connect 15 NA Pin not used No Connect 16 NA Pin not used VCOVSS 17 A_I/O NA VCO power supply ground VCOTUNE 18 A_I NA LO VCO control input. An internal differential varactor diode tunes the LO frequency. The control voltage should be referenced to LOGND. Description Substrate connection Pin not used 5 5033AS–WIRE–10/03 Table 9. Preliminary PIN Description QFN48 (Continued) Num Type Startup Cond CPOUT 19 A_I NA Charge pump output CPVSS 20 A_I/O NA Analog synthesizer ground CPVDD 21 V_I NA Analog synthesizer power supply XTAL1 22 A_I NA Crystal oscillator input 1. One side of oscillator crystal is connected to this pin. XTAL2 23 A_I NA Crystal oscillator input 2. When internal oscillator is used, this pin has crystal connected. When external clock is used, the external clock is input on this pin. XTALVSS 24 A_I/O NA Crystal oscillator ground TXDAT 25 D_I HIGH Transmit data input from the controller No Connect 26 D_I LOW Pin not used SDI 27 D_I NA Serial data input Input to configuration data shift register. Data accepted at the rising edge of SCL. SDO 28 D_O NA Output from configuration data shift register. Data changes at the falling edge of SCL. SCLK 29 D_I NA Serial data clock SEL 30 D_I HIGH SPI slave select line SYSCLK 31 D_O HIGH Clock output to controller. Can be divided by 1 to 16. TX 32 D_I HIGH Mode control input. TX HIGH with RX LOW causes chip to go to transmit. RX 33 D_I HIGH Mode control input. RX HIGH with TX LOW causes chip to go to receive mode. VDDDIG 34 V_I NA Digital power supply input VSSDIG 35 V_I/O NA Digital power supply ground. START 36 D_I HIGH Oscillator start. A transition on this pin will start the internal oscillator. A low on this pin allows the part to run from an external clock. CHPRDY 37 D_O LOW Chip ready. Handshake signal between the controller and the chip. Also acts as fault interrupt. RXDOUT 38 D_O NA Digital data from demodulator No Connect 39 NA Pin not used No Connect 40 NA Pin not used No Connect 41 PPFREG 42 V_I/O RSSI 43 A_0 XTALMODE 44 D_IO TBD Test pin. Enables nand tree test or scan test. CCA 45 D_O LOW Clear channel assessment. Digital signal indicates when channel activity is above a programmable threshold. PIN 6 Description Pin not used VDD Filter cap for internal low dropout regulator for poly phase filter Logarithmic detection current AT86RF210 5033AS–WIRE–10/03 AT86RF210 Table 9. Preliminary PIN Description QFN48 (Continued) Num Type Startup Cond VDDA 46 V_I NA VSSA 47 V_I/O GND LNAOUT 48 A_I/O PIN I/O Table Notes Description Analog (RF) power supply input Analog (RF) power supply ground LNA external inductor. Collector inductor for LNA. P/O RF tuning network. • RF_I RF input • RF_I/O RF input/output • Voltage_I/O Voltage input/output • V_I Voltage input • A_I Analog input • A_O Analog output • D_I Digital input • D_O Digital output 7 5033AS–WIRE–10/03 Figure 2. Typical ZigBee Application Schematic This is a sample application schematic for RF210 (The pinout and component values are preliminary) V_BAT Receiver Tuning C10 TBD L0 TBD C14 100p C13 10n 37 CHPRDY 38 RXDOUT 39 No Connect 40 No Connect 43 RSSI VDD CCA_IN (DIGITAL INTERFACE) 2 LNARFIN 3 LNAVSS PA Matching 7 VSS C19 TBD L2 TBD C22 TBD L6 TBD 8 TSWIN AT86RF210 Z-Link Transceiver 9 PAOUT X RX_DATA CHP_RDY 32 TX 31 SYSCLK x RX TX 30 SELl 10 VSS 29 SCLK SPI_SEL 28 SDO SPI_CLK 27 SDI 11 VDDA (FREQUENCY GENERATION INTERFACES) 26 No connect 12 PAREG 24 XTALVSS 22 XTAL1 23 XTAL2 20 CPVSS 21 CPVDD 18 VCOTUNE 19 CPOUT 17 VCOVSS 16 No connect 15 No connect 13 VCOVDD C20 250u SPI_OUT x SPI_IN TX_DAT_P 25 TXDAT 14 VCOREG C21 100p START 33 RX (DIGITAL INTERFACE) 6 ANT RSSI_ANALOG X 34 VDDDIG (RF INTERFACE) 5 VSS C0 10n 35 VSSDIG 4 RSWOUT C18 100P C1 100p 36 START Z-Link ZigBee Controller L1 TBD C17 TBD C15 TBD 42 PPFREG 45 CCA 47 VSSA 1 SUB 44 XTALMODE Receiver Matching 46 VDDA 48 LNAOUT C23 10n 41 No Connect X X R0 TBD X SYS_CLK_OUT VSS C9 100p C8 10n X X Optional C7 TBD C6 TBD R2 TBD C5 TBD Loop Filter C4 TBD R1 TBD C2 100p C3 10n Atmel RF Design Cent. Note: With pin 44 (Xstal_Sel) low RF210 uses system clock from controller With pin 44 (Xstal_Sel) high RF210 uses external crystal placed across pin 22 & 23 8 9/9/03 AT86RF210 5033AS–WIRE–10/03 AT86RF210 Package Drawing 48QFN D A3 A Index Area E A2 Top View A1 Side View L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL D2 E2 b e E 7.00 BSC MAX D2 2.25 4.70 5.25 E2 2.25 4.70 5.25 A 0.80 0.90 1.00 A1 0.0 0.02 0.05 A2 0.0 0.65 1.00 L Bottom View NOM 7.00 BSC A3 Pin 1 NOTE 0.20 REF 0.30 e b Notes: MIN D 0.40 0.50 0.50 BSC 0.18 0.23 0.30 2 1. This drawing is for general information only. Refer to JEDEC Drawing MO-220, Variation VKKD-2, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 12/10/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 48QN1, 48-lead 7.0 x 7.0 mm Body, 0.50 mm Pitch, Quad Flat No Lead Package (QFN) DRAWING NO. 48QN1 REV. A 9 5033AS–WIRE–10/03 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Literature Requests www.atmel.com/literature Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not auth orized for use as critical components in life support devices or systems. © Atmel Corporation 2003. All rights reserved. Atmel® and combinations thereof are registered trademarks and Z-Link ™ is a trademark of Atmel Corporation or its subsidiaries. ZigBee ™ is a trademark of the ZigBee Alliance. Other terms and product names may be the trademarks of others. Printed on recycled paper. 5033AS–WIRE–10/03