XR-T56L85 ...the analog plus Low Power PCM Line Interface company TM June 1997-3 FEATURES10 APPLICATIONS Low Power (Typical 14mA) Single +5V Supply Up to 2.048 Mbps Operation in Both TX and RX Directions Receiver Input can be: – Balanced Transformer Coupled – Capacitively (Twisted Pair) – Single Coaxial Capacitive Coupling T1 and CEPT Interfaces CPI DMI GENERAL DESCRIPTION The XR-T56L85 is a PCM line interface chip. It consists of both transmit and receive circuitry in a DIL 18 pin package. The maximum bit rate the chip can handle is 2.048 Mbps and the signal level to the received can be attenuated by 10dB of cable loss at half the bit rate. Total current consumption is between 12-16mA at +5V. ORDERING INFORMATION Package Operating Temperature Range XR-T56L85N 18 Lead 300 Mil CDIP -40°C to +85°C XR-T56L85D 18 Lead 300 Mil JEDEC SOIC -40°C to +85°C Part No. BLOCK DIAGRAM PDC 1 Positive Threshold Comparator + – TTL Buffer 11 RPOS RXDATA+ 2 RXDATA- 3 RXVCC 9 Peak Detector TTL Buffer Negative Threshold Comparator – + TTL Buffer 8 RCLK 4 TE 10 RNEG Bias 6 TANK BIAS Bias 5 BIAS RXGND 7 TXVCC 18 TTL Buffer TPOS 17 15 TXDATA+ TCLK 16 TTL Buffer 13 TXDATA- TNEG 12 TXGND 14 Figure 1. Block Diagram Rev. 2.01 1992 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 1 XR-T56L85 PIN CONFIGURATION PDC RXDATA+ RXDATATE BIAS TANK BIAS RXGND RCLK RXVCC 1 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 TXVCC TPOS TCLK TXDATA+ TXGND TXDATATNEG RPOS RNEG PDC RXDATA+ RXDATATE BIAS TANK BIAS RXGND RCLK RXVCC 18 Lead CDIP (0.300”) 1 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 TXVCC TPOS TCLK TXDATA+ TXGND TXDATATNEG RPOS RNEG 18 Lead SOIC (Jedec, 0.300”) PIN DESCRIPTION Pin # Symbol Type Description 1 PDC 2 RXDATA+ I Receive Analog Input Positive. The AMI signal received from the line is applied at this and the RX DATA(-) pin. Data and clock from the signal applied at these two pins recovered and output on the RPOS, RNEG, and RCLK pins, respectively. 3 RXDATA- I Receive Analog Input Negative. See the description for RX DATA(+). 4 TE O LC Tank Excitation Output. This output connects to one side of the tank circuitry. 5 BIAS O Bias. This pin should be tied to ground through a 0.1µF capacitor. 6 TANK BIAS 7 RXGND 8 RCLK 9 RXVCC 10 RNEG O Receive Negative Data Output. A signal at this pin corresponds to the receipt of a negative pulse on the RX DATA(+)/RX DATA(-) pins. This TTL compatible signal is output to the terminal equipment. 11 RPOS O Receive Positive Data Output. A signal at this pin corresponds to the receipt of a positive pulse on the RX DATA(+)/RX DATA pins. This TTL compatible signal is outputed to the terminal equipment. 12 TNEG I Transmit Negative Data Input. TTL input for a negative polarity pulse (the negative portion of the AMI pulse train) to be transmitted to the line via the TX DATA(+) and TX DATA pins. 13 TXDATA- O Transmit Negative Data Output. This pin, along with the TX DATA(+) pin, forms a differential driver output, this is used to drive AMI data down the line via a transformer. Note: This is an open-collector output. 14 TXGND 15 TXDATA+ O Transmit Positive Data Output. Please see description for TX DATA(-). 16 TCLK I Transmit Clock. TPOS and TNEG are sampled on the rising edge of TCLK. 17 TPOS I 18 TXVcc Transmit Positive Data Input. TTL input for a positive polarity pulse (the positive portion of the AMI pulse train) to be transmitted to the line via the TX DATA(+) and TX DATA(-) pins. Transmit Supply Voltage. 5V supply voltage to the transmit section. Peak Detector Capacitor. This pin should be connected to a 0.1µF capacitor Tank Reference. The tank circuitry is biased via this output. Receiver Ground. To minimize ground interference a separate pin is used to ground the receiver section. O Recovered Receive Clock. Recovered clock signal from the AMI signal received at the RX DATA(+) and RX DATA(-) pins. This signal is output to the terminal equipment. Receive Supply Voltage. 5V supply voltage for the Receive Section. Transmit Ground. Rev. 2.01 2 XR-T56L85 ELECTRICAL CHARACTERISTICS Test Conditions: VCC = 5V5%, TA = -40°C to +85°C, Unless Otherwise Specified Parameters Min. Typ. Max. Unit Conditions DC Electrical Characteristics Supply Voltage 4.75 Supply Current 5 5.25 V 14 16 mA Total Current to Pin 9 & Pin 18 (Transmitter Outputs Open and All Ones Pattern) 500 700 µA Measured at Pin 4, VCC= 5V 0.3 0.6 V Measured at Pin 8, IOL = 1.6mA V Measured at Pin 8, IOH =400µA V Measured at Pin 10 & 11, IOL =1.6mA V Measured at Pin 10 & 11, IOH =400µA 1.2 V Measured at Pin 13 & 15, IOL =-40mA 100 µA Measured in Off State Output Pull-up to +20V V Measured at Pin 12, 16 & 17 IOL = -40mA, VOL = 1.0V Receiver Section Tank Drive Current 300 Clock Output Low Clock Output High 3.0 Data Output Low Data Output High 3.6 0.3 3.0 3.6 0.6 0.9 0.6 Transmitter Section Driver Output Low Output Leakage Current Input High Voltage 2.2 Input Low Voltage 0.8 V Measured at Pin 12, 16 & 17 Output Off Input Low Current -1.6 mA Measured at Pin 12, 16 & 17 Input Low Voltage = 0.4V Input High Current 40 µA Measured at Pin 12, 16 & 17 Input Low Voltage = 0.4V Output Low Current -30 mA Measured at Pin 13 & 15 VOL= 1.0V 6.6 Vpp Measured Between Pin 2 & 3 AC Electrical Characteristices Receiver Section Input Level 6 Loss Input Signal Alarm Level 0.6 Vpp Measured Between Pin 2 & 3 Alarm on Pull Data/Clock Output High Input Impedance at 2.048MHz 2.5 kΩ Measured Between Pin 2 & 3 With Sinewave Input Clock Duty Cycle 35 50 65 % Measured at Pin 8 at 2.0V DC Level 20 40 ns Measured at Pin 8, CL = 15pF 35 50 75 % of clock period Measured at Pin 10 & 11 At 1V DC Level, Cable Loss = dB 234 244 264 ns Measured at Pin 13 & 15 Figure 3 Output Rise Time 12 25 ns Figure 3 Output Fall Time 12 25 ns Figure 3 Output Fall Imbalance 2.5 ns At 50% Output Level Clock Rise & Fall Time Data Pulse Width Transmitter Section Pulse Width at 2.048MHz Rev. 2.01 3 XR-T56L85 ABSOLUTE MAXIMUM RATINGS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20V Storage Temperature . . . . . . . . . . . . . . -65°C to 150°C SYSTEM DESCRIPTION appropriate frequency is added externally to provide the appropriate frequency-selective filtering of the received clock signal. The Receiver The incoming bipolar PCM signal, which is attenuated and distorted by the cable is applied to the receiver input, consisting of the RX DATA(+) and RX DATA(-) pins, either through a balanced transformer, a balanced capacitively coupled terminal or a single-ended coaxial cable (see Figure 5). A peak detector following the input generates a DC reference for the positive and negative threshold comparator (to extract the positive and negative data pulses). Information on the positive and negative data pulses is outputed as TTL compatible signals at pins RPOS and RNEG, respectively. More specifically, an output signal present at the RPOS pin indicates that a positive pulse was received at the RX DATA(+)/RX DATA(-) pins, from the incoming bipolar data stream. Likewise an output signal present at the RNEG pin indicates that a negative pulse was received at the RX DATA(+)/RX DATA(-) pins. This conversion from the bipolar signal to TTL compatible signals allows for digital processing of the clock and data signals by the terminal equipment. An example of the waveforms of the TTL compatible recovered clock and data as output by the receiver portion of the chip is presented in Figure 2, Figure 3 and Figure 5. A tank circuit tuned to the The Transmitter The transmitter portion of the chip receives TTL compatible signals and transmits a corresponding bipolar data stream down the line (See Figure 5). TPOS and TNEG are TTL compatible signals that dictate the polarity of the pulse to be generated and transmitted on the output bipolar data stream. Both TPOS and TNEG inputs are sampled by the rising edge of the transmit clock, TCLK. The TX DATA(+) and TX DATA(-) pins form a differential driver output, this is used to drive AMI data down the line via a transformer. The TX DATA(+) and TX DATA(-) pins are open-collector outputs. When a logic “high” signal is applied to the TPOS pin, a positive pulse (the positive portion of the bipolar data stream) will be transmitted to the line via the TX DATA(+) O/P and TX DATA(-) O/P pins. Likewise, when a logic “high” signal is applied to the TNEG pin, a negative pulse will be transmitted to the line via the TX DATA(+) and TX DATA(-) pins. An illustration of the key waveforms involved in this TTL to AMI conversion process, in the Transmitter portion of the chip is presented in Figure 4. Rev. 2.01 4 XR-T56L85 VCC=5V 100 0.1µF Output Pin 13 & 15 2.048Mbps Pulse Generator CL=15pF Pin 9 &18 Input XR-T56L85 0V Pin 12, 16, 17 Pin 7 &14 0V Figure 2. 244ns <5ns 90% Input Pulse from Generator <5ns 3V 90% 1.5V 1.5V 10% 10% 15ns Typ. 0V 15ns Typ. +5V Output from Pin 13 or Pin 15 Vol Pulse Width Fall Time Rise Time Figure 3. Rev. 2.01 5 XR-T56L85 RXDATA+ RCLK Output At Pin 8 RPOS Output At Pin 11 RNEG Output At Pin 10 TCLK Clock To Pin 16 TPOS To Pin 17 TNEG To Pin 12 Bipolar Signal At Transformer Output Figure 4. Receiver Timing Diagram With 1-1-1-1-1-1 Pattern Rev. 2.01 6 XR-T56L85 VCC RCACON 2 0.1µF 0.1µF 3 75 18 5 2 2 0.1µF 3 3 5 5 T1 TIP 1:1 0.1µF 4 L 3 BIAS TXDATA- XR-T56L85 TGND 2 3 0.1µF 56 13 56 PE65415 1:1:1 14 TANK BIAS TCLK 16 TPOS 17 VCC TNEG 0.1µF RING T2 15 5 6 TIP TXDATA+ T.E. C 4.7µF 120 RXDATA- 2 120 RING RXDATA+ VCC 0.1µF 9 RVCC 1 PDC 0.1µF 0.1µF 7 5 0.1µF RPOS RGND L=Tank Coil AIE 415–0804 (1.544 and 2.048 Mbs) 1.544Mbs 2.048Mbs L 60µH 60µH C 175pF 100pF Figure 5. Application Circuit for XR-T56L85 Rev. 2.01 7 11 10 RNEG 8 RCLK U1 56L85TA Device 12 TCLK TPOS TNEG RPOS RNEG RCLK TIP RING XR-T56L85 18 LEAD CERAMIC DUAL-IN-LINE (300 MIL CDIP) Rev. 1.00 18 10 1 9 E E1 D A1 Base Plane Seating Plane A L c e B α B1 INCHES SYMBOL MILLIMETERS MIN MAX MIN MAX A 0.100 0.200 2.54 5.08 A1 0.015 0.070 0.38 1.78 B 0.014 0.026 0.36 0.66 B1 0.045 0.065 1.14 1.65 c 0.008 0.018 0.20 0.46 D 0.860 0.960 21.84 24.38 E1 0.250 0.310 6.35 7.87 E 0.300 BSC 7.62 BSC e 0.100 BSC 2.54 BSC L 0.125 0.200 3.18 5.08 α 0° 15° 0° Note: The control dimension is the inch column 15° Rev. 2.01 8 XR-T56L85 18 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) Rev. 1.00 D 18 10 E H 1 9 C A Seating Plane B e α A1 L INCHES SYMBOL MILLIMETERS MIN MAX MIN A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 B 0.013 0.020 0.33 0.51 C 0.009 0.013 0.23 0.32 D 0.447 0.463 11.35 11.75 E 0.291 0.299 7.40 7.60 e 0.050 BSC MAX 1.27 BSC H 0.394 0.419 10.00 10.65 L 0.016 0.050 0.40 1.27 α 0° 8° 0° 8° Note: The control dimension is the millimeter column Rev. 2.01 9 XR-T56L85 Notes Rev. 2.01 10 XR-T56L85 Notes Rev. 2.01 11 XR-T56L85 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1992 EXAR Corporation Datasheet June 1997 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.01 12