TEMIC U6083B

U6083B
PWM Power Control with Interference Suppression
Description
The U6083B is a PWM IC in bipolar technology for the
control of an N-channel power MOSFET used as a high
side switch. The IC is ideal for use in the brightness control (dimming) of lamps e.g., in dashboard applications.
Features
D Pulse-width modulation up to 2 kHz clock frequency
D Protection against short circuit, load dump
over–voltage and reverse VS
D Interference and damage protection according to
VDE 0839 and ISO/TR 7637/1.
D Charge pump noise suppressed
D Duty cycle 18 to 100% continuously
D Internally reduced pulse slope of lamp’s voltage
D Ground wire breakage protection
Ordering Information
Extended Type Number
U6083B
Package
DIP8
Remarks
Block Diagram
VBatt
C5
VS
1
Rsh
5
6
Current monitoring
+ short circuit detection
C1
47 kW
C2
4
RC oscillator
PWM
7
Charge
pump
C3
47 nF
Logic
3
Control input
Duty cycle
range
18 ... 100%
8
Output
Duty cycle
reduction
GND
Voltage
monitoring
Slew rate
control
2
95 9753
150 W
R3
Ground
Figure 1. Block diagram with external circuit
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
1 (8)
U6083B
Pin Description
VS
1
8
Output
GND
2
7
2 VS
VI
3
6
Sense
Osc
4
5
Delay
Pin
1
2
3
4
5
6
7
8
Symbol
VS
GND
VI
Osc
Delay
Sense
2 VS
Output
Function
Supply voltage VS
IC ground
Control input (duty cycle)
Oscillator
Short circuit protection delay
Current sensing
Voltage doubler
Output
95 9944
Functional Description
Pin 1, Supply Voltage, Vs or VBatt
Overvoltage Detection
Stage 1:
If overvoltages VBatt > 20 V (typ.) occur, the external
transistor is switched off and switched on again at
VBatt < 18.5 V (hysteresis).
Pin 3, Control Input
The pulse width is controlled by means of an external
potentiometer (47 kW). The characteristic (angle of rotation/duty cycle) is linear. The duty cycle can be varied
from 18 to 100%. It is possible to further restrict the duty
cycle with the resistors R1 and R2 (see figure 3).
In order to reduce the power dissipation of the FET and
to increase the lifetime of the lamps, the IC automatically
reduces the maximum duty cycle at Pin 8 if the supply
voltage exceeds V2 = 13 V. Pin 3 is protected against
short-circuit to VBatt and ground (VBatt 16.5 V).
Stage 2:
If VBatt > 28.5 V (typ), the voltage limitation of the IC is
reduced from VS = 26 V to 20 V. The gate of the external
transistor remains at the potential of the IC ground, thus
producing voltage sharing between FET and lamps in the
event of overvoltage pulses occuring (e.g., load dump).
The short-circuit protection is not in operation. At VBatt
approx. < 23 V, the overvoltage detection stage 2 is
switched off. Thus during overvoltage detection stage 2
the lamp voltage Vlamp is calculated to :
VLamp = VBatt – VS – VGS
VS = Supply voltage of the IC at overvoltage detection
stage 2
VGS = Gate – source voltage of the FET
Pin 4, Oscillator
The oscillator determines the frequency of the output
voltage. This is defined by an external capacitor, C2. It is
charged with a constant current, I, until the upper
switching threshold is reached. A second current source
is then activated which taps a double current, 2 I, from
the charging current. The capacitor, C2, is thus discharged
at the current, I, until the lower switching threshold is
reached. The second source is then switched off again and
the procedure starts once more.
Example for Oscillator Frequency Calculation:
A hysteresis ensures that the FET is switched on again at
approximately VBatt 5.4 V.
Switching thresholds
VT100 = High switching threshold (100% duty cycle)
VT100 = VS a1 = (VBatt – IS R3)
a1
VT<100 = High switching threshold (< 100% duty cycle)
a2
VT<100 = VS a2 = (VBatt – IS R3)
VTL = Low switching threshold
a3
VTL = VS a3 = (VBatt – IS R3)
whereas
a1, a2 and a3 are fixed constant.
Pin 2, GND
Calculation Example
Ground-Wire Breakage
The above mentioned threshold voltages are calculated
for the following values given in the data sheet.
Undervoltage Detection
In the event of voltages of approximately VBatt < 5.0 V,
the external FET is switched off and the latch for shortcircuit detection is reset.
To protect the FET in the case of ground-wire breakage,
a 1 MW resistor between gate and source it is recommended to provide proper switch-off conditions.
2 (8)
VBatt = 12 V, IS = 4 mA, R3 = 150 W ,
a1 = 0.7, a2 = 0.67 and a3 = 0.28.
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
U6083B
150 )
VT100 = (12 V – 4 mA
VT<100 = 11.4 V
VTL = 11.4 V
0.7
[8V
0.67 = 7.6 V
dV8/dt = IOSC/(C4 + C2/4)
0.28 = 3.2 V
when
IOSC = 45 A, C4 = 1.8 nF, C2 = 68 nF and 4 = 63
then dV8/dt = 45 A/(1.8 nF + 68 nF/63) = 15.6 V/ms
Oscillator Frequency
3 cases have to be distinguished
1)
f1
f1 for duty cycle = 100%, no slope reduction with
capacitor C4 (see figure 3)
+ 2 (V * V
+ ... + 75 Hz
I osc
T100
f1
2)
)
TL
+
, whereas C 2
68 nF
45 A
I osc
+
C2
f2 for duty cycle < 100%, no slope reduction with
capacitor C4
For a duty cycle of less than 100%, the oscillator
frequency, f, is as follows:
f2
+ 2 ǒV t I * V Ǔ
osc
T 100
f2
3)
f3
TL
+ ... + 69Hz
Via an external capacitor, C4, the slope can be further
reduced as follows:
C2
, whereas C 2
I osc
+ 68 nF
+ 45 A
To damp oscillation tendencies, a resistance of 100 in
series with capacitance C4 is recommended.
Interference Suppression
“On board” radio reception according to VDE 0879 part
3/4.81
Test conditions refering to figure 2.
Application circuit according to figure 1 or 3.
Load: nine 4-W lamps in parallel.
Duty cycle
VBatt
fOsc
= 18%
= 12 V
= 100 Hz
f3 with duty cycle < 100% with slope reduction
capacitor C4 (see page 3 “Output Slope Control”)
+2
(V Tt100
+
+
+
*V
I osc
C2
TL)
) 2V
Batt
C4
whereas C 2
68 nF
1.8 nF
C4
45 A
I osc
f3
...
70 Hz
+ +
By selecting different values of C2 and C4, it is possible
to have a range of oscillator frequency, f, from 10 to
2000 Hz as shown in the data sheet.
Output Slope Control
Figure 2. Voltage spectrum of on-board radio reception
The slope of the lamp voltage is internally limited to
reduce radio interference, by limitation of the voltage
gain of the PWM comparator.
Thus the voltage rise on the lamp is proportional to the
oscillator voltage increase at the switchover time according to the equation.
dV8/dt = 4 dV4/dt =
2 4 f (2 – 3) (VBatt – IS
when
f = 75 Hz, VTX = VT < 100 and 4 = 63
we obtain
dV8/dt=2 63
= 42 V/ms
75 Hz
(0.67–0.28)
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
R3)
(12 V–4 mA 15 )
Pins 5 and 6, Short-Circuit Protection and
Current Sensing,
1. Short-Circuit Detection and Time Delay, td
The lamp current is monitored by means of an external
shunt resistor. If the lamp current exceeds the threshold
for the short-circuit detection circuit (VT2 90 mV), the
duty cycle is switched over to 100% and the capacitor C5
is charged by a current source of Ich – Idis. The external
FET is switched off after the cut-off threshold (VT5) is
reached. Renewed switching on of the FET is possible
only after a power-on reset. The current source, Idis,
ensures that the capacitor C5 is not charged by parasitic
currents.
3 (8)
U6083B
Time delay, td, is as follows:
td = C5 VT5/ (Ich – Idis)
With C5 = 100 nF and VT5 = 10.4 V, Ich =13 mA,
Idis = 3 mA, we have
td = 100 nF 10.4 V/ (13 mA – 3 mA)
occurs only when the short-circuit detection circuit has
responded.
After a power-on reset, the output is inactive for half an
oscillator cycle. During this time, the supply voltage
capacitor can be charged so that current limitation is guaranteed in the event of a short-circuit when the IC is
switched on for the first time.
td = 104 ms
Pins 7 and 8, Charge Pump and Output,
2. Current Limitation:
The lamp current is limited by a control amplifier to
protect the external power transistor. The voltage drop
across an external shunt resistor acts as the measured
variable. Current limitation takes place for a voltage drop
of VT1 100 mV. Owing to the difference
VT1–VT2 10 mV, it is ensured that current limitation
Output, Pin 8, is suitable for controlling a power
MOSFET. During the active integration phase, the supply
current of the operational amplifier is mainly supplied by
the capacitor C3 (bootstrapping). In addition, a trickle
charge is generated by an integrated oscillator
(f7 400 kHz) and a voltage doubler circuit. This
permits a gate voltage supply at a duty cycle of 100%.
Absolute Maximum Ratings
Parameters
Junction temperature
Ambient temperature range
Storage temperature range
Symbol
Tj
Tamb
Tstg
Value
150
–40 to +110
–55 to +125
Unit
°C
°C
°C
Symbol
RthJA
Value
120
Unit
K/W
Thermal Resistance
Parameters
Junction ambient
Electrical Characteristics
Tamb = –40 to +110°C, VBatt = 9 to 16.5 V, (basic function is guaranteed between 6.0 V to 9.0 V) reference point ground,
unless otherwise specified (see figure 1). All other values refer to Pin GND (Pin 2).
Parameters
Current consumption
Supply voltage
Stabilized voltage
Battery undervoltage
detection
4 (8)
Test Conditions / Pins
Pin 1
Overvoltage detection,
stage 1
IS = 10 mA
Pin 1
– on
– off
Symbol
IS
VBatt
Min.
Vs
VBatt
24.5
4.4
4.8
Typ.
5.0
5.4
Max.
7.9
25
Unit
mA
V
27.0
5.6
6.0
V
V
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
U6083B
Parameters
Test Conditions / Pins
Battery overvoltage detection
Stage 1:
– on
– off
Stage 2:
Detection stage 2
Stabilized voltage
Short-circuit protection
Short-circuit current
limitation
Short-circuit detection
Symbol
Min.
Typ.
Max.
Unit
VBatt
18.3
16.7
20.0
18.5
21.7
20.3
V
VBatt
28.5
23.0
20.0
32.5
26.5
21.5
V
Vs
25.5
19.5
18.5
VT1 = VS – V6
VT1
85
100
120
mV
VT2 = VS – V6
VT2
VT1 – VT2
75
3
90
10
105
30
mV
VT5
Ich
Idis
I5
10.2
10.6
5
10.4
13
3
10
15
mA
V7
f7
V7
400
27.5
VS+15
63
520
30.0
VS+16
72
130
kHz
V
a4
2 VS
280
26
VS+14
53
V8
0.35
0.70
0.95
1.5 *)
– on
– off
IS = 30 mA
Pin 1
Pin 6
Delay timer short circuit detection, VBatt = 12 V Pin 5
Switched off threshold
VT5 = VS – V5
Charge current
Discharge current
Capacitance current
I5 = Ich – Idis
Voltage doubler
Pin 7
Voltage
Duty cycle 100%
Oscillator frequency
Internal voltage
g limitation
I7 = 5 mA
(whichever is lower)
Edge steepness
Gate output
Voltage
g
Current
Duty cycle
Oscillator
Frequency
Threshold cycle
Upper
Lower
dv8/dt =a4 dV4/dt
dV8/dtmax
Pin 8
Low level
VBatt = 16.5 V
Tamb = 110°C, R3 = 150 W
High level,
duty cycle 100%
V8 = Low level
V8 = High level, I7 > | I8 |
Min: C2 = 68 nF
Max: VBatt 12.4 V
VBatt = 16.5 V, C2 = 68 nF
v
+ High, a +
V + Low, a +
a + VV
V8
1
8
2
Pin4
V T100
VS
V Tt100
VS
TL
3
S
Oscillator current
Frequency
*)
VBatt = 12 V
C4 open, C2 = 68 nF
duty cycle = 50%
V8
I8
tp/T
f
V/ms
V
V7
1.0
–1.0
15
100
65
mA
18
21
73
81
%
10
0.68
0.7
2000
0.72
a2
0.65
0.67
0.69
a3
0.26
0.28
0.3
34
56
45
75
54
90
f
V
mA
mA
a1
Iosc
V
Hz
mA
Hz
Reference point is battery ground.
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
5 (8)
6 (8)
95 9758
47 mF
C1
C2
4
R2
Low voltage
monitoring
VS
+
–
+
–
Reset
Reset
Switch – on
delay
Overvoltage
monitoring
stage 1
VS
2I
I
Oscillator
VS
47 k W 3
68 nF
R1
VS
R
VS
63 x R
Reset
+
–
VS
C5
GND
Idis
5
150 W
Ich
VS
100 nF
VS
R3
2
Overvoltage
monitoring
stage 2
1
+
–
Current limiting
Voltage
doubler
8
7
6
10 mV
90 mV
VS
VS
Ground
1 MW
C4
1.8 nF
47 nF
Load
RL
C3
Rsh
VBatt
U6083B
Application
Figure 3.
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
U6083B
Package Information
Package DIP8
Dimensions in mm
7.77
7.47
9.8
9.5
1.64
1.44
4.8 max
6.4 max
0.5 min
0.58
0.48
3.3
0.36 max
9.8
8.2
2.54
7.62
8
5
technical drawings
according to DIN
specifications
13021
1
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
4
7 (8)
U6083B
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances ( ODSs).
The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and
forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban
on these substances.
TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of
continuous improvements to eliminate the use of ODSs listed in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency ( EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively.
TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain
such substances.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized
application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of,
directly or indirectly, any claim of personal damage, injury or death associated with such unintended or
unauthorized use.
TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 ( 0 ) 7131 67 2831, Fax number: 49 ( 0 ) 7131 67 2423
8 (8)
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97