Features • • • • • • • Pulse-width Modulation up to 2 kHz Clock Frequency Protection Against Short-circuit, Load Dump Overvoltage and Reverse VS Duty Cycle 18 to 100% Continuously Internally Reduced Pulse Slope of Lamp's Voltage Interference and Damage Protection According to VDE 0839 and ISO/TR 7637/1 Charge-pump Noise Suppression Ground-wire Breakage Protection Description The U6083B is a PWM IC in bipolar technology for the control of an N-channel power MOSFET used as a high-side switch. The IC is ideal for use in brightness control systems (dimming) of lamps, for example, in dashboard applications. PWM Power Control IC with Interference Suppression U6083B Rev. 4770A–AUTO–11/03 Figure 1. Block Diagram with External Circuit VBatt C5 VS 1 Rsh 5 6 Current monitoring + short circuit detection C1 4 Charge pump RC oscillator C3 PWM 47 kΩ 47 nF Logic Control input C2 7 Output 3 Duty cycle range 18 to 100% Duty cycle reduction GND 150 Ω Voltage monitoring 8 Slew rate control 2 R3 Ground 2 U6083B 4770A–AUTO–11/03 U6083B Pin Configuration Figure 2. Pinning DIP8 VS 1 8 OUTPUT GND 2 7 2 VS VI 3 6 SENSE OSC 4 5 DELAY Pin Description Pin Symbol 1 VS 2 GND 3 VI Function Supply voltage VS IC ground Control input (duty cycle) 4 OSC 5 DELAY Oscillator Short-circuit protection delay 6 SENSE Current sensing 7 2 VS Voltage doubler 8 OUTPUT Output 3 4770A–AUTO–11/03 Functional Description Pin 1, Supply Voltage, VS or VBatt Overvoltage Detection Stage 1 If overvoltages of VBatt > 20 V (typically) occur, the external transistor is switched off, and switched on again at VBatt < 18.5 V (hysteresis). Stage 2 If VBatt > 28.5 V (typically), the voltage limitation of the IC is reduced from VS = 26 V to 20 V. The gate of the external transistor remains at the potential of the IC ground, thus producing voltage sharing between FET and lamps in the event of overvoltage pulses (e.g., load dump). The short-circuit protection is not in operation. At VBatt approximately < 23 V, the overvoltage detection stage 2 is switched off. Thus, during overvoltage detection stage 2, the lamp voltage Vlamp is calculated as follows: VLamp = VBatt - VS - VGS VS = supply voltage of the IC at overvoltage detection stage 2 VGS = gate - source voltage of the FET Undervoltage Detection In the event of voltages of approximately VBatt < 5.0 V, the external FET is switched off and the latch for short-circuit detection is reset. A hysteresis ensures that the FET is switched on again at approximately VBatt ³ 5.4 V. Pin 2, GND Ground-wire Breakage To protect the FET in the case of ground-wire breakage, a 1 MW resistor between gate and source is recommended to provide proper switch-off conditions. Pin 3, Control Input The pulse width is controlled by means of an external potentiometer (47 kW). The characteristic (angle of rotation/duty cycle) is linear. The duty cycle can be varied from 18 to 100%. It is possible to further restrict the duty cycle with the resistors R1 and R2 (see Figure 4 on page 10). In order to reduce the power dissipation of the FET and to increase the lifetime of the lamps, the IC automatically reduces the maximum duty cycle at pin 8 if the supply voltage exceeds V 2 = 13 V. Pin 3 is protected against short-circuit to V Batt and ground (VBatt £ 16.5 V). Pin 4, Oscillator 4 The oscillator determines the frequency of the output voltage. This is defined by an external capacitor, C2. It is charged with a constant current, I, until the upper switching threshold is reached. A second current source is then activated which taps a double current, 2 ´ I, from the charging current. The capacitor, C 2 , is thus discharged at the current, I, until the lower switching threshold is reached. The second source is then switched off again and the procedure starts once more. U6083B 4770A–AUTO–11/03 U6083B Example for Oscillator Frequency Calculation Switching thresholds VT100 = High switching threshold (100% duty cycle) VT100 = VS ´ a1 = (VBatt - IS ´ R3) ´ a1 VT<100 = High switching threshold (< 100% duty cycle) VT<100 = VS ´ a2 = (VBatt - IS ´ R3) ´ a2 VTL = Low switching threshold VTL = VS ´ a3 = (VBatt - IS ´ R3) ´ a3 where a1, a2 and a3 are fixed values Calculation Example Oscillator Frequency The above mentioned threshold voltages are calculated for the following values given in the data sheet. VBatt = 12 V, IS = 4 mA, R3 = 150 W, a1 = 0.7, a2 = 0.67 and a3 = 0.28 VT100 = (12 V - 4 mA ´ 150 W) ´ 0.7 » 8 V VT<100 = 11.4 V ´ 0.67 = 7.6 V VTL = 11.4 V ´ 0.28 = 3.2 V 3 cases have to be distinguished 1. f1 for duty cycle = 100%, no slope reduction with capacitor C4 (see Figure 4 on page 10) I OSC - , where C2 = 68 nF, IOSC = 45 µA f 1 = --------------------------------------------------------2 ´ ( V T100 – V TL ) ´ C2 f1 = ... = 75 Hz 2. f2 for duty cycle < 100%, no slope reduction with capacitor C4 For a duty cycle of less than 100%, the oscillator frequency, f, is as follows: I OSC - , where C2 = 68 nF, IOSC = 45 µA f 2 = -----------------------------------------------------------2 ´ ( V T<100 – V TL ) ´ C2 f2 = ... = 69 Hz 3. f3 with duty cycle < 100% with slope reduction capacitor C4 (see “Output Slope Control” on page 6) Iosc f 3 = -----------------------------------------------------------------------------------------------2 ´ ( V T<100 – V TL ) ´ C2 + 2VBatt ´ C 4 where C2 = 68 nF, IOSC = 45 µA, C4 = 1.8 nF f3 = ... = 70 Hz By selecting different values of C2 and C4, it is possible to have a range of oscillator frequencies from 10 to 2000 Hz as shown in the data sheet. 5 4770A–AUTO–11/03 Output Slope Control The slope of the lamp voltage is internally limited to reduce radio interference by limitation of the voltage gain of the PWM comparator. Thus, the voltage rise on the lamp is proportional to the oscillator voltage increase at the switchover time according to the equation. dV8/dt = a4 ´ dV4/dt = 2 ´ a4 ´ f ´ (a2 - a3) ´ (VBatt - IS ´ R3) when f = 75 Hz, VTX = VT < 100 and a4 = 63 then dV8/dt = 2 ´ 63 ´ 75 Hz ´ (0.67 - 0.28) ´ (12 V - 4 mA ´ 15 W) = 42 V/ms Via an external capacitor, C4, the slope can be further reduced as follows: dV8/dt = IOSC/(C4 + C2/a4) when IOSC = 45 µA, C4 = 1.8 nF, C2 = 68 nF and a4 = 63 then dV8/dt = 45 µA/(1.8 nF + 68 nF/63) = 15.6 V/ms To damp oscillation tendencies, a resistance of 100 W in series with capacitance C4 is recommended. Interference Suppression • “On-board” radio reception according to VDE 0879 part 3/4.81 • Test conditions refering to Figure 3 • Application circuit according to Figure 1 on page 2 or Figure 4 on page 10 • Load: nine 4 W lamps in parallel • Duty cycle = 18% • VBatt = 12 V • fOsc = 100 Hz Figure 3. Voltage Spectrum of On-board Radio Reception 6 U6083B 4770A–AUTO–11/03 U6083B Pins 5 and Pin 6, Short-circuit Protection and Current Sensing Short-circuit Detection and Time Delay, td The lamp current is monitored by means of an external shunt resistor. If the lamp current exceeds the threshold for the short-circuit detection circuit (VT2 » 90 mV), the duty cycle is switched over to 100% and the capacitor C5 is charged by a current source of Ich - Idis. The external FET again is switched off after the cut-off threshold (VT5 ) is reached. Switching on the FET again is possible after a power-on reset only. The current source, Idis, ensures that the capacitor C5 is not charged by parasitic currents. The time delay, td, is calculated as follows: td = C5 ´ VT5/(Ich - Idis) With C5 = 100 nF and VT5 = 10.4 V, Ich =13 µA, Idis = 3 µA, the time delay is as follows: td = 100 nF ´ 10.4 V/(13 µA - 3 µA) td = 104 ms Current Limitation The lamp current is limited by a control amplifier to protect the external power transistor. The voltage drop across the external shunt resistor acts as the measured variable. Current limitation takes place for a voltage drop of VT1 » 100 mV. Owing to the difference VT1 - VT2 » 10 mV, it ensures that current limitation occurs only when the short-circuit detection circuit has responded. After a power-on reset, the output is inactive for half an oscillator cycle. During this time, the supply voltage capacitor can be charged so that current limitation is guaranteed in the event of a short-circuit when the IC is switched on for the first time. Pins 7 and 8, Charge Pump and Output Pin 8 (output) is suitable for controlling a power MOSFET. During the active integration phase, the supply current of the operational amplifier is mainly supplied by the capacitor C3 (bootstrapping). In addition, a trickle charge is generated by an integrated oscillator (f7 » 400 kHz) and a voltage doubler circuit. This permits a gate voltage supply at a duty cycle of 100%. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Value Unit Tj 150 °C Ambient temperature range Tamb -40 to +110 °C Storage temperature range Tstg -55 to +125 °C Symbol Value Unit RthJA 120 K/W Junction temperature Thermal Resistance Parameters Junction ambient 7 4770A–AUTO–11/03 Electrical Characteristics Tamb = -40°C to +110°C, VBatt = 9 to 16.5 V, (basic function is guaranteed between 6.0 V to 9.0 V) reference point ground, unless otherwise specified (see Figure 1 on page 2). All other values refer to pin GND (pin 2). Parameters Test Conditions Current consumption Pin 1 Supply voltage Overvoltage detection, stage 1 Stabilized voltage IS = 10 mA Battery undervoltage detection 1 Symbol Min. Typ. Max. Unit IS 7.9 mA VBatt 25 V 27.0 V Vs 24.5 on off VBatt 4.4 4.8 5.0 5.4 5.6 6.0 V Stage 1: on off VBatt 18.3 16.7 20.0 18.5 21.7 20.3 V V Stage 2: Detection stage 2 on off VBatt 25.5 19.5 28.5 23.0 32.5 26.5 V V Stabilized voltage IS = 30 mA Vs 18.5 20.0 21.5 V Battery Overvoltage Detection Short-circuit Protection Short-circuit current limitation Short-circuit detection 6 VT1 = VS - V6 VT1 85 100 120 mV VT2 = VS - V6 VT2 75 90 105 mV VT2 = VS - V6 VT1 - VT2 3 10 30 mV VT5 10.2 10.4 10.6 Delay Timer Short-ciruit Detection, VBatt = 12 V Switched off threshold 1 5 VT5 = VS - V5 V Charge current Ich 13 µA Discharge current Idis 3 µA Capacitance current I5 = Ich - Idis 10 15 mA 280 400 520 kHz V7 26 27.5 30.0 V V7 VS+14 VS+15 VS+16 V a4 53 63 72 130 V/ms Low level V8 0.35 0.70 0.95 V VBatt = 16.5 V Tamb = 110°C, R3 = 150 W V8 1.5(1) V High level, duty cycle 100% V8 V8 = Low level I8 1.0 V8 = High level, I7 > ½ I8 ½ I8 -1.0 tp/T 15 100 65 Voltage Doubler Voltage Duty cycle 100% Internal voltage limitation I7 = 5 mA (whichever is lower) Edge steepness dv8/dt = a4 dV4/dt dV8/dtmax Gate Output Current Duty cycle Note: 8 5 V7 2 VS f7 7 Oscillator frequency Voltage I5 8 Min: C2 = 68 nF Max: VBatt £ 12.4 V VBatt = 16.5 V, C2 = 68 nF V7 V mA mA 18 21 73 81 % 1. Reference point is battery ground U6083B 4770A–AUTO–11/03 U6083B Electrical Characteristics (Continued) Tamb = -40°C to +110°C, VBatt = 9 to 16.5 V, (basic function is guaranteed between 6.0 V to 9.0 V) reference point ground, unless otherwise specified (see Figure 1 on page 2). All other values refer to pin GND (pin 2). Parameters Test Conditions Pin Symbol Min. 4 f 10 Typ. Max. Unit 2000 Hz Oscillator Frequency Threshold cycle V T100 V 8 = High, a 1 = -------------VS a1 0.68 0.7 0.72 Upper VT<100 V 8 = Low, a 2 = ---------------VS a2 0.65 0.67 0.69 Lower V TL a 3 = -------VS a3 0.26 0.28 0.3 Oscillator current VBatt = 12 V ±IOSC 34 45 54 µA Frequency C4 open, C2 = 68 nF duty cycle = 50% f 56 75 90 Hz Note: 1. Reference point is battery ground 9 4770A–AUTO–11/03 10 47 µF C1 C2 4 R2 VS VS 47 kΩ 3 68 nF R1 VS 2I Low voltage monitoring Overvoltage monitoring stage 1 + - + - Reset Reset Switch-on delay Oscillator I VS R VS 63 x R Reset - + VS C5 GND Idis 5 150 Ω Ich VS 100 nF VS 2 R3 Overvoltage monitoring stage 2 1 Current limiting - + VS 8 7 6 10 mV 90 mV Voltage doubler VS C4 Ground 1 MΩ 1.8 nF 47 nF Load RL C3 Rsh VBatt Application Figure 4. Application Circuit U6083B 4770A–AUTO–11/03 U6083B Ordering Information Extended Type Number Package U6083B Remarks DIP8 – Package Information Package DIP8 Dimensions in mm 7.77 7.47 9.8 9.5 1.64 1.44 4.8 max 6.4 max 0.5 min 3.3 0.58 0.48 2.54 0.36 max 9.8 8.2 7.62 8 5 technical drawings according to DIN specifications 1 4 11 4770A–AUTO–11/03 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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