XILINX XC4003A

XC4000A
Logic Cell Array Family

Product Specifications
Features
Description
• Third Generation Field-Programmable Gate Arrays
The XC4000A family of FPGAs offers four devices at the low
end of the XC4000 family complexity range. XC4000A
differs from XC4000 in four areas: fewer routing resources,
fewer wide-edge decoders, higher output sink current, and
improved output slew-rate control.
–
–
–
–
–
–
–
–
Abundant flip-flops
Flexible function generators
On-chip ultra-fast RAM
Dedicated high-speed carry-propagation circuit
Wide edge decoders (two per edge)
Hierarchy of interconnect lines
Internal 3-state bus capability
Eight global low-skew clock or signal distribution
network
• The XC4000 routing structure is optimized for smaller
designs, naturally requiring fewer routing resources. The
XC4000A devices have four Longlines and four singlelength lines per row and column, while the XC4000
devices have six Longlines and eight single-length lines
per row and column. This results in a smaller chip area
and lower cost per device.
• Flexible Array Architecture
– Programmable logic blocks and I/O blocks
– Programmable interconnects and wide decoders
• XC4000A has two wide-edge decoders on every device
edge, while the XC4000 has four. All other wide-decoder
features are identical in XC4000 and XC4000A.
• Sub-micron CMOS Process
– High-speed logic and Interconnect
– Low power consumption
• XC4000A outputs are specified at 24 mA, sink current,
• Systems-Oriented Features
–
–
–
–
IEEE 1149.1-compatible boundary-scan logic support
Programmable output slew rate (4 modes)
Programmable input pull-up or pull-down resistors
24-mA sink current per output (48 per pair)
• Configured by Loading Binary File
– Unlimited reprogrammability
– Six programming modes
• XACT Development System runs on ’386/’486-type PC,
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700 Series
– Interfaces to popular design environments like
Viewlogic, Mentor Graphics and OrCAD
– Fully automatic partitioning, placement and routing
– Interactive design editor for design optimization
– 288 macros, 34 hard macros, RAM/ROM compiler
while XC4000 outputs are specified at 12 mA. The source
current is the same 4 mA for both families.
• The XC4000A family offers a more sophisticated output
slew-rate control structure with four configurable options
for each individual output driver: fast, medium fast, medium slow, and slow. Slew-rate control can alleviate
ground-bounce problems when multiple outputs switch
simultaneously, and it can reduce or eliminate crosstalk
and transmission-line effects on printed circuit boards.
Note that the XC4003 and XC4005 devices are available in
both flavors, the lower-priced XC4003A/XC4005A with reduced routing, and the higher-priced XC4003/XC4005 with
more abundant routing resources. The XC4000A devices
are intended for less demanding and more structured
designs, and the XC4000 devices for more random designs
requiring additional routing resources.
The equivalent devices are pin-compatible and are available in identical packages, but they are not bitstream
compatible. In order to move from a XC4000A to a XC4000,
or vice versa, the design must be recompiled.
Table 1. The XC4000A Family of Field-Programmable Gate Arrays
Device
Appr. Gate Count
CLB Matrix
Number of CLBs
Number of Flip-Flops
Max Decode Inputs (per side)
Max RAM Bits
Number of IOBs
XC4002A
2,000
8x8
64
256
24
2,048
64
2-71
XC4003A
3,000
10 x 10
100
360
30
3,200
80
XC4004A
4,000
12 x 12
144
480
36
4,608
96
XC4005A
5,000
14 x 14
196
616
42
6,272
112
XC4000A Logic Cell Array Family
Absolute Maximum Ratings
Symbol Description
Units
VCC
Supply voltage relative to GND
–0.5 to +7.0
V
VIN
Input voltage with respect to GND
–0.5 to VCC +0.5
V
VTS
Voltage applied to 3-state output
–0.5 to VCC +0.5
V
TSTG Storage temperature (ambient)
–65 to + 150
°C
TSOL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
+ 260
°C
+ 150
°C
Junction temperature
TJ
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions
for extended periods of time may affect device reliability.
Operating Conditions
Symbol
VCC
Description
Min
Max
Units
Supply voltage relative to GND Commercial 0°C to 85°C junction
4.75
5.25
V
Supply voltage relative to GND Industrial -40°C to 100°C junction
4.5
5.5
V
Supply voltage relative to GND
4.5
5.5
V
VCC
V
0.8
V
250
ns
Military –55°C to 125°C case
VIH
High-level input voltage (XC4000 has TTL-like input thresholds)
2.0
VIL
Low-level input voltage (XC4000 has TTL-like input thresholds)
0
TIN
Input signal transition time
At junction temperatures above those listed as Operating conditions, all delay parameters increase by 0.35% per °C.
DC Characteristics Over Operating Conditions
Symbol
Description
Min
VOH
High-level output voltage @ IOH = –4.0 mA, VCC min
2.4
VOL
Low-level output voltage @ IOL = 24 mA, VCC min (Note 1)
0.4
V
ICCO
Quiescent LCA supply current (Note 2)
10
mA
IIL
Leakage current
+10
µA
CIN
Input capacitance (sample tested)
15
pF
IRIN
Pad pull-up (when selected) @ VIN = 0V (sample tested)
0.02
0.25
mA
IRLL
Horizontal Long Line pull-up (when selected) @ logic Low
0.2
2.5
mA
–10
Max
Units
V
Note: 1. With 50% of the outputs simultaneously sinking 24 mA.
2. With no output current loads, no active input or longline pull-up resistors, all package pins at VCC or GND, and
the LCA configured with a MakeBits tie option.
2-72
Wide Decoder Switching Characteristic Guidelines
Speed Grade
Description
Full length, both pull-ups,
inputs from IOB I-pins
Full length, both pull-ups
inputs from internal logic
Half length, one pull-up
inputs from IOB I-pins
Half length, one pull-up
inputs from internal logic
-6
-5
Symbol
Device
Max
Max
TWAF
XC4002A
XC4003A
XC4004A
XC4005A
8.5
9.0
9.5
10.0
7.5
8.0
8.5
9.0
XC4002A
XC4003A
XC4004A
XC4005A
11.5
12.0
12.5
13.0
10.5
11.0
11.5
12.0
XC4002A
XC4003A
XC4004A
XC4005A
8.5
9.0
9.5
10.0
7.5
8.0
8.5
9.0
XC4002A
XC4003A
XC4004A
XC4005A
11.5
12.0
12.5
13.0
10.5
11.0
11.5
12.0
TWAFL
TWAO
TWAOL
PRELIMINARY
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, there derived from benchmark timing patterns. The following
guidelines relflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date
timing information, use the values provided by the XACT timing calculator and used in the simulator.
-4
Max
5.0
6.0
7.0
8.0
6.0
7.0
8.0
9.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the input delay (TPID)
and output delay (one of 4 modes), as listed on page 2-70.
Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Description
Global Signal Distribution
From pad through primary buffer, to any clock k
From pad through secondary buffer, to any clock k
-6
-5
Symbol
Device
Max
Max
TPG
XC4002A
XC4003A
XC4004A
XC4005A
7.7
7.8
7.9
8.0
5.7
5.8
5.9
6.0
XC4002A
XC4003A
XC4004A
XC4005A
8.7
8.8
8.9
9.0
6.7
6.8
6.9
7.0
TSG
2-73
-4
PRELIMINARY
Speed Grade
Max
5.1
5.5
6.3
6.7
Units
ns
ns
ns
ns
ns
ns
ns
ns
XC4000A Logic Cell Array Family
Horizontal Longline Switching Characteristic Guidelines
Speed Grade
Description
TBUF driving a Horizontal Longline (L.L.)
I going High or Low to L.L. going High or Low,
while T is Low, i.e. buffer is constantly active
I going Low to L.L. going from resistive pull-up
High to active Low, (TBUF configured as open drain)
T going Low to L.L. going from resistive pull-up
or floating High to active Low, (TUBF configured
as open drain)
-6
-5
-4
Max
Units
PRELIMINARY
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
ns
ns
ns
ns
Symbol
Device
Max
Max
TIO1
XC4002A
XC4003A
XC4004A
XC4005A
8.2
8.8
9.4
10.0
6.0
6.2
6.6
7.0
XC4002A
XC4003A
XC4004A
XC4005A
8.7
9.3
9.9
10.5
6.5
6.7
7.1
7.5
XC4002A
XC4003A
XC4004A
XC4005A
10.1
10.7
11.4
12.0
8.4
9.0
9.5
10.0
TIO2
TON
T going High to TBUF going inactive, not driving L.L.
TOFF
All devices
3.0
2.0
T going High to L.L. going from Low to High,
pulled up by a single resistor
TPUS
XC4002A
XC4003A
XC4004A
XC4005A
23.0
24.0
25.0
26.0
19.0
20.0
21.0
22.0
XC4002A
XC4003A
XC4004A
XC4005A
10.5
11.0
11.5
12.0
8.5
9.0
9.5
10.0
T going High to L.L. going from Low to High,
pulled up by two resistors
TPUF
2-74
4.4
5.5
5.0
6.0
ns
ns
ns
ns
8.0
ns
ns
ns
ns
1.8
ns
7.2
14.0
16.0
7.0
8.0
ns
ns
ns
ns
ns
ns
ns
ns
Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly. and guaranteed over the operating conditions. The same parameters can also be derived
indirectly from the IOB and Global Buffer specifications. The XACT delay calculator uses this indirect method. When there is a discrepancy
between these two methods, the directly tested values listed below should be used, and the derived values should be ignored.
Description
Global Clock to Output (fast)
Device
TICKOF
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
14.9
15.1
15.3
15.5
19.9
20.1
20.3
20.5
2.6
2.4
2.2
2.0
4.9
5.1
5.3
5.5
12.2
12.5
12.8
13.0
15.2
15.5
15.8
16.0
2.3
2.0
1.7
1.5
3.7
4.0
4.3
4.5
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
21.8
21.5
21.2
21.0
0
0
0
0
18.8
18.5
18.2
18.0
0
0
0
0
TICKO
(Max)
Input Set-up Time, using IFF (no delay)
TPSUF
(Min)
Input Hold time, using IFF (no delay)
TPHF
(Min)
Input Set-up Time, using IFF (with delay)
TPSU
(Min)
Input Hold Time, using IFF (with delay)
TPH
(Min)
Input
Set-Up
&
Hold
Time
IFF
OFF
TPG
Global Clock-to-Output Delay
-4
Units
11.6
12.0
14.6
15.0
1.6
1.2
4.0
4.5
12.0
12.0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Timing is measured at pin threshold, with 50 pF external
capacitive loads (incl. test fixture). When testing fast outputs, only one output switches. When testing slew-rate
limited outputs, half the number of outputs on one side of the
device are switching. These parameter values are tested
and guaranteed for worst-case conditions of supply voltage
and temperature, and also with the most unfavorable clock
polarity choice.
•
•
•
•
•
X3192
TPDLI for -4 Speed Grade
Pad to I1, I2
via transparent
latch, with delay
-5
Symbol
(Max)
Global Clock to Output (slew limited)
-6
PRELIMINARY
Speed Grade
TPICKD for -4 Speed Grade
Input set-up time
pad to clock (IK)
with delay
XC4003A 17.6 ns
XC4005A 17.9 ns
PRELIMINARY
XC4003A 15.6 ns
XC4005A 15.9 ns
PRELIMINARY
X6091
See page 2-76
2-75
XC4000A Logic Cell Array Family
IOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following
guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date
timing information, use the values provided by the XACT timing calculator and used in the simulator.
XC4003A
XC4005A
Description
Symbol
-6
-5
Min Max
Min Max
-4
Min Max Units
INPUT
Propagation Delays
Pad to I1, I2
Pad to I1, I2, via transparent latch (no delay)
Pad to I1, I2, via transparent latch (with delay)
Clock (IK) toI1, I2, (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
TPID
TPLI
TPDLI
TIKRI
TIKLI
Set-up Time (Note 3)
Pad to Clock (IK), no delay
Pad to Clock (IK) with delay
TPICK
TPICKD
7.0
25.0
6.0
24 .0
4.0
**
ns
ns
Hold Time (Note 3)
Pad to Clock (IK), no delay
Pad to Clock (IK) with delay
TIKPI
TIKPID
1.0
neg
1.0
neg
1.0
neg
ns
ns
OUTPUT
Propagation Delays
Clock (OK) to Pad (fast)
Output (O) to Pad (fast)
3-state to Pad begin hi-Z (slew-rate independent)
3-state to Pad active and valid (fast)
TOKPOF
TOPF
TTSHZ
TTSONF
3.0
7.0
24.0
7.0
7.0
2.8
6.0
**
6.0
6.0
ns
ns
ns
ns
ns
Set-up and Hold Times
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
TOOK
TOKO
8.0
0.0
6.0
0.0
PRELIMINARY
4.0
8.0
26.0
8.0
8.0
5.5
0
ns
ns
Clock
Clock High or Low time
TCH/TCL
5.0
4.0
4.0
ns
Global Set/Reset
Delay from GSR net through Q to I1, I2
Delay from GSR net to Pad
GSR width*
TRRI
TRPO
TMRW
Additional Delay
For medium fast outputs
For medium slow outputs
For slow outputs
7.5
9.0
9.0
13.0
7.0
7.0
7.0
10.0
2.0
4.0
6.0
1.5
3.0
4.5
14.5
18.0
21.0
13.5
17.0
18.0
6.5
5.5
6.5
9.5
ns
ns
ns
ns
1.0
2.0
3.0
ns
ns
ns
13.5
14.6
18.0
ns
ns
ns
* Timing is based on the XC4005. For other devices see XACT timing calculator.
** See preceding page.
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture).
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
internal pull-up or pull-down resistor or alternatively configured as a driven output or be driven from an external source.
3. Input pad setup times and hold times are specified with respect to the internal clock (IK). To calculate system setup time,
subtract clock delay (clock pad to IK) from the specified input pad setup time value, but do not subtract below zero.
Negative hold time means that the delay in the input data is adequate for the external system hold time to be zero,
provided the input clock uses the Global signal distribution from pad to IK.
2-76
CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following
guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date
timing information, use the values provided by the XACT timing calculator and used in the simulator.
XC4003A
XC4005A
Speed Grade
Description
Symbol
-6
-5
Min Max
Min
-4
Max
Min Max Units
TILO
TIHO
THHO
6.0
8.0
7.0
4.5
7.0
5.0
4.0
6.0
4.5
ns
ns
ns
CLB Fast Carry Logic
Operand inputs (F1,F2,G1,G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (F1,F3) to COUT
CIN through function generators to X/Y outputs
CIN to COUT, bypass function generators.
TOPCY
TASCY
TINCY
TSUM
TBYP
7.0
8.0
6.0
8.0
2.0
5.5
6.0
4.0
6.0
1.5
5.0
5.5
3.5
5.5
1.5
ns
ns
ns
ns
ns
Sequential Delays
Clock K to outputs Q
TCKO
5.0
3.0
3.0
ns
Set-up Time before Clock K
F/G inputs
F/G inputs via H'
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F'/G'
CIN input via F'/G' and H'
TICK
TIHCK
THHCK
TDICK
TECCK
TRCK
6.0
8.0
7.0
4.0
7.0
6.0
8.0
10.0
Hold Time after Clock K
F/G inputs
F/G inputs via H'
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
TCKI
TCKIH
TCKHH
TCKDI
TCKEC
TCKR
Clock
Clock High time
Clock Low time
PRELIMINARY
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H' to X/Y outputs
C inputs via H' to X/Y outputs
4.5
6.0
5.0
3.0
4.0
4.5
6.0
7.5
4.5
6.0
5.0
3.0
3.0
4.0
5.5
7.3
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
TCH
TCL
5.0
5.0
4.0
4.0
4.0
4.0
ns
ns
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
TRPW
TRIO
5.0
Master Set/Reset*
Width (High or Low)
Delay from Global Set/Reset net to Q
TMRW
TMRQ
21.0
* Timing is based on the XC4005. For other devices see XACT timing calculator.
2-77
4.0
9.0
4.0
8.0
18.0
33.0
7.0
ns
ns
28.0
ns
ns
18.0
31.0
XC4000A Logic Cell Array Family
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following
guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date
timing information, use the values provided by the XACT timing calculator and used in the simulator.
Description
Write Operation
Address write cycle time
Write Enable pulse width (High)
Address set-up time before beginning of WE
Address hold time after end of WE
DIN set-up time before end of WE
DIN hold time after end of WE
Read Operation
Address read cycle time
Data valid after address change
(no Write Enable)
Read Operation, Clocking Data into Flip-Flop
Address setup time before clock K
Read During Write
Data valid after WE going active
(DIN stable before WE)
Data valid after DIN
(DIN change during WE)
Read During Write, Clocking Data into Flip-Flop
WE setup time before clock K
Data setup time before clock K
Speed Grade
Symbol
-6
Min
-5
Max
-4
Min Max
Min Max Units
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
both
TWC
TWCT
TWP
TWPT
TAS
TAST
TAH
TAHT
TDS
TDST
TDHT
9.0
9.0
5.0
5.0
2.0
2.0
2.0
2.0
4.0
5.0
2.0
8.0
8.0
4.0
4.0
2.0
2.0
2.0
2.0
4.0
5.0
2.0
8.0
8.0
4.0
4.0
2.0
2.0
2.0
2.0
4.0
5.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16 x 2
32 x 1
16 x 2
32 x 1
TRC
TRCT
TILO
TIHO
7.0
10.0
5.5
7.5
5.0
7.0
ns
ns
ns
ns
16 x 2
32 x 1
TICK
TIHCK
6.0
8.0
16 x 2
32 x 1
16 x 2
32 x 1
TWO
TWOT
TDO
TDOT
16 x 2
32 x 1
16 x 2
32 x 1
TWCK
TWCKT
TDCK
TDCKT
Note: Timing for the 16 x 1 RAM option is identical to 16 x 2 RAM timing
2-78
6.0
8.0
4.5
7.0
4.5
6.0
12.0
15.0
11.0
14.0
12.0
15.0
11.0
14.0
4.0
6.0
4.5
6.0
10.0
12.0
9.0
11.0
10.0
12.0
9.0
11.0
PRELIMINARY
CLB RAM OPTION
XC4003A
XC4005A
9.0
11.0
8.5
11.0
9.5
11.5
9.0
11.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLB RAM Timing Characteristics
T RC
ADDRESS
WRITE
TAS
T WP
T AH
WRITE ENABLE
T DH
T DS
DATA IN
REQUIRED
TILO
READ
X,Y OUTPUTS
VALID
VALID
READ, CLOCKING DATA INTO FLIP-FLOP
TICK
TCH
CLOCK
T CKO
XQ,YQ OUTPUTS
VALID
(OLD)
VALID
(NEW)
READ DURING WRITE
T WP
WRITE ENABLE
T DH
DATA IN
(stable during WE)
T WO
X,Y OUTPUTS
DATA IN
(changing during WE)
VALID
VALID
OLD
NEW
T WO
X,Y OUTPUTS
VALID
(PREVIOUS)
T DO
VALID
(OLD)
VALID
(NEW)
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
T WP
WRITE ENABLE
TWCK
T DCK
DATA IN
CLOCK
T CKO
XQ,YQ OUTPUTS
X2640
2-79
XC4000A Logic Cell Array Family
2-80
XC4002A Pinouts
Pin
Description
Bound
PC84 PQ100 VQ100 PG120 Scan
Pin
Description
Bound
PC84 PQ100 VQ100 PG120 Scan
Pin
Description
Bound
PC84 PQ100 VQ100 PG120 Scan
VCC
2
92
89
G3
–
I/O
28
23
20
C9
92
–
–
–
–
L9
–
I/O (A8)
3
93
90
G1
26
SGCK2 (I/O)
29
24
21
A12
95
I/O (D6)
58
58
55
M10
157
I/O (A9)
4
94
91
F1
29
O (M1)
30
25
22
B11
98
I/O
–
59
56
N11
160
–
–
95*
92*
E1*
–
GND
31
26
23
C10
–
I/O (D5)
59
60
57
M9
163
–
–
96*
93*
F2*
–
I (M0)
32
27
24
C11
101†
I/O (CSO)
60
61
58
N10
166
I/O (A10)
5
97
94
F3
32
VCC
33
28
25
D11
–
–
–
62*
59*
L8*
–
I/O (A11)
6
98
95
D1
35
I (M2)
34
29
26
B12
102†
–
–
63*
60*
N9*
–
–
–
–
–
E2*
–
PGCK2 (I/O)
35
30
27
C12
103
I/O (D4)
61
64
61
M8
169
I/O (A12)
7
99
96
C1
38
I/O (HDC)
36
31
28
A13
106
I/O
62
65
62
N8
172
I/O (A13)
8
100
97
D2
41
–
–
–
–
B13*
–
VCC
63
66
63
M7
–
–
–
–
–
E3*
–
–
–
–
–
E11*
–
GND
64
67
64
L7
–
–
–
–
–
B1*
–
I/O
–
32
29
D12
109
I/O (D3)
65
68
65
N7
175
178
I/O (A14)
9
1
98
C2
44
I/O (LDC)
37
33
30
C13
112
I/O (RS)
66
69
66
N6
SGCK1 (A15, I/O)
10
2
99
D3
47
I/O
38
34
31
E12
115
–
–
70*
67*
N5*
–
VCC
11
3
100
C3
–
I/O
39
35
32
D13
118
–
–
–
–
M6*
–
GND
12
4
1
C4
–
–
–
36*
33*
F11*
–
I/O (D2)
67
71
68
L6
181
PGCK1 (A16, I/O)
13
5
2
B2
50
–
–
37*
34*
E13*
–
I/O
68
72
69
N4
184
I/O (A17)
14
6
3
B3
53
I/O
40
38
35
F12
121
I/O (D1)
69
73
70
M5
187
–
–
–
–
A1*
–
I/O (ERR, INIT)
41
39
36
F13
124
I/O (RCLK-BUSY/RDY)
70
74
71
N3
190
–
–
–
–
A2*
–
VCC
42
40
37
G12
–
–
–
–
–
M4*
–
I/O (TDI)
15
7
4
C5
56
GND
43
41
38
G11
–
–
–
–
–
L5*
–
I/O (TCK)
16
8
5
B4
59
I/O
44
42
39
G13
127
I/O (D0, DIN)
71
75
72
N2
193
–
–
–
–
A3*
–
I/O
45
43
40
H13
130
SGCK4 (DOUT, I/O)
72
76
73
M3
196
I/O (TMS)
17
9
6
B5
62
–
–
44*
41*
J13*
–
CCLK
73
77
74
L4
–
I/O
18
10
7
A4
65
–
–
45*
42*
H12*
–
VCC
74
78
75
L3
–
–
–
–
–
C6*
–
I/O
46
46
43
H11
133
O (TDO)
75
79
76
M2
–
–
–
11*
8*
A5*
–
I/O
47
47
44
K13
136
GND
76
80
77
K3
–
I/O
19
12
9
B6
68
I/O
48
48
45
J12
139
I/O (A0, WS)
77
81
78
L2
2
I/O
20
13
10
A6
71
I/O
49
49
46
L13
142
PGCK4 (I/O,A1)
78
82
79
N1
5
GND
21
14
11
B7
–
–
–
–
–
K12*
–
–
–
–
–
M1*
–
VCC
22
15
12
C7
–
–
–
–
–
J11*
–
–
–
–
–
J3*
–
I/O
23
16
13
A7
74
I/O
50
50
47
M13
145
I/O (CS1, A2)
79
83
80
K2
8
I/O
24
17
14
A8
77
SGCK3 (I/O)
51
51
48
L12
148
I/O (A3)
80
84
81
L1
11
–
–
18*
15*
A9*
–
GND
52
52
49
K11
–
I/O (A4)
81
85
82
J2
14
–
–
–
–
B8*
–
DONE
53
53
50
L11
–
I/O (A5)
82
86
83
K1
17
I/O
25
19
16
C8
80
VCC
54
54
51
L10
–
–
–
87*
84*
H3*
–
I/O
26
20
17
A10
83
PROG
55
55
52
M12
–
–
–
88*
85*
J1*
–
I/O
27
21
18
B9
86
I/O (D7)
56
56
53
M11
151
I/O (A6)
83
89
86
H2
20
I/O
–
22
19
A11
89
PGCK3 (I/O)
57
57
54
N13
154
I/O (A7)
84
90
87
H1
23
–
–
–
–
B10*
–
–
–
–
–
N12*
–
GND
1
91
88
G2
–
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 199 = BSCANT.UPD
2-81
This document was created with FrameMaker 4 0 2
XC4000A Logic Cell Array Family
XC4003A Pinouts
Pin
Description
VCC
I/O (A8)
I/O (A9)
I/O
I/O
I/O (A10)
I/O (A11)
–
I/O (A12)
I/O (A13)
–
–
I/O (A14)
SGCK1 (A15,I/O)
VCC
GND
PGCK1 (A16, I/O)
I/O (A17)
–
–
I/O (TDI)
I/O (TCK)
–
I/O (TMS)
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
I/O
SGCK2 (I/O)
O (M1)
GND
I (M0)
VCC
I (M2)
PGCK2 (I/O)
I/O (HDC)
–
–
I/O
I/O (LDC)
I/O
I/O
I/O
I/O
I/O
I/O (ERR, INIT)
VCC
PC84
2
3
4
–
–
5
6
–
7
8
–
–
9
10
11
12
13
14
–
–
15
16
–
17
18
–
–
19
20
21
22
23
24
–
–
25
26
27
–
–
28
29
30
31
32
33
34
35
36
–
–
–
37
38
39
–
–
40
41
42
VQ100 PQ100 PG120
89
92
G3
90
93
G1
91
94
F1
92
95
E1
93
96
F2
94
97
F3
95
98
D1
–
–
E2*
96
99
C1
97
100
D2
–
–
E3*
–
–
B1*
98
1
C2
99
2
D3
100
3
C3
1
4
C4
2
5
B2
3
6
B3
–
–
A1*
–
–
A2*
4
7
C5
5
8
B4
–
–
A3*
6
9
B5
7
10
A4
–
–
C6
8
11
A5
9
12
B6
10
13
A6
11
14
B7
12
15
C7
13
16
A7
14
17
A8
15
18
A9
–
–
B8
16
19
C8
17
20
A10
18
21
B9
19
22
A11
–
–
B10*
20
23
C9
21
24
A12
22
25
B11
23
26
C10
24
27
C11
25
28
D11
26
29
B12
27
30
C12
28
31
A13
–
–
B13*
–
–
E11*
29
32
D12
30
33
C13
31
34
E12
32
35
D13
33
36
F11
34
37
E13
35
38
F12
36
39
F13
37
40
G12
Bound
Scan
–
32
35
38
41
44
47
–
50
53
–
–
56
59
–
–
62
65
–
–
68
71
–
74
77
80
83
86
89
–
–
92
95
98
101
104
107
110
113
–
116
119
122
–
125†
–
126†
127
130
–
–
133
136
139
142
145
148
151
154
–
Pin
Description
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
–
I/O
SGCK3 (I/O)
GND
DONE
VCC
PROG
I/O (D7)
PGCK3 (I/O)
–
–
I/O (D6)
I/O
I/O (D5)
I/O (CS0)
I/O
I/O
I/O (D4)
I/O
VCC
GND
I/O (D3)
I/O (RS)
I/O
I/O
I/O (D2)
I/O
I/O (D1)
I/O (RCLK-BUSY/RDY)
–
–
I/O (D0, DIN)
SGCK4 (DOUT, I/O)
CCLK
VCC
O (TDO)
GND
I/O (A0, WS)
PGCK4 (A1, I/O)
–
–
I/O (CS1, A2)
I/O (A3)
I/O (A4)
I/O (A5)
I/O
I/O
I/O (A6)
I/O (A7)
GND
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 247 = BSCANT.UPD
2-82
PC84
43
44
45
–
–
46
47
48
49
–
–
50
51
52
53
54
55
56
57
–
–
58
–
59
60
–
–
61
62
63
64
65
66
–
–
67
68
69
70
–
–
71
72
73
74
75
76
77
78
–
–
79
80
81
82
–
–
83
84
1
VQ100 PQ100 PG120
38
41
G11
39
42
G13
40
43
H13
41
44
J13
42
45
H12
43
46
H11
44
47
K13
45
48
J12
46
49
L13
–
–
K12*
–
–
J11*
47
50
M13
48
51
L12
49
52
K11
50
53
L11
51
54
L10
52
55
M12
53
56
M11
54
57
N13
–
–
N12*
–
–
L9*
55
58
M10
56
59
N11
57
60
M9
58
61
N10
59
62
L8
60
63
N9
61
64
M8
62
65
N8
63
66
M7
64
67
L7
65
68
N7
66
69
N6
67
70
N5
–
–
M6
68
71
L6
69
72
N4
70
73
M5
71
74
N3
–
–
M4*
–
–
L5*
72
75
N2
73
76
M3
74
77
L4
75
78
L3
76
79
M2
77
80
K3
78
81
L2
79
82
N1
–
–
M1*
–
–
J3*
80
83
K2
81
84
L1
82
85
J2
83
86
K1
84
87
H3
85
88
J1
86
89
H2
87
90
H1
88
91
G2
Bound
Scan
–
157
160
163
166
169
172
175
178
–
–
181
184
–
–
–
–
187
190
–
–
193
196
199
202
205
208
211
214
–
–
217
220
223
226
229
232
235
238
–
–
241
244
–
–
–
–
2
5
–
–
8
11
14
17
20
23
26
29
–
XC4004A Pinouts
Pin
Description
Bound
PC84 TQ144 PQ160 PG120 Scan
Pin
Description
Bound
PC84 TQ144 PQ160 PG120 Scan
Pin
Description
Bound
PC84 TQ144 PQ160 PG120 Scan
VCC
2
128
142
G3
–
I/O
28
32
36
C9
140
–
–
–
90*
–
I/O (A8)
3
129
143
G1
38
SGCK2 (I/O)
29
33
37
A12
143
GND
–
81
91
–
–
I/O (A9)
4
130
144
F1
41
O (M1)
30
34
38
B11
146
–
–
82*
92*
–
–
I/O
–
131
145
E1
44
GND
31
35
39
C10
–
–
–
83*
93*
–
–
I/O
–
132
146
F2
47
I (M0)
32
36
40
C11
149†
I/O (D5)
59
84
94
M9
241
I/O (A10)
5
133
147
F3
50
VCC
33
37
41
D11
–
I/O (CSO)
60
85
95
N10
244
I/O (A11)
6
134
148
D1
53
I (M2)
34
38
42
B12
150†
I/O
–
86
96
L8
247
–
–
135*
149*
–
–
PGCK2 (I/O)
35
39
43
C12
151
I/O
–
87
97
N9
250
–
–
136*
150*
–
–
I/O (HDC)
36
40
44
A13
154
I/O (D4)
61
88
98
M8
253
GND
–
137
151
E2
–
I/O
–
41
45
B13
157
I/O
62
89
99
N8
256
–
–
–
–
152*
–
–
I/O
–
42
46
E11
160
VCC
63
90
100
M7
–
–
–
–
153*
–
–
I/O
–
43
47
D12
163
GND
64
91
101
L7
–
I/O (A12)
7
138
154
C1
56
I/O (LDC)
37
44
48
C13
166
I/O (D3)
65
92
102
N7
259
I/O (A13)
8
139
155
D2
59
–
–
–
49*
–
–
I/O (RS)
66
93
103
N6
262
I/O
–
140
156
E3
62
–
–
–
50*
–
–
I/O
–
94
104
N5
265
I/O
–
141
157
B1
65
GND
–
45
51
–
–
I/O
–
95
105
M6
268
I/O (A14)
9
142
158
C2
68
–
–
46*
52*
–
–
I/O (D2)
67
96
106
L6
271
SGCK1 (A15, I/O)
10
143
159
D3
71
–
–
47*
53*
–
–
I/O
68
97
107
N4
274
VCC
11
144
160
C3
–
I/O
38
48
54
E12
169
–
–
98*
108*
–
–
GND
12
1
1
C4
–
I/O
39
49
55
D13
172
–
–
99*
109*
–
–
PGCK1 (A16, I/O)
13
2
2
B2
74
I/O
–
50
56
F11
175
GND
–
100
110
–
–
I/O (A17)
14
3
3
B3
77
I/O
–
51
57
E13
178
–
–
–
111*
–
–
I/O
–
4
4
A1
80
I/O
40
52
58
F12
181
–
–
–
112*
–
–
I/O
–
5
5
A2
83
I/O (ERR, INIT)
41
53
59
F13
184
I/O (D1)
69
101
113
M5
277
I/O (TDI)
15
6
6
C5
86
VCC
42
54
60
G12
–
I/O
(RCLK-BUSY/RDY)
70
102
114
N3
280
I/O (TCK)
16
7
7
B4
89
GND
43
55
61
G11
–
I/O
–
103
115
M4
283
–
–
–
8*
–
–
I/O
44
56
62
G13
187
I/O
–
104
116
L5
286
–
–
–
9*
–
–
I/O
45
57
63
H13
190
I/O (D0, DIN)
71
105
117
N2
289
GND
–
8
10
A3
–
I/O
–
58
64
J13
193
SGCK4 (DOUT, I/O)
72
106
118
M3
292
–
–
9*
11*
–
–
I/O
–
59
65
H12
196
CCLK
73
107
119
L4
–
–
–
10*
12*
–
–
I/O
46
60
66
H11
199
VCC
74
108
120
L3
–
I/O (TMS)
17
11
13
B5
92
I/O
47
61
67
K13
202
O (TDO)
75
109
121
M2
–
I/O
18
12
14
A4
95
–
–
62*
68*
–
–
GND
76
110
122
K3
–
I/O
–
13
15
C6
98
–
–
63*
69*
–
–
I/O (A0, WS)
77
111
123
L2
2
I/O
–
14
16
A5
101
GND
–
64
70
–
–
PGCK4 (I/O,A1)
78
112
124
N1
5
I/O
19
15
17
B6
104
–
–
–
71*
–
–
I/O
–
113
125
M1
8
11
I/O
20
16
18
A6
107
–
–
–
72*
–
I/O
–
114
126
J3
GND
21
17
19
B7
–
I/O
48
65
73
J12
205
I/O (CS1, A2)
79
115
127
K2
14
VCC
22
18
20
C7
–
I/O
49
66
74
L13
201
I/O (A3)
80
116
128
L1
17
I/O
23
19
21
A7
110
I/O
–
67
75
K12
211
–
–
117*
129*
–
–
I/O
24
20
22
A8
113
I/O
–
68
76
J11
214
–
–
–
130*
–
–
I/O
–
21
23
A9
116
I/O
50
69
77
M13
217
GND
–
118
131
–
–
I/O
–
22
24
B8
119
SGCK3 (I/O)
51
70
78
L12
220
–
–
119*
132*
–
–
I/O
25
23
25
C8
122
GND
52
71
79
K11
–
–
–
120*
133*
–
–
I/O
26
24
26
A10
125
DONE
53
72
80
L11
–
I/O (A4)
81
121
134
J2
20
23
–
–
25*
27*
–
–
VCC
54
73
81
L10
–
I/O (A5)
82
122
135
K1
–
–
26*
28*
–
–
PROG
55
74
82
M12
–
–
–
–
136*
–
–
GND
–
27
29
–
–
I/O (D7)
56
75
83
M11
223
I/O
–
123
137
H3
26
–
–
–
30*
–
–
PGCK3 (I/O)
57
76
84
N13
226
I/O
–
124
138
J1
29
–
–
–
31*
–
–
I/O
-
77
85
N12
229
I/O (A6)
83
125
139
H2
32
I/O
27
28
32
B9
128
I/O
-
78
86
L9
232
I/O (A7)
84
126
140
H1
35
I/O
–
29
33
A11
131
I/O (D6)
58
79
87
M10
235
GND
1
127
141
G2
–
I/O
–
30
34
B10
134
I/O
-
80
88
N11
238
I/O
–
31
35
–
137
-
-
-
89*
-
–
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 295 = BSCANT.UPD
2-83
XC4000A Logic Cell Array Family
XC4005A Pinouts
Pin
Description
PC84
VCC
I/O (A8)
I/O (A9)
I/O
I/O
–
–
I/O (A10)
I/O (A11)
I/O
I/O
GND
–
–
–
–
I/O (A12)
I/O (A13)
–
I/O
I/O
I/O (A14)
SGCK1 (A15, I/O)
VCC
–
–
–
–
GND
–
PGCK1 (A16, I/O)
I/O (A17)
I/O
I/O
–
I/O (TDI)
I/O (TCK)
–
–
–
–
GND
I/O
I/O
I/O (TMS)
I/O
–
–
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
–
–
I/O
I/O
I/O
I/O
GND
–
–
–
–
I/O
I/O
I/O
2
3
4
–
–
–
–
5
6
–
–
–
–
–
–
–
7
8
–
–
–
9
10
11
–
–
–
–
12
–
13
14
–
–
–
15
16
–
–
–
–
–
–
–
17
18
–
–
–
–
19
20
21
22
23
24
–
–
–
–
25
26
–
–
–
–
–
–
–
27
–
–
TQ144 PQ160 PQ208 PG156
128
129
130
131
132
–
–
133
134
135
136
137
–
–
–
–
138
139
–
140
141
142
143
144
–
–
–
–
1
–
2
3
4
5
–
6
7
–
–
–
–
8
9
10
11
12
–
–
13
14
15
16
17
18
19
20
21
22
–
–
23
24
25
26
27
–
–
–
–
28
29
30
142
143
144
145
146
–
–
147
148
149
150
151
–
–
152*
153*
154
155
–
156
157
158
159
160
–
–
–
–
1
–
2
3
4
5
–
6
7
8*
9*
–
–
10
11
12
13
14
–
–
15
16
17
18
19
20
21
22
23
24
–
–
25
26
27
28
29
–
–
30*
31*
32
33
34
183
184
185
186
187
188*
189*
190
191
192
193
194
195*
196*
197*
198*
199
200
–
201
202
203
204
205
206*
207*
208*
1*
2
3*
4
5
6
7
–
8
9
10*
11*
12*
13*
14
15
16
17
18
19*
20*
21
22
23
24
25
26
27
28
29
30
31*
32*
33
34
35
36
37
38*
39*
40*
41*
42
43
44
H3
H1
G1
G2
G3
–
–
F1
F2
E1
E2
F3
–
–
D1*
D2*
E3
C1
–
C2
D3
B1
B2
C3
–
–
–
–
C4
–
B3
A1
A2
C5
–
B4
A3
A4*
–
–
–
C6
B5
B6
A5
C7
–
–
B7
A6
A7
A8
C8
B8
C9
B9
A9
B10
–
–
C10
A10
A11
B11
C11
–
–
A12*
–
B12
A13
A14
Bound
Scan
Pin
Description
PC84
–
44
47
50
53
–
–
56
59
62
65
–
–
–
–
–
68
71
–
74
77
80
83
–
–
–
–
–
–
–
86
89
92
95
–
98
101
–
–
–
–
–
104
107
110
113
–
–
116
119
122
125
–
–
128
131
134
137
–
–
140
143
146
149
–
–
–
–
–
152
155
158
I/O
–
I/O
SGCK2 (I/O)
O (M1)
GND
I (M0)
–
–
–
–
VCC
I (M2)
PGCK2 (I/O)
I/O (HDC)
I/O
–
I/O
I/O
I/O (LDC)
–
–
–
–
GND
I/O
I/O
I/O
I/O
–
–
I/O
I/O
I/O
I/O (ERR, INIT)
VCC
GND
I/O
I/O
I/O
I/O
–
–
I/O
I/O
I/O
I/O
GND
–
–
–
–
I/O
I/O
I/O
I/O
I/O
SGCK3 (I/O)
GND
–
DONE
–
–
VCC
–
PROG
I/O (D7)
PGCK3 (I/O)
I/O
–
I/O
I/O(D6)
–
–
28
29
30
31
32
–
–
–
–
33
34
35
36
–
–
–
–
37
–
–
–
–
–
–
–
38
39
–
–
–
–
40
41
42
43
44
45
–
–
–
–
46
47
–
–
–
–
–
–
–
48
49
–
–
50
51
52
–
53
–
–
54
–
55
56
57
–
–
–
58
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
2-84
This document was created with FrameMaker 4 0 2
TQ144 PQ160 PQ208 PG156
31
–
32
33
34
35
36
–
–
–
–
37
38
39
40
41
–
42
43
44
–
–
–
–
45
46
47
48
49
–
–
50
51
52
53
54
55
56
57
58
59
–
–
60
61
62
63
64
–
–
–
–
65
66
67
68
69
70
71
–
72
–
–
73
–
74
75
76
77
–
78
79
35
–
36
37
38
39
40
–
–
–
–
41
42
43
44
45
–
46
47
48
49*
50 *
–
–
51
52
53
54
55
–
–
56
57
58
59
60
61
62
63
64
65
–
–
66
67
68
69
70
–
–
71*
72*
73
74
75
76
77
78
79
–
80
–
–
81
–
82
83
84
85
–
86
87
45
–
46
47
48
49
50
51 *
52 *
53*
54*
55
56
57
58
59
–
60
61
62
63*
64*
65 *
66*
67
68
69
70
71
72*
73 *
74
75
76
77
78
79
80
81
82
83
84*
85*
86
87
88
89
90
91*
92*
93*
94*
95
96
97
98
99
100
101
102*
103
104 *
105 *
106
107*
108
109
110
111
–
112
113
C12
–
B13
B14
A15
C13
A16
–
–
–
–
C14
B15
B16
D14
C15
–
D15
E14
C16
E15*
D16*
–
–
F14
F15
E16
F16
G14
–
–
G15
G16
H16
H15
H14
J14
J15
J16
K16
K15
–
–
K14
L16
M16
L15
L14
–
–
N16*
M15*
P16
M14
N15
P15
N14
R16
P14
–
R15
–
–
P13
–
R14
T16
T15
R13
–
P12
T14
Bound
Scan
161
–
164
167
170
–
173†
–
–
–
–
–
174†
175
178
181
–
184
187
190
–
–
–
–
–
193
196
199
202
–
–
205
208
211
214
–
–
217
220
223
226
–
–
229
232
235
238
–
–
–
–
–
241
244
247
250
253
256
–
–
–
–
–
–
–
–
259
262
265
–
268
271
XC4005A Pinouts (continued)
Pin
Descriptions
I/O
–
–
–
–
GND
I/O
I/O
I/O (D5)
I/O (CS0)
–
–
I/O
I/O
I/O (D4)
I/O
VCC
GND
I/O (D3)
I/O (RS)
I/O
I/O
–
–
I/O (D2)
I/O
I/O
I/O
GND
–
–
–
–
I/O (D1)
I/O (RCLK-BUSY/RDY)
I/O
–
I/O
I/O (D0, DIN)
SGCK4 (DOUT, I/O)
CCLK
VCC
–
–
–
–
O (TDO)
GND
I/O (A0,WS)
PGCK4 (A1,I/O)
I/O
–
I/O
I/O (CS1,A2)
I/O (A3)
–
–
–
–
GND
I/O
I/O
I/O (A4)
I/O (A5)
–
–
I/O
I/O
I/O (A6)
I/O (A7)
GND
PC84
–
–
–
–
–
–
TQ144
80
–
–
–
–
81
PQ160
88
89*
90*
–
–
91
PQ208
114
115*
116*
117*
118*
119
PG156
T13
R12*
T12*
–
–
P11
Bound
Scan
274
–
–
–
–
–
–
–
59
60
–
–
–
–
61
62
63
82
83
84
85
–
–
86
87
88
89
90
92
93
94
95
–
–
96
97
98
99
100
120
121
122
123
124*
125*
126
127
128
129
130
R11
T11
T10
P10
–
–
R10
T9
R9
P9
R8
277
280
283
286
–
–
289
292
295
298
–
64
91
101
131
P8
–
65
66
–
–
–
–
67
68
–
–
–
92
93
94
95
–
–
96
97
98
99
100
102
103
104
105
–
–
106
107
108
109
110
132
133
134
135
136*
137*
138
139
140
141
142
T8
T7
T6
R7
–
–
P7
T5
R6
T4
P6
301
304
307
310
–
–
313
316
319
322
–
–
–
–
–
69
70
–
–
–
71
72
73
74
–
–
–
–
101
102
103
–
104
105
106
107
108
–
–
111*
112*
113
114
115
–
116
117
118
119
120
143*
144*
145*
146*
147
148
149
–
150
151
152
153
154
–
–
R5*
–
T3
P5
R4
–
R3
P4
T2
R2
P3
–
–
–
–
325
328
331
–
334
337
340
–
–
–
–
–
–
75
76
–
–
–
–
109
110
–
–
–
–
121
122
155*
156*
157*
158*
159
160
–
–
–
–
T1
N3
–
–
–
–
–
–
77
78
–
–
–
79
80
–
–
–
–
–
111
112
113
–
114
115
116
117*
–
–
–
118
123
124
125
–
126
127
128
129*
130*
–
–
131
161
162
163
–
164
165
166
167*
168*
169*
170*
171
R1
P2
N2
–
M3
P1
N1
M2*
M1*
–
–
L3
2
5
8
–
11
14
17
–
–
–
–
–
–
–
81
82
–
–
–
–
83
84
1
119
120
121
122
–
–
123
124
125
126
127
132
133
134
135
–
136*
137
138
139
140
141
172
173
174
175
176*
177*
178
179
180
181
182
L2
L1
K3
K2
–
–
K1
J1
J2
J3
H2
20
23
26
29
–
–
32
35
38
41
–
* Indicates unconnected package pins.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 343 = BSCANT.UPD
2-85
XC4000A Logic Cell Array Family
For a detailed description of the device architecture, see pages 2-9 through 2-31.
For a detailed description of the configuration modes and their timing, see pages 2-32 through 2-55.
For detailed lists of package pinouts, see pages 2-57 through 2-81 through 2-85.
For package physical dimensions and thermal data, see Section 4.
Ordering Information
XC4005A-5 PQ160C
Example:
Device Type
Temperature Range
Number of Pins
Speed Grade
Package Type
Component Availability
84
PINS
TYPE
XC4002A
XC4003A
XC4004A
XC4005A
PLAST.
PLAST.
PLCC
PQFP
PC84
CODE
-6
-5
-4
-10
-6
-5
-4
-6
-5
-4
-6
-5
-4
100
120
144
TOP
PLAST. BRAZED CERAM. PLAST.
VQFP
CQFP
PGA
TQFP
156
160
164
191
196
208
TOP
TOP
CERAM PLAST. BRAZED CERAM. BRAZED PLAST.
PGA
PQFP
CQFP
PGA
CQFP
PQFP
223
225
METAL CERAM. PLAST.
PQFP
PGA
BGA
240
299
PLAST.
METAL
METAL
PQFP
PQFP
PQFP
PQ100 VQ100 CB100 PG120 TQ144 PG156 PQ160 CB164 PG191 CB196 PQ208 MQ208 PG223 BG225 PQ240 MQ240 PG299
CI
CI
CI
CI
C
C
C
C
CI
CI
CI
C
C
C
C
C
C
M B
M B
M B
CIMB
C
C
CI
CI
CI
CI
C
C
C
C
CI
CI
C
C = Commercial = 0° to +85° C
B = MIL-STD-883C Class B
CI
CI
C
CI
CI
C
CI
CI
C
CI
CI
C
I = Industrial = -40° to +100° C M = Mil Temp = -55° to +125° C
Parentheses indicate future product plans
2-86