MITSUBISHI M65761FP

MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
SPECIFICATION OF INTEGRATED CIRCUIT
1. TYPE NO.
M65761FP
2. FUNCTION
2.1 CIRCUIT FUNCTION
QM-Coder
2.2 BLOCK DIAGRAM
see the third page
3. APPLICATION
FAX, PPC etc
4. OUTLINE
4.1 PACKAGE
4.2 OUTLINE DRAWING
100 Pin Plastic Molded Quad Flat Package (Fine Pitch)
[100P6S-A]
G465181
5. CIRCUIT DIAGRAM
DRAWING
6. PIN DIAGRAM
see the next page (2page)
7. OTHER SPECIFICATIONS
see cover page of specification
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
VCC
TEST0
TEST1
TOUT1
TOUT2
PXCKO
GND
VCC
D15
D14
D13
D12
GND
VCC
D11
D10
D9
D8
GND
VCC
PIN CONFIGURATION (TOP VIEW)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
80
D7
PD0
2
79
D6
PD1
3
78
D5
PD2
4
77
D4
PD3
5
76
GND
PD4
6
75
VCC
PD5
7
74
D3
PD6
8
73
D2
PD7
9
72
D1
PD8
10
71
D0
PD9
11
70
GND
PD10
12
69
VCC
VCC
13
68
RESET
GND
14
67
A3
PD11
15
66
A2
PD12
16
65
A1
PD13
17
64
A0
PD14
18
63
BHE
PD15
19
62
CS
PD16
20
61
MCLK
PD17
21
60
GND
PD18
22
59
VCC
PD19
23
58
WR
PD20
24
57
RD
PD21
25
56
DMAAK
VCC
26
55
BUS16
GND
27
54
DMARQ
PD22
28
53
INTR
PD23
29
52
XCLK
PD24
30
51
GND
32
33
34
35
36
37 38
39 40
41
42 43
44
45
46
47
48
49
50
PD26
PD27
PD28
PD29
PD30
PD31
VCC
GND
PDRD
PDWR
PDAK
RVID
PRDY
SVID
PTIM
PXCK
XWAIT
VCC
PDRQ
31
PD25
M65761FP
GND
Outline 100P6S-A
PD 0
12
15
PD11
–
PD10
2
PD31
–
41
42
45
PDRD
PDWR
PRDY
46
SVID
52
49
XCLK
XWAIT
(=RPIX)
RVID
44
95
PXCKO
(=SPIX)
48
LINE MEMORY
CONTEXT DATA
87
93
1
100
14
27
40
51
CONTEXT TABLE RAM
70
76
82
TABLE RAM PROBABILITY ESTIMATION
88
94
HOST BUS I/F
–
71 D0
57 RD
58 WR
63 BHE
67 A3
77 D4
74 D3
83 D8
80 D7
89 D12
86 D11
99 TEST0
98 TEST1
61 MCLK
55 BUS16
53 INTR
56 DMAAK
54 DMARQ
92 D15
Leave TOUT1 and TOUT2 open.
–
TOUT1,2
96 97
64 A0
62 CS
68 RESET
BLOCK DIAGRAM
GND
60
–
PXCK
81
PIXEL DATA
75
–
(=XTIM)
PTIM
69
–
–
47
43
PDAK
59
–
–
(=XRDY)
38
50
–
PDRQ
39
–
PD15=PEUPE
PD0-11=CX0-11
–
37
28
–
PD22
–
25
26
–
PD21
13
TYPICAL PREDICTION
IMAGE DATA • CONTEXT I/F
VCC
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
QM-CODER
SWITCH
CONTEXT GENERATION
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
9. CODING SPECIFICATION
(1) Coding Algorithm
• QM-Coder
(JBIG Standard Arithmetic Coding System)
X
X
X
X
X
X
X
?
X
X
A
(2) Context
X
X
X
X
X
A
(i) Built-in Context Mode
X
X
X
?
X
a) Template Model
Fig. 9. 1 Template (X, A)
• 2 or 3 line 10 pixel template (See Fig9. 1)
(Top : 3line, Bottom : 2line)
(This agrees with the template used with the minimum resolution of JBIG)
NOTE:The coding efficiency of the 3-line template is better than that of the 2-line template by several %.
b) Adaptive Template (AT)
X
X
• It is possible to move up to 127pixcels on the coding line.
X
X
X
(The position of ATgiven instruction by the MPU)
A
X
X
?
Note:It is possible to improve the coding effeciency against the dither image
by the use of AT.
MAX127
• It is posible to change the position of AT line by line in the middle of coding
X
X
X
X
and decoding.
A
X
X
X
X
?
Note:It is not possible to change the template at the time when change the
position of the AT pixels.
MAX127
(ii) Extenal Context Mode
Fig. 9. 2 Adaptive template (A)
• It is possible to input any context up to 12 bits.
(It is possible to interface with JBIG Progressive Coding and the Arithmatic Coding of JPEG Option Function)
X
X
X
(3) Typical Prediction
• Agreement with the Typical Prediction of the lowest resolution of JBIG.
The pseudo-pixcel (SLNTP) is geneated by the symbol LNTPwhich shows whether the coding/decoding process agree with the directly
before line.If they agree, the line is not coding/decoding .
This makes it possible to shorten the time of process and rejection of the code data.
SLNTPy =! ( LNTPy + LNTPy-1 ) (y:line number, LNTPy=1; LNTPy-1=1)
(4) Deterministic Prediction
• This LSI is not equipped with the Typical Prediction.However,the DP function is realized when the DP pixels are identified and
eliminated by the extenal circuits during the external context mode.
(5) Coding Data Format
• The Stripe Data Entity (SDE)
(=Stripe coded data with byte stuffing (PSCD) + end marker (SDNORM/ SDRST)) Coding/decoding of one stripe portion os
perfformed.In case of the multi-striped (construct the multi stripes) stripes are activated one at a time.
(6) Marker Code
• The SDE end marker is supported.(SDNORM=02h, SDRST=03h, ABORT=04h)
(During coding the marker code previously set in the register is outputted.During decoding ,the marker code detected by requesting an
interrupt to MPU when the marker is detected is read out od register.)
(7) Rough Estimate of Coding and Decoding Time(T1:M65761FP as a whole,T2;Processing Time of the arithmetic coding section alone)
• The total number of clocks needed for coding and decoding 1 page (stripe)is calculates roughly using the following equations.
T1= (p ∗ Lp) + (9/8 ∗ C) + (α ∗ Lp)
- S ∗ ((1 - β) ∗ p ∗ Ltp - Lp) [clock]
T2= (p ∗ Lp) + (9/8 ∗ C)
- S ∗ ((p ∗ Ltp) - Lp)) [clock]
p : Number of pixcels/line
β : about 0.3
Lp : Number of lines/page
Ltp : Number of TP line /page
C : Number of coded data bits/page
S= 1: TP exists 0: No TP
α : about 10
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
10. FUNCTIONAL DESCRIPTION OF PINS
Classification
Pin name
I/O
BUF
Function
RESET
CS
A0-3
BHE
WR
RD
D0-15
DMARQ
DMAAK
INTR
BUS16
I
I
I
I
I
I
IO
O
I
O
I
S
S
S
8
2
US
2
U
H/W reset signal
Chip select signal
Internal register address select signal
High-order(D8-15)access signal
Write strobe signal
Read strobe signal
I/O data signal (D0-7 used on 8-bit bus)
Code data DMA request signal
Code data DMA acknowledge signal
Interrupt request signal
8-bit bus (D0-7)and 16-bit bus(D0-15)function select bus.
Parallel
PD0-31
PDRQ
PDAK
PDRD
PDWR
IO
O
I
I
I
U2
2
US
US
US
Parallel image I/O bus (PD0-15 used on 16-bit bus)
Image data DMA request signal
Image data DMA acknowledge signal
Image data read strobe signal
Image data write strobe signal
Serial
PRDY
PTIM
PXCK
PXCKO
SVID
RVID
O
I
I
O
I
O
2
US
US
4
U
2
Image data 1-line I/O start ready signal
Image data 1-line transfer section signal
Image data transfer clock signal
Image data transfer sync clock signal
Image data input signal
Image data output signal
CX0-11
PEUPE
SPIX
RPIX
XCLK
XWAIT
XRDY
XTIM
I
I
I
O
O
I
O
I
U
U
U
2
4
US
2
US
Context input (CX0 can be fed back inside LSI)
PE RAM update enable (learning function ON/OFF)
Coded image data input signal
Decoded image data output signal
Context data transfer clock signal
Context data transfer wait signal
Context data 1-stripe I/O start ready signal
Context data 1-stripe transfer section signal
MCLK
TEST0-1
Vcc/GND
I
I
–
DS
–
Master clock input signal
Test signal (should be connected to GND when normally used).
Power supply (+5V)/ground
Host Bus I/F
Image data
I/F
Context I/F
Others
(=PD0-11)
(=PD15)
(=SVID)
(=RVID)
(=PRDY)
(=PTIM)
Notes:Most of the context I/F signals are used in conjunction with the image data I/F signals.
∗ The input buffers of the input terminals (I and IO) are at TTL level.
Options are as follows.
(U:with pull-up resistors,D:with pull-down resistors,S:Schmitt trigger)
∗ Numbers (2,4,8) of the BUF column of the output terminals (O and IO) indicate current value. (one of 2,4,or 8mA)
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
11. REGISTER CONFIGURATION
11. 1 List of registers
Address
0
1
2
Register Name
System setting
Parameter setting
Command
R/W
Description
R/W
• LSI H/W reset
• Coding/decoding/image data through mode selection
• Context selection(internal context/external context)
• Byte swap ON/OFF of coded/image data on host bus
• Bit swap ON/OFF of coded/image data on host bus
• Image data I/O I/F(parallel I/F,serial I/F)
• Image data bus bit width selection(32bits/16bits)
R/W
• Template selection (2-line/3-line template)
• Setting of AT pixel position (up to 127)(IF O is set,AT becomes
non-existent (default position))
• Latch input/through input selection in external context input mode
W
• Context table RAM initialization command
• Coding (decoding,through) start/end command
• Start/stop command for R/W of context table RAM
• Selection of temporary stop and terminating end
2
Status
R
• Processing status (in process/end of processing)
• Coded data read/write ready (ready/busy)
• Marker code detection (SDNORM,SDRST,ABORT,others)
• Interrupt request status
• SC counter over flow
• Processing mode (stop temporary/terminating end)
3
Interrupt enable setting
R/W
• Interrupt enable setting correspondence to each of bits positions of
status register
4,5
Pixel count setting
R/W
• Setting the number of pixels on one line (in multiples of 16or32,up to
10240 pixels)
6,7
Line count setting
R/W
• Setting the number of lines to be coded/decoded(up to 65535 lines)
8,9
Processed line count
R
• Setting the number of coded/decoded lines (up to 65535 lines)
A,B
Data write buffer
W
• Buffer for writing coded data/image data/context table RAM data from
MPU into LSI (DMA transferable)(RAM address is automatically
incremented each time data is written.)
A,B
Data read buffer
R
• Buffer for reading coded data/image data/context table RAM data from
LSI into MPU (DMA transferable)(RAM address is automatically
incremented each time data is read).
C
Marker code setting
W
• Setting a terminal marker code in coding (SDNORM/SDRST)
C
Marker code read
R
• Reading a marker code in decoding (SDNORM,SDRST,ABORT,others)
R/W
• Reduction in coding (1/2 reduction in horizontal and vertical directions,
horizontal OR processing)
• Magnification during decoding ( × 2 lengthwise and width)
• Select throwing away the leading 1byte of the coded data read when
decoding
• Selecting the typical prediction
• Selection of prohibiting line memory initialization
D
Scaling
Notes:When the 8bit bus is used for the data read/write buffer,use Address A only.
Incase of the 16-bit buffer,only the word access is possible.
(The byte access is not possible).
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
11. 2 Description of Registers
(1) System Set Up Register (W/R) (address : 0)
d7(MSB)
d0
d0(HR)
: H/W reset (0:Active, 1:Reset state)
SYS_REG : PB PI BX BS CX
MOD
HR
To make a H/W reset ,set this bit to 1 then to 0.
Reset initializes the entire LSI including the group of register and Line Memory. However, the context table RAM is not
initialized.
d1-2(MOD) :This sets up the operating modes.
(d2=0,d1=0:coding, d2=1,d1=0:iage data through (Iage data I/F→Host I/F),
d2=0,d1=1:decoding, d2=1,d1=1:Iage data through (Host I/F→Iage data I/F))
:Context select (0:internal context, 1:Image data through)
NOTE:The internal context should be selected when the image data through mode is used.
When initializing or processing R/W of the Context table RAM and coding /decoding,
This bit must be set the same.(Because RAM configration changes depending on internal/external modes.)
:Select data bit swap of the host bus. (0:MSB(d7)first, 1:LSB(d0)first)
:Select data byte swap of the host bus.(0:Lower byte(A)first, 1:Upper byte(B)first)
NOTE:BX is valid only when the host bus is 16 bits.(BUS16=HIGH)
d3(CX)
d4(BS)
d5(BX)
Table 11. 2 The coed data and image data line-up on the Host bus
Bus width
BUS16
Swap
BX BS
1
16bit
0
0
1
1
0
1
0
1
0
8bit
–
–
0
1
d6(PI)
d7(PB)
Upper address(B)
d15 •
b8 •
b15 •
b0 •
b7 •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Lower address(A)
d8
b15
b8
b7
b0
d7 •
b0 •
b7 •
b8 •
b15 •
–
–
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
d0
b7
b0
b15
b8
b0 • • • • • • b7
b7 • • • • • • b0
b0 is the first coded data on the time
series/the left-hand side image data on the
screen.
b15 is the last coded data on the time
series/the right-hand image data on the
screen.
:Selects the image data I/O I/F (0:Serial /F, 1:ParallelI/F)
:Selects the bit width of the iamge data bus (0:32bit bus (PD0-31), 1:16bit bus(PD0-15))
Table 11. 3 The image data line-up on the image data parallel bus
bit width
PB=0
PB=1
PD31 • • • • • • PD16
PD15 • • • • • • PD0
p0
p16
p0
• • • • • • p15
–
p0 is the image data on the left-hand on the screen.
p31is the image data on the right-hand on the screen.
• • • • • • p31
• • • • • • p15
(2) Parameter Setup Register (W/R) (Address:1)
d7
d4
1) External Context Mode
0
0
PARA_REG : C0 LC
d6 (LC) :Condition of taking in the input from the external context are selected.
(0:through onput, 1:latch input)
When this bit is set to 1,the CX0 to CX11 of the context input is latched once using the transfer clock.("XCLK")
d7 (C0) : When this bit is set to 1,CX0 is selected.
(0:CX0 external input, 1:CX0 internal feedback)
d7
2) Internal Context Mode
PARA_REG :
d0-4 (AT<0>-AT<4>) :ATpixel position Lower 5bits. (See Fig.9. 2)
d5 (TM) :Template select (0:3line template, 1:2line template)
d6 -7(AT<5>-AT<6>) :AT pixel position upper 2bits (the 6th and 7th bits)
d7
2line template,AT=48 :
d7
0
0
1
0
1
0
d4
1
d5
TM
d0
d4
0
Example : 3line template,AT=4 :
d6
AT
0
0
1
0
0
0
0
d0
0
NOTE) The AT pixel position at time of the internal context mode is set up by using all the AT<6:0> (0 to 127)
When the default position (when the AT pixels are not used) is used, At is set to 0.
When the 2-line templsate is used, AT should not be set to 1 to 4. In case of the 3-line template,
AT=1 to 2 is not allowed.
d4
d0
d0
AT
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
(3) Command Register (W) (address : 2)
d7
CMD_REG :
d3
JP
0
RC
JC
d0
IC
d0 (IC) :This command starts initialization of Context Table RAM (1:start initialization)
When this bit goes 1,the Context Rable RAM initialization starts.This bit returns to 0 automatically when the initialization is
completed.
d1 (JC) :Processing (Coding/Decoding/Through) start /end command (1:start processing, 0:end processing)
When this bit goes 1,processing(coding/decoding/through)starts.
This bit returns to 0 automatically when processing of the number of set lines is finished during the selection of end of
termination.
And if this JC bit is made 0 and inputting the image data is stopped during the coding porocess,the coding is stopped (flushed)
even if the set lines are not filled.Mreover,if this bit made 0 during decoding and no more coded data is coming in,it is
assumed that the '00'of the coded data came in and the preset lines have been processed.However,in case of the multistriped coding ,processing should not end by making this bit "0" except in case of last stripe.
d2 (RC) :This command starts and stops R/W of Context Table RAM. (1:R/W start, 0:R/W end)
The Context Table RAM is read out or written in by making this bit to "1".
When reading/writing is finished,this bit must have "0" on it.
d3 (JP) :This selectd temporary stop and the end of termination of coding/decoding/through processing.
(1:Temporary stop selected, 0:End of processing selected)
When the process start command d1(JC)is issued by making this JP bit to 1,the processing stops temporarily when the set
number of lines have been processed. Then, if the process satart command d1(JC) is issued,processing restarts.(See 11.4(3))
d7
(4) Status Register (R) (address : 2)
STAT_REG :
0
d5
PS
SC
IS
MS
DS
d0
JS
d0 (JS) :This register indicates the status of processing in initialization,coding,decoding and through.
(0:Processing in progress(being initialized),1:End of processing)
This JS bit goes to "1"when the initialization is completed as RAM initialization command is issued.
(IC=1) This JS bit goes to "1"when all coded data has been read out during coding in case when the process start command
of the processing end is issued.(JC=1,JP=0) This JS bit goes to "1" when reading all the image data has been completed
during the image data through and decoding. Moreover,this JS bit stays "0" even when the set number of lines have been
processed when the command to start processing the process which has been stopped temporarily has been issued (JC=1,
JP=1). (However,interrupts are issued during the temporary stops.)
d1 (DS) :This is used for read and write ready of coded data.(In case of the through mode,this is used for the image data.)(1:Ready,
0:Reading no possible)
It is possible to do R/W of data by the way of the data write/read buffer when this bit is 1.
d2 (MS) :This detects the marker code during decoding.(0:not detected, 1:detected)
This bit goes to "1" if any marker is detected during decoding.
d3 (IS)
:This indicates the status of the interrupt request.(0:No request, 1:Request exists)
d4(SC)
:This shows the SC count over error during coding.(0:Normal, 1:There is a SC counter overflow)
NOTE:The SC counter counts the "FF" data bytes which occur duriing coding.Coding continues even when the SC counter
overflows.this means correct coding data will not be outputted.(Coding error)
d5(PS) :processing modes (Stopped temporary /End of trailer)(1:Process temporaryily stopped, 0:End of processing)
This PS bit corresponds to the temporary stop and end of processing of d3 bit (JP) processing of the command register.
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
(5) Interrupt Enable Register (W/R) (address : 3)
d7
IENB_REG : MP
d3
SE
0
ME
DE
d0
JE
d0 (JE) :Temporary stop/End of trailer interrupt of initialization/coding/decoding/through .
(0:interrupt mask, 1:interrupt enable)
d1 (DE) :Coded data(Image data)read out/write in ready interrupt.
(0:interrupt mask, 1:interrupt enable)
d2 (ME) :Marker code detection interrupt during decoding. (0:interrupt mask, 1:interrupt enable)
d3 (SE) :SC count over error interrupt during coding.(0:interrupt mask, 1:interrupt enable))
This bit sets to 1 beforehand, it occurs the interruption when the SC counter is overflow during coding. Processing of coding
continues, but the correct coded data is not output.
NOTE:Bits,d0-d3,are for interrupt enable of bits d0-d2 and d4 of the Status Register.
The interrupt request signal(INTR) is asserted when any one of the status bit set in the interrupt enable (D0(JE)generates
interrupts even during the temporary stop),the status goes to "0" due to H/W reset or the INTR signal is negated when the
interrupt mask causes factors for interrupt to be lost. Moreever, the status register will not be cleared by the generation of
interrupts or the R/W of the interrupt enable register.
d7 (MP) :This specified the marker code detection time halt. (0:Continue/restart, 1:temporary halt)
Decoding will stop temporarily when the marker code is detected if this MP bit is preset to "1"during decoding. (it occures
interruption when the marker code is detected, if the ME bit preset to "1".)
if decoding is not completed during the temporary halt,it is possible to reset the line number setup
register. Next, if this MP bit is set to "0",decoding is restarted(Decoding continues to the line number set.)
(6) Register used to set the number of pixels (W/R)
(address:4)
(address:5)
d0-7 (PEL_L) :Number of pixels/line is set (Lower byte)
d0
d7
PEL_REG_L :
PEL_REG_H :
PEL_L
d7
0
d5
d0
PEL_H
d0-5 (PEL_H):Number of pixels/line is set (Upper byte)
It is possible to set up 8192 pixels maximum when 3-line template is used. It is used to set up 10240 pixels maximum when 2-line
template is used. The number of pixels actually coded (or decoded)should be set when reducing(or expanding).When the image
bus uses 16bits(or 32bits)in parallel I/F,multiples of 16 (or 32) should be set. In case of serial I/F,multiples of 8 should be used.
(7) Line Number Setting Register (W/R)
(Address:6)
(Address:7)
d0
d7
LSET_REG_L :
LSET_REG_H :
LSET_L
LSET_H
d0-7 (LSET_L):This sets the number of lines to be processed. (Lower bytes)
(1 to 65535, 0 line not used)
d0-7 (LSET_H):This sets the number of lines to be processed. (Upper bytes)
When reducing(magnification)the actual number of lines to be coded (decoded) should be set.The number of lines (relative number of
lines)from the process start command to be issued from now the immediately following temporary stop/end of trailer should be set. This
register should be set to the value specified before the process star command is issued. Moreover,this register can be rewritten during
processing as long as the following conditions are met:
• If the maximum value, (65535), is set before the process start command is issued,it can be reset once during processing.
• If a value other than maximum value (65535) is set before the process start command is issued and if resetting becomes necessary
during processing,the maximum value (65535) has to be reset once and desired value should the reset.
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
(8) Number of Lines to be Processed Specified (R)
d0
d7
(address:8)
LIN_REG_L :
LINE_L
(address:9)
LIN_REG_H :
LINE_H
d0-7 (LINE_L):The number of lines actually processed is read out (Lower bytes) (0 to 65535)
d0-7 (LINE_H):The number of lines actually processed is read out (Upper bytes)
When the number of lines processed≥number of lines set,coding/decoding/through stops temporarily/end of processing
∗ NOTE:The number of lines to be processed by this processing is cleared to 0 by the issuance of process start command.
(9) Data write in buffer (W) (See Note1)
d0
d7
(address:A)
DWR_BUF_L :
(address:B)
DWR_BUF_H :
DWR_L
DWR_H
d0-7 (DWR_L):This writes in the coded data/image data/context table RAM data (Lower bytes)
d0-7 (DWR_H):This writes in the coded data/image data/context table RAM data (Upper bytes)
(10) Data read out buffer (R) (See Note1)
d7
(address:A)
DRD_BUF_L :
(address:B)
DRD_BUF_H :
d0
DRD_L
DRD_H
d0-7 (DRD_L) :This read out the coded data/image data/context table RAM data. (Lower bytes)
d0-7 (DRD_H) :This read out the coded data/image data/context table RAM data. (Upper bytes)
∗ NOTE1:Address A is used with 8bit bus. In case of the 16 bit bus, only the word access is possible.
(Not byte access). If the number of coded data bytes is an odd number during coding, an one byte pad ("00") is attached after the
end marker is issued in order to use it as a word boundary.
See Table 11.2 for the bit arrangement used during the coded data/image data. In case of the context table RAM data, only the
lower byte becomes valid data regardless of the bus width of the host bus (BUS16).
Table 11. 4 Context data line-up
Host I/F
Bus Width
8bit
16bit
Upper address (B)
d15 • • • • • • • d8
–
–
Lower address (A)
d7
d6 • • • • • d0
mps
mps
s6 • • • • • s0
s6 • • • • • s0
mps:Superior symbol MPS (expected value ∗o/1)
s6-0:Status number ST (0 to 112)
d0
d7
(11) Marker code set up register (W) (address:C)
MSET_REG :
MSET
d0-7 (MSET):The end marker code used during coding is set.(SDNORM=02h, SDRST=03h)
The byte set to this register is outputted as the end marker during coding.
d0
d7
(12) Marker code read out register (R) (address:C)
d0-7 (MDET):The marker codes detected during decoding are read out.
(SDNORM=02h, SDRST=03h, ABORT=04h etc)
The marker codes detected during decoding read out as is.
MDET_REG :
MDET
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
(13) This register sets up various functions (W/R)
(address:D)
d7
CONV_REG :
TP
d0
LI
OB
HO HR
VR
HE
VE
d0 (VE):Selects expansion in lengthwise direction during decoding. (0:Equal dimension, 1:∗2 expansion)
d1 (HE):Selects expansion sideways during decoding. (0:Equal dimension, 1:∗2 expansion)
∗d0 and d1 are possible only during decoding.
d2 (VR):Selects reduction in lengthwise direction during coding. (0:Equal dimension, 1:1/2 reduction)
d3 (HR):Selects sideways reduction during coding. (0:Equal dimension, 1:1/2 reduction)
∗d2 and d3 are possible only during coding.
d4 (HO):Selects thinning in sideways direction during coding. (0:simple thinning, 1:OR processing)
This reduction is valid only during coding.
Note 1:This lengthwise 1/2 reduction during coding is used for the simple thinning. (Odd lines are skipped)
Note 2: The number of lines for image data to be inputs when VR=1 for coding must be twice the value set by the register which
sets the number of lines.
Note 3:The number of lines for image data to be outputs when VE=1 for decoding must be twice the value set by the register which
sets the number of lines.
d5(OB):This selects if the leading 1 byte is discarded during decoding. (0:Normal processing (No discarding),
1:The leading 1 byte is discarded)
If a command to start processing the first the stripe decoding is issued during decoding while OB is set to "1", the leading 1 byte
of the input data is discarded. (Not used for decoding) If OB=0,the one of byte discarding process is not used. (Normal decoding
used) For example, this function is used by the Host 16 bits bus when the leading 1 byte of the input data word is an invalid data.
Note :Selecting this function is valid in case of the Host 8 bits bus and the external context mode also.
d6 (LI):Line memory initialization is prohibited. (0:Initialization specified, 1:Initialization prohibited)
When a command to start processing coding/decoding of the first stripe is issued, if L1=1, the initialization of the internal line
memory is prohibited. (The last image data of the immediately prior coding/decoding left in the line memory is used as the
leading reference line data o the next coding/ decoding.) When LI=0, the internal line memory is initialized. (All white (0) data is
used as the leading reference line data of the next coding /decoding.)In case when the previous stripe ended with SDNORM
during coding/decoding of multi-stripe by setting this bit in the initialization prohibit (1).
Note :Even when LI=1is set, this LI bit is cleared (0) and the internal line memory will be initialized the same line due to the fact that
the H/W reset is written into the external reset terminal or the system set up register.
d7 (TP):This selects the Typical prediction when coding and decoding. (0:Typical prediction off, 1:Typical prediction ON)
11. 3 Initialization of register
Each register is initialized as shown in the table below by writing H/W reset to the external RESET terminals or the system set up registers.
Table 11. 5 Initialization values for registers
Registers
System set up
Parameter set up
Command
Status
Interrupt enable
Number of pixels set up
Set up number of lines
Number of lines processed
Data buffer
Marker code set up
Marker code read out
Various functions set up
Initialization values
00h Notes
00h
00h
00h
00h
00h
00h
00h
Inderfinite
00h
00h
00h
Note:When writing H/W RESET into the System
Setup Register,the value written into is set
up in the System Setup Register.
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
11. 4 Sequence of setting up registers
(1) Initialization sequence of the internal line memory and context table RAM
This sequence starts with the initialization set up (See Note) of internal line memory by the H/W RESET. It is followed by the
initialization of the Context table RAM. (Clear)
1
d7
H/W Reset
Context mode set up
d0
SYS_REG:
0 0 0 0 0 0 0 1
;H/W reset bit ON
SYS_REG:
0 0 0 0 C 0 0 0
;H/W reset bit OFF
;C=Context mode set up
∗ The ON time for H/W RESET bit (The time from d0="1" is
written in to the time when d0="0" is written in)should be 100ns more.
Context table RAM
Initialization command issued
CMD_REG:
0 0 0 0 0 0 0 1
;Context table initialized
Interrupt enable set up
IENB_REG:
0 0 0 0 0 0 0 1
;Process ens interrupt enable
[During this time,the context table RAM is initialized.]
The number of clocks needed for initialization is as follows,
When the internal text mode is used, 1024 + α [clocks]
When the external text mode is used, 4096 + α [clocks]
(Interrupt generation)
d7
d0
Set up interrupt enable
IENB_REG:
0 0 0 0 0 0 0 1
;Interrupt disable
Status register read out
(Check if procesing finished)
STAT_REG
– – – – – – – J
;j=End of processing
CMD_REG:
0 0 0 0 0 0 0 0
;End of initialization
j=1?
N
(Error)
Y
End of initialization command
to 2
Note: Initialization of the line memory by H/W RESET is provided for for the start of coding and decoding by preparing the all white (0) data
as a reference line. At the same time,it initializes the LNTP bit to LNTP=1 for the Typical Prediction .
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
(2) Coding/decoding of stripes (No change in the AT pixel position)/Image data through processing sequence
2
SYS_REG:
d7
d0 ;mm=operating mode(Coding/decoding)
;C=context selection(Internal/external)
b p x s C m m 0
;s,x=Bit,byte swap
;p,b=Image data I/F, bit width
∗
PARA_REG:
c/a l/a t a a a a a
;aa,aaaaa=AT pixel position
;t=Template selection
;l=Conditions to take in external context
;c=External context CX0 selects
Set up number of pixels ∗
PEL_REG_L:
PEL_REG_H:
pel_l
∗
LSET_REG_L:
LSET_REG_H:
lset_h
MSET_REG:
mset
System set up
(LSI mode set up)
Parameter set up
(Template,context)
Set up number of lines
Set up marker code
(Note:Coding only)
pel_h
0 0
lset_l
;pel_l,pel_h=Number of pixels per line
;lset_l,lset_h=Number of lines processed
;mset=marker code byte set up
(SDNORM=02h,SDRST=03h)
;Ve,He=Select expansion during decoding
;Vr,Hr,Ho=Select reduction during coding
∗
Set up functions
CONV_REG: Tp Li Ob Ho Hr Vr He Ve ;Ob=Select discarding leading 1 byte during decoding
;Tp=ON/OFF of typical prediction function
;Li=Select prohibiting initialization of line memory
Note:Set Li to "0" when it is the leading stripe of
single or multi stripe.
Process start command
(Coding/decoding/through)
Set up interrupt enable
CMD_REG:
0 0 0 0 0 0 1 0
;End of trailer processing (Coding/decoding/through)
start command
IENB_REG:
0 0 0 0 0 0 0 1
;Processing end interrupt enable
∗ When the external context mode is used,it is not necessary to set the position of AT pixels,number of
pixels,number of lines,and expansion,reduction/typical prediction/line memory initialization selection.
(They will be invalid)
[Coding and decoding are performed during this time]– – –I/O of image data and code data is performed.
(Coding and decoding of stripe is performed.)
(Interrupt is generated)
Interrupt disable is set up
IENB_REG:
Status register is read out
(Check end of processing)
d7
d0
;Interrupt disable
0 0 0 0 0 0 0 0
STAT_REG:
– – – s – m – j
;j=End of processing
;m=Marker detection
;s=SC counter overflow
N
j=1?
(Error)
Y
N (Coded)
Decoded?
Y (Decoded)
s=0?
N (Marker not yet detected)
(Error)
Y (Marker detected)
End
(Error)
Y
m=1?
Marker code read out
Note:only for decoding
N (SC counter overflow)
End
MDET_REG:
mdet
;mdet=marker code read out
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
(3) Processing sequence of coding/decoding of stripes (Internal context mode and AT pixel position may change)
2
SYS_REG:
Parameter set up
(Template,At pixel position)
PARA_REG:
Set up number of pixels
PEL_REG_L:
PEL_REG_H:
Set up number of lines
Set up marker code
(Note:Coding only)
Set up various functions
b p x s C m m 0
;mm=operating mode(Coding/decoding)
;C=0 Internal context selected
;s,x=Bit and byte swap
;p,b=Image data I/F, bit width
a a t a a a a a
;aa,aaaaa=AT pixel position
;t=Template selection
d7
System set up
(LSI mode set up)
d0
pel_l
0 0
pel_h
lset_l
LSET_REG_L:
LSET_REG_H:
lset_h
MSET_REG:
mset
CONV_REG:
Tp Li Ob Ho Hr Vr He Ve
Note:Set Li to "0" when the leading stripe of
single or multi stripe is used.
;pel_l,pel_h=Number of pixels per 1 line
;lset_l,lset_h=Number of lines process
Note:The number of lines up to the point
where AT pixel position is changed is set.
;mset=marker code byte set up
(SDNORM=02h,SDRST=03h)
;Ve,He=Expansion selection for decoding
;Vr,Hr,Ho=Select reduction during coding
;Ob=Select discarding leading 1 byte when coding
;Tp=ON/OFF of typical prediction function
;Li=Select prohibiting initialization of line memory. Note
Process start command
(Stop processing temporarily)
CMD_REG:
0 0 0 0 1 0 1 0
;Stop processing temporarily (Coding/decoding)
Set up interrupt enable
IENB_REG:
0 0 0 0 0 0 0 1
;Processing stop interrupt enable
[Coding /decoding go on during this time] – – – I/O of the first image data and code data take place.
Note:During the first processing,if it is coding,(the number of lines of the input image data)=
(the value set in the register which sets the number of lines)+1
During decoding,(number of lines of the output image data)=(the value set in the register which sets the number of lines)-1
(Interrupt is generated)
Interrupt disable is set up
IENB_REG:
d7
d0
0 0 0 0 0 0 0 0
Status register is read out
STAT_REG:
– – p – – – – j
Set up the last AT
;Interrupt disable
;Status check
;j=0,p=1;temporary check
Last set up
Go to 3
Middle of set up
Set up AT pixel position
PARA_REG:
a' a' t a' a' a' a' a'
;AT pixel change set up (a'a'a'a'a'a'a')
∗ Template not to be changed
Set up number of lines
to Next page
LSET_REG_L:
LSET_REG_H:
lset_l
lset_h
;lset_l,lset_h=Number of lines process
Note:Set up the number of lines to be processed from
the time processing restarted to the position where
next the next AT pixel is changed.
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
This routine is repeated the (AT move -1) times
(To previous page)
Process start command
(Temporary stop command)
CMD_REG:
0 0 0 0 1 0 1 0
;Command to restart processing which stopped
temporarily (Coding/decoding)
Set up interrupt enable
IENB_REG:
0 0 0 0 0 0 0 1
;Processing end interrupt enable
[Coding and decoding are performed during this time] – – – I/O of image data and code data is performed.
Note:During the above processing the following is true.
During coding,
(The number of lines of the input image data) = (Number of lines set in the line number setting register)
During decoding,
(Number of lines of the output image data) = ( Number of lines set in the line number setting register)
(Interrupt is generated)
d7
d0
Interrupt disable is set up
IENB_REG:
0 0 0 0 0 0 0 0
;Interrupt disable
Status register is read out
(Check end of processing)
STAT_REG:
– – – s – m – j
;j=End of processing
;m=Marker detection
;s=SC counter overflow
j=1?
Y
Decoded?
N
(Error)
N (Coded)
Y (Decoded)
s=0?
N (Marker not yet detected)
m=1?
Y
N (SC counter overflow)
(Error)
End
(Error)
Y (Marker detected)
Marker code read out
Note:only for decoding
End
MDET_REG:
mdet
;mdet=marker code read out
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
(4) Read out /write in sequence of context table RAM
This sequence dies R/W of context table RAM.
d7
d0
Set context mode
SYS_REG:
– – – – C – – 0
;H/Wreset bit OFF
;C=Context mode set
Start command for R/W
of RAM
CMD_REG:
0 0 0 0 0 1 0 0
;Start of R/W context table RAM
[Reading (writing) of Context table RAM continues during this time.]
RAM data is outputted (inputted) by way of data read (write) buffer.
The RAM address is automatically incremented every time 1 byte is read out (write in)
(Note) It I not possible to mix reading and writing.
End of R/W command of RAM
CMD_REG:
0 0 0 0 0 0 0 0
;End of R/W command of RAM
This does not end automatically.
Be sure to write the end of R/W command.
Note:The assignment of address for context table RAM is as follows.
Internal context mode:Address 0 to 1023 of (LSB:0, MSB:9) as shown below.
External context mode:Address 0 to 4095 of (LSB:CX0, MSB:CS11)
8 7 6
5 4 3 2 9
1 0 ?
3-line template
8 5 4 3 2 9
7 6 1 0 ?
2-line template
(AT pixel is MSB:9)
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
(5) Overall sequence of multi-stripe coding/decoding
The image whose 1page is composed of multiple stripes must perform (2) or (3) by stripes after the initialization of (1).
(Note1) When 16 bit bus is used for the host-bus during coding , in
multi-stripe
coding/decoding
order to use the word boundary, he pad byte ("00") 1byte long tends
to follow behind the end marker code of each stripe.This must be
eliminated externally.
(Note2) When starting decoding of each stripe (during decoding),
Internal memory & context
table RAM are initialized.
(1) processing
inputting must start from the leading coded data of SDE (Stripe data
entity). If necessary, the leading 1 byte is discarded. (In case when
the leading portion of coded data of the next stripe is already
inputted in LSI (FIFO) or when it is not lined up with the lead
Coding/decoding of 1st stripe
(2) or (3) processing
All stripes
process ended?
boundary during decoding of each stripe ends,external management
is needed.
Y
End of page
This routine is repeated(Number of stripes -1)
N
(Note3) Management of marker codes (AT MOVE,
NEWLEN, etc) processing (Insertion at the time of coding
Is the previous
stripe SDNORM?
Y
N (SDRST)
and detection/removing at the time of decoding) should be
done externally.
(SDNORM)
Stripe coding/decoding
Initialization of internal
line memory and Context table
RAM
(1) processing
(Line memory initialization
prohibited:Li=1,AT pixel=
the value of previous stripe
[(2)or (3) is processed]
(Description)
If the end marker of the stripe one before is SDNORM,
stripe coding/decoding
process (line memory
initialization is specified
by Li=0, AT pixel =default
position(0)
[ (2) or (3) is processed]
do not initialize the line memory nor the Context table
RAM. The AT pixel position will use the last value of
the previous stripe and starts processing next stripe.
In case of SDRST,initialization takes place first and
then the AT pixel position is returned to the default
position. Then the processing of the next stripe begins.
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
12. ABSOLUTE MAXIMUM RATINGS (Ta=–20 to +70°C unless otherwise noted)
Symbol
Parameter
VCC
Supply voltage
VI
Input voltage
VO
Output voltage
Tstg
Storage temperature
Pd
Power dissipation
Conditions
Ta=25°C
When single IC is used
Ratings
Unit
-0.3 to +7.0
V
-0.3 to VCC+0.3
V
0 to VCC
V
-65 to +150
°C
1380
mW
Note : All of the voltage is reference the GND terminal of the circuit .
Maximum value and minimum value are expression of absolute value.
13. RECOMMEND OPERATING CONDITIONS
Limits
Symbol
Parameter
VCC
Supply voltage
GND
GND voltage
VI
Input voltage
Topr
Operating temperature range
CL
Output capacitance(against IC)
Unit
Test conditions
Min
Typ
Max
4.5
5.0
5.5
0
V
V
0
VCC
V
-20
+70
°C
50
pF
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
14. ELECTRICAL CHARACTERISTICS (Ta=-20 to +70°C, VCC=5V±10% unless otherwise noted)
Limits
Symbol
Parameter
Unit
Test conditions
Min
VIH
"H"input voltage
VIL
"L"input voltage
VIH
"H"input voltage
VIL
"L"input voltage
VT+
Positive
threshold voltage
VT-
Negative
threshold voltage
VH
Hysteresis width
VOH
"H"output voltage
Typ
Max
V
2.0
PD<31:0>,A<3:0>,
D<15:0>,SVID,
BUS16,CS,BHE
0.8
V
4.5
MCLK,PXCK
PDRD,DMAAK,
PDAK,PTIM
XWAIT,PDWR,
TEST1,TEST0,
RD,WR,RESET
0.0
V
2.4
V
V
0.6
V
0.2
IOH=-8mA
V
VCC-0.8
V
D<15:0>
VOL
"L"output voltage
VOH
"H"output voltage
IOH=8mA
IOH=-4mA
0.55
VCC-0.8
V
V
XCLK,PXCKO
VOL
"L"output voltage
IOH=4mA
VOH
"H"output voltage
VOL
"L"output voltage
IIH
"H"Input current
IIL
"L"Input current
IOZH
"H"output current
in OFF state
IOZL
"L"output current
in OFF state
RU
Pull up Resister
PD<31:0>,PDRD,
PDWR,PDAK,
SVID,PTIM,
PXCK,XWAIT,
BUS16,DMAAK
VCC=5.5V, VI=0V
RD
Pull down Resister
TEST1,TEST0
VCC=5.5V, VI=5V
ICCA
Dynamic consumption
0.55
VCC-0.8
V
PD<31:0>,INTR,
DMARQ,PDRQ,
PRDY,RVID
IOH=-2mA
IOH=2mA
0.55
V
A<3:0>,
D<15:0>,RD,WR,
MCLK,BHE,
RESET,CS
VCC=5.5V, VI=5.5V
-1.0
µA
1.0
µA
-5.0
µA
5.0
µA
25∗
100∗
kΩ
21∗
100∗
kΩ
V
VCC=5.5V, VI=0V
VCC=5.5V, VI=5.5V
D<15:0>
VCC=5.5V, VI=0V
∗ The value of register is 50kΩ buffer's value.
VCC=5.5V, VI=VCC, GND
100
mA
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
15. TIMING CHARACTERISTICS (Ta=-20 to +70°C, VCC=5V±10% unless otherwise noted)
1) Host Bus I/F
Symbol
tPZL
(RD-D0 to 15)
tPZH
(RD-D0 to 15)
Parameter
tPHL
(DMAAK-DMARQ)
Limits
Unit
Min
Typ
Max
0
30
ns
0
30
ns
0
30
ns
0
30
ns
20
ns
Test
circuit
D0 to 15 output define time
for RD assert
tPLZ
(RD-D0 to 15)
tPHZ
(RD-D0 to 15)
Test
conditions
CL=50pF
1
D0 to 15 output hold time for RD assert
DMARQ negate time for DMAAK assert
2) Image data I/F
Symbol
tPLH
(PTIM-PRDY)
tPHL
(PXCK-RVID)
tPLH
(PXCK-RVID)
Parameter
Test
conditions
Limits
Unit
Min
PRDY negate time for PTIM assert
tPHL
(PXCKO-RVID)
tPLH
(PXCKO-RVID)
RVID output define time
for the fall of PXCKO
CL=50pF
RVID negate time for PTIM negate
tPHL
(PDAK-PDRQ)
PDRQ negate time for PDAK assert
tPZH
(PDRD-PD0 to 31)
ns
25
ns
25
ns
15
ns
15
ns
10
ns
10
ns
0
ns
20
ns
0
30
ns
0
30
ns
0
30
ns
0
30
ns
PD0 to 31 output define time
for PDRD assert
tPLZ
(PDRD-PD0 to 31)
tPHZ
(PDRD-PD0 to 31)
30
Test
circuit
PXCKO delay time for PXCK
tPLH
(PTIM-RVID)
tPZL
(PDRD-PD0 to 31)
Max
RVID output define time
for the fall of PXCK
tPHL
(PXCK-PXCKO)
tPLH
(PXCK-PXCKO)
Typ
PD0 to 31 hold time for PDRD negate
1
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
3) Context I/F
Symbol
tPLH
(XTIM-XRDY)
tPLH
(XCLK-RPIX)
tPHL
(XCLK-RPIX)
Parameter
Limits
Unit
Min
XRDY negate time for XTIM assert time
Typ
Max
30
ns
0
30
ns
0
30
ns
30
ns
30
ns
Test
circuit
RPIX output define time
for the fall of XCLK
CL=50pF
tPLH
(MCLK-XCLK)
tPHL
(MCLK-XCLK)
Test
conditions
XCLK delay time for MCLK
1
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
16. TIMING CHARACTERISTICS (Ta=-20 to +70°C, VCC=5V±10% unless otherwise noted)
1) Host Bus I/F
Symbol
Parameter
tw(RESET)
RESET assert time
tsu(RD-CS)
Test
conditions
Limits
Unit
Min
Typ
Max
100
ns
CS set up time for RD assert
20
ns
th(RD-CS)
CS hold time for RD negate
20
ns
tsu(RD-A0 to 3)
A0 to 3 set up time for RD assert
20
ns
tsu(RD-BHE)
BHE set up time for RD assert
20
ns
tw(RD)
RD assert time
30
ns
th(RD-A0 to 3)
A0 to 3 hold time for RDnegate
20
ns
th(RD-BHE)
BHE hold time for RD negate
20
ns
tsu(WR-CS)
CS set up time for WR assert
20
ns
th(WR-CS)
CS hold time for WR negate
20
ns
tsu(WR-A0 to 3)
A0 to 3 set up time for WR assert
20
ns
tsu(WR-BHE)
A0 to 3 set up time for WR assert
20
ns
tw(WR)
WR assert time
30
ns
th(WR-A0 to 3)
A0 to 3 hold time for WR negate
20
ns
th(WR-BHE)
BHE hold time for WR negate
20
ns
tsu(WR-D0 to 15)
D0 to 15 input set up time for WR negate
20
ns
th(WR-D0 to 15)
D0 to 15 input hold time for WR negate
20
ns
tsu(RD-DMAAK)
DMAAK set up time for RD assert
20
ns
th(RD-DMAAK)
DMAAK hold time for RD negate
20
ns
tsu(WR-DMAAK)
DMAAK set up time for WR assert
20
ns
th(WR-DMAAK)
DMAAK hold time for WR negate
20
ns
CL=50pF
Test
circuit
1
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
2) Image Data I/F
Symbol
Parameter
Test
conditions
Limits
Min
Typ
Max
Unit
tci(MCLK)
MCLK period(Mx)
when used image data I/F
50
ns
twi+(MCLK)
MCLK high level time(Mh)
when used image data I/F
20
ns
twi-(MCLK)
MCLK low level time(Ml)
when used image data I/F
20
ns
tri(MCLK)
MCLK rising time
when used image data I/F
20
ns
tfi(MCLK)
MCLK falling time
when used image data I/F
20
ns
tsu(PXCK-PTIM)
PTIM set up time for the fall of PXCK
20
ns
th(PXCK-PTIM)
PTIM hold time for the rise of PXCK
20
ns
tw+(PXCK)
PXCK high time
20
ns
tw-(PXCK)
PXCK low time
20
ns
tc(PXCK)
PXCK period
50
ns
CL=50pF
Test
circuit
1
tsu(PXCK-SVID)
SVID set up time for the fall of PXCK
10
ns
th(PXCK-SVID)
SVID set up time for the fall of PXCK
10
ns
tsu(PDRD-PDAK)
PDAK set up time for PDRD assert
20
ns
th(PDRD-PDAK)
PDAK hold time for PDRD negate
20
ns
tw(PDRD)
PDRD assert time
30
ns
tsu(PDWR-PDAK)
PDAK set up time for PDWR assert
20
ns
th(PDWR-PDAK)
PDAK hold time for PDWR negate
20
ns
tw(PDWR)
PDWR assert time
20
ns
tsu(PDWR-PD0 to 31)
PD0 to 31 input set up time
for PDWR negate
20
ns
th(PDWR-PD0 to 31)
PD0 to 31 input hold time
for PDWR negate
20
ns
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
3) Context I/F
Symbol
Parameter
tcc(MCLK)
MCLK period(Mx)
when used context I/F
twc+(MCLK)
Test
conditions
Limits
Min
Typ
Max
Unit
100
ns
MCLK high level time(Mh)
when used context I/F
40
ns
twc-(MCLK)
MCLK low level time(Ml)
when used context I/F
40
ns
trc(MCLK)
MCLK rising time
when used context I/F
20
ns
tfc(MCLK)
MCLK falling time
when used context I/F
20
ns
tsu(MCLK-XTIM)
XTIM assert time for the rise of MCLK
th(XCLK-XTIM)
XTIM negate time for the rise of XCLK
tw+(XCLK)
XCLK high time
Mh
ns
tw-(XCLK)
XCLK low time
Ml
ns
tc(XCLK)
XCLK period
Mx
ns
th(XCLK-XWAIT)
XWAIT negate time for the rise of XCLK
20
ns
20
0
Test
circuit
10
ns
ns
CL=50pF
1
tsul(XCLK-CX0 to 11)
CX0 to 11 set up time
for the rise of XCLK
20
ns
tsul(XCLK-PEUPE)
PEUPE set up time for the rise of XCLK
20
ns
tsul(XCLK-SPIX)
SPIX set up time for the rise of XCLK
20
ns
thl(XCLK-CX0 to 11)
CX0 to 11 hold time for the rise of XCLK
20
ns
thl(XCLK-PEUPE)
PEUPE hold time for the rise of XCLK
20
ns
thl(XCLK-SPIX)
SPIX hold time for the rise of XCLK
20
ns
tsut(XCLK-CX0 to 11)
CX0 to 11 set up time
for the rise of XCLK
70
ns
tsut(XCLK-SPIX)
SPIX set up time for the rise of XCLK
70
ns
tht(XCLK-CX0 to 11)
CX0 to 11 hold time for the rise of XCLK
20
ns
tht(XCLK-SPIX)
SPIX hold time for the rise of XCLK
20
ns
tk(XCLK-PEUPE)
PEUPE input define time
for the rise of XCLK
20
ns
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
17. TEST CIRCUIT
1
Input
VCC
Output
VCC
RL=1kΩ
SW1
PG
DUT
SW2
50Ω
GND
CL
RL=1kΩ
Parameter
SW1
SW2
tPLH, tPHL
Open
Open
tPLZ
Close
Open
tPHZ
Open
Close
tPZL
Close
Open
tPZH
Open
Close
(1) characteristic of pulse generation (PG) (10% to 90%)
tr=3ns, tf=3ns
(2) Capacitance CL includes stray wiring capacitance
and probe input capacitance.
Master clock
tci(MCLK)
tcc(MCLK)
twi+(MCLK)
twc+(MCLK)
tfi(MCLK)
tfc(MCLK)
tri(MCLK)
trc(MCLK)
twi-(MCLK)
twc-(MCLK)
90%
90%
MCLK
10%
10%
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
HOST BUS I/F
(1) MPU access
RESET
tw
(RESET)
CS
tsu
(RD-CS)
th
(RD-CS)
tsu
(WR-CS)
th
(WR-CS)
A0 to 3
BHE
tsu
(RD-A0 to 3)
tw(RD)
tsu
(RD-BHE)
th
(RD-A0 to 3)
tsu
(WR-A0 to 3)
th
(WR-A0 to 3)
th
(RD-BHE)
tsu
(WR-BHE)
th
(WR-BHE)
RD
WR
tw(WR)
tPLZ
(RD-D0 to 15)
tPZL
(RD-D0 to 15)
D0 to 15
50%
tPZH
(RD-D0 to 15)
90%
D0 to 15
th
(WR-D0 to 15)
tsu
(WR-D0 to 15)
10%
tPHZ
(RD-D0 to 15)
Input
50%
(2) DMA access
DMARQ
50%
tPHL
(DMAAK-DMARQ)
DMAAK
tsu
(RD-DMAAK)
tw(RD)
th
(RD-DMAAK)
RD
tsu
(WR-DMAAK)
WR
tPZL
(RD-D0 to 15)
10%
D0 to 15
th
(WR-DMAAK)
tPLZ
(RD-D0 to 15)
50%
D0 to 15
tw(WR)
tPZH
(RD-D0 to 15)
90%
50%
tPHZ
(RD-D0 to 15)
tsu
(WR-D0 to 15)
Input
th
(WR-D0 to 15)
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
IMAGE DATA I/F
(1) Serial image data I/F
50%
PRDY
tPLH
(PTIM-PRDY)
PTIM
tc(PXCK)
tsu
(PXCK-PTIM)
tw+(PXCK)
th
(PXCK-PTIM)
tw-(PXCK)
PXCK
tPHL
(PXCK-RXCKO)
tPLH (PXCK-RXCKO)
tPLH (PXCKO-RVID)
PXCKO
tPHL (PXCKO-RVID)
50%
PVID
tPLH
(PTIM-RVID)
tPLH
(PXCK-RVID)
tPHL (PXCK-RVID)
50%
50%
th
(PXCK-SVID)
tsu
(PXCK-SVID)
SVID
(2) Pallarell Image Data
50%
PDRQ
tPHL
(PDAK-PDRQ)
PDAK
tsu
(PDRD-PDAK)
th
(PDRD-PDAK)
tw(PDRD)
PDRD
tsu
(PDWR-PDAK)
tw(PDWR)
th
(PDWR-PDAK)
PDWR
tPZL
(PDRD-PD0 to 31)
tPLZ
(PDRD-PD0 to 31)
50%
PD0 to 31
10%
tPZH
(PDRD-PD0 to 31)
90%
50%
tsu
(PDWR-PD0 to 31)
tPHZ
(PDRD-PD0 to 31)
Input
th
(PDWR-PD0 to 31)
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
CONTEXT I/F
(1) Latch input mode
XRDY
50%
tPLH
(XTIM-XRDY)
XTIM
tsu
(MCLK-XTIM)
MCLK
tPHL
(MCLK-XCLK)
tPLH
(MCLK-XCLK)
XWAIT
th
(XCLK-XTIM)
tc(XCLK)
th
(XCLK-XWAIT)
tw(XCLK)
XCLK
tw+
(XCLK)
tsul
(XCLK-CX0 to 11)
thl
(XCLK-CX0 to 11)
tsul
(XCLK-PEUPE)
thl
(XCLK-PEUPE)
tsul
(XCLK-SPIX)
thl
(XCLK-SPIX)
CX0 to 11
PEUPE
SPIX
tPHL
(XCLK-SPIX)
RPIX
50%
tPLH
(XCLK-SPIX)
50%
MITSUBISHI ICs (LSI)
M65761FP
QM-CODER
(2) Through input mode
XRDY
50%
tPLH
(XTIM-XRDY)
XTIM
tsu
(MCLK-XTIM)
MCLK
tPHL
(MCLK-XCLK)
tPLH
(MCLK-XCLK)
XWAIT
tc(XCLK)
th
(XCLK-XWAIT)
tw(XCLK)
th
(XCLK-XTIM)
XCLK
tw+
(XCLK)
tsut
(XCLK-CX0 to 11)
tht
(XCLK-CX0 to 11)
tsut
(XCLK-SPIX)
tht
(XCLK-SPIX)
CX0 to 11
SPIX
tk
(XCLK-PEUPE)
PEUPE
tPLH
(XCLK-RPIX)
RPIX
50%
tPHL
(XCLK-RPIX)
50%