RENESAS M65762FP

M65762FP
QM-Coder
REJ03F0235-0200
Rev.2.00
Sep 14, 2007
Description
The M65762FP is a compression and decompression LSI conforming to the high efficiency encoding system (QMCoder) in the International Standard, the JBIG/JPEG (ITU-T Recommendations T.81 and T.82) for coding still images.
It also conforms to the International Standard (ITU-T Recommendation T.85) for facsimile.
The QM-Coder is an information dependent type which is capable of completely restoring original image data, and is
equipped with the learning function to always optimize parameters according to the statistical characteristics of images.
The QM-Coder is therefore superior in compression ratio compared with the existing binary coding system
(MH/MR/MMR) and can greatly improve the half toning image (dithered half toning image) whose compression ratio is
especially poor.
Features
• Completely conforms to the International Standard (ITU-T T.85) for facsimile.
• Achieves encoding/decoding with the arithmetic coder (QM-Coder) conforming to the recommendation of the
International Standard JBIG/JPEG.
• Is expected to conform to the International Standard for color facsimile (T. Palette-colour).
• High speed processing that puts into effect coding and decoding at 40 million pixels per second maximum.
• Is possible data-through processing without coding and decoding.
• Can select context
 Provides 10 pixel template model for minimum resolution conforming to JBIG and can select 2-line or 3-line
template model.
• Built-in typical prediction function
 Capable of coding and decoding by using the typical prediction.
 Since use of the typical prediction does not require the processing of the line (TP line) which is matched the
previous line's data, is capable of reducing data and processing time.
• Built-in adaptive template (AT) function
 Is capable of setting AT pixels before 127 pixels on the coding line.
 Since it is possible to change the position of AT pixel in a specified line, is capable of improving compression
characteristics even when image characteristic is changed in the middle of the screen.
• Supporting multi-stripe
 When a page consists of more than one stripe, is capable of repeating encoding/decoding process in stripes.
• Built-in load/store function of line memory → Supporting multiple planes and multi-stripe function
 Is capable of loading image data for reference line from outside to line memory of the LSI and storing image
data from line memory to outside.
• Number of processing lines
 Is capable of issuing the start of processing (temporary stop command) several times to encode/decode any lines
more than or equal to 65535 lines.
• Supporting 3-bus interface
 An 8-bit host bus corresponds to the MPU is available to load and store of context table RAM.
 For input/output of binary image data, is capable of performing 32-bit or 16-bit parallel or serial input/output.
 For input/output of coding data, is capable of selecting 32-bit /16-bit/8-bit bus to perform DMA transfer of
coding data.
• Is capable of making scale-down for coding and scale-up for decoding.
• Is capable of setting marker code for coding and detecting marker code for decoding
• Built-in RAM for 4096 bytes for line memory, built-in context table RAM and built-in probability estimation table
ROM of 113 status
• +5 V single power supply
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M65762FP
Application
• OA equipment including facsimile, copier and printer
• Digital and amusement equipment for the purpose of reducing memory
Block Diagram
55
PXCK*
56
PXCKO*
59
SVID*
57
RVID*
Pixel data
58
Code data I/F
Context table RAM
Context generation
108
CDRQ
109
CDAK*
110
CDRD*
111
CDWR*
132
RESET*
135
HCS*
HA0 to 3
Host bus I/F
54
PTIM*
Probability estimation table ROM
PRDY*
Typical prediction
51
Line memory
PDWR*
50
Image data I/F
PDRD*
49
Parallel I/F
PDAK*
48
Serial I/F
PDRQ
Encoding/decoding
CD0 to 31
PD0 to 31
134
HWR*
133
HRD*
HD0 to 7
112
INTR
129
MCLK
(Asterisk "*" indicates negative logic.)
Description on Block Functions
(1) Host bus I/F block
This bus is used to set command parameters and load the status between the MPU and this block. It is 8-bit bus.
This block is also available to load and store of context table RAM via the host bus.
(2) Code data I/F block
Bus for input/output of coding data. For the bus width, 32 bits, 16 bits or 8 bits can be selected.
Image data can also be transferred (in through mode) between the image data I/F and this block via built-in line
memory. FIFO buffer for 16 bytes are provided in the code data I/F block.
(3) Image data I/F block
The Image data I/F is used for input/output of binary image data. The 32-/16-bit parallel I/F or serial I/F can be
selected. Selection of the serial I/F transfers data in units of 1 pixel in synchronization with the line, using the
handshake signal (PRDY*, PTIM*).
Selection of parallel I/F uses an external DMA controller for DMA transfer (in units of stripe).
The image data I/F provides a function for scale-down of length and breadth by 1/2 in coding and a function for
scale-up of length and breadth by twice in decoding.
(4) Line memory block
4 K-byte memory. This block can be set to a maximum of 8192 pixels/line for 3-line template and can be set to a
maximum of 10240 pixels/line for 2-line template. A line is used for input/output processing of image data to/from
outside and the other lines (2 or 3 lines) are used for encoding/decoding processing. These two processes can be
independently carried out in synchronization with each line.
The contents of line memory can be loaded or stored via the image data I/F or coding data I/F.
(5) Typical prediction block
In the typical prediction mode, compares the encoding/decoding process line agree with the immediately preceding
line and generates pseudo-pixel (SLNTP).
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M65762FP
(6) Context generator
By using the 10-pixel template of 2-lines or 3-lines, (including AT pixel) the standard context minimum of JBIG is
generated with the resolution.
(7) Context table RAM block
Corresponds to the 10-bit standard context. This block can initialize, load and store the context table RAM.
(8) Coding/decoding block
This block performs arithmetic coding and decoding.
It contains a ROM which contains a table capable of estimating 113 states and is capable of byte stuffing function
('OO' byte insertion/rejection) and is capable of end marker code control (Marker insertion/detection).
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M65762FP
73 GND
74 CD8
75 CD9
76 CD10
77 CD11
78 CD12
79 VDD
80 GND
81 CD13
82 CD14
83 CD15
84 CD16
85 CD17
86 VDD
87 GND
88 CD18
89 CD19
90 CD20
91 CD21
92 CD22
93 VDD
94 GND
95 CD23
96 CD24
97 CD25
98 CD26
99 CD27
100 VDD
101 GND
102 CD28
103 CD29
104 CD30
105 CD31
106 VDD
107 GND
108 CDRQ
Pin Arrangement
CDAK 109
72
VDD
CDRD 110
71
CD7
CDWR 111
70
CD6
INTR 112
69
CD5
VDD 113
68
CD4
GND 114
67
GND
HD0 115
66
VDD
HD1 116
65
CD3
HD2 117
64
CD2
HD3 118
63
CD1
HD4 119
62
CD0
VDD 120
61
GND
GND 121
60
VDD
HD5 122
59
PXCKO
HD6 123
58
RVID
HD7 124
57
SVID
TEST0 125
56
PXCK
55
PTIM
VDD 127
54
PRDY
GND 128
53
GND
MCLK 129
52
VDD
VDD 130
51
PDWR
GND 131
50
PDRD
RESET 132
49
PDAK
HRD 133
48
PDRQ
HWR 134
47
GND
HCS 135
46
VDD
VDD 136
45
PD31
GND 137
44
PD30
HA0 138
43
PD29
HA1 139
42
GND
HA2 140
41
VDD
HA3 141
40
PD28
TOUT1 142
39
PD27
TOUT2 143
38
PD26
VDD 144
37
PD25
M65762FP
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PD15
PD16
PD17
PD18
PD19
VDD
GND
PD20
PD21
PD22
PD23
PD24
VDD
GND
15
GND
22
14
VDD
GND
13
PD9
21
12
PD8
VDD
11
PD7
20
10
PD6
PD14
9
PD5
19
8
GND
PD13
7
VDD
18
6
PD4
PD12
5
PD3
17
4
PD2
PD11
3
PD1
16
2
PD0
PD10
1
GND
TEST1 126
(Top view)
Outline: PLQP0144KA-A (144P6Q-A)
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M65762FP
Pin Description
Pin No.
I/O
1
Power supply
Pin Name
GND
Pin No.
I/O
51
I
Pin Name
PDWR
Pin No.
I/O
101
Power supply
Pin Name
GND
2
I/O
PD0
52
Power supply
VDD
102
I/O
CD28
3
I/O
PD1
53
Power supply
GND
103
I/O
CD29
4
I/O
PD2
54
O
PRDY
104
I/O
CD30
5
I/O
PD3
55
I
PTIM
105
I/O
6
I/O
PD4
56
I
PXCK
106
Power supply
7
Power supply
VDD
57
I
SVID
107
Power supply
8
Power supply
GND
58
O
RVID
108
O
CDRQ
CD31
VDD
GND
9
I/O
PD5
59
O
PXCKO
109
I
CDAK
10
I/O
PD6
60
Power supply
VDD
110
I
CDRD
11
I/O
PD7
61
Power supply
GND
111
I
CDWR
12
I/O
PD8
62
I/O
CD0
112
O
13
I/O
PD9
63
I/O
CD1
113
Power supply
VDD
14
Power supply
VDD
64
I/O
CD2
114
Power supply
GND
15
Power supply
GND
65
I/O
CD3
115
I/O
HD0
16
I/O
PD10
66
Power supply
VDD
116
I/O
HD1
17
I/O
PD11
67
Power supply
GND
117
I/O
HD2
18
I/O
PD12
68
I/O
CD4
118
I/O
HD3
19
I/O
PD13
69
I/O
CD5
119
I/O
HD4
20
I/O
PD14
70
I/O
CD6
120
Power supply
VDD
GND
INTR
21
Power supply
VDD
71
I/O
CD7
121
Power supply
22
Power supply
GND
72
Power supply
VDD
122
I/O
HD5
23
I/O
PD15
73
Power supply
GND
123
I/O
HD6
24
I/O
PD16
74
I/O
CD8
124
I/O
HD7
25
I/O
PD17
75
I/O
CD9
125
I
TEST0
26
I/O
PD18
76
I/O
CD10
126
I
TEST1
27
I/O
PD19
77
I/O
CD11
127
Power supply
VDD
28
Power supply
VDD
78
I/O
CD12
128
Power supply
GND
29
Power supply
GND
79
Power supply
VDD
129
I
30
I/O
PD20
80
Power supply
GND
130
Power supply
VDD
31
I/O
PD21
81
I/O
CD13
131
Power supply
GND
32
I/O
PD22
82
I/O
CD14
132
I
RESET
33
I/O
PD23
83
I/O
CD15
133
I
HRD
34
I/O
PD24
84
I/O
CD16
134
I
HWR
35
Power supply
VDD
85
I/O
CD17
135
I
HCS
36
Power supply
GND
86
Power supply
VDD
136
Power supply
VDD
37
I/O
PD25
87
Power supply
GND
137
Power supply
GND
38
I/O
PD26
88
I/O
CD18
138
I
HA0
39
I/O
PD27
89
I/O
CD19
139
I
HA1
40
I/O
PD28
90
I/O
CD20
140
I
HA2
41
Power supply
VDD
91
I/O
CD21
141
I
HA3
42
Power supply
GND
92
I/O
CD22
142
O
TOUT1
43
I/O
PD29
93
Power supply
VDD
143
O
44
I/O
PD30
94
Power supply
GND
144
Power supply
CD23
45
I/O
PD31
95
I/O
46
Power supply
VDD
96
I/O
CD24
47
Power supply
GND
97
I/O
CD25
48
O
PDRQ
98
I/O
CD26
49
I
PDAK
99
I/O
50
I
PDRD
100
Power supply
MCLK
TOUT2
VDD
CD27
VDD
Notes: 1. Directly connect the input pin having pull-up (see "Description on Pin Functions") to VCC when the pin is not
used.
2. Directly connect the input pin having pull-down (see "Description on Pin Functions") to GND when the pin is
not used.
3. Connect test input pin TEST 0/1 to GND.
4. Leave test output pin TOUT 1/2 open.
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
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M65762FP
Description on Pin Functions
(Asterisk "*" in signal name indicates negative logic.)
I/F
Host bus I/F
Pin Name
RESET*
HCS*
HA0 to 3
HWR*
HRD*
HD0 to 7
INTR
I/O
I
I
I
I
I
I
O
BUF
S
CD0 to 31
I/O
UR8
CDRQ
CDAK*
CDRD*
CDWR
O
I
I
I
4
US
US
US
Coding data input/output bus signal
(CD0 to 15 is used in 16-bit bus and CD0 to 7 is used in 8-bit bus.)
DMA request signal for coding data (image data)
DMA acknowledge signal for coding data (image data)
Read strobe signal for coding data (image data)
Write strobe signal for coding data (image data)
Parallel
PD0 to 31
PDRQ
PDAK*
PDRD*
PDWR*
I/O
O
I
I
I
UR8
4
US
US
US
Parallel image data input/output bus (PD0 to 15 is used in 16-bit bus.)
DMA request signal for image data
DMA acknowledge signal for image data
Read strobe signal for image data
Strobe signal for image data
Serial
PRDY*
PTIM*
PXCK*
PXCKO*
O
I
I
O
4
US
US
4
SVID*
RVID*
MCLK
TEST0, 1
I
O
I
I
U
4
1-line input/output start ready signal for image data
1-line transfer sector signal for image data
Transfer clock signal for image data
Transfer clock signal for image data
(LSI internal loop back output signal of PXCK*)
Image data input signal
Image data output signal
DS
Master clock input signal
Test input signal 0/1
(Should be connected to GND when used normally.)
VDD
GND
—
—
—
—
Power supply (+5 V)
Ground
Code data I/F
Image
data
I/F
Others
Note:
S
S
R8
4
Function
H/W reset signal
Chip select signal
Address select signal of internal register
Write strobe signal
Read strobe signal
Input/output data bus signal
Interrupt request signal
Input buffer for the input pins ("I" and "IO") are set at the TTL level and the options are as follows.
(U: Having pull-up resistance, D: Having pull-down resistance, S: Schmitt trigger, R: Through rate control)
Numbers (4, 8) in the BUF column for the output pins ("O" and "IO") indicate Io (= 4 or 8 mA).
Specifications
(1) Package
Plastic QFP 144 pins (20 mm × 20 mm)
(2) Power consumption
5 V, 120 mA (600 mW)
(3) Maximum clock frequency
40 MHz
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M65762FP
Specifications of Coding Functions
(1) Coding algorithm
• QM-Coder (JBIG standard arithmetic coding system)
(2) Context
a) Template model
• 2- or 3-line of 10-pixel template (see figure 1)
(Conforming to the template for JBIG minimum resolution)
Note: The coding efficiency of the 3-line template is better than that of 2-line template by several %.
b) Adaptive template (AT)
• It is possible to move up to 127 pixels on the coding line.
(AT position is indicated by MPU.)
Note: AT is available to improve the coding efficiency for dither image.
• Even in the middle of coding/decoding, the position of AT line can be changed for a line (AT move)
Note: When the position the AT pixel of is changed, the template model cannot be changed concurrently.
X
X
X
X
X
X
X
X
X
X
?
X
X
A
X
X
X
X
X
?
X
A
Figure 1 Template (X, A) (Upper: 3 lines, Lower: 2 lines)
X
X
A
X
X
X
X
X
?
X
X
MAX127
A
X
X
X
X
X
X
X
X
?
X
MAX127
Figure 2 Adaptive Template (A)
(3) Typical prediction
• Agreement with the typical prediction of the minimum resolution of JBIG.
The pseudo-pixel (SLNTP) is generated by the symbol LNTP which shows whether the coding/decoding
process lines agree with the immediately preceding line. If they agree, the pseudo-pixel only is coded. This
makes it possible to shorten the time of process and rejection of the code data.
SLNTPy = ! (LNTPy ⊕ LNTPy – 1)
(Where: y indicates a lien No., y = 1 indicates that lines do not match each other, and initial value LNTP for
head line is given with y – 1 = 1)
(4) Coding data format
• The stripe data entity.
(SDE = stripe coded data with byte stuffing (PSCD) + end marker (SDNORM/SDRST))
Performs coding and decoding of one stripe (see "Appendix A.1")
In the case of multi-striped (multi-stripes), can be supported by activation for each stripe.
(5) Marker code
• Supports the SDE end marker
(During coding, the marker code previously set in the register is outputted. During decoding, the marker
code byte detected by requesting on interrupt to MPU when the maker is detected is read out of the register.)
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M65762FP
(6) Estimation of coding/decoding speed
Figure 3 compares the estimation of coding/decoding speed between the M65762FP and the existing product type
(M65760/1FP). Polygonal lines in the diagram are processing speeds of images theoretically generated assuming
the unmatched estimation ratio as a parameter. In addition, {…∆ indicate processing speeds of real image (without
TP function).
As shown in this diagram, the M65762FP has been largely improved in the processing speed compared with existing
product types. If the compression ratio is reduced, the reduction ratio of processing speed is moderated.
When a theoretical image is used to compare processing speeds in the worst case, the processing speed of existing
product type is about 9.4 M pixels/s (1 / compression ratio ≈ is about 1), while the processing speed of the
M65762FP is about 27.5 M pixels/s (1 / compression ratio ≈ 0.9) for coding and is about 31.2 M pixels/s (1 /
compression ratio ≈ 0.75) for decoding.
20
Coding/decoding of
existing product
type (M65760/1FP)
15
Cafeteria, error diffusion image
25
Coding of
M65762FP
Baud rate, error diffusion image
Processing Speed (M pixels/s)
30
Decoding of M65762FP
Cafeteria and dither images
35
Baud rate and dither images
Average of test charts 1 to 8 of former CCITT
40
10
(Legend)
Theoretical
image
Actual
image
Decoding of M65762FP
5
Coding of M65762FP
Coding/decoding of existing
product type
0
0
0.25
0.5
0.75
1 / Compression Ratio
Figure 3 Estimated Processing Speed
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1.0
1.2
M65762FP
Register Configuration
1. List of Registers
Table 1
Address
List of Registers
Register Name
R/W
0
System setting
W/R
1
Parameter setting
W/R
2
Command
2
Status
3
Interrupt enable setting
W
R
W/R
Content
•
•
•
•
•
•
•
•
•
LSI H/W reset
Selects bit width of code data bus (32 bits/16 bits/8 bits)
Selects coding (image) data byte swap on code data bus
Selects coding (image) data bit swap on code data bus
Selects image data bit swap on image data bus
Selects image data I/F (parallel I/F and serial I/F)
Selects bit width of image data bus (32 bits/16 bits)
Template selection (3-line template/2-line template)
Sets up the AT pixel position (127 max)
(When set to 0, selects non-AT (default position))
• Context table RAM initializing processing command
• Start/stop command
•
•
•
•
•
•
•
•
•
•
(Coding/decoding, image data through, load/store of the line memory)
Start/stop command of load/store of context table RAM
Selects temporary stop/termination end mode
Processing status (in process/end of process)
Ready for reading/writing coding (image) data on code data bus
Detects marker code (SDNORM, SDRST, ABORT, etc)
Interrupt request status
SC counter overflow error
Processing mode (temporary stop/end of termination)
Interrupt enable setting corresponding to each bit position of status
register
Indicates pause/restart with marker code detected
(at time of decoding)
Sets the number of pixels per line
(a maximum of 10240 pixels with 2-line template selected)
4, 5
Setting number of
pixels
W/R
•
6, 7
Setting number of lines
W/R
• Sets the number of lines to be coded/decoded
8, 9
Number of processing
lines
R
A
Load/store buffer
(1 line or more, a maximum of 65535 lines)
B
Operation mode setting
• Number of setting the coded/decoded lines
(a maximum of 65535 lines)
W/R
W/R
• Buffer register that loads/stores context table RAM data from the
•
•
C
C
Marker code setting
Marker code reading
W
R
MPU
(RAM address is automatically incremented each time data is
written/read.)
Sets the operation mode
(Coding/decoding, image data through, and load/store of line
memory)
Selects read-through of head coding data in decoding
(0 to 3 bytes)
Selects the typical prediction function
Selects prohibition of line memory initialization
•
•
• Sets the terminal marker code in encoding (SDNORM/SDRST)
• Reads a marker code in decoding
(SDNORM, SDRST, ABORT, others)
D
Scale-up/scale-down
setting
W/R
• Scale down in coding
(1/2 scale-down of horizontal and vertical, horizontal OR processing)
• Scale-up at time of decoding
(scale-up of horizontal and vertical by twice)
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M65762FP
2. Description on Register
(1) System setting register (W/R)
(Address: 0)
SYS_REG:
d0 (HR):
d7(MSB)
PB
PI
BX
BS
DS
d0 (LSB)
HR
CB
H/W reset (0: Active status, 1: Reset status)
To reset H/W, set this bit to 1 then to 0. The entire LSI including register group and line memory is
initialized by writing in this reset. However, context table RAM is not initialized.
d1 to 2 (CB):
Selects the bit width of code data bus
(d2 = 0, d1 = 0: 8-bit bus (CD0 to 7), d2 = 0, d1 = 1: 16-bit bus (CD0 to 15), d2 = 1, d1 = 0: 32-bit bus
(CD0 to 31))
d3 (DS):
Notes: 1. Prohibition of setting for d2 = 1, d1 = 1
2. For encoding in 16-/32-bit bus, the last encoding data is output followed by bit byte of "00"
(3 bytes maximum) for word alignment of encoding data at the end.
Selects data bit swap of image data bus (0: MSB first, 1: LSB first) → see table 3.
d4 (BS):
Selection of data bit swap of code data bus (0: MSB first, 1: LSB first) → see table 2.
d5 (BX):
Selection of data byte swap of code data bus
(0: low order byte first, 1: high order byte first) → see table 2.
Note: BX is effective only when the host bus selects 16-bit/32-bit bus.
Selection of image data input/output I/F (0: serial I/F, 1: parallel I/F)
d6 (PI):
d7 (PB):
Selection of bit width of image data bus
(0: 32-bit bus (PD0 to 31), 1: 16-bit bus (PD0 to 15) → see table 3.
Note: PB and DS are effective only when PI = 1.
Table 2
Line Up of Coded Data/Image Data in Code Data Bus
Bus Width
(CB)
Swap
(BX, BS)
d2
d1
1
0
(32 bits)
d5
0
0
1
d4
0
1
0
CD31
b24
b31
b0
•••
•••
•••
•••
CD24
b31
b24
b7
CD23
b16
b23
b8
•••
•••
•••
•••
CD16
b23
b16
b15
CD15
b8
b15
b16
•••
•••
•••
•••
CD8
b15
b8
b23
CD7
b0
b7
b24
•••
•••
•••
•••
CD0
b7
b0
b31
1
0
0
1
1
0
1
0
b7
•••
—
—
—
b0
b15
•••
—
—
—
b8
b23
b8
b15
b0
•••
•••
•••
•••
b16
b15
b8
b7
b31
b0
b7
b8
•••
•••
•••
•••
b24
b7
b0
b15
1
—
—
1
0
1
b7
•••
—
—
b0
b15
b0
b7
•••
•••
•••
b8
b7
b0
0
1
(16 bits)
0
0
(8 bits)
Note:
—
—
—
—
—
—
b0 is image data, given in time series, on the left side of the first encoding data/screen. b31 is image data, given
in time series, on the right side of the last encoding data/screen.
Table 3
Bit Width
Order of Image Data on Image Data Parallel Bus
Swap
PB = 0
DS = 0
DS = 1
PB = 1
DS = 0
DS = 1
Note:
Order of Data in Code Data Bus (CD)
PD31
•••••
PD16
PD15
•••••
PD0
p0
p31
•••••
•••••
p15
p16
p16
p15
•••••
•••••
p31
p0
p0
p15
•••••
•••••
p15
p0
—
—
p0 is image data on the left side of the screen. p31 is image data on the right side of the screen.
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M65762FP
(2) Parameter setting register (W/R)
(Address: 1)
PARA_REG:
d7
d6
d5
TM
AT
d4
d0
AT
d0 to 4 (AT<0> to AT<4>):
Low order 5 bits of AT pixel position (see figure 2)
d5 (TM):
Selection of template (0: 3-line template, 1: 2-line template)
d6 to 7 (AT<5> to AT<6>):
High-order 2 bits of AT pixel position (6th/7th bit)
(Example)
3-line template, AT = 4
2-line template, AT = 48
Note:
d7
d4
d0
0
0
0
0
0
1
0
0
0
1
1
1
0
0
0
0
AT pixel position is set (0 to 127) with AT<6:0>. At the default position (AT pixel is not used), set AT = 0. The 2line template, prohibits AT = 1 to 4 from being set. The 3-line template prohibits AT = 1 to 2 from being set.
(3) Command register (W)
(Address: 2)
CMD_REG:
d0 (IC):
d7
0
d3
JP
RC
JC
d0
IC
Context table RAM initialization start command (1: Start initialization)
Setting this bit to 1 starts to initialize context table RAM.
When the initialization is completed automatically returns this bit to 0.
d1 (JC):
Processing (coding/decoding/through) start/end command (1: Start of processing, 0: End of processing)
Setting this bit to 1 starts processing (coding/decoding, image data through and lead/store of line
memory).
Before the issuance of this command, concrete operation mode must be set in the operation mode setup
register.
When the processing for the number of setup lines ends with the end of termination selected this bit
automatically returns to 0.
d2 (RC):
Note: When this JC bit is set to 0 during the coding process (is in progress,) and input of image data is
stopped, the coding is stopped (flashed) even if the set lines are not filled. When this bit is set to
0 during decoding process, and input of encoding data ceases, processing for the number of
setup lines is carried out assuming coding data "00" to have been input. In the case of multistripe coding, however, process must not be stopped by setting this bit to 0 except for the final
stripe.
Load/store start/end command of context table RAM (1: Start of load/store, 0: End of load/store)
Setting this bit to 1 can load context data into context table RAM from outside via a buffer register or
can store context data in outside. (see the section for buffer register.)
When load/store processing is completed, this bit must be set to 0.
d3 (JP):
Temporary stop mode of processing (coding/decoding/through)/termination end mode selection
(1: Selection of temporary stop, 0: Selection of termination end)
Issuance of processing start command d1 (JC) with this JP bit set to 1 temporarily stops performing the
process operation at the completion of processing for the number of setup lines. After that, reissuance of
processing start command d1 (JC) restarts processing. (see " Register Setting Sequence" (3))
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M65762FP
(4) Status register (R)
(Address: 2)
STAT_REG:
d0 (JS):
d7
0
d5
PS
SC
IS
MS
DS
d0
JS
Processing (initialization/coding/decoding/through) status
(0: Processing in progress (temporary stop or initial), 1: Completion of processing)
This JS bit is set to 1 in the following cases: when the initialization is complete with the RAM
initialization command issued (IC = 1), when all coding data is read completely at time of coding with
the start command of termination end processing issued (JC = 1, JP = 0), and when all image data is read
completely at time of image data through and at time of decoding. When the temporary stop processing
start command is issued (JC = 1, JP = 1), this JS bit remains to be 0, even if the process for the number
of setup lines ends. (However, an interruption occurs at time of temporary stop.)
d1 (DS):
Ready for reading/writing coding data (image data case of the through mode) on the code data bus
(1: Ready, 0: Read/write disabled)
When this bit is set to 1, data can be read/written on the code data bus. (This bit is equivalent to the
CDRQ pin.)
d2 (MS):
Detects marker code at time of decoding (0: Not detected, 1: Detected)
This bit is set to 1 when some marker code is detected at time of decoding.
d3 (IS):
Status of interrupt request (INTR pin) (0: Not requested, 1: Requested)
d4 (SC):
SC count-over error at time of coding (0: Normal, 1: Occurrence of SC counter overflow)
Note: The SC counter is a counter for consecutive "FF" data bytes generated in the coding process.
Though coding process continues if the SC counter overflows, normal coding data is not output
(encoding error).
d5 (PS):
Processing (temporary stop/termination end) mode
(1: Temporary stop processing mode, 0: Termination end processing mode)
This PS bit corresponds to the selection of process temporary stop/termination end of the d3 (JP) bit of
command register.
(5) Interrupt enable register (W/R)
(Address: 3)
IENB_REG:
d0 (JE):
d7
MP
0
d3
SE
ME
DE
d0
JE
Processing (initialization/coding/decoding/through)
Temporary stop/termination end interrupt (0: Interrupt mask, 1: Interrupt enable)
d1 (DE):
Coding data (image data) read/write ready interrupt (0: Interrupt mask, 1: Interrupt enable)
d2 (ME):
Marker code detection interrupt at time of decoding (0: Interrupt mask, 1: Interrupt enable)
d3 (SE):
SC count-over error interrupt at time of coding (0: Interrupt mask, 1: Interrupt enable)
Note: Bits d0 to d3 are interrupt enable of bits d0 to d2 and d4 corresponding to the status register.
When one of the status bits set to interrupt enable is set to 1, the interrupt request signal (INTR)
is asserted (for d0 (JE), an interrupt occurs even at the time of temporary stop).
When the status is set to 0 by H/W reset etc., or when interrupt factor is eliminated by
interruption masking, INTR is negated. The status register is not cleared by occurrence of
interruption or by R/W of interruption enable register.
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M65762FP
d7 (MP):
Indication of pause at time of marker code detection
(0: Indication of continuation/restart, 1: Indication of temporary pause)
If this MP bit is in advance set to 1 in decoding, the decoding temporarily pauses at the time of marker
code detected.
(When the ME bit is set to 1, an interruption occurs when marker code is detected.)
When decoding process is not completed at time of temporary pause of marker detection, the register for
setting the number of lines can be respecified (see item (7)). Afterwards, setting this MP bit to 0 restarts
the decoding process (the decoding process is carried out for the number of set lines).
(6) Register for setting the number of pixels (W/R)
(Address: 4)
PEL_REG_L:
d7
d0
PEL_L
(Address: 5)
PEL_REG_H:
0
d7
PEL_H
d5
d0
d0 to 7 (PEL_L):
Sets the number of pixels in a line. (Low byte)
d0 to 5 (PEL_H):
Sets the number of pixels in a line. (Upper byte)
A maximum of 8192 pixels can be set at the 3-line template. A maximum of 10240 pixels
can be set at the 2-line template.
Set the number of pixels to be actually coded (decoded) at time of scale-up (scale-down).
When the image data bus is 16 bits (32 bits) with the parallel I/F selected, set the number of
pixels to multiples of 16 (multiples of 32).
With the serial I/F selected, set the number of pixels to multiples of 8.
(7) Register for setting the number of lines (W/R)
(Address: 6)
d7
d0
LSET_REG_L:
(Address: 7)
LSET_L
LSET_REG_H:
LSET_H
d0 to 7 (LSET_L):
Sets the number of lines to be processed. (Low order byte) (1 to 65535: 0 line is not allowed.)
d0 to 7 (LSET_H):
Sets the number of lines to be processed. (High order byte)
At time of scale-down (scale-up), set the number of lines to be actually coded (decoded).
Set the number of lines (number of relative lines) ranging from the processing start command
to be issued next to the temporary stop/termination end just after. This register must be set to
a specific value before the issuance of the process start command.
As far as the following conditions are satisfied, this register can be rewritten in the course of
processing.
• When the maximum value (65535) is set before issuance of the processing start command,
an arbitrary value can be set once in the course of processing.
• When a value except for the maximum value (65535) is set before issuance of the
processing start command, and the value requires to be respecified in the course, respecify
the maximum value (65535) once and then respecify a desired value.
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M65762FP
(8) Processing line count register (R)
(Address: 8)
LIN_REG_L:
d7
d0
LINE_L
(Address: 9)
LIN_REG_H:
LINE_H
d0 to 7 (LINE_L):
Read out the number of lines actually processed (Low byte) (0 to 65535)
d0 to 7 (LINE_H):
Read out the number of lines actually processed (Upper byte)
The number of processed lines number of set lines, coding/decoding/through processing stop
temporary/end of processing.
Note: The number of lines in this process is cleared to 0 with the processing start command
issued.
(9) Buffer register (W/R)
(Address: A)
d7
d0
DWR_BUF:
d0 to 7 (DWR):
DWR
Data for loading/storing context table RAM
This register is a buffer for loading data into the context table RAM via the host bus or for
storing data outside. After issuance of load/store start command of the context table RAM
(command register d3 = 1), this register is available to start loading or storing data. Prediction
value (MPS) and prediction unmatched probability (LSZ) can be stored in context table RAM
for a unit of 1024 contexts in total. Figure 4 and table 4 provide the address assignment of
context table RAM and the data bit array.
Since context table RAM is 2-byte data, access is gained alternately in order from low byte to
upper byte. Each time two-byte access is gained, the RAM address is automatically
incremented (sequential access from address 0).
Notes: 1. Data is not allowed to be loaded and stored at a time. Random access to RAM is
not allowed.
2. Only 133 types specified by the JBIG international standard (see " Appendix A.2")
are allowed to be specified for the LSZ value. (For example, load '5a1d' for
initialization.)
8 7 6
5 4 3 2 9
1 0 ?
8 5 4 3 2 9
7 6 1 0 ?
3-line template
2-line template
Figure 4 Address Assignment of Context Table RAM
(Number for Address Bit (LSB: 0, MSB: 9), MSB: 9 for AT Pixel)
Table 4
Data Bit Array of Context Table RAM
High Order Byte
d15
MPS
Note:
d14
L14
•••••
•••••
Low Order Byte
d8
L8
d7
L7
MPS: Prediction value MPS (0/1)
L14 to 0: Low 15 bits of prediction unmatched probability LSZ ('0001' to '5b12')
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
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•••••
•••••
d0
L0
M65762FP
(10) Operation mode setting register (W/R)
(Address: B)
MOD_REG:
d7
d0
TP
LI
OB
LIO
MOD
This register is used to set the LSI operation mode and requires to be set before issuance of the processing start
command (command register d1 (JC) = 1).
d0, 1 (MOD):
Operation mode setting
(d1 = 0, d0 = 0: Coding, d1 = 1, d0 = 0: Image data through (image data I/F → Code data I/F)
load/store, d1 = 0, d0 = 1: Decoding, d1 = 1, d0 = 1: Image data through (Code data I/F → Image
data I/F) load/store)
d2, 3 (LIO):
Load/store selection of image data of line memory (d2 = selection of load, d3 = selection of store)
In the case of multi-stripe, this LIO bit is set according to the following table, to load image data
for reference line from outside into line memory before coding/decoding of stripes or to store
image data stored in line memory into outside after encoding/decoding of stripes. This LIO bit is
effective only in the image data through mode (d1 = 1).
Notes: 1. LIO (d3, d2) = (1, 1) not allowed being set.
2. When selection of load/store of image data of line memory, temporary stop (d3 (JP) = 1
of command register) is not allowed to be set.
3. When load/store mode of image data is selected, the number of lines to be transferred
must be set in the register setting the number of lines.
4. The number of lines for image data load to line memory must be 2-line either case of 2line template or 3-line template. (This is because typical prediction (LNTP) cannot be
judged correctly with only a line.)
Table 5
Operation Mode List
Operation
Mode (d1, d0)
Load/Store
LIO (d3, d2)
Operation Mode
Remarks
0
0
0
1
X
X
X
X
Coding mode
Normal coding mode
Decoding mode
Normal decoding mode
1
0
0
0
0
1
Image data through (image data I/F → code data I/F)
For inter-I/F transfer of image data
Image data load to line memory (input from image data I/F)
For loading of reference line to LSI
1
0
0
0
Image data store of line memory (output to code data I/F)
For storing line memory to outside
Image data through (code data I/F → image data I/F)
For inter-I/F transfer of image data
0
1
1
0
Image data load to line memory (input from code data I/F)
For loading of reference line to LSI
Image data store of line memory (output to image data I/F)
For storing line memory to outside
1
1
d4, 5 (OB):
Sets head of the coding data read-through at time of decoding
(0 to 3: Sets the number of read-through bytes. For example, with d4 = 0 and d5 = 1, read-through
of 2 bytes)
When OB is set to 1 to 3 at time of decoding, and the first stripe decoding processing start
command is issued, the head data for the number of set bytes is to be read through (not used for
decoding process). With OB set to 0, no data is read through (normal decoding process).
For example, if the code data bus is 32/16 bits, and the head of coding data does not contact the
word boundary, this function is used.
Note: When the code data bus is 8 bits, this function is effective.
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
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M65762FP
d6 (LI):
Prohibition of line memory initialization
(0: Indication of initialization, 1: Prohibition of initialization)
When first stripe coding/decoding process start command is issued, and LI = 1, initialization of
built-in line memory is prohibited.
(The final image data, coded/decoded just before, that is left in line memory is used as the
reference line data at the head of next coding/decoding operation). With LI = 0, built-in line
memory is initialized. (Full white (0) data is used as the reference line data at the head of next
coding/decoding operation.)
When the previous stripe is terminated at the SDNORM marker with coding/decoding of the multistripe configuration, this bit is set to initialization prohibition (1) to make the data of previous
stripe left in line memory available as the coding reference line data of the next stripe. (For details,
see " Register Setting Sequence " (6) sequence.)
d7 (TP):
Note: With LI =1, this LI bit is cleared (to 0) by H/W reset writing to an external reset pin or
system setup register. At the same time, built-in line memory is also initialized.
Selection of typical prediction at time of coding/decoding
(0: Sets typical prediction function to OFF, 1: Sets typical prediction function to ON.)
This bit is set to 1 when encoding/decoding process is carried out using the typical prediction
function.
(11) Marker code set up register (W)
(Address: C)
d7
MSET_REG:
d0 to 7 (MSET):
d0
MSET
The end marker code used during coding is set (SDNORM = 02h, SDRST = 03h, etc.)
The byte set to this register is output attached to coding data as the end marker during coding.
(12) Marker code read out register (R)
(Address: C)
MDET_REG:
d7
d0
d0 to 7 (MDET):
Reads out the marker code detected during decoding
(SDNORM = 02h, SDRST = 03h, ABORT = 04h, etc.)
MDET
Marker code bytes detected at time of decoding can be read directly.
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M65762FP
(13) Scale-up/scale-down set register (W/R)
(Address: D)
CONV_REG:
d7
0
d4
HO
d0
HR
VR
HE
d0 (VE):
Selection of scale-up in vertical direction during decoding (0: Equal size, Scale-up by twice)
d1 (HE):
Selection of scale-up in horizontal direction during decoding (0: Equal size, Scale-up by twice)
VE
Note: Scale-up function is effective only in decoding (Scale-up enabled)
d2 (VR):
Selection of scale-down in vertical direction (0: Equal size, Scale-down by 1/2)
d3 (HR):
Selection of scale-down in horizontal direction (0: Equal size, Scale-down by 1/2)
d4 (HO):
Selection of thinned-out processing in horizontal direction (0: Simple thinned-out, 1: OR processing)
Note: Scale-down function is effective only in encoding (Scale-down enabled)
Notes: 1. During coding, simple thinned-out is applied to 1/2 scale-down in vertical direction (Odd lines are
skipped in reading.)
2. With VR = 1 during coding, the number of lines on input image data must be larger by twice than
the set value of line count setup register.
3. With VE = 1 during decoding, the number of lines on output image data must be larger by twice
than the set value of line count setup register.
3. Register Initial Value
Registers are initialized as provided in the following table by writing H/W reset into the external reset pin or system
setup register.
Table 6
Initial Values of Registers
Register
System setting
Parameter setting
Command
Status
Interrupt enable
Pixel setting
Line count setting
Note:
Initial Value
00h (Note)
00h
00h
00h
00h
00h
00h
Register
Number of processed lines
Buffer register
Operation mode setting
Marker code setting
Marker code reading
Scale-up/scale-down setting
Initial Value
00h
Indefinite
00h
00h
00h
00h
When H/W reset is written into the system setting register, written value is set in the system setting register.
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
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M65762FP
4. Register Setting Sequence
(1) Initialization sequence of built-in line memory and context table RAM
This sequence is used to carry out initialization sequence (0 clear) of context table RAM after the initialization (Note)
of the built-in line memory by H/W reset.
When the initialization is unnecessary (the contents of the current status table are directly used), this sequence is
unnecessary.
1
d7
H/W Reset
Context mode set up
d0
SYS_REG:
0
0
0
0
0
0
0
1
; H/W reset bit ON
SYS_REG:
0
0
0
0
0
0
0
0
; H/W reset bit OFF
* Period of H/W reset bit set to ON (time from when d0 = "1"
is written until d0 = "0" is written) requires 100 ns or more.
Issue context table RAM
initialization command
CMD_REG:
0
0
0
0
0
0
0
1
; Initializes context table RAM
Set interrupt enable
IENB_REG:
0
0
0
0
0
0
0
1
; Process end interrupt enable
Context table RAM is initialized (0 clear) in this period.
The number of clocks required for initialization is as follows:
1024 + a [Clock]
(Occurrence of interrupt)
d7
d0
Set interrupt disable
IENB_REG:
0
0
0
0
0
0
0
0
; Interrupt disable
Read out status register
(check the end of processing)
STAT_REG:
−
−
−
−
−
−
−
j
; j = End of processing
CMD_REG:
0
0
0
0
0
0
0
0
; End of initialization
N
j=1?
(Error)
Y
End of initialization command
2
Note:
To 2)
Line memory is initialized by H/W reset to prepare the all white (0) data as a reference line to provide
for the start of coding/decoding process and to initialize LNTP bit (LNTP = 1) for typical prediction.
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
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M65762FP
(2) Stripe coding/decoding (without change in AT pixel position)/image data through processing sequence
2
d7
Set system
(set LSI mode)
SYS_REG:
Set operation mode
MOD_REG:
; Cb, Cb = Bit width of code data bus
; Bs, Bx = Code data bus bit, byte swap
; Pb, Pi = Bit width of image data bus,
I/F selection
; mm = Operation mode
(coding/decoding/through)
; Ob, Ob = Selection of head byte read-through
during decoding (0 to 3)
; Li = Selection of inhibition of line memory
initialization Note
; Tp = Typical prediction function ON/OFF
; aa, aaaaa = AT pixel position
; t = Template selection
d0
Pb Pi Bx Bs 0 Cb Cb 0
Tp Li Ob Ob 0
0
m m
Note: Set Li = 0 for the head stripe of single
stripe of multi stripe.
Set parameter
(template, context)
PARA_REG:
a
a
Set the number of pixels
PEL_REG_L:
PEL_REG_H:
0
0
t
a
a
a
a
pel_l
; pel_l, pel_h = Number of pixels per 1 line
pel_h
LSET_REG_L:
LSET_REG_H:
lset_h
Set marker code
(Note: Required cording only)
MSET_REG:
mset
Set scale-up/scale-down
Set the number of lines
a
lset_l
; lset_l, lset_h = Number of processing lines
; mset = sets marker code byte
(SDNORM = 02h, SDRST = 03h)
CONV_REG:
0
0
0 Ho Hr Vr He Ve
Processing start command
(coding/decoding/through)
CMD_REG:
0
0
0
0
0
0
1
0
Set interrupt enable
IENB_REG:
0
0
0
0
0
0
0
1
; Ve, He = Selection of scale-up during
decoding
; Vr, Hr, Ho = Selection of scale-down
at time of coding
; Termination end processing
(coding/decoding/through)
Start command
; Process end interrupt enable
[Performs coding/decoding processing during this period.]−−−Inputs/outputs image data and coding data
(Coding/decoding/through processing for a stripe.)
(Occurrence of interrupt)
d7
d0
Set interrupt disable
IENB_REG:
0
0
0
0
0
0
0
0
; Interrupt disable
Read out status register
(check process for end)
STAT_REG:
−
−
−
s
−
m
−
j
; j = End of processing
; m = Marker detection
; s = SC counter over error
N
j=1?
(Error)
Y
N (Coding)
Decoding ?
Y
(Decoding)
N (Marker not detected)
(Error)
End
(Error)
(Marker detection)
Read marker code
(Note: At time of decoding only)
N (SC counter over)
Y
m=1?
Y
s=0?
MDET_REG:
End
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
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mdet
; mdet = Read marker code
M65762FP
(3) Stripe encoding/decoding (with change in AT pixel position) processing sequence
2
; Cb, Cb = Bit width of code data bus
; Bs, Bx = Code data bus bit, byte swap
; Pb, Pi = Bit width of image data bus, I/F
Pb
Pi
Bx
0
Cb
Cb
0
Bs
SYS_REG:
selection
; m = Operation mode (encoding/decoding)
; Ob, Ob = Selection of head byte read-through
MOD_REG: Tp Li Ob Ob 0 0 0 m
during decoding (0 to 3)
; Li = Selection of inhibition of line memory
Note: Set Li = 0 for single stripe or the head
initialization Note
; Tp = Typical prediction function ON/OFF
stripe of multi-stripe.
; aa,aaaaa = AT pixel position
PARA_REG: a a t a a a a a
; t = Template selection
d7
Set system
(set LSI mode)
Set operation mode
Set parameter
(template, context)
d0
Set the number of pixels
PEL_REG_L:
PEL_REG_H:
Set the number of lines
LSET_REG_L:
LSET_REG_H:
lset_h
Set marker code
(Note: Required cording only)
MSET_REG:
mset
Set scale-up/scale-down
CONV_REG:
0
0
0 Ho Hr Vr He Ve
Processing start command
(temporary stop processing)
CMD_REG:
0
0
0
0
1
0
1
0
Set interrupt enable
IENB_REG:
0
0
0
0
0
0
0
1
pel_l
0
0
; pel_l, pel_h = Number of pixels per 1 line
pel_h
; lset_l, lset_h = Number of processing lines
lset_l
Note: Set the number of processing lines to
position change of AT pixel.
; mset = Sets marker code byte
(SDNORM = 02h, SDRST = 03h)
; Ve, He = Selection of scale-up at time of
decoding
; Vr, Hr, Ho = Selection of scale-down at
time of coding
; Temporary stop processing
(coding/decoding)
Start command
; Process end interrupt enable
[Performs coding/decoding processing during this period.]−−−Input/output first image data and coding data.
Repeat this routine (for the number of AT moves − 1)
Note: At time of coding in the first processing, (number of lines of input image data) = (value set in the line
count set register) + 1. During decoding, (number of lines in output image data) = (value set in the
(Occurrence of interruption) line set register) − 1
d7
d0
Set interrupt disable
IENB_REG:
0
0
0
0
0
0
0
0
; Interrupt disable
Read status register
STAT_REG:
−
−
p
−
−
−
−
j
; Status check
; j = 0, p = 1, temporary stop status
a' a'
t'
a' a' a' a' a'
Set final AT
Final set
3
Set in the course
Set AT pixel position
Set the number of lines
PARA_REG:
LSET_REG_L:
LSET_REG_H:
; Set change of AT pixel (a'a', a'a'a'a'a')
Note: Template is not allowed to be
changed
; lset_l, lset_h = Number of processing lines
lset_l
Note: Set the number of processing lines
ranging from processing restart to
change of AT pixel position
lset_h
Processing start command
(temporary stop processing)
CMD_REG:
0
0
0
0
1
0
1
0
Set interrupt enable
IENB_REG:
0
0
0
0
0
0
0
1
; Temporary stop processing
(encoding/decoding)
Start command
; Process stop interrupt enable
[Performs encoding/decoding process during this period.]−−−Input/outputs image data and coding data in the course.
Note: During encoding in the course of processing, (number of lines of input image data) = (value set
in the line count set register). At time of decoding, (number of lines in output image data) =
(value set in the line count set register).
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
Page 20 of 34
M65762FP
3
Set AT pixel position
PARA_REG:
a" a"
t
a" a" a" a" a"
; Set change in final AT pixel.
(a"a", a"a"a"a"a")
Note: Template is not allowed to be changed
LSET_REG_L:
LSET_REG_H:
Set number of lines
; lset_l, lset_h = Number of processing lines
lset_l
Note: Enter the number of processing lines
ranging from restart of processing to the
final line.
lset_h
Processing start command
(termination end processing)
CMD_REG:
0
0
0
0
0
0
1
0
Set interrupt enable
IENB_REG:
0
0
0
0
0
0
0
1
; Termination end processing
(coding/decoding)
Start command
; Process stop interrupt enable
[Performs coding/decoding processing during this period.]−−−Inputs/outputs final image data and coding data.
Note: During coding in the final processing, (number of lines in input image data) = (value set in the line count
set register) − 1. During decoding, (number of lines in output image data) = (value set in the line count
(Occurrence of interrupt) set register) + 1.
d7
d0
Set interrupt disable
IENB_REG:
0
0
0
0
0
0
0
0
Read out status register
(check end of processing)
STAT_REG:
−
−
−
s
−
m
−
j
N
; Interrupt disable
; j = End of processing
; m = Marker detection
; s = SC counter over error
j=1?
(Error)
Y
N (Encoding)
Decoding ?
Y
N (SC counter over)
s=0?
(Decoding)
(Error)
N (Marker not detected)
Y
m=1?
End
(Error)
Y (Marker detection)
Read out marker code
(Note: Decoding only)
MDET_REG:
; mdet = Read marker code
mdet
End
(4) Load/store processing sequence of the context table RAM
This sequence is used to load or store context table RAM.
d7
RAM load/store start
command
CMD_REG:
0
d0
0
0
0
0
0
0
0
; Starts to load/store context table RAM
[Stores (loads) the context table RAM during this period.]
Context RAM data is stored (loaded) via buffer register.
Reading (writing) 2 bytes automatically increments the RAM address.
Note: Reading (storing) operation and writing (loading) operation are not allowed to be done at a time.
End of RAM
load/store command
CMD_REG:
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
Page 21 of 34
0
0
0
0
0
1
0
0
; End of loading/storing RAM
Since the operation does not automatically stop,
be sure to write the load/store end command.
M65762FP
(5) Load/store processing sequence of line memory image data
2
d7
SYS_REG:
Set system (set LSI mode)
d0
Pb Pi Bx Bs Ds Cb Cb 0
Set operation mode
MOD_REG:
Set parameter*
(selection of template)
PARA_REG:
−
−
Set number of pixels*
PEL_REG_L:
PEL_REG_H:
0
0
Set number of lines (= 2)
Tp Li
0
0 Lio Lio 1
t
−
−
−
−
pel_l
; m = Operation mode (selection of through mode)
; Lio, Lio = 01 or 10 (selection of load or store)
; Li = 1 (selection of prohibition of line memory
initialization)
; Tp = Typical prediction function ON/OFF Note1
; t = Selection of template
; pel_l, pel_h = Number of pixels per line
pel_h
LSET_REG_L:
LSET_REG_H:
Set scale-up/scale-down*
−
m
; Cb,Cb = Bit width of code data bus
; Ds = Bit swap of image data bus
; Bs, Bx = Code data bus bit, byte swap
; Pb, Pi = Bit width of image data bus, I/F selection
lset_l
; lset_l, lset_h = 2 (Number of processed lines)Note2
lset_h
CONV_REG:
0
0
0 Ho Hr Vr He Ve
Processing start command
(load/store into line memory)
CMD_REG:
0
0
0
0
0
0
1
0
Set interrupt enable
IENB_REG:
0
0
0
0
0
0
0
1
; Ve, He = Selection of scale-up during
decoding
; Vr, Hr, Ho = Selection of scale-down
during coding
; Load/store processing start command of
image data
; Process end interrupt enable
* Settings of template selection, number of pixels per line, selection of scale-up/scale-down and
typical prediction function must meet the settings at time of stripe coding/decoding to be carried
out after this.
[Performs loading/storing process during this period.]−−−Inputs (outputs) image data. (Transfer processing of image data for 2 lines)
(Occurrence of interrupt)
d7
d0
Set interruption disable
IENB_REG:
0
0
0
0
0
0
0
0
; Interrupt disable
Read out status register
(check end of processing)
STAT_REG:
−
−
−
−
−
−
−
j
; j = End of processing
N
j=1?
(Error)
Y
End
Stripe
Head line
Notes: 1. For ON/OFF bit of TP function in the image data processing,
the ON/OFF bit of the TP function just before coding/decoding
shall be kept.
2. In the image data load/store processing, be sure to set the
number of transfer lines to "2".
(The 1st line is data on the line (final line – 1) of the stripe.
The 2nd line is data on the last line of stripe.)
When a line stripe is adopted for the first stripe of the page in
the image data store processing, and read out line of the first
line is outside data of stripe, the all white data must used for
replacement or the image data load function must be used in
advance to clear line memory.
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
Page 22 of 34
•
•
•
(Final line − 1) line
1st line
Final line
2nd line
M65762FP
(6) Total sequence of multi-stripe coding/decoding
For an image with a page consisting of more than one stripe or plane, coding or decoding process must be carried
out in units of stripe after initialization.
Multi-stripe
coding/decoding
Initialization of built-in memory
and context table RAM
[Process (1)]
1st stripe coding/decoding
processing
[Process (2) or (3)]
End of processing
of all stripes?
Y
End of page
Repetition of this routine (for the number of stripes − 1)
N
Is previous stripe
SDNORM?
N
Y (SDNORM)
Y (Same plane)
(SDRST)
[case 1]
Does the same plane
stripe continue?
N (Difference plane)
[case 3]
Initialization of line memory and
context table RAM
[Process (1)]
Loading of image data of line
memory, and loading of context
table RAM
[Processes (4) and (5)]
[case 2]
Stripe coding/decoding
processing (Indication of line
memory initialization: Li = 0, AT
pixel = Default position (0))
[Process (2) or (3)]
Stripe coding/decoding
processing (Prohibition of line
memory initialization: Li = 1, AT
pixel = Previous stripe taken
over)
[Process (2) or (3)]
Stripe coding/decoding
processing
(Prohibition of line memory
initialization: Li = 1, AT pixel =
Respecify)
[Process (2) or (3)]
Storing of image data of line
memory and storing of context
table RAM
[Processes (4) and (5)]
Notes:
1.
2.
3.
Since use of the host bus with 32-/16-bit bus during coding adopts word boundary, the end marker code
may be followed by the pad bytes ("00") of 1 to 3-byte. These pad bytes must be removed outside. (see
"Description on Register" (7))
When decoding of stripes starts at time of decoding, the head coding data of SDE (stripe data entity)
must be first entered. Read-through of head byte is indicated, if necessary. (At time of end of decoding
stripes, the head block of coding data may be entered into LSI (FIFO) or may not be arranged in the
word boundary. Management is therefore required outside.)
The process of inter-stripe marker codes (ATMOVE, NEWLEN, etc.) (insert at time of coding and
detection/removal at time of decoding) must be carried out outside.
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
Page 23 of 34
M65762FP
Description
If the end marker of the previous stripe is SDRST, the status must be initialized for coding/decoding the next stripe.
Start to carry out the process of next stripe by returning the AT pixel position to the default position after the
initialization of built-in line memory and context table RAM. [case 1]
If the termination marker of the previous stripe is SDNORM, the status of the previous stripe must be taken over for
coding/decoding the next stripe. If the stripe of the same plane is continuously coded/decoded, the AT pixel position
takes over the final value of the previous stripe and the process of the next stripe is to start without initializing line
memory and context table RAM to use the status of line memory and context table RAM at the end of previous stripe
for the next stripe. [case 2]
On the other hand, since the status at the end of pre-stripe status of the same plane must be respecified for the status of
line memory and context table RAM, line memory and context table RAM are to be loaded into LSI to respecify the AT
pixel position and to start processing the next stripe when alternately coding/decoding stripes of different planes. After
coding/decoding of stripe, save line memory and context table RAM for next stripe. [case 3]
(Example)
• Single plane, multi-stripe
Plane
1
2
• Multiple planes and multi-stripe
3
Plane 1
1
4
7
10
Plane 2
2
5
8
11
Stripe
Plane 3
(Processes in numeric order)
3
6
9
12
4
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
Page 24 of 34
M65762FP
Timing Chart
1. Host Bus I/F
CS*
RD*
WR*
A0 to 3
D0 to 7
Read access
Write access
2. Code Data I/F
(a) For 8-bit bus
CDRQ
CDAK*
CDRD*/CDWR*
CD0 to 7
(b) For 16-bit bus
CDRQ
CDAK*
CDRD*/CDWR*
CD0 to 15
Note: For 16-bit bus, only the word access (CD0 to 15) is allowed.
(c) For 32-bit bus
CDRQ
CDAK*
CDRD*/CDWR*
CD0 to 31
Note: For 32-bit bus, only the long word access (CD0 to 31) is allowed.
Description
CDRQ can be checked for being asserted (H) to assert (L) CDAK*.
Asserting (L) CDAK* negates (L) CDRQ.
Asserting (L) section of CDRD*/CDWR* must be included in the CDAK* asserting section (L).
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
Page 25 of 34
M65762FP
3. Image Data I/F
(1) Serial image data I/F
PRDY*
PTIM*
PXCK*
PXCKO*
SVID*/RVID*
1
2
3
4
5
N
Note: The above chart shows a timing for a line (N pixel/line).
Description
PRDY* can be checked for being asserted (L) to assert (L) PTIM*.
Asserting (L) PTIM* negates (H) PRDY*.
PXCKO* is an output of having gated PXCK* input with PTIM*.
The image data (SVID*/RVID*) is input/output in synchronization with PXCK* or PXCKO*.
(2) Parallel image data I/F
(a) 16-bit bus
PDRQ
PDAK*
PDRD*
/PDWR*
PD0 to 15
Note: For 16-bit bus, only the word access (PD0 to 15) is allowed.
(b) 32-bit bus
PDRQ
PDAK*
PDRD*
/PDWR*
PD0 to 31
Note: For 32-bit bus, only the long word access (PD0 to 31) is allowed.
Description
PDRQ can be checked for being asserted (H) to assert (L) PDAK*.
Asserting (L) PDAK* negates (H) PDRQ.
Asserting (L) section of PDRD*/PDWR* must be included in the asserting section (L) of PDAK*.
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
Page 26 of 34
M65762FP
Examples of System Configuration
1. Example of Application for Digital PPC and Multifunctional FAX Machine
Image
sensor
Binaly
image
processing
Printer
No frame memory
required by QM-Coder
Reduction of memory size and
increase of memory efficiency
by QM-Coder
QM-Coder
(M65762FP)
MPU
QM-Coder
(M65762FP)
DMAC
Signed
memory
Communications
control
Disk device
High-speed communications
by QM-Coder
Figure 5 Example of Application for Digital PPC and Multifunctional FAX Machine
2. Example of Application for Printer
High-speed communications
by QM-signed data
Signed memory
QM encoder
(hardware or software)
Image data file
QM decoder
(M65762FP)
Printer (LBP)
PC/WS
Reduction of memory size
by real-time decoding
Figure 6 Example of Application for Printer
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
Page 27 of 34
Memory
M65762FP
[Appendix A.1] JBIG Data Structure
B I
E
; Bi-level
B I H
DL
D
P
XD
YD
LD
MX
MY
Order
1
1
1
1
4
4
4
1
1
1
HITOLO
SEQ
ILEAVE
SMID
Options 1
Image
Entity
; Bi-level Image Header
; lowest resolution layer
; final resolution layer
; number of bit-planes
; dummy 0
; horizontal dimension at highest resolution
; vertical dimension at highest resolution
; number of lines per stripe at lowest resolution
; maximum horizontal offsets allowed for AT pixel
; maximum vertical offsets allowed for AT pixel
; order byte
b7-4
b3
b2
b1
b0
; dummy 0
; resolution-order distinction
; progressive-versus-seqential distinction
; interleaving of multiple bit-planes
; indexed over stripe is in middle
; option byte
LRLTWO
VLENGTH
TPDON
TPBON
DPON
DPPRIV
DPLAST
DPTABLE
0/1728
b7 ; dummy 0
b6 ; lowest resolution-layer two line template
b5 ; NEWLEN (new vertical dimension) marker enable
b4 ; differential-layer TP enable
b3 ; lowest-resolution-layer TP enable
b2 ; DP enable
b1 ; private DP table
b0 ; DP table last is to be reused
; private DP table
(It is present only if DPON = 1, DPPRIV = 1, DPLAST = 0)
B I
D
; bi-level Image Data (( 1 2 ) x N)
1 Floating Marker Segments ( a ~ c )
a AT move marker
ESC
ATMOVE
YAT
τX
τY
1
1
4
1
1
; FFh
; 06h
; line in which an AT switch is to be made
; horizontal offset of the AT pixel
; vertical offset of the AT pixel
1
1
4
; FFh
; 05h
; new YD
1
1
4
LC
; FFh
; 07h
; length in bytes of private comment
; contents of comment
b new-length marker
ESC
NEWLEN
YD
c comment marker
ESC
COMMENT
LC
comment
2 SDE
; Stripe
Data
Entry
(Within the frame: LSI support range)
PSCD
ESC
SDNORM/SDRST
1
1
abort BID marker
ESC
ABORT
1
1
; FFh
; 04h
reserved marker
ESC
RESERVE
1
1
; FFh
; 01h
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
Page 28 of 34
; Protected Stripe Coded Data
= byte stuffed SCD (Stripe Code Data)
; FFh
; normal terminate (02h)
; /reset "state" for next SDE (03h)
M65762FP
[Appendix A.2] JBIG Probability Estimation Table
ST
LSZ
NLPS
NMPS
SWTCH
ST
LSZ
NLPS
NMPS
0
0x5ald
1
1
1
57
0x01a4
55
58
SWTCH
0
1
0x2586
14
2
0
58
0x0160
56
59
0
2
0x1114
16
3
0
59
0x0125
57
60
0
3
0x080b
18
4
0
60
0x00f6
58
61
0
4
0x03d8
20
5
0
61
0x00cb
59
62
0
5
0x01da
23
6
0
62
0x00ab
61
63
0
6
0x00e5
25
7
0
63
0x008f
61
32
0
7
0x006f
28
8
0
64
0x5b12
65
65
1
8
0x0036
30
9
0
65
0x4d04
80
66
0
9
0x001a
33
10
0
66
0x412c
81
67
0
10
0x000d
35
11
0
67
0x37d8
82
68
0
11
0x0006
9
12
0
68
0x2fe8
83
69
0
0
12
0x0003
10
13
0
69
0x293c
84
70
13
0x0001
12
13
0
70
0x2379
86
71
0
14
0x5a7f
15
15
1
71
0x1edf
87
72
0
15
0x3f25
36
16
0
72
0x1aa9
87
73
0
16
0x2cf2
38
17
0
73
0x174e
72
74
0
17
0x207c
39
18
0
74
0x1424
72
75
0
0
18
0x17b9
40
19
0
75
0x119c
74
76
19
0x1182
42
20
0
76
0x0f6b
74
77
0
20
0x0cef
43
21
0
77
0x0d51
75
78
0
21
0x09a1
45
22
0
78
0x0bb6
77
79
0
22
0x072f
46
23
0
79
0x0a40
77
48
0
23
0x055c
48
24
0
80
0x5832
80
81
1
24
0x0406
49
25
0
81
0x4d1c
88
82
0
25
0x0303
51
26
0
82
0x438e
89
83
0
26
0x0240
52
27
0
83
0x3bdd
90
84
0
27
0x01b1
54
28
0
84
0x34ee
91
85
0
28
0x0144
56
29
0
85
0x2eae
92
86
0
29
0x00f5
57
30
0
86
0x299a
93
87
0
30
0x00b7
59
31
0
87
0x2516
86
71
0
31
0x008a
60
32
0
88
0x5570
88
89
1
32
0x0068
62
33
0
89
0x4ca9
95
90
0
33
0x004e
63
34
0
90
0x44d9
96
91
0
34
0x003b
32
35
0
91
0x3e22
97
92
0
35
0x002c
33
9
0
92
0x3824
99
93
0
36
0x5ae1
37
37
1
93
0x32b4
99
94
0
37
0x484c
64
38
0
94
0x2e17
93
86
0
38
0x3a0d
65
39
0
95
0x56a8
95
96
1
39
0x2ef1
67
40
0
96
0x4f46
101
97
0
40
0x261f
68
41
0
97
0x47e5
102
98
0
41
0x1f33
69
42
0
98
0x41cf
103
99
0
42
0x19a8
70
43
0
99
0x3c3d
104
100
0
43
0x1518
72
44
0
100
0x375e
99
93
0
44
0x1177
73
45
0
101
0x5231
105
102
0
45
0x0e74
74
46
0
102
0x4c0f
106
103
0
46
0x0bfb
75
47
0
103
0x4639
107
104
0
47
0x09f8
77
48
0
104
0x415e
103
99
0
48
0x0861
78
49
0
105
0x5627
105
106
1
49
0x0706
79
50
0
106
0x50e7
108
107
0
50
0x05cd
48
51
0
107
0x4b85
109
103
0
51
0x04de
50
52
0
108
0x5597
110
109
0
52
0x040f
50
53
0
109
0x504f
111
107
0
53
0x0363
51
54
0
110
0x5a10
110
111
1
54
0x02d4
52
55
0
111
0x5522
112
109
0
55
0x025c
53
56
0
112
0x59eb
112
111
1
56
0x01f8
54
57
0
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
Page 29 of 34
M65762FP
[Appendix B] Timing Characteristics
(Conditions: VDD = 5 V ± 5%, C = 50 pF, Ta = 0 to 70°C)
1. Host Bus I/F
RESET*
t0
CS*
t1
t2
t12
t11
A0 to 3
t4
t3
t5
t13
t15
RD*
t14
WR*
t6
t7
t16
Input
Output
D0 to 7
t17
2. Code Data I/F
CDRQ
t20
CDAK*
t22
t21
CDRD*
t32
t31
t24
t34
CDWR*
t27
t26
CD0 to 31
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
Page 30 of 34
Output
t37
t36
Input
M65762FP
Table B.1 Host Bus I/F Timing Characteristics
(Unit: ns)
Abbreviation
Item
Min
Timing Conditions
Typ
Max
t0
t1
t2
t3
t4
t5
t6
t7
RESET* assert time
CS* setup time to RD* assert
CS* hold time to RD* negate
A0 to 3 setup time to RD* assert
RD* assert time
A0 to 3 hold time to RD* negate
D0 to 7 output determination time to RD* assert
D0 to 7 output hold time to RD* negate
100
15
15
15
20
15
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20
20
t11
t12
t13
t14
t15
t16
t17
CS* setup time to WR* assert
CS* hold time to WR* negate
A0 to 3 setup time to WR* assert
WR* assert time
A0 to 3 hold time to WR* negate
D0 to 7 input setup time to WR* negate
D0 to 7 input hold time to WR* negate
15
15
15
15
15
20
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table B.2 Timing Characteristics of Code Data Bus I/F
Timing Conditions
Abbreviation
Item
t20
t21
t22
t24
t26
t27
CDRQ negate time to CDAK* assert
CDAK* setup time to CDRD* assert
CDAK* hold time to CDRD* negate
CDRD* assert time
CD0 to 31 output determination time to CDRD* assert
CD0 to 31 output hold time to CDRD* negate
Min
—
15
15
20
0
0
Typ
—
—
—
—
—
—
Max
15
—
—
—
20
20
t31
t32
t34
t36
t37
CDAK* setup time to CDWR* assert
CDAK* hold time to CDWR* negate
CDWR* assert time
CD0 to 31 input setup time to CDWR* negate
CD0 to 31 input hold time to CDWR* negate
15
15
15
15
5
—
—
—
—
—
—
—
—
—
—
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
Page 31 of 34
M65762FP
3. Image Data I/F
(1) Serial image data I/F
PRDY*
t40
t45
PTIM*
t41
t44
t43
t42
PXCK*
t47
t46
PXCKO*
t49
t50
t51
RVID*
1
t56
SVID*
t48
2
3
N
t57
1
2
3
N
(2) Parallel image data I/F
PDRQ
t60
PDAK*
t61
t62
PDRD*
t71
t72
t64
t74
PDWR*
t66
Output
PD0 to 31
Input
4. Master Clock Input Frequency (LSI Operating Frequency)
Mx
Mh
MCLK
Ml
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
Page 32 of 34
t77
t76
t67
M65762FP
Table B.3 Timing Characteristics of Image Data I/F
(Unit: ns)
Abbreviation
Item
Min
Timing Conditions
Typ
Max
t40
t41
t42
t43
t44
t45
t46
t47
t48
t49
PRDY* negate time to PTIM* assert
PTIM* setup time to PXCK* fall
PTIM* hold time to PXCK* rise
PXCK* high time
PXCK* low time
PXCK* cycle
RVID* output determination time to PXCK* fall
RVID* output change time to PXCK* fall
RVID* negate time to PTIM* negate
PXCKO* delay time to PXCK*
—
15
15
10
10
25
—
—
0
—
—
—
—
—
—
—
—
—
—
—
20
—
—
—
—
—
20
20
—
10
t50
t51
RVID* output determination time to PXCKO* fall
RVID* output change time to PXCKO* fall
—
—
—
—
12
12
t56
t57
SVID* setup time to PXCK* rise
SVID* hold time to PXCK* rise
10
10
—
—
—
—
t60
t61
t62
t64
t66
t67
PDRQ negate time to PDAK* assert
PDAK* setup time to PDRD* assert
PDAK* hold time to PDRD* negate
PDRD* assert time
PD0 to 31 output determination time to PDRD* assert
PD0 to 31 output hold time to PDRD* negate
—
15
15
20
0
0
—
—
—
—
—
—
15
—
—
—
20
20
t71
t72
t74
t76
t77
PDAK* setup time to PDWR* assert
PDAK* hold time to PDWR* negate
PDWR* assert time
PD0 to 31 input setup time to PDWR* negate
PD0 to 31 input hold time to PDWR* negate
15
15
15
15
5
—
—
—
—
—
—
—
—
—
—
Table B.4 Master Clock Frequencies
(Unit: ns)
Timing Conditions
Item
MCLK cycle (Mx)
MCLK high level time (Mh)
MCLK low level time (Ml)
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
Page 33 of 34
Min
25
10
10
Typ
—
—
—
Max
—
—
—
Max Frequency
40 MHz
M65762FP
Package Dimensions
JEITA Package Code
P-LQFP144-20x20-0.50
RENESAS Code
PLQP0144KA-A
Previous Code
144P6Q-A / FP-144L / FP-144LV
MASS[Typ.]
1.2g
HD
*1
D
108
73
109
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
72
bp
c
Reference
Symbol
*2
E
HE
c1
b1
36
A
1
ZD
Index mark
c
37
A2
144
ZE
Terminal cross section
A1
F
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
L1
*3
e
y
bp
x
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
Page 34 of 34
Detail F
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
19.9 20.0 20.1
19.9 20.0 20.1
1.4
21.8 22.0 22.2
21.8 22.0 22.2
1.7
0.05 0.1 0.15
0.17 0.22 0.27
0.20
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.10
1.25
1.25
0.35 0.5 0.65
1.0
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