M65761FP
QM-Coder
REJ03F0234-0200
Rev.2.00
Sep 14, 2007
Description
The M65761FP is a compression and decompression LSI conforming to the high efficiency encoding system (QMCoder) in the International Standard, the JBIG/JPEG (ITU-T Recommendations T.81 and T.82) for coding still images.
It also conforms to the International Standard (ITU-T Recommendation T.85) for facsimile.
Features
• 100 pin plastic molded quad flat package (fine pitch): PRQP0100JB-A (100P6S-A)
Application
• OA equipment including facsimile, copier and printer
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 1 of 33
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 2 of 33
12
15
25
28
37
PD10
PD11
PD21
PD22
PD31
41
42
45
PDRD
PDWR
PRDY
46
SVID
52
49
XCLK
XWAIT
(= RPIX)
RVID
44
95
PXCKO
(= SPIX)
48
PXCK
(= XTIM)
26
39
50
59
81
Pixel data
75
Context data
69
Typical prediction
PTIM
47
43
PDAK
(= XRDY)
38
PDRQ
PD15 = PEUPE
PD0 to 11 = CX0 to 11
2
PD0
13
VCC
87
1
93 100
Table RAM probability estimation
Context table RAM
Switch
Context generation
Line memory
Image data context I/F
TOUT1, 2
96 97
Host bus I/F
GND
14 27 40 51 60 70 76 82 88 94
Leave TOUT1 and TOUT2 open.
99 TEST0
98 TEST1
61 MCLK
55 BUS16
53 INTR
56 DMAAK
54 DMARQ
92 D15
89 D12
86 D11
83 D8
80 D7
77 D4
74 D3
71 D0
57 RD
58 WR
63 BHE
67 A3
64 A0
62 CS
68 RESET
M65761FP
Block Diagram
QM-coder
M65761FP
Pin Arrangement
VCC
GND
D8
D9
D10
D11
VCC
GND
D12
D13
D14
D15
VCC
GND
PXCKO
TOUT2
TOUT1
TEST1
TEST0
VCC
M65761FP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
GND
1
80
D7
PD0
2
79
D6
PD1
3
78
D5
PD2
4
77
D4
PD3
5
76
GND
PD4
6
75
VCC
PD5
7
74
D3
PD6
8
73
D2
PD7
9
72
D1
PD8
10
71
D0
PD9
11
70
GND
PD10
12
69
VCC
VCC
13
68
RESET
GND
14
67
A3
PD11
15
66
A2
PD12
16
65
A1
PD13
17
64
A0
PD14
18
63
BHE
PD15
19
62
CS
PD16
20
61
MCLK
PD17
21
60
GND
PD18
22
59
VCC
PD19
23
58
WR
PD20
24
57
RD
PD21
25
56
DMAAK
VCC
26
55
BUS16
GND
27
54
DMARQ
PD22
28
53
INTR
PD23
29
52
XCLK
PD24
30
51
GND
Outline: PRQP0100JB-A (100P6S-A)
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 3 of 33
VCC
XWAIT
PXCK
SVID
(Top view)
PTIM
PRDY
RVID
PDAK
PDWR
GND
PDRD
VCC
PDRQ
PD31
PD30
PD29
PD28
PD27
PD26
PD25
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
M65761FP
Pin Description
Classification
Host bus I/F
Image
data
I/F
Parallel
Serial
Context I/F
Others
Note:
Pin Name
RESET
CS
A0 to 3
BHE
WR
RD
D0 to 15
DMARQ
DMAAK
INTR
BUS16
PD0 to 31
PDRQ
PDAK
PDRD
PDWR
PRDY
PTIM
PXCK
PXCKO
SVID
RVID
CX0 to 11
PEUPE
SPIX
RPIX
XCLK
XWAIT
XRDY
XTIM
MCLK
TEST0, 1
VCC/GND
I/O
BUF
I
I
I
I
I
I
IO
O
I
O
I
IO
O
I
I
I
O
I
I
O
I
O
I
I
I
O
O
I
O
I
I
I
—
S
S
S
8
2
US
2
U
U2
2
US
US
US
2
US
US
4
U
2
U
U
U
2
4
US
2
US
DS
—
Function
H/W reset signal
Chip select signal
Internal register address select signal
High-order (D8 to 15) access signal
Write strobe signal
Read strobe signal
I/O data signal (D0 to 7 used on 8-bit bus)
Code data DMA request signal
Code data DMA acknowledge signal
Interrupt request signal
8-bit bus (D0 to 7) and 16-bit bus (D0 to 15) function select bus
Parallel image I/O bus (PD0 to 15 used on 16-bit bus)
Image data DMA request signal
Image data DMA acknowledge signal
Image data read strobe signal
Image data write strobe signal
Image data 1-line I/O start ready signal
Image data 1-line transfer section signal
Image data transfer clock signal
Image data transfer sync clock signal
Image data input signal
Image data output signal
Context input (CX0 can be fed back inside LSI)
(= PD0 to 11)
PE RAM up date enable (learning function ON/OFF)
(= PD15)
Coded image data input signal
(= SVID)
Decoded image data output signal
(= RVID)
Context data transfer clock signal
Context data transfer wait signal
Context data 1-stripe I/O start ready signal
(= PRDY)
Context data 1-stripe transfer section signal
(= PTIM)
Master clock input signal
Test signal (should be connected to GND when normally used)
Power supply (+5 V)/ground
Most of the context I/F signals are used in conjunction with the image data I/F signals.
The input buffers of the input terminals (I and IO) are at TTL level.
Options are as follows.
(U: with pull-up resistors, D: with pull-down resistors, S: Schmitt trigger)
Numbers (2, 4, 8) of the BUF column of the output terminals (O and IO) indicate current value. (one of 2, 4, or 8
mA)
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 4 of 33
M65761FP
Absolute Maximum Ratings
(Ta = –20 to +70 °C unless otherwise noted)
Item
Supply voltage
Symbol
VCC
Input voltage
Output voltage
VI
VO
Storage temperature
Power dissipation
Tstg
Pd
Note:
Ratings
–0.3 to +7.0
Unit
V
–0.3 to VCC + 0.3
0 to VCC
V
V
–65 to +150
1380
°C
mW
Conditions
Ta = 25 °C, when single IC is used
All of the voltage is reference the GND terminal of the circuit.
Maximum value and minimum value are expression of absolute value.
Recommend Operating Conditions
Min
Limits
Typ
Max
Unit
Supply voltage
GND voltage
VCC
GND
4.5
—
5.0
0
5.5
—
V
V
Input voltage
Operating temperature range
VI
Topr
0
–20
—
—
VCC
+70
V
°C
Output capacitance (against IC)
CL
—
50
—
pF
Item
Symbol
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 5 of 33
Test Conditions
M65761FP
Electrical Characteristics
(Ta = –20 to +70°C, VCC = 5 V ± 10% unless otherwise noted)
Item
"H" input voltage
"L" input voltage
"H" input voltage
V
VIL
—
—
0.8
V
MCLK, PXCK
VIH
4.5
—
—
V
VIL
VT+
—
—
—
—
0.0
2.4
V
V
VT–
0.6
—
—
V
VH
—
0.2
—
V
VOH
VOL
VCC – 0.8
—
—
—
—
0.55
V
V
IOH = –8 mA
VOH
VOL
VCC – 0.8
—
—
—
—
0.55
V
V
IOH = –4 mA
PD<31:0>, INTR,
DMARQ, PDRQ,
PRDY, RVID
VOH
VCC – 0.8
—
—
V
IOH = –2 mA
VOL
—
—
0.55
V
IOH = 2 mA
A<3:0>, D<15:0>,
RD, WR, MCLK,
BHE, RESET, CS
IIH
—
—
–1.0
µA
VCC = 5.5 V, VI = 5.5 V
IIL
—
—
1.0
µA
VCC = 5.5 V, VI = 0 V
D<15:0>
IOZH
—
—
–5.0
µA
VCC = 5.5 V, VI = 5.5 V
IOZL
—
—
5.0
µA
VCC = 5.5 V, VI = 0 V
"L" output voltage
XCLK, PXCKO
"L" output voltage
"H" input current
"L" input current
"H" output current
in OFF state
Test Conditions
—
D<15:0>
"L" output voltage
Unit
—
"H" output voltage
"H" output voltage
Max
2.0
Hysteresis width
"H" output voltage
Limits
Typ
VIH
PDRD, DMAAK,
PDAK, PTIM,
XWAIT, PDWR,
TEST1, TEST0,
RD, WR, RESET
Negative
threshold voltage
Min
PD<31:0>,
A<3:0>, D<15:0>,
SVID, BUS16, CS,
BHE
"L" input voltage
Positive
threshold voltage
Symbol
"L" output current
in OFF state
IOH = 8 mA
IOH = 4 mA
Pull up resistor
PD<31:0>, PDRD,
PDWR, PDAK,
SVID, PTIM,
PXCK, XWAIT,
BUS16, DMAAK
RU
25
—
100
kΩ
VCC = 5.5 V, VI = 0 V
Pull down resistor
TEST1, TEST0
RD
ICCA
21
—
—
100
100
—
kΩ
mA
VCC = 5.5 V, VI = 5 V
Dynamic consumption
Note:
The value of resistor is 50 kΩ buffer's value.
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 6 of 33
VCC = 5.5 V, VI = VCC,
GND
M65761FP
Coding Specification
(1) Coding Algorithm
• QM-Coder
(JBIG standard arithmetic coding system)
(2) Context
(i) Built-in context mode
a) Template model
• 2 or 3 line 10 pixel template (see figure 1)
(This agrees with the template used with the minimum resolution of JBIG)
Note: The coding efficiency of the 3-line template is better than that of the 2-line template by several %.
b) Adaptive template (AT)
• It is possible to move up to 127 pixels on the coding line.
(The position of AT given instruction by the MPU)
Note: It is possible to improve the coding efficiency against the dither image by the use of AT.
• It is possible to change the position of AT line by line in the middle of coding and decoding.
Note: It is not possible to change the template at the time when change the position of the AT pixels.
(ii) External context mode
• It is possible to input any context up to 12 bits.
(It is possible to interface with JBIG Progressive Coding and the Arithmatic Coding of JPEG Option
Function)
X
X
X
X
X
X
X
X
X
X
?
X
X
A
X
X
X
X
X
?
X
A
Figure 1 Template (X, A) (Top: 3-line, Bottom: 2-line)
A
X
X
X
X
X
X
X
?
X
X
X
X
X
X
X
?
X
Max 127
X
A
X
X
Max 127
Figure 2 Adaptive Template (A)
(3) Typical Prediction
• Agreement with the Typical Prediction of the lowest resolution of JBIG.
The pseudo-pixel (SLNTP) is generated by the symbol LNTP which shows whether the coding/decoding
process agree with the directly before line. If they agree, the line is not coding/decoding.
This makes it possible to shorten the time of process and rejection of the code data.
SLNTPy =! (LNTPy ⊕ LNTPy – 1)
(y: line number, LNTPy = 1; LNTPy – 1 = 1)
(4) Deterministic Prediction
• This LSI is not equipped with the Typical Prediction. However, the DP function is realized when the DP
pixels are identified and eliminated by the external circuits during the external context mode.
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 7 of 33
M65761FP
(5) Coding Data Format
• The Stripe Data Entity (SDE) (= Stripe coded data with byte stuffing (PSCD) + end marker (SDNORM /
SDRST)) Coding/decoding of one stripe portion as performed. In case of the multi-striped (construct the
multi stripes) stripes are activated one at a time.
(6) Marker Code
• The SDE end marker is supported. (SDNORM = 02h, SDRST = 03h, ABORT = 04h)
(During coding the marker code previously set in the register is outputted. During decoding, the marker code
detected by requesting an interrupt to MPU when the marker is detected is read out of register.)
(7) Rough Estimate of Coding and Decoding Time
(T1: M65761FP as a Whole, T2: Processing Time of the Arithmetic Coding Section Alone)
• The total number of clocks needed for coding and decoding 1 page (stripe) is calculates roughly using the
following equations.
T1 ≈ (p Lp) + (9/8 C) + ( Lp)
p:
Number of pixels/line
–S ((1 – ) p Ltp – Lp) [clock]
Lp:
Number of lines/page
T2 ≈ (p Lp) + (9/8 C)
Ltp:
Number of TP line/page
–S ((p Ltp) – Lp)) [clock]
C:
Number of coded data bits/page
S = 1: TP exists
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 8 of 33
0: No TP
: about 0.3
: about 10
M65761FP
Register Configuration
List of Registers
Address
Register Name
R/W
0
System setting
R/W
1
Parameter setting
R/W
Description
•
•
•
•
•
•
•
•
•
LSI H/W reset
Coding/decoding/image data through mode selection
Context selection (internal context/external context)
Byte swap ON/OFF of coded/image data on host bus
Bit swap ON/OFF of coded/image data on host bus
Image data I/O I/F (parallel I/F, serial I/F)
Image data bus bit width selection (32 bits/16 bits)
Template selection (2-line/3-line template)
Setting of AT pixel position (up to 127) (If 0 is set, AT becomes
non-existent (default position))
Latch input/through input selection in external context input mode
Context table RAM initialization command
Coding (decoding, through) start/end command
Start/stop command for R/W of context table RAM
Selection of temporary stop and terminating end
2
Command
W
2
Status
R
3
Interrupt enable setting
R/W
•
•
•
•
•
•
•
•
•
•
•
•
4, 5
Pixel count setting
R/W
•
6, 7
Line count setting
R/W
• Setting the number of lines to be coded/decoded (up to 65535
8, 9
Processed line count
R
A, B
Data write buffer
W
Processing status (in process/end of processing)
Coded data read/write ready (ready/busy)
Marker code detection (SDNORM, SDRST, ABORT, others)
Interrupt request status
SC counter overflow
Processing mode (stop temporary/terminating end)
Interrupt enable setting correspondence to each of bits positions
of status register
Setting the number of pixels on one line (in multiples of 16 or 32,
up to 10240 pixels)
lines)
Setting the number of coded/decoded lines (up to 65535 lines)
•
• Buffer for writing coded data/image data/context table RAM data
from MPU into LSI (DMA transferable) (RAM address is
automatically incremented each time data is written.)
Buffer for reading coded data/image data/context table RAM data
from LSI into MPU (DMA transferable) (RAM address is
automatically incremented each time data is read).
A, B
Data read buffer
R
•
C
C
Marker code setting
Marker code read
W
R
• Setting a terminal marker code in coding (SDNORM/SDRST)
• Reading a marker code in decoding (SDNORM, SDRST, ABORT,
D
Scaling
R/W
• Reduction in coding (1/2 reduction in horizontal and vertical
others)
•
•
•
•
Note:
directions, horizontal OR processing)
Magnification during decoding (×2 lengthwise and width)
Select throwing away the leading 1-byte of the coded data read
when decoding
Selecting the typical prediction
Selection of prohibiting line memory initialization
When the 8-bit bus is used for the data read/write buffer, use address A only.
Incase of the 16-bit buffer, only the word access is possible.
(The byte access is not possible.)
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 9 of 33
M65761FP
Description of Registers
(1) System set up register (W/R)
(Address: 0)
SYS_REG:
d0 (HR):
d7 (MSB)
PB
PI
BX
BS
CX
d0
HR
MOD
H/W reset (0: Active, 1: Reset state)
To make a H/W reset, set this bit to 1 then to 0.
Reset initializes the entire LSI including the group of register and line memory. However, the
context table RAM is not initialized.
d1, d2 (MOD):
This sets up the operating modes.
(d2 = 0, d1 = 0: coding, d2 = 1, d1 = 0: lage data through (lage data I/F Host I/F),
d2 = 0, d1 = 1: decoding, d2 = 1, d1 = 1: lage data through (Host I/F lage data I/F))
d3 (CX):
Context select (0: internal context, 1: Image data through)
d4 (BS):
Note: The internal context should be selected when the image data through mode is used.
When initializing or processing R/W of the context table RAM and coding/decoding.
This bit must be set the same. (Because RAM configuration changes depending on
internal/external modes.)
Select data bit swap of the host bus. (0: MSB (d7) first, 1: LSB (d0) first)
d5 (BX):
Select data byte swap of the host bus. (0: Lower byte (A) first, 1: Upper byte (B) first)
Note: BX is valid only when the host bus is 16 bits. (BUS16 = HIGH)
Table 1 The Coed Data and Image Data Lineup on the Host Bus
Bus Width
BUS16
1
16-bit
0
8-bit
Note:
Swap
Upper Address (B)
Lower Address (A)
BX
0
BS
0
d15
b8
•••••
•••••
d8
b15
d7
b0
•••••
•••••
d0
b7
0
1
1
0
b15
b0
•••••
•••••
b8
b7
b7
b8
•••••
•••••
b0
b15
1
—
1
0
b7
•••••
—
b0
b15
b0
•••••
•••••
b8
b7
—
1
b7
•••••
b0
—
b0 is the first coded data on the time series/the left-hand side image data on the screen.
b15 is the last coded data on the time series/the right-hand image data on the screen.
b6 (PI):
Selects the image data I/O I/F (0: Serial I/F, 1: Parallel I/F)
b7 (PB):
Selects the bit width of the image data bus (0: 32-bit bus (PD0 to 31), 1: 16-bit bus (PD0 to 15))
Table 2 The Image Data Lineup on the Image Data Parallel Bus
Bit Width
PB = 0
PB = 1
Note:
PD31
p0
•••••
•••••
—
PD16
p15
p0 is the image data on the left-hand on the screen.
p31 is the image data on the right-hand on the screen.
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 10 of 33
PD15
p16
p0
•••••
•••••
•••••
PD0
p31
p15
M65761FP
(2) Parameter setup register (WR)
1) External context mode
(Address: 1)
PARA_REG:
d6 (LC):
d7
d4
C0
LC
d0
0
0
Condition of taking in the input from the external context are selected.
(0: through output, 1: latch input)
When this bit is set to 1, the CX0 to CX11 of the context input is latched once using the transfer
clock. ("XCLK")
d7 (C0):
When this bit is set to 1, CX0 is selected.
(0: CX0 external input, 1: CX0 internal feedback)
2) Internal context mode
(Address: 1)
PARA_REG:
d7
d6
d5
TM
AT
d4
d0
AT
d0 to 4 (AT<0> to AT<4>):
AT pixel position lower 5 bits. (see figure 2)
d5 (TM):
Template select (0: 3-line template, 1: 2-line template)
d6, d7 (AT<5>, AT<6>):
AT pixel position upper 2 bits (the 6th and 7th bits)
Example:
3-line template, AT = 4:
d7
d4
0
0
0
0
1
1
d7
2-line template, AT = 48:
d0
0
0
1
0
0
1
0
0
0
0
d4
d0
Note: The AT pixel position at time of the internal context mode is set up by using all the AT<6:0> (0 to 127).
When the default position (when the AT pixels are not used) is used, AT is set to 0.
When the 2-line template is used, AT should not be set to 1 to 4. In case of the 3-line template, AT = 1 to 2 is
not allowed.
(3) Command register (W)
(Address: 2)
CMD_REG:
d0 (IC):
d7
0
d3
JP
RC
JC
d0
IC
This command starts initialization of context table RAM (1: start initialization)
When this bit goes 1, the context table RAM initialization starts. This bit returns to 0 automatically when
the initialization is completed.
d1 (JC):
Processing (coding/decoding/through) start/end command (1: start processing, 0: end processing)
When this bit goes 1, processing (coding/decoding/through) starts.
This bit returns to 0 automatically when processing of the number of set lines is finished during the
selection of end of termination.
And if this JC bit is made 0 and inputting the image data is stopped during the coding process, the coding is
stopped (flushed) even if the set lines are not filled. Moreover, if this bit made 0 during decoding and no
more coded data is coming in, it is assumed that the "00" of the coded data came in and the preset lines have
been processed. However, in case of the multi-striped coding, processing should not end by making this bit
"0" except in case of last stripe.
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 11 of 33
M65761FP
d2 (RC):
This command starts and stops R/W of context table RAM. (1: R/W start, 0: R/W end)
The context table RAM is read out or written in by making this bit to "1".
When reading/writing is finished, this bit must have "0" on it.
d3 (JP):
This selected temporary stop and the end of termination of coding/decoding/through processing.
(1: Temporary stop selected, 0: End of processing selected)
When the process start command d1 (JC) is issued by making this JP bit to 1, the processing stops
temporarily when the set number of lines have been processed. Then, if the process start command d1 (JC)
is issued, processing restarts. (See " Sequence of Setting Up Registers " (3))
(4) Status register (R)
(Address: 2)
STAT_REG:
d0 (JS):
d7
0
d5
PS
SC
IS
MS
DS
d0
JS
This register indicates the status of processing in initialization, coding, decoding and through.
(0: Processing in progress (being initialized), 1: End of processing)
This JS bit goes to "1" when the initialization is completed as RAM initialization command is issued.
(IC = 1) This JS bit goes to "1" when all coded data has been read out during coding in case when the
process start command of the processing end is issued. (JC = 1, JP = 0) This JS bit goes to "1" when
reading all the image data has been completed during the image data through and decoding. Moreover, this
JS bit stays "0" even when the set number of lines have been processed when the command to start
processing the process which has been stopped temporarily has been issued (JC = 1, JP = 1). (However,
interrupts are issued during the temporary stops.)
d1 (DS):
This is used for read and write ready of coded data. (In case of the through mode, this is used for the image
data.) (1: Ready, 0: Reading no possible)
It is possible to do R/W of data by the way of the data write/read buffer when this bit is 1.
d2 (MS):
This detects the marker code during decoding. (0: not detected, 1: detected)
This bit goes to "1" if any marker is detected during decoding.
d3 (IS):
This indicates the status of the interrupt request. (0: No request, 1: Request exists)
d4 (SC):
This shows the SC count over error during coding. (0: Normal, 1: There is a SC counter overflow)
Note: The SC counter counts the "FF" data bytes which occur during coding. Coding continues even
when the SC counter overflows, this means correct coding data will not be outputted. (Coding error)
d5 (PS):
Processing modes (Stopped temporary/End of trailer) (1: Process temporarily stopped, 0: End of processing)
This PS bit corresponds to the temporary stop and end of processing of d3 bit (JP) processing of the
command register.
(5) Interrupt enable register (W/R)
(Address: 3)
IENB_REG
d0 (JE):
d7
MP
0
d3
SE
ME
Temporary stop/end of trailer interrupt of initialization/coding/decoding/through.
(0: interrupt mask, 1: interrupt enable)
d1 (DE):
Coded data (image data) read out/write in ready interrupt.
(0: interrupt mask, 1: interrupt enable)
d2 (ME):
Marker code detection interrupt during decoding. (0: interrupt mask, 1: interrupt enable)
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 12 of 33
DE
d0
JE
M65761FP
d3 (SE):
SC count over error interrupt during coding. (0: interrupt mask, 1: interrupt enable)
This bit sets to 1 beforehand, it occurs the interruption when the SC counter is overflow during coding.
Processing of coding continues, but the correct coded data is not output.
d7 (MP):
Note: Bits, d0 to d3, are for interrupt enable of bits d0 to d2 and d4 of the status register.
The interrupt request signal (INTR) is asserted when any one of the status bit set in the interrupt
enable (D0 (JE) generates interrupts even during the temporary stop), the status goes to "0" due to
H/W reset or the INTR signal is negated when the interrupt mask causes factors for interrupt to be
lost. Moreover, the status register will not be cleared by the generation of interrupts or the R/W of
the interrupt enable register.
This specified the marker code detection time halt. (0: continue/restart, 1: temporary halt)
Decoding will stop temporarily when the marker code is detected if this MP bit is preset to "1" during
decoding. (It occurs interruption when the marker code is detected, if the ME bit preset to "1".)
If decoding is not completed during the temporary halt, it is possible to reset the line number setup register.
Next, if this MP bit is set to "0", decoding is restarted. (Decoding continues to the line number set.)
(6) Register used to set the number of pixels (W/R)
(Address: 4)
PEL_REG_L:
d7
(Address: 5)
PEL_REG_H:
d7
d0
PEL_L
d5
d0
0
d0 to 7 (PEL_L):
Number of pixels/line is set (Lower byte)
d0 to 5 (PEL_H):
Number of pixels/line is set (Upper byte)
PEL_H
It is possible to set up 8192 pixels maximum when 3-line template is used. It is used to set up
10240 pixels maximum when 2-line template is used. The number of pixels actually coded (or
decoded) should be set when reducing (or expanding). When the image bus uses 16 bits (or 32 bits)
in parallel I/F, multiples of 16 (or 32) should be set. In case of serial I/F, multiples of 8 should be
used.
(7) Line number setting register (W/R)
(Address: 6)
LSET_REG_L:
d7
LSET_L
(Address: 7)
LSET_REG_H:
d0 to 7 (LSET_L):
d0
LSET_H
This sets the number of lines to be processed. (Lower bytes)
(1 to 65535, 0 line not used)
d0 to 7 (LSET_H):
This sets the number of lines to be processed. (Upper bytes)
When reducing (magnification) the actual number of lines to be coded (decoded) should be set.
The number of lines (relative number of lines) from the process start command to be issued from
now the immediately following temporary stop/end of trailer should be set. This register should
be set to the value specified before the process star command is issued. Moreover, this register
can be rewritten during processing as long as the following conditions are met:
• If the maximum value, (65535), is set before the process start command is issued, it can be
reset once during processing.
• If a value other than maximum value (65535) is set before the process start command is
issued and if resetting becomes necessary during processing, the maximum value (65535) has
to be reset once and desired value should the reset.
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 13 of 33
M65761FP
(8) Number of lines to be processed specified (R)
(Address: 8)
LIN_REG_L:
d7
d0
LINE_L
(Address: 9)
LIN_REG_H:
LINE_H
d0 to 7 (LINE_L):
The number of lines actually processed is read out (Lower bytes) (0 to 65535)
d0 to 7 (LINE_H):
The number of lines actually processed is read out (Upper bytes)
When the number of lines processed number of lines set, coding/decoding/through stops
temporarily/end of processing.
Note: The number of lines to be processed by this processing is cleared to 0 by the issuance of
process start command.
(9) Data write in buffer (W) (See note 1)
(Address: A)
d7
d0
DWR_BUF_L:
(Address: B)
DWR_L
DWR_BUF_H:
DWR_H
d0 to 7 (DWR_L):
This writes in the coded data/image data/context table RAM data (Lower bytes)
d0 to 7 (DWR_H):
This writes in the coded data/image data/context table RAM data (Upper bytes)
(10) Data read out buffer (R) (See note 1)
(Address: A)
d7
d0
DRD_BUF_L:
(Address: B)
DRD_L
DRD_BUF_H:
DRD_H
d0 to 7 (DRD_L):
This read out the coded data/image data/context table RAM data. (Lower bytes)
d0 to 7 (DRD_H):
This read out the coded data/image data/context table RAM data. (Upper bytes)
Note: 1. Address A is used with 8-bit bus. In case of the 16-bit bus, only the word access is possible. (Not byte
access) If the number of coded data bytes is an odd number during coding, an one byte pad ("00") is
attached after the end marker is issued in order to use it as a word boundary.
See table 1 for the bit arrangement used during the coded data/image data. In case of the context table RAM
data, only the lower byte becomes valid data regardless of the bus width of the host bus (BUS16).
Table 3 Context Data Lineup
Host I/F
Bus Width
8-bit
16-bit
Note:
Upper Address (B)
d15
•••••
—
-—
Lower Address (A)
d8
mps: Superior symbol MPS (expected value 0/1)
s6 to 0: Status number ST (0 to 112)
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 14 of 33
d7
mps
mps
d6
s6
s6
•••••
•••••
•••••
d0
s0
s0
M65761FP
(11) Marker code set up register (W)
(Address: C)
MSET_REG:
d0 to 7 (MSET):
d7
d0
MSET
The end marker code used during coding is set. (SDNORM = 02h, SDRST = 03h)
The byte set to this register is outputted as the end marker during coding.
(12) Marker code read out register (R)
(Address: C)
MDET_REG:
d0 to 7 (MDET):
d7
d0
MDET
The marker codes detected during decoding are read out.
(SDNORM = 02h, SDRST = 03h, ABORT = 04h, etc.)
The marker codes detected during decoding read out as is.
(13) This register sets up various functions (W/R)
(Address: D)
CONV_REG:
d7
d0
TP
LI
OB
HO
HR
VR
HE
d0 (VE):
Selects expansion in lengthwise direction during decoding. (0: Equal dimension, 1: 2 expansion)
d1 (HE):
Selects expansion sideways during decoding. (0: Equal dimension, 1: 2 expansion)
VE
d0 and d1 are possible only during decoding.
d2 (VR):
Selects reduction in lengthwise direction during coding. (0: Equal dimension, 1: 1/2 reduction)
d3 (HR):
Selects sideways reduction during coding. (0: Equal dimension, 1: 1/2 reduction)
d2 and d3 are possible only during coding.
d4 (HO):
Selects thinning in sideways direction during coding. (0: Simple thinning, 1: OR processing)
This reduction is valid only during coding.
d5 (OB):
Notes: 1. This lengthwise 1/2 reduction during coding is used for the simple thinning. (Odd lines are
skipped)
2. The number of lines for image data to be inputs when VR = 1 for coding must be twice the
value set by the register which sets the number of lines.
3. The number of lines for image data to be outputs when VE = 1 for decoding must be twice the
value set by the register which sets the number of lines.
This selects if the leading 1 byte is discarded during decoding. (0: Normal processing (No discarding), 1:
The leading 1 byte is discarded)
If a command to start processing the first the stripe decoding is issued during decoding while OB is set to
"1", the leading 1 byte of the input data is discarded. (Not used for decoding) If OB = 0, the one of byte
discarding process is not used. (Normal decoding used) For example, this function is used by the Host 16
bits bus when the leading 1 byte of the input data word is an invalid data.
Note: Selecting this function is valid in case of the host 8 bits bus and the external context mode also.
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 15 of 33
M65761FP
d6 (LI):
Line memory initialization is prohibited. (0: Initialization specified, 1: Initialization prohibited)
When a command to start processing coding/decoding of the first stripe is issued, if L1 = 1, the
initialization of the internal line memory is prohibited. (The last image data of the immediately prior
coding/decoding left in the line memory is used as the leading reference line data of the next
coding/decoding.) When LI = 0, the internal line memory is initialized. (All white (0) data is used as the
leading reference line data of the next coding/decoding.) In case when the previous stripe ended with
SDNORM during coding/decoding of multi-stripe by setting this bit in the initialization prohibit (1).
Note: Even when LI = 1 is set, this LI bit is cleared (0) and the internal line memory will be initialized
the same line due to the fact that the H/W reset is written into the external reset terminal or the
system set up register.
d7 (TP):
This selects the typical prediction when coding and decoding. (0: Typical prediction OFF, 1: Typical
prediction ON)
Initialization of Register
Each register is initialized as shown in the table below by writing H/W reset to the external RESET terminals or the
system set up registers.
Table 4 Initialization Values for Registers
Registers
Initialization Values
Note
System set up
Parameter set up
00h
00h
Command
Status
00h
00h
Interrupt enable
Number of pixels set up
00h
00h
Set up number of lines
Number of lines processed
00h
00h
Data buffer
Marker code set up
Indefinite
00h
Marker code read out
Various functions set up
00h
00h
Note:
When writing H/W RESET into the System Setup Register, the value written into is set up in the System Setup
Register.
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 16 of 33
M65761FP
Sequence of Setting Up Registers
(1) Initialization sequence of the internal line memory and context table RAM
This sequence starts with the initialization set up (see note) of internal line memory by the H/W RESET. It is
followed by the initialization of the context table RAM. (Clear)
1
d7
H/W Reset
Context mode set up
d0
SYS_REG:
0
0
0
0
0
0
0
1
SYS_REG:
0
0
0
0
C
0
0
0
; H/W reset bit ON
; H/W reset bit OFF
; C = Context mode set up
The ON time for H/W RESET bit (The time from d0 = "1" is written
in to the time when d0 = "0" is written in) should be 100 ns more.
Context table RAM
Initialization command issued
Interrupt enable set up
CMD_REG:
0
0
0
0
0
0
0
1
; Context table initialized
IENB_REG:
0
0
0
0
0
0
0
1
; Process end interrupt enable
[During this time, the context table RAM is initialized.]
The number of clocks needed for initialization is as follows,
When the internal text mode is used.
1024 + [clocks]
When the external text mode is used. 4096 + [clocks]
(Interrupt generation)
d7
d0
Set up interrupt enable
IENB_REG:
0
0
0
0
0
0
0
1
; Interrupt disable
Status register read out
(Check if processing finished)
STAT_REG:
−
−
−
−
−
−
−
j
; j = End of processing
CMD_REG:
0
0
0
0
0
0
0
0
; End of initialization
j=1?
N
(Error)
Y
End of initialization command
to 2
Note:
Initialization of the line memory by H/W RESET is provided for the start of coding and decoding by
preparing the all white (0) data as a reference line. At the same time, it initializes the LNTP bit to
LNTP = 1 for the Typical Prediction.
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 17 of 33
M65761FP
(2) Coding/decoding of stripes (no change in the AT pixel position)/image data through processing sequence
2
d7
System set up
(LSI mode set up)
SYS_REG:
b
d0
p
x
s
C m m
0
c/a l/a
t
a
a
a
Parameter set up
(Template, context)
PARA_REG:
Set up number of pixels
PEL_REG_L:
PEL_REG_H:
Set up number of lines
LSET_REG_L:
LSET_REG_H:
lset_h
Set up marker code
(Note: coding only)
MSET_REG:
mset
Set up functions
CONV_REG:
Tp Li Ob Ho Hr Vr He Ve
a
a
pel_l
0
0
; mm = Operating mode (Coding/decoding)
; C = Context selection (Internal/external)
; s, x = Bit, byte swap
; p, b = Image data I/F, bit width
; aa,aaaaa = AT pixel position
; t = Template selection
; l = Conditions to take in external context
; c = External context CX0 selects
; pel_l, pel_h = Number of pixels per line
pel_h
lset_l
; lset_l, lset_h = Number of lines processed
Note: Set Li to "0" when it is the leading
stripe of single or multi stripe.
; mset = marker code byte set up
(SDNORM = 02h, SDRST = 03h)
; Ve, He = Select expansion during decoding
; Vr, Hr, Ho = Select reduction during coding
; Ob = Select discarding leading 1 byte during decoding
; Tp = ON/OFF of typical prediction function
; Li = Select prohibiting initialization of line memory
Process start command
(Coding/decoding/through)
CMD_REG:
0
0
0
0
0
0
1
0
; End of trailer processing (Coding/decoding/through)
start command
Set up interrupt enable
IENB_REG:
0
0
0
0
0
0
0
1
; Processing end interrupt enable
When the external context mode is used, it is not necessary to set the position of AT pixels, number of
pixels, number of lines, and expansion, reduction/typical prediction/line memory initialization selection.
(They will be invalid)
[Coding and decoding are performed during this time]−−−I/O of image data and code data is performed.
(Coding and decoding of stripe is performed.)
(Interrupt is generated)
d7
d0
Interrupt disable is set up
IENB_REG:
0
0
0
0
0
0
0
0
; Interrupt disable
Status register is read out
(Check end of processing)
STAT_REG:
−
−
−
s
−
rn
−
j
; j = End of processing
; m = Marker detection
; s = SC counter overflow
N
j=1?
(Error)
Y
N (Coded)
Decoded ?
Y
s=0?
(Decoded)
(Error)
N (Marker not yet detected)
Y
m=1?
Y
(Error)
(Marker detected)
Marker code read out
Note: only for decoding
N (SC counter overflow)
MDET_REG:
End
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 18 of 33
End
mdet
; mdet = marker code read out
M65761FP
(3) Processing sequence of coding/decoding of stripes (internal context mode and AT pixel position may change)
2
System set up
(LSI mode set up)
d7
d0
SYS_REG:
b
p
x
s
C m m
0
Parameter set up
(Template, AT pixel position)
PARA_REG:
a
a
t
a
a
a
Set up number of pixels
PEL_REG_L:
PEL_REG_H:
0
0
Set up number of lines
LSET_REG_L:
LSET_REG_H:
lset_h
MSET_REG:
mset
CONV_REG:
Tp Li Ob Ho Hr Vr He Ve
Set up marker code
(Note: coding only)
Set up various functions
a
a
pel_l
; mm = Operating mode (Coding/decoding)
; C = 0 Internal context selected
; s, x = Bit and byte swap
; p, b = Image data I/F, bit width
; aa,aaaaa = AT pixel position
; t = Template selection
; pel_l, pel_h = Number of pixels per 1 line
pel_h
; lset_l, lset_h = Number of lines process
lset_l
Note: The number of lines up to the point
where AT pixel position is changed is set.
Note: Set Li to "0" when the leading
stripe of single or multi stripe is used.
; mset = Marker code byte set up
(SDNORM = 02h, SDRST = 03h)
; Ve, He = Expansion selection for decoding
; Vr, Hr, Ho = Select reduction during coding
; Ob = Select discarding leading 1 byte when coding
; Tp = ON/OFF of typical prediction function
; Li = Select prohibiting initialization of line memory Note
Process start command
(Stop processing temporarily)
CMD_REG:
0
0
0
0
1
0
1
0
; Stop processing temporarily (Coding/decoding)
Set up interrupt enable
IENB_REG:
0
0
0
0
0
0
0
1
; Processing stop interrupt enable
[Coding/decoding go on during this time]−−−I/O of the first image data and code data take place.
Note: During the first processing, if it is coding, (the number of lines of the input image data) =
(the value set in the register which sets the number of lines) + 1
During decoding, (number of lines of the output image data) = (the value set in the register which sets the number of lines) − 1
(Interrupt is generated)
d7
Interrupt disable is set up
Status register is read out
Set up
the last AT
d0
IENB_REG:
0
0
0
0
0
0
0
0
; Interrupt disable
STAT_REG:
−
−
p
−
−
−
−
j
; Status check
; j = 0, p = 1, temporary check
Last set up
Go to 3
Middle of set up
Set up AT pixel position
PARA_REG:
Set up number of lines
LSET_REG_L:
LSET_REG_H:
a' a'
t
a' a' a' a' a'
; AT pixel change set up (a'a', a'a'a'a'a')
Note: Template not to be changed
; lset_l, lset_h = Number of lines process
to Next page
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 19 of 33
lset_l
lset_h
Note: Set up the number of lines to be processed from
the time processing restarted to the position where
next the next AT pixel is changed.
M65761FP
This routine is repeated the (AT move − 1) times
(To previous page)
Process start command
(Temporary stop command)
CMD_REG:
0
0
0
0
1
0
1
0
; Command to restart processing which stopped
temporarily (Coding/decoding)
Set up interrupt enable
IENB_REG:
0
0
0
0
0
0
0
1
; Processing end interrupt enable
[Coding and decoding are performed during this time]−−−I/O of image data and code data is performed.
Note: During the above processing the following is true.
During coding,
(The number of lines of the input image data) = (Number of lines set in the line number setting register)
During decoding,
(Number of lines of the output image data) = (Number of lines set in the line number setting register)
(Interrupt is generated)
d7
d0
Interrupt disable is set up
IENB_REG:
0
0
0
0
0
0
0
0
; Interrupt disable
Status register is read out
(Check end of processing)
STAT_REG:
−
−
−
s
−
m
−
j
; j = End of processing
; m = Marker detection
; s = SC counter overflow
N
j=1?
(Error)
Y
N (Coded)
Decoded ?
Y
s=0?
(Decoded)
N (SC counter overflow)
(Error)
Y
N (Marker not yet detected)
m=1?
End
(Error)
Y
(Marker detected)
Marker code read out
Note: only for decoding
MDET_REG:
End
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 20 of 33
mdet
; mdet = Marker code read out
M65761FP
(4) Read out/write in sequence of context table RAM
This sequence dies R/W of context table RAM.
d7
Set context mode
Start command for R/W
of RAM
d0
SYS_REG:
−
−
−
−
C
−
−
0
; H/W reset bit OFF
; C = Context mode set
CMD_REG:
0
0
0
0
0
1
0
0
; Start of R/W context table RAM
[Reading (writing) of context table RAM continues during this time.]
RAM data is outputted (inputted) by way of data read (write) buffer.
The RAM address is automatically incremented every time 1 byte is read out (write in).
Note: It is not possible to mix reading and writing.
End of R/W command of RAM
CMD_REG:
0
0
0
0
0
0
0
0
; End of R/W command of RAM
This does not end automatically.
Be sure to write the end of R/W command.
Note: The assignment of address for context table RAM is as follows
Internal context mode: Address 0 to 1023 of (LSB: 0, MSB: 9) as shown below.
External context mode: Address 0 to 4095 of (LSB: CX0, MSB: CS11)
8 7 6
5 4 3 2 9
1 0 ?
3-line template
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 21 of 33
8 5 4 3 2 9
7 6 1 0 ?
2-line template
(AT pixel is MSB: 9)
M65761FP
(5) Overall sequence of multi-stripe coding/decoding
The image whose 1 page is composed of multiple stripes must perform (2) or (3) by stripes after the initialization of
(1).
multi-stripe
coding/decoding
Internal memory & context
table RAM are initialized.
(1) processing
Coding/decoding of 1st stripe
(2) or (3) processing
All stripes
process ended?
Y
End of page
This routine is repeated (Number of stripes − 1)
N
Notes:
Is the previous
stripe SDNORM?
Y
(SDNORM)
Stripe coding/decoding
(Line memory initialization
prohibited: Li = 1, AT pixel =
the value of previous stripe
[(2) or (3) is processed]
N (SDRST)
Initialization of internal
line memory and context table RAM
(1) processing
stripe coding/decoding
process (line memory
initialization is specified
by Li = 0, AT pixel = default
position (0)
[(2) or (3) is processed]
1. When 16-bit bus is used for the host-bus during coding, in order to use the word boundary, the
pad byte ("00") 1 byte long tends to follow behind the end marker code of each stripe. This
must be eliminated externally.
2. When starting decoding of each stripe (during decoding), inputting must start from the leading
coded data of SDE (stripe data entity). If necessary, the leading 1 byte is discarded. (In case
when the leading portion of coded data of the next stripe is already inputted in LSI (FIFO) or
when it is not lined up with the lead boundary during decoding of each stripe ends, external
management is needed.
3. Management of marker codes (AT MOVE, NEWLEN, etc.) processing (insertion at the time of
coding and detection/removing at the time of decoding) should be done externally.
Description
If the end marker of the stripe one before is SDNORM, do not initialize the line memory nor the context table RAM.
The AT pixel position will use the last value of the previous stripe and starts processing next stripe. In case of SDRST,
initialization takes place first and then the AT pixel position is returned to the default position. Then the processing of
the next stripe begins.
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 22 of 33
M65761FP
Timing Characteristics 1
(Ta = –20 to +70°C, VCC = 5 V ± 10% unless otherwise noted)
1) Host Bus I/F
Item
D0 to 15 output define
time for RD assert
D0 to 15 output hold
time for RD assert
DMARQ negate time
for DMAAK assert
Min
Limits
Typ
Max
Unit
Test Circuit
tPZL
(RD-D0 to 15)
tPZH
(RD-D0 to 15)
0
—
30
ns
1
0
—
30
ns
tPLZ
(RD-D0 to 15)
tPHZ
(RD-D0 to 15)
0
—
30
ns
0
—
30
ns
tPHL
(DMAAK-DMARQ)
—
—
20
ns
Symbol
Test
Conditions
CL = 50 pF
2) Image Data I/F
Limits
Item
Symbol
Min
—
Typ
—
Max
30
Unit
Test Circuit
ns
1
PRDY negate time for
PTIM assert
tPLH
(PTIM-PRDY)
RVID output define
time for the fall of
PXCK
tPHL
(PXCK-RVID)
tPLH
(PXCK-RVID)
—
—
25
ns
—
—
25
ns
PXCKO delay time for
PXCK
tPHL
(PXCK-PXCKO)
tPLH
(PXCK-PXCKO)
—
—
15
ns
—
—
15
ns
RVID output define
time for the fall of
PXCKO
tPHL
(PXCKO-RVID)
tPLH
(PXCKO-RVID)
—
—
10
ns
—
—
10
ns
RVID negate time for
PTIM negate
PDRQ negate time for
PDAK assert
tPLH
(PTIM-RVID)
tPHL
(PDAK-PDRQ)
0
—
—
ns
—
—
20
ns
PD0 to 31 output
define time for PDRD
assert
tPZL
(PDRD-PD0 to 31)
tPZH
(PDRD-PD0 to 31)
0
—
30
ns
0
—
30
ns
PD0 to 31 hold time for
PDRD negate
tPLZ
(PDRD-PD0 to 31)
tPHZ
(PDRD-PD0 to 31)
0
—
30
ns
0
—
30
ns
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 23 of 33
Test
Conditions
CL = 50 pF
M65761FP
3) Context I/F
Limits
Item
Symbol
Min
—
Typ
—
Max
30
Unit
Test Circuit
ns
1
XRDY negate time for
XTIM assert time
tPLH
(XTIM-XRDY)
RPIX output define
time for the fall of
XCLK
tPLH
(XCLK-RPIX)
tPHL
(XCLK-RPIX)
0
—
30
ns
0
—
30
ns
XCLK delay time for
MCLK
tPLH
(MCLK-XCLK)
tPHL
(MCLK-XCLK)
—
—
30
ns
—
—
30
ns
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 24 of 33
Test
Conditions
CL = 50 pF
M65761FP
Timing Characteristics 2
(Ta = –20 to +70°C, VCC = 5 V ± 10% unless otherwise noted)
1) Host Bus I/F
Item
Symbol
Min
Limits
Typ
Max
Unit
RESET assert time
CS set up time for RD
asset
tw (RESET)
tsu (RD-CS)
100
20
—
—
—
—
ns
ns
CS hold time for RD
negate
A0 to 3 set up time for
RD assert
th (RD-CS)
20
—
—
ns
tsu (RD-A0 to 3)
20
—
—
ns
tsu (RD-BHE)
20
—
—
ns
tw (RD)
30
—
—
ns
th (RD-A0 to 3)
20
—
—
ns
th (RD-BHE)
20
—
—
ns
tsu (WR-CS)
20
—
—
ns
th (WR-CS)
20
—
—
ns
tsu (WR-A0 to 3)
20
—
—
ns
tsu (WR-BHE)
20
—
—
ns
WR assert time
A0 to 3 hold time for WR
negate
tw (WR)
th (WR-A0 to 3)
30
20
—
—
—
—
ns
ns
BHE hold time for WR
negate
D0 to 15 input set up
time for WR negate
th (WR-BHE)
20
—
—
ns
tSU (WR-D0 to 15)
20
—
—
ns
D0 to 15 input hold time
for WR negate
DMAAK set up time for
RD assert
th (WR-D0 to 15)
20
—
—
ns
tsu (RD-DMAAK)
20
—
—
ns
DMAAK hold time for RD
negate
DMAAK set up time for
WR assert
th (RD-DMAAK)
20
—
—
ns
tsu (WR-DMAAK)
20
—
—
ns
DMAAK hold time for
WR negate
th (WR-DMAAK)
20
—
—
ns
BHE set up time for RD
asset
RD asset time
A0 to 3 hold time for RD
negate
BHE hold time for RD
negate
CS set up time for WR
assert
CS hold time for WR
negate
A0 to 3 set up time for
WR assert
BHE set up time for WR
assert
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 25 of 33
Test
Circuit
1
Test
Conditions
CL = 50 pF
M65761FP
2) Image Data I/F
Limits
Item
Symbol
Typ
—
Max
—
Unit
Test
Circuit
ns
1
MCLK period (Mx)
when used image
data I/F
tci (MCLK)
Min
50
MCLK high level time
(Mh) when used
image data I/F
MCLK low level time
(Ml) when used
image data I/F
twi+ (MCLK)
20
—
—
ns
twi– (MCLK)
20
—
—
ns
MCLK rising time
when used image
data I/F
MCLK falling time
when used image
data I/F
tri (MCLK)
—
—
20
ns
tfi (MCLK)
—
—
20
ns
PTIM set up time for
the fall of PXCK
PTIM hold time for
the rise of PXCK
tsu (PXCK-PTIM)
20
—
—
ns
th (PXCK-PTIM)
20
—
—
ns
PXCK high time
PXCK low time
tw+ (PXCK)
tw– (PXCK)
20
20
—
—
—
—
ns
ns
PXCK period
SVID set up time for
the fall of PXCK
tc (PXCK)
tsu (PXCK-SVID)
50
10
—
—
—
—
ns
ns
SVID hold time for
the rise of PXCK
PDAK set up time for
PDRD assert
th (PXCK-SVID)
10
—
—
ns
tsu (PDRD-PDAK)
20
—
—
ns
PDAK hold time for
PDRD negate
PDRD assert time
th (PDRD-PDAK)
20
—
—
ns
tw (PDRD)
30
—
—
ns
PDAK set up time for
PDWR assert
PDAK hold time for
PDWR negate
tsu (PDWR-PDAK)
20
—
—
ns
th (PDWR-PDAK)
20
—
—
ns
PDWR assert time
PD0 to 31 input set
up time for PDWR
negate
tw (PDWR)
tsu (PDWR-PD0 to 31)
20
20
—
—
—
—
ns
ns
PD0 to 31 input hold
time for PDWR
negate
th (PDWR-PD0 to 31)
20
—
—
ns
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 26 of 33
Test
Conditions
CL = 50 pF
M65761FP
3) Context I/F
Limits
Item
Symbol
Typ
—
Max
—
Unit
Test
Circuit
ns
1
MCLK period (Mx)
when used context I/F
tcc (MCLK)
Min
100
MCLK high level time
(Mh) when used
context I/F
MCLK low level time
(Ml) when used context
I/F
twc+ (MCLK)
40
—
—
ns
twc– (MCLK)
40
—
—
ns
MCLK rising time when
used context I/F
MCLK falling time
when used context I/F
trc (MCLK)
—
—
20
ns
tfc (MCLK)
—
—
20
ns
XTIM assert time for
the rise of MCLK
XTIM negate time for
the rise of XCLK
tsu (MCLK-XTIM)
20
—
—
ns
th (XCLK-XTIM)
—
—
20
ns
XCLK high time
XCLK low time
tw+ (XCLK)
tw– (XCLK)
—
—
Mh
Ml
—
—
ns
ns
XCLK period
XWAIT negate time for
the rise of XCLK
tc (XCLK)
th (XCLK-XWAIT)
—
0
Mx
—
—
10
ns
ns
CX0 to 11 set up time
for the rise of XCLK
PEUPE set up time for
the rise of XCLK
tsul (XCLK-CX0 to 11)
20
—
—
ns
tsul (XCLK-PEUPE)
20
—
—
ns
SPIX set up time for
the rise of XCLK
CX0 to 11 hold time for
the rise of XCLK
tsul (XCLK-SPIX)
20
—
—
ns
thl (XCLK-CX0 to 11)
20
—
—
ns
PEUPE hold time for
the rise of XCLK
SPIX hold time for the
rise of XCLK
thl (XCLK-PEUPE)
20
—
—
ns
thl (XCLK-SPIX)
20
—
—
ns
CX0 to 11 set up time
for the rise of XCLK
SPIX set up time for
the rise of XCLK
tsut (XCLK-CX0 to 11)
70
—
—
ns
tsut (XCLK-SPIX)
70
—
—
ns
CX0 to 11 hold time for
the rise of XCLK
SPIX hold time for the
rise of XCLK
tht (XCLK-CX0 to 11)
20
—
—
ns
tht (XCLK-SPIX)
20
—
—
ns
PEUPE input define
time for the rise of
XCLK
tk (XCLK-PEUPE)
—
—
20
ns
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 27 of 33
Test
Conditions
CL = 50 pF
M65761FP
Test Circuit
Input
1
Output
VCC
VCC
RL = 1 kΩ
SW1
PG
DUT
SW2
50 Ω
GND
Item
SW1
SW2
tPLH, tPHL
Open
Open
tPLZ
Close
Open
tPHZ
Open
Close
tPZL
Close
Open
tPZH
Open
Close
CL
RL = 1 kΩ
(1) Characteristic of pulse generation (PG) (10% to 90%)
tr = 3 ns, tf = 3 ns
(2) Capacitance CL includes stray wiring capacitance and
probe input capacitance.
Master Clock
tci (MCLK)
tcc (MCLK)
twi+ (MCLK)
twc+ (MCLK)
tfi (MCLK)
tfc (MCLK)
tri (MCLK)
trc (MCLK)
twi− (MCLK)
twc− (MCLK)
90%
90%
MCLK
10%
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 28 of 33
10%
M65761FP
Host Bus I/F
(1) MPU Access
RESET
tw
(RESET)
CS
tsu
(RD-CS)
tsu
(WR-CS)
th
(RD-CS)
th
(WR-CS)
A0 to 3
BHE
tw (RD)
tsu
(RD-A0 to 3)
th
(RD-A0 to 3)
th
(RD-BHE)
tsu
(RD-BHE)
th
(WR-A0 to 3)
tsu
(WR-A0 to 3)
tsu
(WR-BHE)
RD
th
(WR-BHE)
tw (WR)
WR
tPZL
(RD-D0 to 15)
tPLZ
(RD-D0 to 15)
D0 to 15
50%
tsu
(WR-D0 to 15)
10%
tPZH
(RD-D0 to 15)
D0 to 15
90%
tPHZ
(RD-D0 to 15)
th
(WR-D0 to 15)
Input
50%
(2) DMA Access
DMARQ
50%
tPHL
(DMAAK-DMARQ)
DMAAK
tsu
(RD-DMAAK)
tw (RD)
th
(RD-DMAAK)
RD
tsu
(WR-DMAAK)
WR
tPZL
(RD-D0 to 15)
tPLZ
(RD-D0 to 15)
50%
D0 to 15
10%
D0 to 15
th
(WR-DMAAK)
tw (WR)
tPZH
(RD-D0 to 15)
90%
50%
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 29 of 33
tPHZ
(RD-D0 to 15)
tsu
(WR-D0 to 15)
Input
th
(WR-D0 to 15)
M65761FP
Image Data I/F
(1) Serial Image Data I/F
50%
PRDY
tPLH
(PTIM-PRDY)
PTIM
tc (PXCK)
tsu
(PXCK-PTIM)
th
(PXCK-PTIM)
tw− (PXCK)
tw+ (PXCK)
PXCK
tPHL
(PXCK-RXCKO)
tPLH (PXCK-RXCKO)
tPLH (PXCKO-RVID)
PXCKO
tPHL (PXCKO-RVID)
tPLH
(PXCK-RVID)
tPHL (PXCK-RVID)
50%
PVID
tPLH
(PTIM-RVID)
50%
tsu
(PXCK-SVID)
50%
th
(PXCK-SVID)
SVID
(2) Parallel Image Data
PDRQ
50%
tPHL
(PDAK-PDRQ)
PDAK
tsu
(PDRD-PDAK)
th
(PDRD-PDAK)
tw (PDRD)
PDRD
tsu
(PDWR-PDAK)
th
(PDWR-PDAK)
tw (PDWR)
PDWR
tPZL
(PDRD-PD0 to 31)
tPLZ
(PDRD-PD0 to 31)
50%
PD0 to 31
10%
tPZH
(PDRD-PD0 to 31)
90%
50%
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 30 of 33
tsu
(PDWR-PD0 to 31)
tPHZ
(PDRD-PD0 to 31)
Input
th
(PDWR-PD0 to 31)
M65761FP
Context I/F
(1) Latch Input Mode
XRDY
50%
tPLH
(XTIM-XRDY)
XTIM
tsu
(MCLK-XTIM)
MCLK
tPHL
(MCLK-XCLK)
tPLH
(MCLK-XCLK)
XWAIT
th
(XCLK-XTIM)
tc (XCLK)
th
(XCLK-XWAIT)
tw−
(XCLK)
XCLK
tw+
(XCLK)
tsul
(XCLK-CX0 to 11)
thl
(XCLK-CX0 to 11)
tsul
(XCLK-PEUPE)
thl
(XCLK-PEUPE)
tsul
(XCLK-SPIX)
thl
(XCLK-SPIX)
CX0 to 11
PEUPE
SPIX
tPHL
(XCLK-SPIX)
RPIX
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 31 of 33
50%
tPLH
(XCLK-SPIX)
50%
M65761FP
(2) Through Input Mode
XRDY
50%
tPLH
(XTIM-XRDY)
XTIM
tsu
(MCLK-XTIM)
MCLK
tPHL
(MCLK-XCLK)
tPLH
(MCLK-XCLK)
XWAIT
tc (XCLK)
th
(XCLK-XWAIT)
tw−
(XCLK)
th
(XCLK-XTIM)
XCLK
tw+
(XCLK)
tsut
(XCLK-CX0 to 11)
tht
(XCLK-CX0 to 11)
tsut
(XCLK-SPIX)
tht
(XCLK-SPIX)
CX0 to 11
SPIX
tk
(XCLK-PEUPE)
PEUPE
tPLH
(XCLK-RPIX)
RPIX
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 32 of 33
50%
tPHL
(XCLK-RPIX)
50%
M65761FP
Package Dimensions
JEITA Package Code
P-QFP100-14x20-0.65
RENESAS Code
PRQP0100JB-A
Previous Code
100P6S-A
MASS[Typ.]
1.6g
HD
*1
D
80
51
81
50
HE
*2
E
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
ZE
Reference
Symbol
100
31
30
c
F
A2
Index mark
ZD
A1
A
1
L
*3
e
y
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Page 33 of 33
bp
Detail F
D
E
A2
HD
HE
A
A1
bp
c
e
y
ZD
ZE
L
Dimension in Millimeters
Min Nom Max
19.8 20.0 20.2
13.8 14.0 14.2
2.8
22.5 22.8 23.1
16.5 16.8 17.1
3.05
0.1 0.2
0
0.25 0.3 0.4
0.13 0.15 0.2
0°
10°
0.5 0.65 0.8
0.10
0.575
0.825
0.4 0.6 0.8
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
http://www.renesas.com
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .7.0