PRELIMINARY CMOS SRAM KM68V257C Document Title 32Kx8 Bit High Speed Static RAM(3.3V Operating), Evolutionary Pin out. Revision History Rev No. History Draft Data Remark Rev. 0.0 Initial release with Preliminary. Jun. 1st, 1994 Preliminary Rev. 1.0 Release to final Data Sheet. 1. Delete Preliminary Oct. 4th, 1994 Final Rev. 2.0 2.1. Add 28-TSOP1 Package. Feb. 22th, 1996 Final Rev. 3.0 3.1. Delete DIP Package. 3.2. Delete 20ns part 3.3. Add Capacitive load of the test environment in A.C test load Feb. 25th, 1998 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Rev 3.0 February 1998 PRELIMINARY CMOS SRAM KM68V257C 32K x 8 Bit High-Speed CMOS Static RAM (3.3V Operating) FEATURES GENERAL DESCRIPTION • Fast Access Time 15, 17ns(Max.) • Low Power Dissipation Standby (TTL) : 30mA(Max.) (CMOS) : 0.1mA(Max.) Operating KM68V257C - 15 : 90mA(Max.) KM68V257C - 17 : 80mA(Max.) • Single 3.3±0.3V Power Supply • TTL Compatible Inputs and Outputs • Fully Static Operation - No Clock or Refresh required • Three State Outputs • 2V Minimum Data Retention; L-ver. only • Standard Pin Configuration KM68V257CJ : 28-SOJ-300 KM68V257CTG : 28-TSOP1-0813, 4F The KM68V257C is a 262,144-bit high-speed Static Random Access Memory organized as 32,768 words by 8 bits. The KM68V257C uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM68V257C is packaged in a 300mil 28-pin plastic SOJ or TSOP1 forward. PIN CONFIGURATION(Top View) OE A11 A9 A8 A13 WE Vcc A14 A12 A7 A6 A5 A4 A3 FUNCTIONAL BLOCK DIAGRAM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pre-Charge-Circuit Clk Gen. A14 1 28 Vcc A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 A6 A7 A8 A12 Row Select A4 A5 Memory Array 512 Rows 64x8 Columns A3 7 Data Cont. I/O Circuit Column Select CLK Gen. SOJ A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 A0 A1 A2 22 OE A2 8 21 A10 A1 9 20 CS A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 Vss 14 15 I/O4 A13 A14 I/O1~I/O8 TSOP1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PIN FUNCTION A0 A1 A2 A9 A10 A11 Pin Name A0 - A14 CS WE OE WE Write Enable CS Chip Select OE Output Enable I/O1 ~ I/O8 -2- Pin Function Address Inputs Data Inputs/Outputs VCC Power(+3.3V) VSS Ground Rev 3.0 February 1998 PRELIMINARY CMOS SRAM KM68V257C ABSOLUTE MAXIMUM RATINGS* Parameter Symbol Voltage on Any Pin Relative to VSS Rating Unit VIN, VOUT -0.5 to 4.6 V VCC -0.5 to 4.6 V Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature PD 1.0 W TSTG -65 to 150 °C TA 0 to 70 °C * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C) Parameter Symbol Min Typ Max Unit Supply Voltage VCC 3.0 3.3 3.6 V Ground VSS 0 0 0 V Input High Voltage VIH 2.2 - VCC+0.3** V Input Low Voltage VIL -0.3* - 0.8 V * VIL(Min) = -2.0(Pulse Width ≤ 12ns) for I ≤ 20mA ** VIH(Max) = VCC+2.0V(Pulse Width ≤ 12ns) for I ≤ 20mA DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C,VCC=3.3±0.3V, unless otherwise specified) Parameter Symbol Test Conditions Min Max Unit Input Leakage Current ILI VIN = VSS to VCC -2 2 µA Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL VOUT = VSS to VCC -2 2 µA Operating Current ICC Min. Cycle, 100% Duty CS=VIL, VIN = VIH or VIL, IOUT=0mA 15ns - 90 mA 17ns - 80 ISB Min. Cycle, CS=VIH - 30 mA ISB1 f=0MHz, CS≥VCC-0.2V, VIN≥VCC-0.2V or VIN≤0.2V - 0.1 mA Output Low Voltage Level VOL IOL=8mA - 0.4 V Output High Voltage Level VOH IOH=-4mA 2.4 - V Standby Current CAPACITANCE*(TA=25°C, f=1.0MHz) Symbol Test Conditions MIN Max Unit Input/Output Capacitance Item CI/O VI/O=0V - 8 pF Input Capacitance CIN VIN=0V - 7 pF * Capacitance is sampled and not 100% tested. -3- Rev 3.0 February 1998 PRELIMINARY CMOS SRAM KM68V257C AC CHARACTERISTICS(TA=0 to 70°C, VCC=3.3±0.3V, unless otherwise noted.) TEST CONDITIONS Parameter Value Input Pulse Levels 0V to 3V Input Rise and Fall Times 3ns Input and Output timing Reference Levels 1.5V Output Loads See below Output Loads(A) Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +3.3V RL = 50Ω DOUT 319Ω VL = 1.5V ZO = 50Ω DOUT 30pF* 353Ω 5pF* * Including Scope and Jig Capacitance * Capacitive Load consists of all components of the test environment. READ CYCLE Parameter KM68V257C-15 Symbol Min KM68V257C-17 Max Min Max Unit Read Cycle Time tRC 15 - 17 - ns Address Access Time tAA - 15 - 17 ns Chip Select to Output tCO - 15 - 17 ns Output Enable to Valid Output tOE - 7 - 8 ns Chip Enable to Low-Z Output tLZ 3 - 3 - ns Output Enable to Low-Z Output tOLZ 0 - 0 - ns Chip Disable to High-Z Output tHZ 0 7 0 8 ns Output Disable to High-Z Output tOHZ 0 7 0 8 ns Output Hold from Address Change tOH 3 - 3 - ns Chip Selection to Power Up Time tPU 0 - 0 - ns Chip Selection to Power DownTime tPD - 15 - 17 ns -4- Rev 3.0 February 1998 PRELIMINARY CMOS SRAM KM68V257C WRITE CYCLE Parameter KM68V257C-15 Symbol KM68V257C-17 Min Max Min Max Unit Write Cycle Time tWC 15 - 17 - ns Chip Select to End of Write tCW 11 - 12 - ns Address Setup Time tAS 0 - 0 - ns Address Valid to End of Write tAW 11 - 12 - ns Write Pulse Width(OE High) tWP 11 - 12 - ns Write Pulse Width(OE Low) tWP1 15 - 17 - ns Write Recovery Time tWR 0 - 0 - ns Write to Output High-Z tWHZ 0 6 0 6 ns Data to Write Time Overlap tDW 8 - 8 - ns Data Hold from Write Time tDH 0 - 0 - ns End Write to Output Low-Z tOW 0 - 0 - ns TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tRC Address tOH Data Out tAA Valid Data Previous Valid Data -5- Rev 3.0 February 1998 PRELIMINARY CMOS SRAM KM68V257C TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO CS tHZ(3,4,5) tOHZ tOE OE tOLZ tOH tLZ(4,5) Data out Valid Data VCC ICC Current ISB tPU tPD 50% 50% NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) tWC Address tWR(5) tAW OE tCW(3) CS tWP(2) tAS(4) WE tDW Data in High-Z tDH Valid Data tOHZ(6) High-Z(8) Data out -6- Rev 3.0 February 1998 PRELIMINARY CMOS SRAM KM68V257C TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) tWC Address tWR(5) tAW tCW(3) CS tAS(4) tWP1(2) WE tDW Data in High-Z tDH Valid Data tWHZ(6) tOW (10) (9) High-Z(8) Data out TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled) tWC Address tAW tWR(5) tCW(3) CS tAS(4) tWP(2) WE tDW Data in High-Z Valid Data tLZ Data out tDH High-Z tWHZ(6) High-Z(8) High-Z NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. -7- Rev 3.0 February 1998 PRELIMINARY CMOS SRAM KM68V257C FUNCTIONAL DESCRIPTION CS WE OE Mode I/O Pin Supply Current H X X* Not Select High-Z ISB, ISB1 L H H Output Disable High-Z ICC L H L Read DOUT ICC L L X Write DIN ICC * NOTE : X means Don′t Care. DATA RETENTION CHARACTERISTICS(TA=0 to 70°C) Parameter VCC for Data Retention Symbol Test Condition Min. Typ. Max. Unit 2.0 - 3.6 V VCC = 3.0V, CS≥VCC - 0.2V - - 0.07 mA See Data Retention Wave form(below) 0 - - ns 5 - - ms VDR CS≥VCC - 0.2V Data Retention Current IDR Data Retention Set-Up Time tSDR Recovery Time tRDR DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 3.0V VIH VDR CS≥VCC - 0.2V CS GND -8- Rev 3.0 February 1998 PRELIMINARY CMOS SRAM KM68V257C PACKAGE DIMENSIONS Units:millimeters/Inches 28-SOJ-300 #28 7.62 0.300 #15 8.51 ±0.12 0.335 ±0.005 6.86 ±0.25 0.270 ±0.010 +0.10 -0.05 0.20 #1 0.008+0.004 -0.002 #14 0.69 MIN 0.027 18.82 MAX 0.741 18.41 ±0.12 0.725 ±0.005 ( 1.30 ) 0.051 ( 1.30 ) 0.051 0.43 ( 0.95 ) 0.0375 +0.10 -0.05 0.017 +0.004 -0.002 1.27 0.050 0.71 3.76 MAX 0.148 0.10 0.004MAX +0.10 -0.05 0.028+0.004 -0.002 28-TSOP1-0813.4F 0.10 MAX 0.004 MAX Units:millimeters/Inches 13.40 ±0.20 0.528 ±0.008 #28 #14 #15 ( 8.40 0.331 MAX #1 0.55 0.0217 0.25 0.010 TYP 0.425 ) 0.017 8.00 0.315 +0.10 -0.05 0.008 +0.004 -0.002 0.20 1.00 ±0.10 0.039 ±0.004 11.80 ±0.10 0.465 ±0.004 0.15 0.006 +0.10 -0.05 +0.004 -0.002 1.20 0.047 MAX 0.05 0.002 MIN 0~8° 0.45 ~0.75 0.018 ~0.030 ( -9- 0.50 ) 0.020 Rev 3.0 February 1998