FAIRCHILD FAB2210

FAB2210 — Audio Subsystem with Class-G Headphone and
3.3W Mono Class-D Speaker with Dynamic Range Compression
Features
Description

High-Efficiency Stereo Class-G Headphone
- 100dB SNR Headphone Amplifier
- Capacitor-Free Outputs for High-Frequency
Response
The FAB2210 combines a Class-G stereo capacitorfree headphone amplifier with a mono Class-D
speaker amplifier into one IC package.

Mono Filterless Class-D Speaker Amplifier
- 91% Efficiency for Extended Battery Runtime
- DRC for Louder SPL and Speaker Protection
- 3.3W into 4Ω at 5.0V, THD+N < 10%
- 1.27W into 8Ω at 4.2V, THD+N < 10%
- Low EMI Edge-Rate Controlled output
- 97dB Signal-to-Noise Ratio (SNR)


Click and Pop Suppression

High Power Supply Rejection Ration (PSRR)
Rejects 217Hz GSM Noise


Highly Configurable using I2C Control
The headphone and speaker amplifiers incorporate
Class-G and Class-D topologies, respectively, for low
power dissipation, which extends battery runtime.
The Class-G headphone amplifier incorporates an
integrated charge pump that generates a negative
supply rail for ground-centered headphone outputs.
The Class-D amplifier includes programmable
Dynamic Range Compression (DRC) that maximizes
Sound Pressure Level (SPL) for maximum loudness,
while protecting the speaker from damage.
Selectable Single-Ended or Differential Audio
Inputs for High Common-Mode Rejection
The noise gate can automatically mute the speaker or
headphone amplifiers to reduce noise when input
signals are LOW.
Low-Power, Software Standby Mode
Ordering Information
Part Number
Operating Temperature Range
Package
Packing Method
FAB2210UCX
-40°C to +85°C
20-Bump, Wafer-Level Chip-Scale
Package (WLCSP), 0.4mm Pitch
3000 Units on
Tape & Reel
Typical Application Circuit
SCL
SDA
Headphone
Volume
HVSS
0dB / 1.5dB /
3dB / 6dB
Noise
Gate
HOUTR
Mixer/
MUX
Speaker Volume
Class-D Speaker
Amp
Preamp B
-3dB to 18dB
Noise
Gate /
DRC
SOUT+
SOUT-
16dB/20dB/24dB
DGND
SGND
Figure 1.
HSENSE
-64dB to 0dB
-64dB to 0dB
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
CP-
Class-G Cap-Free
Headphone Amps
HOUTL
Preamp A
-3dB to 18dB
0.1µF
INB1
0.1µF
INB2
2.2µF
Charge
Pump
I2C
0.1µF
INA1
0.1µF
INA2
2.2µF
CP+
SVDD
2.2µF
HVDD
1.6V – 2.8V
2.2µF
DVDD
2.8V – 5.25V
10µF 2.2µF
Typical Application Circuit
www.fairchildsemi.com
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
April 2012
Figure 2.
Pin Assignments, Top View (Bump Side Down)
Pin Definitions
Pin #
Name
Type
Description
A2
SVDD
Power Input
Power supply for Class-D amplifier
C1
SGND
Power Input
Class-D amplifier ground
C2
DVDD
Power Input
Power supply for charge pump
A3
DGND
Power Input
Headphone amplifier ground
C3
HVDD
Power Output
C4
HVSS
Power Output Charge pump output; negative mirror of HVDD
B4
CP+
Power
Charge pump flying capacitor positive terminal
A4
CP-
Power
Charge pump flying capacitor negative terminal
Charge pump output; positive power supply for headphone amplifier, input
preamplifiers, and mixers
E3
NC
No Connect
D1
INA1
Input
Single-ended line level audio input A1 (or non-inverting differential input INA+)
No connect can be tied to SGND for additional thermal dissipation
E1
INA2
Input
Single-ended line level audio input A2 (or inverting differential input INA-)
D2
INB1
Input
Single-ended line level audio input B1 (or non-inverting differential input INB+)
E2
INB2
Input
E4
HOUTL
Output
Left headphone amplifier output
D4
HOUTR
Output
Right headphone amplifier output
D3
HSENSE
Input
A1
SOUT+
Output
Positive Class-D amplifier output
B1
SOUT-
Output
Negative Class-D amplifier output
B3
SCL
Input
B2
SDA
Bidirectional
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
Single-ended line level audio input B2 (or inverting differential input INB-)
Sense ground; connect to DGND close to shield terminal of headphone jack
I2C clock input
I2C data I/O
www.fairchildsemi.com
2
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
Pin Configuration
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. All voltages are referenced to GND.
Symbol
Parameter
Min.
Max.
Unit
VDD
Voltage on SVDD Pin
-0.3
6.0
V
VDVDD
Voltage on DVDD Pin
-0.3
3.2
V
VSVDD
Voltage on SVDD + DVDD Pins
VIN
8
V
(1)
Voltage on INA1, INA2, INB1, INB2 Pins
VHVSS-0.3
VHOUT
Voltage on HOUTL, HOUTR Pins
VHVSS-0.3
VDVDD+0.3
V
VSENSE
Voltage on HSENSE Pin
-0.3
0.3
V
Voltage on SDA, SCL Pins
-0.3
VSVDD
V
Voltage on SOUT+, SOUT- Pins
-0.3
VSVDD+0.3
Headphone Impedance
12.8
VD
VSOUT
RHP
VDVDD+0.3 or 2.1
V
V
Ω
Note:
1. Whichever is less.
Reliability Information
Symbol
TJ
TSTG
Parameter
Min.
Typ.
Junction Temperature
Storage Temperature Range
-65
Max.
Unit
150
°C
150
°C
300
°C
TL
Lead Temperature (Soldering, 10 Seconds)
θJA
Thermal Resistance, JEDEC Standard, Multilayer Test
Boards, Still Air
66
TSD
Thermal Shutdown Threshold
150
°C
THYS
Thermal Shutdown Hysteresis
15
°C
°C/W
Electrostatic Discharge Protection
Symbol
ESD
Parameter
Min.
Unit
Human Body Model; JESD22-A114 Level 2; Compatible with IEC61340-3-1:
2002 Level 2 or ESD-STM5.1-2001 Level 2 or MIL-STD-883E 3015.7 Level 2
±2.00
KV
Charged Device Model; JESD22-C101 Level III
Compatible with IEC61340-3-3 level C4 or ESD-STM5.3.1-1999 Level C4
±1.25
KV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
VSVDD
VDVDD
Parameter
Min.
Typ.
Max.
Unit
Operating Temperature Range
-40
85
°C
Speaker Supply Voltage Range(2,3)
2.80
3.60
5.25
V
1.6
1.8
2.8
V
Headphone Supply Voltage Range
(2,3)
Notes:
2. VSVDD must be greater than or equal to VDVDD at all times.
3. VSVDD and VDVDD slew rates must be less than 1V/µs.
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
3
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
Absolute Maximum Ratings
Unless otherwise noted: audio BW=22Hz to 20KHz, fIN=1KHz, DIFA=1, DIFB=0, HP_AMIX=0, HP_BMIX=1,
SP_AMIX=1, SP_BMIX=0, unused inputs are AC grounded, DRC is off, preamplifier gains=0dB, headphone
volume=0dB, headphone amplifier gain=0dB, speaker volume=0dB, SP_GAIN=00, edge-rate control is on, spread
spectrum is on, HP_NG_RAT=100, SP_NG_RAT=001, SRST=0, SDA and SCL pull-up voltage=DVDD, ZSPK
=8Ω+33µH, RHP=32Ω, HP_HIZ=0, SVDD=3.6V, DVDD=1.8V, and TA=25°C.
Symbol
ISTBY
tON
RIN
Parameter
Condition
Min.
Typ.
Max.
Unit
Standby Current (SRST=1)
SVDD + DVDD
2
µA
Turn-On Time
Time from Standby to Full
Speaker and Headphone
Operation, ZCD and Ramps
Disabled
1.6
ms
Preamplifier Gain=12.0dB
7.7
Preamplifier Gain=6.0dB
12.8
Preamplifier Gain=4.5dB
14.3
Preamplifier Gain=3.0dB
15.9
Preamplifier Gain=1.5dB
17.5
Preamplifier Gain=0.0dB
19.2
Preamplifier Gain=-1.5dB
20.8
Preamplifier Gain=-3.0dB
22.4
Input Resistance
Maximum Input Signal Swing Preamplifier Gain=0dB
(SVDD=2.8V to 5.25V, SinglePreamplifier Gain=12dB
Ended Input)
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
kΩ
VDVDD
Vpk-pk
VDVDD ÷ 4
Vpk-pk
www.fairchildsemi.com
4
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
Electrical Characteristics
Unless otherwise noted: audio BW=22Hz to 20KHz, fIN=1KHz, DIFA=1, DIFB=0, HP_AMIX=0, HP_BMIX=0,
SP_AMIX=1, SP_BMIX=0, unused inputs are AC grounded, DRC is off, preamplifier gains=0dB, headphone
volume=0dB, headphone amplifier gain=0dB, speaker volume=0dB, SP_GAIN=00, edge-rate control is on, spread
spectrum is on, HP_NG_RAT=000, SP_NG_RAT=000, SRST=0, SDA and SCL pull-up voltage=DVDD, ZSPK
=8Ω+33µH, RHP=32Ω, HP_HIZ=0, SVDD=3.6V, DVDD=1.8V, and TA=25°C.
Symbol
Parameter
Condition
ICC
Current Consumption
SP_NG_RAT=001
VOS
Output Offset Voltage
Volume=0dB
PSRR
Power-Supply Rejection
Ratio
THD+N
SNR
Output Power
Total Harmonic Distortion
Plus Noise
SVDD
2.7
DVDD
1.6
200mVpk-pk Ripple on
SVDD,
SP_NG_RAT=001
f=217Hz
70
f=1KHz
70
f=20KHz
63
f=217Hz
74
f=1KHz
70
f=20KHz
44
THD+N < 10%, SVDD=5.0V,
ZSPK=4Ω + 33µH
3.3
THD+N < 1%, SVDD=5.0V,
ZSPK=4Ω + 33µH
2.6
THD+N < 10%, SVDD=4.2V
1.27
THD+N < 1%, SVDD=4.2V
1.00
THD+N < 10%, SVDD=3.6V
0.92
THD+N < 1%, SVDD=3.6V
0.73
POUT=0.7W, SVDD=4.2V
0.04
POUT=0.7W, SVDD=3.6V
0.17
Max.
Unit
mA
mV
dB
W
%
A-wt, POUT=700mW
97
A-wt, POUT=700mW, SVDD=4.2V
97
Spread Spectrum
300
Fixed Frequency
300
Efficiency
POUT=720mW
91
%
DC Detect Voltage
Absolute Value, Measured
Differentially Across SOUT+ and
SOUT-
1.5
Vpk
DCERR_TIME=10
15
DCERR_TIME=01
5
DCERR_TIME=00
2
Amp. Off, SP_HIZ=0, f < 40KHz
2
OTP_ERR=1, f < 40KHz
2
DC_ERR=1, f < 40KHz
2
Amp. Off, SP_HIZ=1, f < 40KHz
35
OCP_ERR=1, f < 40KHz
2
Signal-to-Noise Ratio
Class-D Frequency
tDCERR
Typ.
±0.4
200mVpk-pk Ripple on
SVDD
POUT
Min.
DC Detect Time
Single-Ended Output
Impedance
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
dB
KHz
ms
kΩ
www.fairchildsemi.com
5
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
Electrical Characteristics (Speaker Amplifier)
Unless otherwise noted: audio BW=22Hz to 20KHz, fIN=1KHz, DIFA=1, DIFB=0, HP_AMIX=0, HP_BMIX=1,
SP_AMIX=0, SP_BMIX=0, unused inputs are AC grounded, DRC is off, preamplifier gains=0dB, headphone
volume=0dB, headphone amplifier gain=0dB, speaker volume=0dB, SP_GAIN=00, edge-rate control is on, spread
spectrum is on, HP_NG_RAT=000, SP_NG_RAT=000, SRST=0, SDA and SCL pull-up voltage=DVDD, ZSPK
=8Ω+33µH, RHP=32Ω, HP_HIZ=0, SVDD=3.6V, DVDD=1.8V, and TA=25°C.
Symbol
Parameter
Condition
ICC
Current Consumption
HP_NG_RAT=100
VOS
Output Offset Voltage
Volume=Mute
PSRR
Power-Supply Rejection
Ratio
THD+N
Output Power
Total Harmonic
Distortion Plus Noise
SVDD
0.8
DVDD
1.9
200mVpk-pk Ripple on
SVDD,
HP_NG_RAT=100
f=217Hz
93
f=1KHz
94
f=20KHz
97
f=217Hz
93
f=1KHz
93
f=20KHz
97
THD+N < 0.1%
27
THD+N < 1%, Headphone Amplifier
Gain=6dB
29
THD+N < 1%, Headphone Amplifier
Gain=6dB, SVDD=4.2V
29
POUT=10mW
0.01
POUT=10mW, SVDD=4.2V
0.01
POUT=20mW
CL
Xtak
Signal-to-Noise Ratio
A-wt,
HP_NG_RAT POUT=10mW, SVDD=4.2V
=100
POUT=20mW
POUT=10mW, SVDD=3.6V
A-wt,
HP_NG_RAT POUT=10mW, SVDD=4.2V
=000
POUT=20mW
Capacitive Drive
Crosstalk
Output Impedance
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
Max.
Unit
mA
mV
dB
dB
mW
%
0.01
POUT=10mW, SVDD=3.6V
SNR
Typ.
±0.1
200mVpk-pk Ripple on
SVDD
POUT
Min.
102.5
102.5
105.5
97
dB
97
100
100
POUT=10mW, f=100Hz
-96
POUT=20mW, f=100Hz
-95
POUT=10mW, f=1KHz
-93
POUT=20mW, f=1KHz
-92
POUT=10mW, f=10KHz
-79
POUT=20mW, f=10KHz
-79
pF
dB
Headphone to Speaker, POUT=10mWx2
-91
Speaker to Headphone, POUT=700mW
-106
Amp. Off, HP_HIZ=0
130
Ω
OTP_ERR=1
170
Ω
Amp. Off, HP_HIZ=1
15
kΩ
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6
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
Electrical Characteristics (Headphone Amplifiers)
Unless otherwise noted, SVDD=2.8V to 5.25V, DVDD=1.6V to 2.8V, TA=-40°C to 85°C.
Symbol
Fast Mode (400kHz)
Parameter
Min.
Max.
0.6
Unit
VIL
Low-Level Input Voltage
-0.3
VIH
High-Level Input Voltage
1.3
V
VOL
Low-Level Output Voltage at 3mA Sink Current
(Open-Drain or Open-Collector)
0
0.4
V
IIH
High-Level Input Current of Each I/O Pin, Input Voltage=VSVDD
-1
1
µA
IIL
Low-Level Input Current of Each I/O Pin, Input Voltage=0V
-1
1
µA
V
I2C AC Electrical Characteristics
Unless otherwise noted, SVDD=2.8V to 5.25V, DVDD=1.6V to 2.8V, TA=-40°C to 85°C.
Symbol
fSCL
tHD;STA
Fast Mode (400kHz)
Parameter
SCL Clock Frequency
Min.
Max.
Unit
0
400
kHz
Hold Time (Repeated) START Condition
0.6
µs
tLOW
Low Period of SCL Clock
1.3
µs
tHIGH
High Period of SCL Clock
0.6
µs
tSU;STA
Set-up Time for Repeated START Condition
0.6
µs
tHD;DAT
Data Hold Time
tSU;DAT
tr
tf
tSU;STO
tBUF
0
0.9
µs
(4)
100
Rise Time of SDA and SCL Signals(5)
20+0.1Cb
300
ns
20+0.1Cb
300
ns
Data Set-up Time
(5)
Fall Time of SDA and SCL Signals
ns
Set-up Time for STOP Condition
0.6
µs
Bus-Free Time between STOP and START Conditions
1.3
µs
tSP
Pulse Width of Spikes that Must Be Suppressed by the Input Filter
0
50
ns
Notes:
4. A Fast-Mode I2C-Bus® device can be used in a Standard-Mode I2C-Bus system, but the requirement tSU;DAT
≥250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
2
Serial Data (SDA) line tr_max + tSU;DAT=1000 + 250=1250ns (according to the Standard-Mode I C Bus specification)
before the SCL line is released.
5. Cb equals the total capacitance of one bus line in pf. If mixed with High-Speed Mode devices, faster fall times are
allowed according to the I2C specification.
Figure 3. Definition of Timing for Full-Speed Mode Devices on the I2C Bus
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
7
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
I2C DC Electrical Characteristics
System
Unless otherwise noted: audio BW=22Hz to 20KHz, fIN=1KHz, DIFA=1, DIFB=0, HP_AMIX=0, HP_BMIX=1,
SP_AMIX=1, SP_BMIX=0, unused inputs are AC grounded, DRC is off, preamplifier gains=0dB, headphone
volume=0dB, headphone amplifier gain=0dB, speaker volume=0dB, SP_GAIN=00, edge-rate control is on, spread
spectrum is on, HP_NG_RAT=100, SP_NG_RAT=001, SRST=0, SDA and SCL pull-up voltage=DVDD, ZSPK
=8Ω+33µH, RHP=32Ω, HP_HIZ=0, SVDD=3.6V, DVDD=1.8V, and TA=25°C.
4
2.5
Speaker Amplifier Mode
Inputs AC grounded
HP_BMIX = 0
HP_NG_RAT[2:0] = 000
SP_NG_RAT[2:0] = 001
2
DVDD Current (mA)
SVDD Current (mA)
3.5
3
2.5
1
Speaker Amplifier Mode
Inputs AC grounded
HP_BMIX = 0
HP_NG_RAT[2:0] = 000
SP_NG_RAT[2:0] = 001
0.5
2
0
2.5
3
3.5
4
SVDD Voltage (V)
4.5
5
5.5
1.6
Figure 4. Quiescent Current vs. Supply Voltage
1.8
2
2.2
2.4
DVDD Voltage (V)
2.6
2.8
Figure 5. Quiescent Current vs. Supply Voltage
2
3.5
Headphone Amplifier Mode
Inputs AC grounded
SP_AMIX = 0
HP_NG_RAT[2:0] = 100
SP_NG_RAT[2:0] = 000
3
2.5
DVDD Current (mA)
1.5
SVDD Current (mA)
1.5
1
0.5
2
1.5
1
Headphone Amplifier Mode
Inputs AC grounded
SP_AMIX = 0
HP_NG_RAT[2:0] = 100
SP_NG_RAT[2:0] = 000
0.5
0
0
2.5
3
3.5
4
SVDD Voltage (V)
4.5
5
5.5
1.6
Figure 6. Quiescent Current vs. Supply Voltage
1.8
2
2.2
2.4
DVDD Voltage (V)
2.6
2.8
Figure 7. Quiescent Current vs. Supply Voltage
10
20
SRST = 1
9
18
16
14
Preamplifier Gain (dB)
SVDD Current (µA)
8
7
6
5
4
3
12
10
8
6
4
2
0
2
-2
-4
1
2.5
3
3.5
4
SVDD Voltage (V)
4.5
5
5.5
5
10
15
20
Input Resistance (Kohm)
25
30
Figure 9. Input Resistance vs. Preamplifier Gain
Figure 8. Standby Current vs. Supply Voltage
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
0
www.fairchildsemi.com
8
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
Typical Performance Characteristics
Speaker Amplifier
Unless otherwise noted: audio BW=22Hz to 20KHz, fIN=1KHz, DIFA=1, DIFB=0, HP_AMIX=0, HP_BMIX=0,
SP_AMIX=1, SP_BMIX=0, unused inputs are AC grounded, DRC is off, preamplifier gains=0dB, headphone
volume=0dB, headphone amplifier gain=0dB, speaker volume=0dB, SP_GAIN=00, edge-rate control is on, spread
spectrum is on, HP_NG_RAT=000, SP_NG_RAT=000, SRST=0, SDA and SCL pull-up voltage=DVDD, ZSPK
=8Ω+33µH, RHP=32Ω, HP_HIZ=0, SVDD=3.6V, DVDD=1.8V, and TA=25°C.
10
10
f = 1KHz
ZSPK = 8ohm+33uH
SVDD=2.8V
SVDD=3.6V
SVDD=4.2V
SVDD=5.0V
1
THD+N (%)
THD+N (%)
1
POUT = 500mW
ZSPK = 8ohm+33uH
0.1
0.1
0.01
0.01
0.001
0.01
0.1
Output Power (W)
1
10
0.01
Figure 10. THD+N vs. Output Power
THD+N = 10%
1.6
THD+N = 1%
80
70
1.4
Efficiency (%)
Output Power (W)
100
90
1.8
1.2
1
0.8
60
50
40
30
0.6
0.4
20
0.2
10
0
0
2.5
3
3.5
4
SVDD Voltage (V)
4.5
5
f = 1KHz
ZSPK = 8ohm+33uH
SVDD = 3.6V
SVDD = 4.2V
0
5.5
Figure 12. Output Power vs. Supply Voltage
0.2
0.4
0.6
0.8
Output Power (W)
1
1.2
1.4
Figure 13. Efficiency vs. Output Power
100
10
Inputs AC Grounded
VRIPPLE = 200mVPP
SP_NG_RAT = 000
5
BW = <10Hz to 80KHz
POUT = 700mW
Cin = 1.0uF
Cin = 0.1uF
70
60
Amplitude (dB)
PSRR (dB)
10
100
f = 1KHz
ZSPK = 8ohm+33uH
2
80
1
Frequency (KHz)
Figure 11. THD+N vs. Frequency
2.2
90
0.1
50
40
0
-5
30
20
-10
10
0
-15
0.01
0.1
1
Frequency (KHz)
10
100
0.01
Figure 14. PSRR vs. Frequency
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
0.1
1
Frequency (KHz)
10
100
Figure 15. Frequency Response
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9
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
Typical Performance Characteristics
Speaker Amplifier (Continued)
0
f=
1KHz
Amplitude (dBV)
-30
-60
-90
-120
-150
0
5
10
Frequency (KHz)
15
20
Figure 16. Output vs. Frequency
Headphone Amplifiers
Unless otherwise noted: audio BW=22Hz to 20KHz, fIN=1KHz, DIFA=1, DIFB=0, HP_AMIX=0, HP_BMIX=1,
SP_AMIX=0, SP_BMIX=0, unused inputs are AC grounded, DRC is off, preamplifier gains=0dB, headphone
volume=0dB, headphone amplifier gain=0dB, speaker volume=0dB, SP_GAIN=00, edge-rate control is on, spread
spectrum is on, HP_NG_RAT=000, SP_NG_RAT=000, SRST=0, SDA and SCL pull-up voltage=DVDD, ZSPK
=8Ω+33µH, RHP=32Ω, HP_HIZ=0, SVDD=3.6V, DVDD=1.8V, and TA=25°C.
1
10
f = 1KHz
HP_GAIN[1:0] = 11
CIN = 1uF
HP_GAIN[1:0] = 11
Pout = 10mW/Channel
Pout = 20mW/Channel
0.1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.01
0.001
0.01
0.1
1
Output Power (mW)
10
0.01
100
1
Frequency (KHz)
10
100
Figure 18. THD+N vs. Frequency
Figure 17. THD+N vs. Output Power
70
0
f = 1KHz
HP_GAIN[1:0] = 11
HP_NG_RAT[2:0] =
000
60
POUT = 10mW
-20
50
-40
Crosstalk (dB)
Power Dissipation (mW)
0.1
40
30
-60
-80
20
-100
10
-120
0
0
10
20
30
40
50
Output Power(mW)
60
70
0.01
80
1
Frequency (KHz)
10
100
Figure 20. Crosstalk vs. Frequency
Figure 19. Power Dissipation vs. Output Power
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
0.1
www.fairchildsemi.com
10
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
Typical Performance Characteristics
Headphone Amplifiers (Continued)
120
10
BW = <10Hz to 80KHz
POUT = 10mW
100
Cin = 1.0uF
5
Cin = 0.1uF
Amplitude (dB)
PSRR (dB)
80
60
0
-5
40
20
-10
Inputs AC Grounded
VRIPPLE = 200mVPP
HP_NG_RAT = 000
0
0.01
0.1
1
Frequency (KHz)
10
-15
100
0.01
Figure 21. PSRR vs. Frequency
0.1
1
Frequency (KHz)
10
100
Figure 22. Frequency Response
0
f = 1KHz
HP_NG_RAT = 000
-20
Amplitude (dBV)
-40
-60
-80
-100
-120
-140
-160
0
5
10
Frequency (KHz)
15
20
Figure 23. Output vs. Frequency
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
11
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
Typical Performance Characteristics
2
During DC output shutdown, the I C port remains
functional and the DC_ERR bit is set to 1. Other bits
retain their values and are not reset. The speaker
amplifier remains off and the DC_ERR bit remains HIGH
until SRST is cycled or power is cycled.
Shutdown Modes
Standby
When the SRST bit is set to 1, the FAB2210 enters a
low-power Standby Mode.
2
While SRST=1, I C communications are available and
2
I C values are reset to default values. Any values written
to the I2C registers (except SRST) while in Standby
Mode are ignored and default values is preserved.
Signal Path
Audio signals pass from the input pins through a
preamplifier, a mixer, a volume control, and finally
through an amplifier. The preamplifiers can be set to
-3dB to 18dB of gain. The headphone and speaker
paths have volume controls that range from -64dB to
0dB. The headphone amplifier has gain settings of 0dB,
1.5dB, 3dB, and 6dB. The speaker amplifier has gain
settings of 16dB, 20dB, and 24dB.
To achieve low supply current during Standby Mode, all
inputs must be DC. Audio inputs must be AC grounded.
VSVDD and VDVDD must be within recommended
operating conditions. I2C pins must be grounded or
pulled HIGH with no toggling. If AC is presented to the
inputs during Standby Mode, standby current may
increase slightly, but there are no other negative effects.
A variety of combinations of the input signals can be
routed from the preamplifiers to the headphone and
speaker volume blocks. Routing is controlled by the
HP_AMIX, HP_BMIX, SP_AMIX, SP_BMIX, DIFA,
DIFB, and MONO bits.
Thermal Shutdown Protection (TSP)
If the junction temperature of the device exceeds the
thermal shutdown threshold of 150°C (see the Electrical
Characteristics table), the device protects itself by
turning off the amplifiers. The I2C port remains functional
and the OTP_ERR bit is set to 1. Other bits retain their
values and are not reset. See the Electrical
Characteristics table for output impedances. The
amplifiers remain off until the junction temperature falls
below the thermal shutdown recovery point and SRST is
cycled or power is cycled.
For example, to connect the left headphone amplifier
channel to INA1 and the right headphone amplifier
channel to INA2, set HP_AMIX to 1. HP_BMIX, DIFA,
and MONO should be set to 0.
To configure INB1 and INB2 as a differential input and
route the signal to the speaker amplifier, set DIFB and
SP_BMIX to 1. SP_AMIX should be set to 0.
Over-Current Protection (OCP)
If the speaker amplifier’s output current limit of 1.3APEAK
is exceeded (see the Electrical Characteristics table),
the amplifier turns off. During current-limit shutdown, the
I2C port remains functional and the OCP_ERR bit is set
to 1. Other bits retain their values and are not reset. The
speaker amplifier remains off and the OCP_ERR
remains HIGH until SRST is cycled or power is cycled.
When HP_AMIX and HP_BMIX are both 0, the
headphone amplifier is off. When SP_AMIX and
SP_BMIX are both 0, the speaker amplifier is off.
Unused audio input pins must be grounded either
directly or through a DC-blocking capacitor.
To prevent internal clipping in the headphone amplifier
path, internal signal amplitudes from the preamplifier
outputs to the headphone amplifier input should not
exceed a peak-to-peak voltage equivalent to VDVDD 0.2V. If HP_MONO = 1, the peak-to-peak voltage can
be as high as (VDVDD * 2) - 0.2V. Extra caution should be
taken if mixing signals together.
DC Output Protection
If the magnitude of the speaker amplifier output voltage
across SOUT+ and SOUT- exceeds the DC detect
voltage of 1.5Vpk for more than tDCERR (see the Electrical
Characteristics table), the speaker amplifier turns off.
This protects the loudspeaker from damage due to DC
signals. Low-frequency audio input signals may trigger
unintentional DC output shutdown. Set the input DC
coupling capacitor value small enough to avoid a DC
output shutdown caused by a low-frequency audio
signal. For the default tDCERR setting of 2ms, the input
DC-coupling capacitor value must be 0.1F or lower.
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
To prevent internal clipping in the speaker amplifier
path, internal signal amplitudes from the preamplifier
outputs to the speaker amplifier input should not exceed
a peak-to-peak voltage equivalent to VDVDD - 0.2V. Extra
caution should be taken if mixing signals together.
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12
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
Detailed Description
The FAB2210 includes an inverting charge pump that
generates HVDD and HVSS (the headphone amplifier
power supplies) from the DVDD power supply input. The
HVSS rail is a negative mirror of HVDD and allows the
headphone amplifier to be ground referenced. The
ground-referenced biasing scheme allows the
headphone amplifier outputs to be biased at ground
while operating from a single external supply. This
eliminates the need for the large, expensive, DCcoupling capacitors between the headphone amplifier
output and load that are required on traditional, singlesupply, VDD/2, biased headphone amplifiers.
The transition from the lower magnitude rails to the
higher magnitude rails occurs fast enough to prevent
audible artifacts during headphone playback. The
transition from the higher magnitude rails to the lower
magnitude rails occurs 15ms (typical) from the last
threshold crossing (low to high) and only after the
headphone output amplitude has stayed below the
threshold level. The 15ms (typical) hysteresis prevents
the headphone amplifier power rails from bouncing
between high and low rails when the audio signal
approaches the threshold level.
The negative HVSS rail allows the input preamplifiers to
be ground referenced. Input DC-blocking capacitors are
still required at INA1, INA2, INB1, and INB2 if the audio
source driving the input preamplifiers is biased above
ground. The input DC-blocking capacitors are not
required if the audio source driving the input
preamplifiers is also ground referenced and does not
present any DC offset to the FAB2210.
Class-G Operation
Compared with a traditional Class-AB amplifier, the
FAB2210’s Class-G architecture reduces power
consumption and extends battery life during headphone
playback. The power supply rails (HVDD and HVSS) of
the Class-G headphone amplifier adapt to the level of
audio signal present at the output. The adaptive nature
of the power supply rails ensures that energy is not
wasted during quiet passages of music or when the
volume of the headphone path is reduced.
Due to the flexible input to output routing capabilities of
the FAB2210, additional logic added to the Class-G
audio-level-detection circuit ensures that enough
headroom is available to avoid saturating the audio
input signals at the INA1, INA2, INB1, and INB2
preamplifiers. This is especially useful in cases where
both the Class-D amplifier path and/or mono headphone
path are selected for playback.
Figure 24. Class-G Headphone Amplifier Power Supply Rail Operation
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
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13
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
During stereo headphone playback, when the
headphone output amplitude is below the VTH threshold
level of 250mVpk (typical); the charge pump efficiently
divides VDVDD so that VHVSS = -VDVDD/2 and VHVDD =
VDVDD/2. When the headphone output amplitude
exceeds 250mVpk (typical), the charge pump generates
higher magnitude rails, where VHVSS=-VDVDD and VHVDD =
VDVDD to allow for higher output amplitudes. Due to the
high crest factor of music and speech, a significant
portion of the audio content is below the VTH threshold,
even at typical volume level settings for headphone
playback. When operating at the lower magnitude rails,
less power is dissipated within the headphone amplifier.
Charge Pump
The FAB2210 headphone outputs are placed in a HighImpedance Mode by setting the HP_HIZ bit to 1 and
turning off the headphone amplifier. This can be useful if
the system’s headphone jack is shared with other
devices. For proper high-impedance operation, SRST
must be set to 0 and the headphone amplifier must be
off (see HP_MONO, HPAMIX, and HP_BMIX register
definitions). Voltages on the HOUTL and HOUTR pins
must not exceed DVDD and must not be below -DVDD.
The HP_SVOFF and HP_ZCSOFF bits control the
headphone volume when HP_ATT is changed.
HP_SVOFF and HP_ZCSOFF do not slow down turn-on
or turn-off when using the HP_AMIX, HP_BMIX, or
SRST bits. Thermal shutdown conditions are not slowed
by HP_SVOFF or HP_ZCSOFF.
Table 1. Headphone Volume-Change Behavior
HP_SVOFF HP_ZCSOFF Behavior when HP_ATT is Changed
1
1
Volume changes immediately.
1
0
For each channel, wait until a zero crossing occurs in the input before changing
volume. If a zero crossing does not occur within 200µs, volume is forced to the new
setting.
0
1
Volume is ramped to the new setting at a rate of 200µs per step.
0
0
Volume is changed by one step when a zero crossing occurs. If a zero crossing does
not occur within 200µs, a step is forced. Only the first zero crossing within 200µs
triggers a volume change; volume does not change again until the next 200µs.
Programmable Spread Spectrum
Modulation
Headphone Amplifier Noise Gate
The headphone noise gate automatically reduces the
headphone volume when its input amplitudes are low to
reduce noise during inactivity. (This function is more
useful for speech than music.) The amplitude is
measured after input preamplifiers, but before the
headphone volume control. The headphone noise gate’s
threshold level is set by the HP_NG_RAT register. The
amplitudes of both channels must be less than the noise
gate threshold for the hold-time determined by the
NG_ATRT register.
Spread spectrum modulation is employed to reduce EMI
generated at the Class-D amplifier outputs. Spread
spectrum modulates the Class-D amplifier’s switching
frequency by a programmable percentage centered
around the base switching frequency of 300kHz,
dispersing the spectral energy of the switching
waveform over a wider band. This significantly reduces
the amount of concentrated spectral energy at multiples
of the switching frequency that fixed-frequency Class-D
amplifiers emit. Spread spectrum modulation eliminates
the need for output filters, as long as the distance from
the Class-D amplifier outputs to the speaker transducer
is kept short.
The amount of volume reduction is set by the
HP_NG_ATT register. The speed at which the volume is
reduced is determined by the attack time setting in the
NG_ATRT register. When the volume is reduced by the
noise gate, the HP_ATT register’s readback value
remains unchanged. An internal register keeps track of
the actual volume setting.
Edge Rate Control (ERC)
The Edge Rate Control (ERC) circuit minimizes EMI
generated by the high-current switching waveform of the
Class-D amplifier output. One of the main contributors
to EMI generated by Class-D amplifiers is the highfrequency energy produced by rapid (large dV/dt)
transitions at the edges of the switching waveform. The
ERC circuit suppresses the high-frequency component
of the switching waveform by extending the rise and fall
times of the output FET transitions, without
compromising efficiency and THD+N performance. Rise
and fall times are set to approximately 20ns per
transition at all power levels.
If either headphone channel’s amplitude goes above the
headphone noise gate threshold, headphone volume is
raised back to the HP_ATT value at a rate determined
by the release time setting in the NG_ATRT register. If
HP_MONO=1, only left channel amplitude is monitored.
To avoid unpredictable behavior, noise gate settings
should not change while the headphone amplifier is on.
Class-D Speaker Amplifier
The FAB2210 utilizes a “Filterless” modulation scheme
to achieve 92% efficiency, extending battery life and
reducing component count. The pulse-width modulated,
differential outputs of the Class-D amplifier switch at
300kHz. When an audio input signal is not present, the
Class-D outputs switch in-phase at 50% duty cycle,
minimizing idle current and saving power.
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
14
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
Headphone Volume Ramp and Zero
Crossing Detection
Headphone Amplifier High-Impedance Mode
The speaker amplifier’s DRC can be used to limit output
amplitude and reduce clipping even as the supply
voltage varies. The DRC allows high gain settings while
preventing distortion and speaker damage. This results
in louder speaker playback without increasing the
maximum peak amplitude of the speaker signal path.
DRC release occurs when the DRC determines that, for
a given input amplitude, the actual output amplitude is
lower than the target output amplitude and release
speed (defined in the DATRT register) is not be
exceeded. When these criteria are met, volume is
increased by one step.
To avoid unpredictable behavior, DRC settings should
not be changed while the speaker amplifier is on.
Figure 25 shows the speaker amplifier’s target output
amplitude with respect to the DRC’s input amplitude
when programmed at various Class-D output gain
settings. The DRC’s input amplitude is measured after
the speaker volume control, but before the speaker
amplifier block.
When the volume is changed by the DRC, the SP_ATT
register readback value remains unchanged. An internal
register keeps track of the actual volume setting.
When 2:1 compression is enabled, the overall gain of the
speaker amplifier path is increased by 6dB, as shown in
Figure 26.
The DRC has three regions of operation: linear,
compression, and limiter. When the output amplitude is
initially low, the DRC operates in the linear region and
does not apply any gain changes to the signal. The
volume control remains fixed at the level defined in
SP_ATT. When the output amplitude has increased
above the dynamic range compression threshold, the
DRC reduces the gain of SP_ATT, thereby applying
compression to the output signal.
15
11.57
10
DRC Limiter Threshold (DPLT Limiter = 3.79Vpk and DALC Limiter off)
8dB
5
3.57
OUTPUT LEVEL (dBVpk)
Compression Region
DRC Compressor Threshold
0
The compression region is defined by the compression
ratio and the dynamic range compression threshold.
The dynamic range compression threshold is set by the
DPLT register. The dynamic range compression
threshold is set 8dB below the DPLT threshold level.
The DRC applies a 2:1 compression ratio for output
signals between the dynamic range compression
threshold and limiter threshold. In the compression
region; for every 2dB rise of input amplitude, the target
output amplitude only rises by 1dB. This continues until
the output amplitude has increased above the DRC
limiter threshold.
Limiter Region
Linear Region
‐5
‐10
‐15
‐20
‐25
‐30
‐35
‐40
‐40
‐35
‐30
‐25
‐20
‐15
‐10
‐5
0
5
10
15
INPUT LEVEL (dBVpk)
Figure 25. Dynamic Range Compression
Response vs. Class-D Output Gain Settings
The limiter region is defined by the DALC and DPLT
registers. In the limiter region, the target output
amplitude does not increase with the input amplitude.
The DPLT register sets an output voltage limit
independent of the battery voltage. This is useful for
speaker protection. The DALC register defines an
output voltage limit that is a percentage of the battery
voltage. Since the battery voltage sets the maximum
output amplitude, the DALC register is used as a
distortion limiter by setting the allowed clipping amount.
15
12.46
10
5
3.57
VSVDD = 4.2V Clip Threshold (DPLT Limiter Off, DALC Limiter Off)
Compression Region
DRC Compressor Threshold
OUTPUT LEVEL (dBVpk)
0
The DRC limiter threshold is defined as the lower of the
two limiter voltages set by the DPLT and DALC settings.
For example, in Figure 27; if DPLT=111, DALC=001,
and SVDD=4.5Vpk, the DRC limit is 3.79Vpk as defined by
DPLT. However, if SVDD falls to 3.0V, the DRC limiter
threshold falls to 2.7Vpk, as defined by DALC.
Linear Region
‐5
‐10
‐15
‐20
6dB
‐25
‐30
The speed at which gain is changed is regulated by the
attack and release settings in the DATRT register.
Figure 28 shows DRC attack and release behavior.
‐35
‐40
‐40
‐35
‐30
‐25
‐20
‐15
‐10
‐5
0
5
10
15
INPUT LEVEL (dBVpk)
Figure 26. Gain Boost when Enabling DRC
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
15
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
DRC attack occurs when the DRC determines that, for
given input amplitude, the actual output amplitude is
higher than the target output amplitude and attack
speed (defined in the DATRT register) is not to be
exceeded. When these criteria are met, volume is
reduced by one step.
Dynamic Range Compression (DRC)
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
5
4.5
AGC Limit (Vpk)
4
DPLT
AGC Limit
3.5
SVDD = 3.0V
SVDD = 4.5V
3
2.5
2
2.5
3
3.5
4
4.5
5
5.5
SVDD (V)
Figure 27. DRC Limiter Threshold when
DPLT=3.79Vpk (111) and DALC=0.9*SVDD (001)
Start
Reset the timers.
yes
Does the actual
output amplitude match
the target output
amplitude?
no
yes
no
Is the
actual output
amplitude above
the target output
Amplitude?
Has enough
time (attack speed)
passed since the last
gain change?
no
Has enough
time (decay speed)
passed since the last
gain change?
yes
no
yes
Reduce gain by
1 step
Increase gain by
1 step.
Figure 28. DRC Flowchart
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
16
The speaker noise gate automatically mutes the
speaker amplifier when its input amplitude is below a
predetermined noise gate threshold to reduce noise
during inactivity. (This function is more useful for speech
than music.) The amplitude is measured after the
speaker volume control, but before the speaker amplifier
block. The speaker noise gate’s threshold level is set by
the SP_NG_RAT register. The amplitude must be less
than the noise gate threshold for the hold time
determined by the NG_ATRT register.
If the speaker channel’s amplitude goes above the
speaker noise gate threshold, the speaker volume is
raised back to the SP_ATT value at a rate determined
by the release time setting in the NG_ATRT register.
To avoid unpredictable behavior, noise gate settings
should not be changed while the speaker amplifier is on.
Table 2. Speaker Volume Change Behavior
SP_SVOFF
SP_ZCSOFF Behavior when SP_ATT is Changed
1
1
Volume changes immediately.
1
0
Wait until a zero crossing occurs in the input before changing volume. If a zero
crossing does not occur within 200µs, volume is forced to the new setting.
0
1
Volume is ramped to the new setting at a rate of 200µs per step.
0
0
Volume is changed by one step when a zero crossing occurs. If a zero crossing
does not occur within 200µs, a step is forced. Only the first zero crossing within
200µs triggers a volume change; volume does not change again until the next
200µs.
Note that there are no unused clock cycles during any
operation; therefore, there must be no breaks in the
stream of data and ACKs/NACKs during data transfers.
Speaker Volume Ramp and Zero-Crossing
Detection
The SP_SVOFF and SP_ZCSOFF I2C bits control the
speaker volume when SP_ATT is changed.
For most operations, I2C protocol requires the SDA line
to remain stable (unmoving) whenever SCL is HIGH; i.e.
transitions on the SDA line can only occur when SCL is
LOW. The exceptions to this rule are when the master
device issues a START or STOP condition. The slave
device cannot issue a START or STOP condition.
SP_SVOFF and SP_ZCSOFF do not slow down turn-on
or turn-off when using the SP_AMIX, SP_BMIX, or
SRST bits. Thermal, over-current, and DC offset
shutdown conditions are not slowed by SP_SVOFF and
SP_ZCSOFF.
START Condition: This condition occurs when the SDA
line transitions from HIGH to LOW while SCL is HIGH.
The master device uses this condition to indicate that a
data transfer is about to begin.
SP_SVOFF and SP_ZCSOFF have no effect on DRC
and noise gate timing. DRC and noise gate timing have
no effect on speaker volume ramp and zero-crossing
detection. In the event of a conflict between these
systems, the lowest volume setting is chosen.
STOP Condition: This condition occurs when the SDA
line transitions from LOW to HIGH while SCL is HIGH.
The master device uses this condition to signal the end
of a data transfer.
I2C Control
Writing to and reading from registers is accomplished
2
2
via the I C interface. The I C protocol requires that one
device on the bus initiates and controls all read and
write operations. This device is called the “master”
device. The master device generates the SCL signal,
which is the clock signal for all other devices on the bus.
All other devices on the bus are called “slave” devices.
The FAB2210 is a slave device. Both the master and
slave devices can send and receive data on the bus.
Acknowledge and Not Acknowledge: When data is
transferred to the slave device, the slave device sends
an acknowledge (ACK) after receiving every byte of
data. The receiving device sends an ACK by pulling
SDA LOW for one clock cycle.
When the master device is reading data from the slave
device, the master sends an ACK after receiving every
byte of data. Following the last byte, a master device
sends a “not acknowledge” (NACK) instead of an ACK,
followed by a STOP condition. A NACK is indicated by
leaving SDA HIGH during the clock after the last byte.
During I2C operations, one data bit is transmitted per
clock cycle. All I2C operations follow a repeating nine
clock-cycle pattern that consists of eight bits (one byte)
of transmitted data followed by an acknowledge (ACK)
or not acknowledge (NACK) from the receiving device.
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
17
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
The speed at which the volume is reduced is
determined by the attack time setting in the NG_ATRT
register. When the volume is reduced by the noise gate,
the SP_ATT register’s readback value remains
unchanged. An internal register keeps track of the
actual volume setting.
Speaker Amplifier Noise Gate
To read from a register other than the one currently
indicated by the command register, a pointer to the
desired register must be set. Immediately following the
pointer set, the master must perform a REPEAT START
condition (see Figure 32), which indicates to the
FAB2210 that a new operation is about to occur. If the
REPEAT START condition does not occur, the
FAB2210 assumes that a write is taking place and the
selected register is overwritten by the upcoming data on
the data bus. After the START condition, the master
must again send the device address and read/write bit.
This time, the read/write bit must be set to 1 to indicate
a read. The rest of the read cycle is the same as
described in the previous paragraphs for reading from a
preset pointer location.
Writing to and Reading from the FAB2210
All read and write operations must begin with a START
condition generated by the master. After the START
condition, the master must immediately send a slave
address (7 bits), followed by a read/write bit. If the slave
address matches the address of the FAB2210, the
FAB2210 sends an ACK after receiving the read/write
bit by pulling the SDA line LOW for one clock cycle.
Setting the Pointer
For all operations, the pointer stored in the command
register must be pointing to the register that is going to
be written or read. To change the pointer value in the
command register, the read/write bit following the
address must be 0. This indicates that the master writes
new information into the command register.
Writing
All writes must be preceded by a pointer set, even if the
pointer is already pointing to the desired register.
After the FAB2210 sends an ACK in response to
receiving the address and read/write bit, the master
must transmit an appropriate 8-bit pointer value, as
explained in the I2C Registers section. The FAB2210
sends an ACK after receiving the new pointer data.
Immediately following the pointer set, the master must
begin transmitting the data to be written. After
transmitting each byte of data, the master must release
the Serial Data (SDA) line for one clock cycle to allow
the FAB2210 to acknowledge receiving the byte. The
write operation should be terminated by a STOP
condition from the master (see Figure 31).
The pointer set operation is illustrated in Figure 31 and
Figure 32. Any time a pointer set is performed, it must
be immediately followed by a read or write operation.
The command register retains the current pointer value
between operations; therefore, once a register is
indicated, subsequent read operations do not require a
pointer set cycle. Write operations always require the
pointer be reset.
As with reading, the master can write multiple bytes by
continuing to send data. The FAB2210 increments the
pointer by one and accepts data for the next register.
The master indicates the last data byte by issuing a
STOP condition.
Reading
If the pointer is already pointing to the desired register,
the master can read from that register by setting the
read/write bit (following the slave address) to 1. After
sending an ACK, the FAB2210 begins transmitting data
during the following clock cycle. The master should
respond with a NACK, followed by a STOP condition
(see Figure 29).
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
18
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
The master can read multiple bytes by responding to the
data with an ACK instead of a NACK and continuing to
send SCL pulses, as shown in Figure 30. The FAB2210
increments the pointer by one and sends the data from
the next register. The master indicates the last data byte
by responding with a NACK, followed by a STOP.
Slave Address
Each slave device on the bus must have a unique
address so the master can identify which device is
sending or receiving data. The FAB2210 slave address
is 1001101X binary where “X” is the read/write bit.
Master write operations are indicated when X=0. Master
read operations are indicated when X=1.
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
Read / Write Diagrams
2
Figure 29. I C Read
2
Figure 30. I C Multiple Byte Read
Figure 31. I2C Write
Figure 32. I2C Write Followed by Read
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
19
The I2C slave address is 1001101X, where X=0 for write operations and X=1 for read operations.
ADDR
B7
0x15
B6
B5
REVISION_ID[2:0]
0x1A
0
0x1B
0
B4
B3
RSVD
RSVD
DCERR_TIME[1:0]
MCSSMT[2:0]
SRST
0x81
DRC_MODE[1:0]
SSMT[2:0]
0
0x82
0
0
DATRT[1:0]
0
0
ERC
0
0
0
NG_ATRT[1:0]
0
MODESEL
HP_NG_RAT[2:0]
NCLIP
0x84
HP_NG_ATT[1:0]
SP_NG_RAT[2:0]
SP_NG_ATT[1:0]
VA[3:0]
DIFA
DIFB
VB[3:0]
0
0
HP_SVOFF
0x86
0
SP_ATT[6:0]
0x87
0
HP_ATT[6:0]
OCP_ERR OTP_ERR
0xC0
0
0xC1
0
0
1
0
DPLT[2:0]
0x85
B0
DRCMIN[6:0]
0x80
0x88
B1
RSVD
SOFTVOL
0x1D
0x83
B2
DC_ERR
HP_MONO
HP_AMIX
0
0
DALC[2:0]
0
0
HP_HIZ
SP_SVOFF
SP_HIZ
HP_BMIX
SP_AMIX
SP_BMIX
HP_GAIN[1:0]
SP_GAIN[1:0]
HP_ZCSOFF
0
SP_ZCSOFF
Notes:
6. Bits labeled “0” are reserved. Only zeros should be written to these bits.
7. Bits labeled “1” are reserved. Only ones should be written to these bits.
8. Bits labeled “RSVD” are for testing only. Writing to these bits has no effect. When read, they may return any value.
9. Bits and addresses not listed in the register map are for testing only. These bits should never be written. When
read, they may return any value.
Register Descriptions
ADDR
B7
0x15
Default
B6
B5
REVISION_ID[2:0]
0
1
1
REVISION_ID[2:0]
(read only)
011 = Silicon revision 3.
DCERR_TIME[1:0]
DC error time control
11=DC output detection disabled
10=15ms
01=5ms
00=2ms
ADDR
B7
B6
0x1A
0
SOFTVOL
Default
0
0
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
B4
B3
RSVD
RSVD
B2
B1
DCERR_TIME[1:0]
B0
0
0
0
0
B2
B1
B0
B5
B4
20
B3
RSVD
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FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
Register Map
Sets volume ramp speed; sets noise gate release speed when MODESEL=1.
1=2ms/step
0=200µs/step
ADDR
B7
0x1B
0
default
0
B6
B5
B4
B3
B2
B1
B0
0
0
0
DRCMIN[6:0]
0
0
0
0
DRCMIN[6:0]
Sets the minimum gain that the DRC applies to a signal during attack.
DRCMIN
[6:0]
Speaker
Volume
(dB)
DRCMIN
[6:0]
Speaker
Volume
(dB)
DRCMIN
[6:0]
Speaker
Volume
(dB)
DRCMIN
[6:0]
Speaker
Volume
(dB)
1111111
0.00
1011111
-10.00
0111111
-36.00
0011111
Reserved
1111110
-0.25
1011110
-10.50
0111110
-37.00
0011110
Reserved
1111101
-0.50
1011101
-11.00
0111101
-38.00
0011101
Reserved
1111100
-0.75
1011100
-11.50
0111100
-39.00
0011100
Reserved
1111011
-1.00
1011011
-12.00
0111011
-40.00
0011011
Reserved
1111010
-1.25
1011010
-12.50
0111010
-41.00
0011010
Reserved
1111001
-1.50
1011001
-13.00
0111001
-42.00
0011001
Reserved
1111000
-1.75
1011000
-13.50
0111000
-43.00
0011000
Reserved
1110111
-2.00
1010111
-14.00
0110111
-44.00
0010111
Reserved
1110110
-2.25
1010110
-14.50
0110110
-45.00
0010110
Reserved
1110101
-2.50
1010101
-15.00
0110101
-46.00
0010101
Reserved
1110100
-2.75
1010100
-15.50
0110100
-47.00
0010100
Reserved
1110011
-3.00
1010011
-16.00
0110011
-48.00
0010011
Reserved
1110010
-3.25
1010010
-17.00
0110010
-49.00
0010010
Reserved
1110001
-3.50
1010001
-18.00
0110001
-50.00
0010001
Reserved
1110000
-3.75
1010000
-19.00
0110000
-51.00
0010000
Reserved
1101111
-4.00
1001111
-20.00
0101111
-52.00
0001111
Reserved
1101110
-4.25
1001110
-21.00
0101110
-53.00
0001110
Reserved
1101101
-4.50
1001101
-22.00
0101101
-54.00
0001101
Reserved
1101100
-4.75
1001100
-23.00
0101100
-55.00
0001100
Reserved
1101011
-5.00
1001011
-24.00
0101011
-56.00
0001011
Reserved
1101010
-5.25
1001010
-25.00
0101010
-57.00
0001010
Reserved
1101001
-5.50
1001001
-26.00
0101001
-58.00
0001001
Reserved
1101000
-5.75
1001000
-27.00
0101000
-59.00
0001000
Reserved
1100111
-6.00
1000111
-28.00
0100111
-60.00
0000111
Reserved
1100110
-6.50
1000110
-29.00
0100110
-61.00
0000110
Reserved
1100101
-7.00
1000101
-30.00
0100101
-62.00
0000101
Reserved
1100100
-7.50
1000100
-31.00
0100100
-63.00
0000100
Reserved
1100011
-8.00
1000011
-32.00
0100011
-64.00
0000011
Reserved
1100010
-8.50
1000010
-33.00
0100010
Reserved
0000010
Reserved
1100001
-9.00
1000001
-34.00
0100001
Reserved
0000001
Reserved
1100000
-9.50
1000000
-35.00
0100000
Reserved
0000000
Mute
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
21
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
SOFTVOL
B7
B6
0x1D
B5
B4
MCSSMT[2:0]
default
1
0
B3
B2
SSMT[2:0]
0
0
0
B1
B0
ERC
0
1
0
0
MCSSMT[2:0]
Sets the master clock spread spectrum modulation percentage. A setting of 000 results in a ±9.4% modulation.
Modulating the master clock does not modulate the class-D output frequency because the triangle wave generator is
PLL controlled.
MCSSMT[2:0]
± Modulation %
111
10.3
110
9.0
101
8.5
100
6.5
011
37.7
010
21.6
001
15.6
000
9.4
SSMT[2:0]
Sets the Class-D spread-spectrum modulation percentage. A setting of 000 results in ±9.4% modulation.
SSMT[2:0]
± Modulation %
111
10.3
110
9.0
101
8.5
100
6.5
011
37.7
010
21.6
001
15.6
000
9.4
ERC
1=Class-D edge rate control on.
0=Class-D edge rate control off.
ADDR
B7
0x80
SRST
0
0
Default
1
0
0
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
B6
B5
B4
0 0 22
B3
B2
B1
B0
0
1
0
0
0
1
0
0
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FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
ADDR
1=Low-power Standby Mode. All registers are reset to their default values. All I2C write commands to bits other than
SRST are ignored.
0=Normal operation.
ADDR
B7
0x81
B6
B5
DRC_MODE[1:0]
default
0
B4
B3
DATRT[1:0]
0
0
1
B2
B1
B0
NG_ATRT[1:0]
0
MODESEL
1
0
0
1
DRC_MODE[1:0]
Sets the DRC’s compression ratio.
DRC_MODE[1:0]
Compression Ratio
11
Reserved
10
Reserved
01
2:1
00
Off
DATRT[1:0]
Sets the DRC’s attack and release times. To avoid extraneous noise, do not change this setting while the speaker
amplifier is on.
DATRT[1:0]
Attack Time (ms/step)
Release Time (ms/step)
11
1.0
200
10
0.5
200
01
0.1
200
00
0.1
20
NG_ATRT[1:0], MODESEL
Sets the noise gate attack, hold, and release times for the headphone and speaker amplifiers. To avoid extraneous
noise, do not change this setting while the headphone or speaker amplifiers are on.
Attack Time
(ms/step)
MODESEL NG_ATRT[1:0]
Release Time
Release Time
(µs/step) SOFTVOL=0 (µs/step) SOFTVOL=1
Hold
Time
(ms)
1
11
800
200
2000
44
1
10
400
200
2000
44
1
01
100
200
2000
44
1
00
25
200
2000
44
0
11
800
1400
1400
44
0
10
400
1400
1400
44
0
01
100
1400
1400
44
0
00
25
1400
1400
44
ADDR
B7
0x82
Default
B6
B5
B4
DPLT[2:0]
0
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
0
B3
B2
HP_NG_RAT[2:0]
0
1
0
B1
B0
HP_NG_ATT[1:0]
0
0
0
www.fairchildsemi.com
23
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
SRST
Sets the DRC’s limiter value, regardless of SVDD supply voltage. Also sets dynamic range compression threshold.
To avoid extraneous noise, do not change this setting while the speaker amplifier is on.
DPLT[2:0]
Limiter Voltage (Vpk)
Maximum Power with Sine Wave
and 8Ω Load (mW)
DRC Threshold at
Class-D Output (dB Vpk)
111
3.79
900
-12.5
110
3.69
850
-12.7
101
3.58
800
-13.0
100
3.46
750
-13.3
011
3.35
700
-13.5
010
3.22
650
-13.8
001
3.10
600
-14.0
000
No Limit
No Limit
-12.5
HP_NG_RAT[2:0]
Sets the headphone noise gate threshold level. Detection is at the input to the headphone volume block.
HP_NG_RAT[2:0]
Threshold (mVpk)
111
Reserved
110
Reserved
101
18
100
12
011
Noise Gate Disabled
010
Noise Gate Disabled
001
Noise Gate Disabled
000
Noise Gate Disabled
HP_NG_ATT[1:0]
Sets the headphone noise gate attenuation level.
HP_NG_ATT[1:0]
Attenuation Level (dB)
11
-6.0
10
-12.0
01
-18.0
00
Mute
ADDR
B7
B6
B5
0x83
0
0
NCLIP
Default
0
0
0
B4
B3
B2
SP_NG_RAT[2:0]
1
0
B1
B0
SP_NG_ATT[1:0]
0
0
0
NCLIP
1=Turns on the DRC’s clip limiter. Amount of clipping is set by DALC.
0=DRC clip limiter is disabled.
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
24
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
DPLT[2:0]
Sets the speaker noise gate threshold. Detection is at the output of the speaker volume block. To avoid extraneous
noise, do not change this setting while the speaker amplifier is on.
SP_NG_RAT[2:0]
Threshold (mVpk)
111
Reserved
110
Reserved
101
29
100
24
011
14
010
9
001
6
000
Noise Gate Disabled
SP_NG_ATT[1:0]
Sets the speaker noise gate attenuation level.
ADDR
SP_NG_ATT[1:0]
Attenuation Level (dB)
11
Mute
10
-10
01
-20
00
-40
B7
B6
0
0
0x84
B5
B4
B3
B2
1
0
0
0
VA[3:0]
Default
B1
B0
1
0
VB[3:0]
VA[3:0], VB[3:0]
Sets pre-amplifier gain.
VA[3:0] or VB[3:0]
Gain (dB)
VA[3:0] or VB[3:0]
Gain (dB)
1111
Reserved
0111
7.5
1110
Reserved
0110
6.0
1101
Reserved
0101
4.5
1100
18.0
0100
3.0
1011
15.0
0011
1.5
1010
12.0
0010
0.0
1001
10.5
0001
-1.5
1000
9.0
0000
-3.0
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
25
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
SP_NG_RAT [2:0]
B7
B6
B5
B4
B3
B2
B1
B0
0x85
DIFA
DIFB
0
0
HP_SVOFF
HP_HIZ
SP_SVOFF
SP_HIZ
Default
0
0
0
0
0
1
0
0
DIFA
1=INA1 and INA2 are configured as a differential pair.
0=INA1 and INA2 are configured as separate single-ended inputs.
DIFB
1=INB1 and INB2 are configured as a differential pair.
0=INB1 and INB2 are configured as separate single-ended inputs.
HP_SVOFF
1=Headphone volume ramping is off.
0=Headphone volume ramping is on.
HP_HIZ
1=Headphone amplifier output impedance is 12.5kΩ when amplifier is off and SRST=0.
0=Headphone amplifier output is shorted to DGND when amplifier is off and SRST=0.
SP_SVOFF
1=Speaker volume ramping is off.
0=Speaker volume ramping is on.
SP_HIZ
1=Speaker amplifier output is high impedance when amplifier is off and SRST=0.
0=Speaker amplifier output is connected to SGND with an internal 2KΩ resistor when amplifier is off and SRST=0.
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
26
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
ADDR
B7
0x86
0
Default
0
B6
B5
B4
0
0
0
B3
B2
B1
B0
0
0
0
SP_ATT[6:0]
0
SP_ATT[6:0]
Sets the speaker volume.
SP_ATT
[6:0]
Speaker
Volume
(dB)
SP_ATT
[6:0]
Speaker
Volume
(dB)
SP_ATT
[6:0]
Speaker
Volume
(dB)
SP_ATT
[6:0]
Speaker
Volume
(dB)
1111111
0.00
1011111
-10.00
0111111
-36.00
0011111
Reserved
1111110
-0.25
1011110
-10.50
0111110
-37.00
0011110
Reserved
1111101
-0.50
1011101
-11.00
0111101
-38.00
0011101
Reserved
1111100
-0.75
1011100
-11.50
0111100
-39.00
0011100
Reserved
1111011
-1.00
1011011
-12.00
0111011
-40.00
0011011
Reserved
1111010
-1.25
1011010
-12.50
0111010
-41.00
0011010
Reserved
1111001
-1.50
1011001
-13.00
0111001
-42.00
0011001
Reserved
1111000
-1.75
1011000
-13.50
0111000
-43.00
0011000
Reserved
1110111
-2.00
1010111
-14.00
0110111
-44.00
0010111
Reserved
1110110
-2.25
1010110
-14.50
0110110
-45.00
0010110
Reserved
1110101
-2.50
1010101
-15.00
0110101
-46.00
0010101
Reserved
1110100
-2.75
1010100
-15.50
0110100
-47.00
0010100
Reserved
1110011
-3.00
1010011
-16.00
0110011
-48.00
0010011
Reserved
1110010
-3.25
1010010
-17.00
0110010
-49.00
0010010
Reserved
1110001
-3.50
1010001
-18.00
0110001
-50.00
0010001
Reserved
1110000
-3.75
1010000
-19.00
0110000
-51.00
0010000
Reserved
1101111
-4.00
1001111
-20.00
0101111
-52.00
0001111
Reserved
1101110
-4.25
1001110
-21.00
0101110
-53.00
0001110
Reserved
1101101
-4.50
1001101
-22.00
0101101
-54.00
0001101
Reserved
1101100
-4.75
1001100
-23.00
0101100
-55.00
0001100
Reserved
1101011
-5.00
1001011
-24.00
0101011
-56.00
0001011
Reserved
1101010
-5.25
1001010
-25.00
0101010
-57.00
0001010
Reserved
1101001
-5.50
1001001
-26.00
0101001
-58.00
0001001
Reserved
1101000
-5.75
1001000
-27.00
0101000
-59.00
0001000
Reserved
1100111
-6.00
1000111
-28.00
0100111
-60.00
0000111
Reserved
1100110
-6.50
1000110
-29.00
0100110
-61.00
0000110
Reserved
1100101
-7.00
1000101
-30.00
0100101
-62.00
0000101
Reserved
1100100
-7.50
1000100
-31.00
0100100
-63.00
0000100
Reserved
1100011
-8.00
1000011
-32.00
0100011
-64.00
0000011
Reserved
1100010
-8.50
1000010
-33.00
0100010
Reserved
0000010
Reserved
1100001
-9.00
1000001
-34.00
0100001
Reserved
0000001
Reserved
1100000
-9.50
1000000
-35.00
0100000
Reserved
0000000
Mute
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
27
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
ADDR
B7
0x87
0
default
0
B6
B5
B4
B3
B2
B1
B0
0
0
0
HP_ATT[6:0]
0
0
0
0
HP_ATT[6:0]
Sets the headphone volume.
HP_ATT Headphone
[6:0]
Volume (dB)
HP_ATT Headphone
[6:0]
Volume (dB)
HP_ATT Headphone
[6:0]
Volume (dB)
HP_ATT Headphone
[6:0]
Volume (dB)
1111111
0.00
1011111
-10.00
0111111
-36.00
0011111
Reserved
1111110
-0.25
1011110
-10.50
0111110
-37.00
0011110
Reserved
1111101
-0.50
1011101
-11.00
0111101
-38.00
0011101
Reserved
1111100
-0.75
1011100
-11.50
0111100
-39.00
0011100
Reserved
1111011
-1.00
1011011
-12.00
0111011
-40.00
0011011
Reserved
1111010
-1.25
1011010
-12.50
0111010
-41.00
0011010
Reserved
1111001
-1.50
1011001
-13.00
0111001
-42.00
0011001
Reserved
1111000
-1.75
1011000
-13.50
0111000
-43.00
0011000
Reserved
1110111
-2.00
1010111
-14.00
0110111
-44.00
0010111
Reserved
1110110
-2.25
1010110
-14.50
0110110
-45.00
0010110
Reserved
1110101
-2.50
1010101
-15.00
0110101
-46.00
0010101
Reserved
1110100
-2.75
1010100
-15.50
0110100
-47.00
0010100
Reserved
1110011
-3.00
1010011
-16.00
0110011
-48.00
0010011
Reserved
1110010
-3.25
1010010
-17.00
0110010
-49.00
0010010
Reserved
1110001
-3.50
1010001
-18.00
0110001
-50.00
0010001
Reserved
1110000
-3.75
1010000
-19.00
0110000
-51.00
0010000
Reserved
1101111
-4.00
1001111
-20.00
0101111
-52.00
0001111
Reserved
1101110
-4.25
1001110
-21.00
0101110
-53.00
0001110
Reserved
1101101
-4.50
1001101
-22.00
0101101
-54.00
0001101
Reserved
1101100
-4.75
1001100
-23.00
0101100
-55.00
0001100
Reserved
1101011
-5.00
1001011
-24.00
0101011
-56.00
0001011
Reserved
1101010
-5.25
1001010
-25.00
0101010
-57.00
0001010
Reserved
1101001
-5.50
1001001
-26.00
0101001
-58.00
0001001
Reserved
1101000
-5.75
1001000
-27.00
0101000
-59.00
0001000
Reserved
1100111
-6.00
1000111
-28.00
0100111
-60.00
0000111
Reserved
1100110
-6.50
1000110
-29.00
0100110
-61.00
0000110
Reserved
1100101
-7.00
1000101
-30.00
0100101
-62.00
0000101
Reserved
1100100
-7.50
1000100
-31.00
0100100
-63.00
0000100
Reserved
1100011
-8.00
1000011
-32.00
0100011
-64.00
0000011
Reserved
1100010
-8.50
1000010
-33.00
0100010
Reserved
0000010
Reserved
1100001
-9.00
1000001
-34.00
0100001
Reserved
0000001
Reserved
1100000
-9.50
1000000
-35.00
0100000
Reserved
0000000
Mute
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
28
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
ADDR
B7
B6
B5
B4
B3
B2
B1
B0
0x88
OCP_ERR
OTP_ERR
DC_ERR
HP_MONO
HP_AMIX
HP_BMIX
SP_AMIX
SP_BMIX
0
0
0
0
0
Default
OCP_ERR
(Read only)
1=Indicates that the speaker amplifier current limit of 1.3APEAK has been exceeded. Speaker amplifier turns off. Bit
remains HIGH and amplifier stays off until power or SRST are cycled.
0=Normal operation.
OTP_ERR
(Read only)
1=Indicates that the temperature limit of 150°C has been exceeded. Speaker amplifier turns off. Bit remains HIGH
and amplifier stays off until temperature falls below thermal shutdown hysteresis (see Electrical Characteristics) or
power or SRST are cycled.
0=Normal operation.
DC_ERR
(Read only)
1=Indicates that the DC voltage across the speaker amplifier terminals has exceeded 1.5Vpk. Speaker amplifier turns
off. Bit remains high and amplifier stays off until power or SRST are cycled.
0=Normal operation.
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
29
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
ADDR
Selects inputs to the headphone amplifiers.
HP_MONO DIFA DIFB HP_AMIX
HP_BMIX
HOUTL
HOUTR
1
1
1
1
1
(INA1-INA2+INB1-INB2)/2
Amplifier Off
1
1
1
1
0
(INA1-INA2)/2
Amplifier Off
1
1
1
0
1
(INB1-INB2)/2
Amplifier Off
1
1
1
0
0
Amplifier Off
Amplifier Off
1
1
0
1
1
(INA1-INA2+INB1+INB2)/2
Amplifier Off
1
1
0
1
0
(INA1-INA2)/2
Amplifier Off
1
1
0
0
1
(INB1+INB2)/2
Amplifier Off
1
1
0
0
0
Amplifier Off
Amplifier Off
1
0
1
1
1
(INA1+INA2+INB1-INB2)/2
Amplifier Off
1
0
1
1
0
(INA1+INA2)/2
Amplifier Off
1
0
1
0
1
(INB1-INB2)/2
Amplifier Off
1
0
1
0
0
Amplifier Off
Amplifier Off
1
0
0
1
1
(INA1+INA2+INB1+INB2)/2
Amplifier Off
1
0
0
1
0
(INA1+INA2)/2
Amplifier Off
1
0
0
0
1
(INB1+INB2)/2
Amplifier Off
1
0
0
0
0
Amplifier Off
Amplifier Off
0
1
1
1
1
(INA1-INA2+INB1-INB2)
(INA1-INA2+INB1-INB2)
0
1
1
1
0
(INA1-INA2)
(INA1-INA2)
0
1
1
0
1
(INB1-INB2)
(INB1-INB2)
0
1
1
0
0
Amplifier Off
Amplifier Off
0
1
0
1
1
[(INA1-INA2)]+INB1
[(INA1-INA2)]+INB2
0
1
0
1
0
(INA1-INA2)
(INA1-INA2)
0
1
0
0
1
INB1
INB2
0
1
0
0
0
Amplifier Off
Amplifier Off
0
0
1
1
1
INA1+[(INB1-INB2)]
INA2+[(INB1-INB2)]
0
0
1
1
0
INA1
INA2
0
0
1
0
1
(INB1-INB2)
(INB1-INB2)
0
0
1
0
0
Amplifier Off
Amplifier Off
0
0
0
1
1
INA1+ INB1
INA2+INB2
0
0
0
1
0
INA1
INA2
0
0
0
0
1
INB1
INB2
0
0
0
0
0
Amplifier Off
Amplifier Off
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
30
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
HP_MONO, HP_AMIX, HP_BMIX
Selects inputs to the speaker amplifier.
DIFA
DIFB
SP_AMIX
SP_BMIX
Speaker Volume Inputs
1
1
1
1
(INA1-INA2+INB1-INB2)/2
1
1
1
0
(INA1-INA2)/2
1
1
0
1
(INB1-INB2)/2
1
1
0
0
Speaker Amplifier Off
1
0
1
1
(INA1-INA2+INB1+INB2)/2
1
0
1
0
(INA1-INA2)/2
1
0
0
1
(INB1+INB2)/2
1
0
0
0
Speaker Amplifier Off
0
1
1
1
(INA1+INA2+INB1-INB2)/2
0
1
1
0
(INA1+INA2)/2
0
1
0
1
(INB1-INB2)/2
0
1
0
0
Speaker Amplifier Off
0
0
1
1
(INA1+INA2+INB1+INB2)/2
0
0
1
0
(INA1+INA2)/2
0
0
0
1
(INB1+INB2)/2
0
0
0
0
Speaker Amplifier Off
ADDR
B7
0xC0
0
Default
0
B6
B5
B4
DALC[2:0]
0
0
1
B3
B2
B1
B0
HP_GAIN[1:0]
SP_GAIN[1:0]
0
0
0
0
DALC[2:0]
Sets the DRC’s clip limiter. To avoid extraneous noise, do not change this setting while the speaker amplifier is on.
DALC[2:0]
SVDD Fraction (V/V)
THD with 1KHz Sine Wave (%) (VSVDD=3.7V, 8Ω Load)
111
Reserved
Reserved
110
Reserved
Reserved
101
Reserved
Reserved
100
1.15
10
011
1.00
4.9
010
0.95
3
001
0.90
1
000
Reserved
Reserved
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
31
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
SP_AMIX, SP_BMIX
Sets the gain of the headphone amplifier block.
HP_GAIN[1:0]
Headphone Amplifier Gain (dB)
11
6.0
10
3.0
01
1.5
00
0
SP_GAIN[1:0]
Sets the speaker amplifier gain.
SP_GAIN[1:0]
Speaker Amplifier Gain (dB)
11
Reserved
10
24
01
20
00
16
ADDR
B7
B6
B5
B4
B3
B2
B1
B0
0xC1
0
0
0
0
0
HP_ZCSOFF
0
SP_ZCSOFF
Default
0
0
0
0
0
1
0
1
SP_ZCSOFF
1=Speaker volume zero-crossing detection is off.
0=Speaker volume zero-crossing detection is on.
HP_ZCSOFF
1=Headphone volume zero-crossing detection is off.
0=Headphone volume zero-crossing detection is on.
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
32
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
HP_GAIN[1:0]
Layout Considerations
Recommended Routing/Layout Rules
General layout and supply bypassing play a major role
in analog performance and thermal characteristics.
Fairchild provides a demonstration board to guide layout
and aid device evaluation. A graphical user interface
software program allows control of the I2C registers to
optimize the performance of the device in various
applications. For the best results, follow the steps and
recommended routing rules listed below.


Do not run analog and digital signals in parallel.

Traces should run on top of the ground plane at all
times.



No trace should run over ground/power splits.

Minimize all trace lengths to reduce series
inductance.
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
Use separate analog and digital power planes to
supply power.
Avoid routing at 90-degree angles.
Place bypass capacitors within 2.54mm (0.1
inches) of the device power pin.
www.fairchildsemi.com
33
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
Applications Information
BALL A1
INDEX AREA
F
A
E
1.20
B
0.03 C
Ø0.20
Cu Pad
A1
2X
1.60
D
0.40
Ø0.30 Solder
Mask Opening
0.40
0.03 C
2X
TOP VIEW
RECOMMENDED LAND PATTERN
(NSMD TYPE)
0.06 C
0.625
0.547
0.05 C
C
0.378±0.018
0.208±0.021
E
SEATING PLANE
SIDE VIEWS
D
NOTES:
0.005
1.20
A. NO JEDEC REGISTRATION APPLIES.
C A B
B. DIMENSIONS ARE IN MILLIMETERS.
Ø0.260±0.02
20X
0.40
E
D
C
B
1.60
0.40
C. DIMENSIONS AND TOLERANCE
PER ASMEY14.5M, 1994.
D. DATUM C IS DEFINED BY THE SPHERICAL
CROWNS OF THE BALLS.
(Y) ±0.018
A
1 2 3 4
E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS
±39 MICRONS (547-625 MICRONS).
F
(X) ±0.018
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
BOTTOM VIEW
G. DRAWING FILNAME: MKT-UC020AArev2.
External Product Dimensions
Product
D
E
X
Y
FAB2210UCX
1.96mm
1.96mm
0.018mm
0.018mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent version. Package specifications do not expand Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductors online packaging area for the most recent packaging drawings and tape and reel
specifications: http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1
www.fairchildsemi.com
34
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
Physical Dimensions
FAB2210 — Audio Subsystem with Class-G Headphone and 3.3W Mono Class-D Speaker with Dynamic Range Compression
35
www.fairchildsemi.com
© 2011 Fairchild Semiconductor Corporation
FAB2210 • Rev. 1.1.1