FAN7930B Critical Conduction Mode PFC Controller Features Description The FAN7930B is an active power factor correction (PFC) controller for boost PFC applications that operate in critical conduction mode (CRM). It uses a voltage-mode PWM that compares an internal ramp signal with the error amplifier output to generate a MOSFET turn-off signal. Because the voltage-mode CRM PFC controller does not need rectified AC line voltage information, it saves the power loss of an input voltage sensing network necessary for a current-mode CRM PFC controller. Additional OVP Detection Pin Input Voltage Absent Detection Circuit Maximum Switching Frequency Limitation Internal Soft-Start and Overshoot-less Control Internal Total Harmonic Distortion (THD) Optimizer Precise Adjustable Output Over-Voltage Protection Open-Feedback Protection and Disable Function Zero Current Detector 150μs Internal Startup Timer MOSFET Over-Current Protection Under-Voltage Lockout with 3.5V Hysteresis Low Startup and Operating Current Totem-Pole Output with High State Clamp +500/-800mA Peak Gate Drive Current 8-Pin Small Outline Package (SOP) Related Resources Applications FAN7930B provides over-voltage protection, openfeedback protection, over-current protection, inputvoltage-absent detection, and under-voltage lockout protection. The additional OVP pin can be used to shut down the boost power stage when output voltage exceeds OVP level due to the resistors that are connected at INV pin are damaged. The FAN7930B can be disabled if the INV pin voltage is lower than 0.45V and the operating current decreases to a very low level. Using a new variable on-time control method, THD is lower than the conventional CRM boost PFC ICs. AN-8035 — Design Consideration Conduction Mode PFC Using FAN7930 Adapter for Boundary Ballast LCD TV, CRT TV SMPS Ordering Information Part Number Operating Temperature Range Top Mark -40 to +125°C FAN7930B Package FAN7930BM Packing Method Rail FAN7930BMX © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 8-Lead Small Outline Package (SOP) Tape & Reel www.fairchildsemi.com FAN7930B — Critical Conduction Mode PFC Controller October 2010 Figure 1. Typical Boost PFC Application Internal Block Diagram Figure 2. © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 FAN7930B — Critical Conduction Mode PFC Controller Application Diagram Functional Block Diagram www.fairchildsemi.com 2 VCC OUT GND ZCD FAN7930B 8-SOP INV Figure 3. OVP COMP CS Pin Configuration (Top View) Pin Definitions Pin # Name Description 1 INV This pin is the inverting input of the error amplifier. The output voltage of the boost PFC converter should be resistively divided to 2.5V. 2 OVP This pin is used to detect PFC output over voltage when INV pin information is not correct. 3 COMP 4 CS 5 ZCD This pin is the input of the zero-current detection block. If the voltage of this pin goes higher than 1.5V, then goes lower than 1.4V, the MOSFET is turned on. 6 GND This pin is used for the ground potential of all the pins. For proper operation, the signal ground and the power ground should be separated. 7 OUT This pin is the gate drive output. The peak sourcing and sinking current levels are +500mA and 800mA, respectively. For proper operation, the stray inductance in the gate driving path must be minimized. 8 VCC This is the IC supply pin. IC current and MOSFET drive current are supplied using this pin. This pin is the output of the transconductance error amplifier. Components for the output voltage compensation should be connected between this pin and GND. FAN7930B — Critical Conduction Mode PFC Controller Pin Configuration This pin is the input of the over-current protection comparator. The MOSFET current is sensed using a sensing resistor and the resulting voltage is applied to this pin. An internal RC filter is included to filter switching noise. © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC Parameter Min. Supply Voltage Max. Unit VZ V IOH, IOL Peak Drive Output Current -800 +500 mA ICLAMP Driver Output Clamping Diodes VO>VCC or VO<-0.3V -10 +10 mA -10 +10 mA -0.3 8.0 -10 6 IDET VIN Detector Clamping Diodes Error Amplifier Input, Output, OVP Input, ZCD and OVP Pin CS Input Voltage (2) TJ Operating Junction Temperature TA Operating Temperature Range Storage Temperature Range TSTG ESD (1) Electrostatic Discharge Capability V +150 °C -40 +125 °C -65 +150 °C Human Body Model, JESD22-A114 2.5 Charged Device Model, JESD22-C101 2.0 kV Notes: 1. When this pin is supplied by external power sources by accident, its maximum allowable current is 50mA. 2. In case of DC input, acceptable input range is -0.3V~6V: within 100ns -10V~6V is acceptable, but electrical specifications are not guaranteed during such a short time. FAN7930B — Critical Conduction Mode PFC Controller Absolute Maximum Ratings Thermal Impedance Symbol ΘJA Parameter Min. (3) Thermal Resistance, Junction-to-Ambient 150 Max. Unit °C/W Note: 3. Regarding the test environment and PCB type, please refer to JESD51-2 and JESD51-10. © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 www.fairchildsemi.com 4 VCC = 14V, TA = -40°C~+125°C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units VCC Section VSTART Start Threshold Voltage VCC Increasing 11 12 13 V VSTOP Stop Threshold Voltage VCC Decreasing 7.5 8.5 9.5 V 3.0 3.5 4.0 V 20 22 HYUVLO UVLO Hysteresis VZ Zener Voltage VOP Recommended Operating Range ICC=20mA 13 24 V 20 V Supply Current Section ISTART Startup Supply Current VCC=VSTART-0.2V 120 190 µA IOP Operating Supply Current Output Not Switching 1.5 3.0 mA IDOP Dynamic Operating Supply Current 50kHZ, CI=1nF 2.5 4.0 mA 90 160 230 µA 2.465 2.500 2.535 V 0.1 10.0 mV IOPDIS Operating Current at Disable VINV=0V Error Amplifier Section VREF1 ΔVREF1 ΔVREF2 Voltage Feedback Input Threshold1 TA=25°C Line Regulation VCC=14V~20V Temperature Stability of VREF1 (4) 20 IEA,BS Input Bias Current VINV=1V~4V IEAS,SR Output Source Current VINV=VREF -0.1V -12 µA IEAS,SK Output Sink Current VINV=VREF +0.1V 12 µA VEAH Output Upper Clamp Voltage VINV=1V, VCS=0V VEAZ Zero Duty Cycle Output Voltage gm Transconductance (4) -0.5 mV 0.5 µA 6.0 6.5 7.0 V 0.9 1.0 1.1 V 90 115 140 µmho 35.5 41.5 47.5 µs 11.2 13.0 14.8 µs 0.7 0.8 0.9 V -1.0 -0.1 1.0 µA 350 500 ns FAN7930B — Critical Conduction Mode PFC Controller Electrical Characteristics Maximum On-Time Section tON,MAX1 Maximum On-Time Programming 1 TA=25°C, VZCD=1V tON,MAX2 Maximum On-Time Programming 2 TA=25°C, IZCD=0.469mA Current-Sense Section VCS ICS,BS tCS,D Current Sense Input Threshold Voltage Limit Input Bias Current VCS=0V~1V Current Sense Delay to Output dV/dt=1V/100ns, from 0V to 5V (4) Continued on the following page… © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 www.fairchildsemi.com 5 VCC = 14V, TA = -40°C~+125°C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units 1.35 1.50 1.65 V 0.05 0.10 0.15 V 5.5 6.2 7.5 V 0 0.65 1.00 V -1.0 -0.1 1.0 µA Zero-Current Detect Section VZCD HYZCD Input Voltage Threshold (4) (4) Detect Hysteresis VCLAMPH Input High Clamp Voltage IDET=3mA VCLAMPL Input Low Clamp Voltage IDET= -3mA IZCD,BS Input Bias Current VZCD=1V~5V (4) IZCD,SR Source Current Capability TA=25°C -4 mA IZCD,SK Sink Current Capability TA=25°C 10 mA tZCD,D Maximum Delay From ZCD to Output (4) Turn-On dV/dt=-1V/100ns, from 5V to 0V 100 200 ns 9.2 (4) Output Section VOH Output Voltage High IO=-100mA, TA=25°C 11.0 12.8 V VOL Output Voltage Low IO=200mA, TA=25°C 1.0 2.5 V (4) CIN=1nF 50 100 ns (4) CIN=1nF 50 100 ns 13.0 14.5 V 1 V tRISE tFALL Rising Time Falling Time VO,MAX Maximum Output Voltage VCC=20V, IO=100µA VO,UVLO Output Voltage with UVLO Activated VCC=5V, IO=100µA 11.5 FAN7930B — Critical Conduction Mode PFC Controller Electrical Characteristics Restart / Maximum Switching Frequency Limit Section tRST fMAX Restart Timer Delay (4) Maximum Switching Frequency 50 150 300 µs 250 300 350 kHz 3 5 7 ms Soft-Start Timer Section tSS (4) Internal Soft-Soft Protections TA=25°C 2.620 2.675 2.730 V HYOVP,INV OVP Hysteresis at INV pin VOVP,INV TA=25°C 0.120 0.175 0.230 V VOVP,OVP OVP Threshold Voltage at OVP pin TA=25°C 2.740 2.845 2.960 V HYOVP,OVP OVP Hysteresis at OVP pin TA=25°C VEN HYEN TSD THYS OVP Threshold Voltage at INV pin Enable Threshold Voltage Enable Hysteresis Thermal Shutdown Temperature (4) 0.345 V 0.40 0.45 0.50 V 0.05 0.10 0.15 V 125 140 155 °C (4) Hysteresis Temperature of TSD 60 °C Note: 4. These parameters, although guaranteed by design, are not production tested. © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 www.fairchildsemi.com 6 Function FAN7530 FAN7930B FAN7930B Advantages None Integrated No External Circuit for additional OVP OVP Pin None Integrated Abnormal CCM Operation Prohibited Frequency Limit AC Absent Detection Integrated Increase System Reliability with AC On-Off Test None Soft-Start and Startup without Overshoot Integrated Reduce Voltage and Current Stress at Startup None Can Avoid Burst Operation at Light Load and High Input Voltage Reduce Probability of Audible Noise Due to the Burst Operation No External Resistor is Needed Control Range Compensation None Integrated THD Optimizer External Internal TSD None 140°C with 60°C Hysteresis Reduction of Power Loss and BOM Cost Caused by additional OVP Circuit Abnormal Inductor Current Accumulation can be Prohibited Guarantee Stable Operation at Short Electric Power Failure Eliminate Audible Noise due to Unwanted OVP Triggering Stable and Reliable TSD Operation FAN7930B — Critical Conduction Mode PFC Controller Comparison between FAN7530 and FAN7930B Converter Temperature Range Limited Range Comparison between FAN7930 and FAN7930B Function FAN7930 FAN7930B RDY Pin Integrated None OVP Pin None Integrated Control Range Compensation None Integrated © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 FAN7930B Remark User Choice for the Use of Number #2 Pin www.fairchildsemi.com 7 Figure 4. Voltage Feedback Input Threshold 1 (VREF1) vs. TA Figure 6. Stop Threshold Voltage (VSTOP) vs. TA Figure 8. Operating Supply Current (IOP) vs. TA © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 Figure 5. Figure 7. Figure 9. Start Threshold Voltage (VSTART) vs. TA FAN7930B — Critical Conduction Mode PFC Controller Typical Performance Characteristics Startup Supply Current (ISTART) vs. TA Output Upper Clamp Voltage (VEAH) vs. TA www.fairchildsemi.com 8 Figure 10. Zero Duty Cycle Output Voltage (VEAZ) vs. TA Figure 11. Maximum On-Time Program 1 (tON,MAX1) vs. TA Figure 12.Maximum On-Time Program 2 (tON,MAX2) vs. TA Figure 13. Current Sense Input Threshold Voltage Limit (VCS) vs. TA Figure 14. Input High Clamp Voltage (VCLAMPH) vs. TA © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 Figure 15. FAN7930B — Critical Conduction Mode PFC Controller Typical Performance Characteristics Input Low Clamp Voltage (VCLAMPL) vs. TA www.fairchildsemi.com 9 Figure 16. Output Voltage High (VOH) vs. TA Figure 17. Output Voltage Low (VOL) vs. TA Figure 18. Restart Timer Delay (tRST) vs. TA Figure 19. OVP Threshold at OVP Pin (VOVP,OVP) vs. TA Figure 20. Output Saturation Voltage (VRDY,SAT) vs. TA Figure 21. OVP Threshold Voltage (VOVP) vs. TA © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 FAN7930B — Critical Conduction Mode PFC Controller Typical Performance Characteristics www.fairchildsemi.com 10 1. Startup: Normally, supply voltage (VCC) of a PFC block is fed from the additional power supply, which can be called standby power. Without this standby power, auxiliary winding to detect zero current detection can be used as a supply source. Once the supply voltage of the PFC block exceeds 12V, internal operation is enabled until the voltage drops to 8.5V. If VCC exceeds VZ, 20mA current is sinking from VCC. Figure 23. Figure 22. Circuit Around INV Pin Startup Circuit 2. INV Block: Scaled-down voltage from the output is the input for the INV pin. Many functions are embedded based on the INV pin: transconductance amplifier, output OVP comparator and disable comparator. For the output voltage control, a transconductance amplifier is used instead of the conventional voltage amplifier. The transconductance amplifier (voltagecontrolled current source) aids the implementation of OVP and disables function. The output current of the amplifier changes according to the voltage difference of the inverting and non-inverting input of the amplifier. To cancel down the line input voltage effect on power factor correction, effective control response of PFC block should be slower than the line frequency and these conflicts with the transient response of controller. Twopole one-zero type compensation may be used to meet both requirements. Figure 24. Timing Chart for INV Block 3. OVP Pin: Over-Voltage Protection (OVP) is embedded by the information at the INV pin. That information comes from the output through the voltage dividing resistors. To scale down from high voltage to low one, high resistance normally used with low resistance. In cases the resistor of high resistance get a damage and resistance is changed to high, though INV pin information is normal output voltage exceeds its rated output. Once this happen, output electrolytic capacitor may be exploded. To prevent such a catastrophe additional OVP pin is assigned to double check output voltage. Thus additional OVP may be nd st called 2 OVP while INV pin OVP can be called 1 OVP. The OVP comparator shuts down the output drive block when the voltage of the INV pin is higher than 2.675V and there is 0.175V hysteresis. The disable comparator disables the operation when the voltage of the inverting input is lower than 0.35V and there is 100mV hysteresis. An external small-signal MOSFET can be used to disable the IC. The IC operating current decreases to reduce power consumption if the IC is disabled. 0 is the timing chart of the internal circuit near the INV pin when rated PFC output voltage is assumed at 390VDC and VCC supply voltage is 15V. © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 FAN7930B — Critical Conduction Mode PFC Controller Applications Information www.fairchildsemi.com 11 where, VAUX is the auxiliary winding voltage, TIND and TAUX are boost inductor turns and auxiliary winding turns respectively, VAC is input voltage for PFC converter and VOUT_PFC is output voltage from the PFC converter. Figure 26. Figure 25. st Comparison of 1 and 2 Recovering Mode nd Because auxiliary winding voltage can swing from negative voltage to positive voltage, the internal block in ZCD pin has both positive and negative voltage clamping circuits. When the auxiliary voltage is negative, internal circuit clamps the negative voltage at the ZCD pin around 0.65V by sourcing current to the serial resistor between the ZCD pin and the auxiliary winding. When the auxiliary voltage is higher than 6.5V, current is sinked through a resistor from the auxiliary winding to the ZCD pin. OVP 4. Control Range Compensation: On time is controlled by the output voltage compensator with FAN7930B. Due to this when input voltage is high and load is light, control range become narrow compared when input voltage is low. That control range decrease is antiproportional to the double square of the input voltage. Thus at high line unwanted burst operation easily happens at light load and audible noise may be generated from the boost inductor or inductor at input filter. Different from the other converters, burst operation in PFC block is not needed because PFC block itself is normally disabled during standby mode. To improve this kind of unwanted burst operation at light load, internal control range compensation function is implemented and approximately shows no burst operation until 5% load at high line. Figure 27. Auxiliary Voltage Depends on MOSFET Switching To check the boost inductor current zero instance, auxiliary winding voltage is used. When boost inductor current becomes zero, there is a resonance between boost inductor and all capacitors at MOSFET drain pin, including COSS of the MOSFET; an external capacitor at the D-S pin to reduce the voltage rising and falling slope of the MOSFET; a parasitic capacitor at inductor; and so on to improve performance. Resonated voltage is reflected to the auxiliary winding and can be used as detecting zero current of boost inductor and valley position of MOSFET voltage stress. For valley detection, a minor delay by the resistor and capacitor is needed. A capacitor increases the noise immunity at the ZCD pin. If ZCD voltage is higher than 1.5V, an internal ZCD comparator output becomes HIGH and LOW when the ZCD goes below 1.4V. At the falling edge of comparator output, internal logic turns on the MOSFET. 5. Zero-Current Detection: Zero-current detection (ZCD) generates the turn-on signal of the MOSFET when the boost inductor current reaches zero using an auxiliary winding coupled with the inductor. When the power switch turns on, negative voltage is induced at the auxiliary winding due to the opposite winding direction (see Equation 1) and positive voltage is induced (see Equation 2) when the power switch turns off. T VAUX = − AUX ⋅ VAC TIND (1) T VAUX = AUX ⋅ (VPFCOUT − VAC ) TIND (2) © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 Circuit Near ZCD FAN7930B — Critical Conduction Mode PFC Controller Since the two OVP conditions are quite different, protection recovering mode is different. Once the first OVP triggers, switching stops immediately and recovers switching when the output voltage is decreased with a hysteresis. When the second OVP triggers, switching can be recovered only when the VCC supply voltage falls below VSTOP and builds up higher than VSTART again and VOVP should be lower than hysteresis. If the second OVP is not used, the OVP pin must be connected to the INV pin or to the ground. www.fairchildsemi.com 12 Maximum Switching Frequency Limit Operation 6. Control: The scaled output is compared with the internal reference voltage and sinking or sourcing current is generated from the COMP pin by the transconductance amplifier. The error amplifier output is compared with the internal sawtooth waveform to give proper turn-on time based on the controller. Figure 28. Auxiliary Voltage Threshold When no ZCD signal is available, the PFC controller cannot turn on MOSFET, so the controller checks every switching off time and forces MOSFET turn on when the off time is longer than 150μs. It is called restart timer. Restart timer triggers MOSFET turn on at startup and may be used at the input voltage zero cross period. Figure 31. Restart Timer at Startup Because the MOSFET turn on depends on the ZCD input, switching frequency may increase to higher than several megahertz due to the miss-triggering or noise on the nearby ZCD pin. If the switching frequency is higher than needed for critical conduction mode (CRM), operation mode shifts to continuous conduction mode (CCM). In CCM, unlike CRM where the boost inductor current is reset to zero at the next switch on; inductor current builds up at every switching cycle and can be raised to very high current, that exceeds the current rating of the power switch or diode. This can seriously damage the power switch and result in burn down. To avoid this, maximum switching frequency limitation is embedded. If ZCD signal is applied again within 3.3μs after the previous rising edge of gate signal, this signal is ignored internally and FAN7930B waits for another ZCD signal. This slightly degrades the power factor performance at light load and high input voltage. © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 Control Circuit Unlike a conventional voltage-mode PWM controller, FAN7930B turns on the MOSFET at the falling edge of ZCD signal. On instance is decided by the external signal and the turn-on time lasts until the error amplifier output (VCOMP) and sawtooth waveform meet. When load is heavy, output voltage decreases, scaled output decreases, COMP voltage increases to compensate low output, turn-on time lengthens to give more inductor turn-on time, and increased inductor current raises the output voltage. This is how PFC negative feedback controller regulates output. 150μs Figure 29. FAN7930B — Critical Conduction Mode PFC Controller Figure 30. The maximum of VCOMP is limited to 6.5V, which dictates the maximum turn-on time, and switching stops when VCOMP is lower than 1.0V. 0.155 V / μs Figure 32. Turn-On Time Determination www.fairchildsemi.com 13 VCC VSTART=12V VREFSS VREFEND=2.5V 5ms VINV=0.4V gM ISOURCECOMP (VREFSS-VINV) VCOMP ISOURCECOMP gM=ISOURCECOMP RCOMP=VCOMP FAN7930 Rev.00 t Figure 33. Figure 35. Compensators Gain Curve 8. Startup without Overshoot: Feedback control speed of PFC is quite slow. Due to the slow response, there is a gap between output voltage and feedback control. That is why over-voltage protection (OVP) is critical at the PFC controller and voltage dip caused by fast load changes from light to heavy is diminished by a bulk capacitor. OVP is easily triggered at startup phase. Operation on and off by OVP at startup may cause audible noise and can increase voltage stress at startup, which is normally higher than in normal operation. This operation is better when soft-start time is very long. However, too long startup time enlarges the output voltage building time at light load. FAN7930B has “overshoot-less” control at startup. During startup, the feedback loop is controlled by an internal proportional gain controller and when the output voltage reaches the rated value, it switches to an external compensator after a transition time of 30ms. In short, an internal proportional gain controller eliminates overshoot at startup and an external conventional compensator takes over successfully afterward. For the transconductance error amplifier side, gain changes based on differential input. When the error is large, gain is large to make the output dip or peak to suppress quickly. When the error is small, low gain is used to improve power factor performance. 250 μmho 115 μmho Figure 34. Soft-Start Sequence FAN7930B — Critical Conduction Mode PFC Controller The roles of PFC controller are regulating output voltage and input current shaping to increase power factor. Duty control based on the output voltage should be fast enough to compensate output voltage dip or overshoot. For the power factor, however, the control loop must not react to the fluctuating AC input voltage. These two requirements conflict; therefore, when designing a feedback loop, the feedback loop should be least 10 times slower than AC line frequency. That slow response is made by C1 at compensator. R1 makes gain boost around operation region and C2 attenuates gain at higher frequency. Boost gain by R1 helps raise the response time and improves phase margin. Gain Characteristic 7. Soft-Start: When VCC touches VSTART, internal reference voltage is increased like a stair step for 5ms. As a result, VCOMP is also raised gradually and MOSFET turn-on time increases smoothly. This reduces voltage and current stress on the power switch during startup. Figure 36. © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 Overshoot-less Startup Control www.fairchildsemi.com 14 Figure 37. Figure 38. To improve this, lengthened turn-on time near the zero cross region is a well-known technique, though the method may be different from company to company and may be proprietary. FAN7930B embodies this by sourcing current through the ZCD pin. Auxiliary winding voltage becomes negative when the MOSFET turns on and is proportional to input voltage. The negative clamping circuit of ZCD outputs the current to maintain the ZCD voltage at a fixed value. The sourcing current from the ZCD is directly proportional to the input voltage. Some portion of this current is applied to the internal sawtooth generator together with a fixed-current source. Theoretically, the fixed-current source and the capacitor at sawtooth generator decide the maximum turn-on time when no current is sourcing at ZCD clamp circuit and available turn-on time gets shorter proportional to the ZCD sourcing current. Input and Output Current Near Input Voltage Peak Circuit of THD Optimizer Figure 40. Effect of THD Optimizer By THD optimizer, turn-on time over one AC line period is proportionally changed, depending on input voltage. Near zero cross, lengthened turn-on time improves THD performance. Input and Output Current Near Input Voltage Peak Zero Cross © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 Figure 39. FAN7930B — Critical Conduction Mode PFC Controller 9. THD Optimization: Total harmonic distortion (THD) is the factor that dictates how closely input current shape matches sinusoidal form. The turn-on time of the PFC controller is almost constant over one AC line period due to the extremely low feedback control response. The turn-off time is decided by the current decrease slope of the boost inductor made by the input voltage and output voltage. Once inductor current becomes zero, resonance between COSS and the boost inductor makes oscillating waveforms at the drain pin and auxiliary winding. By checking the auxiliary winding voltage through the ZCD pin, the controller can check the zero current of boost inductor. At the same time, a minor delay time is inserted to determine the valley position of drain voltage. The input and output voltage difference is at its maximum at the zero cross point of AC input voltage. The current decrease slope is steep near the zero cross region and more negative inductor current flows during a drain voltage valley detection time. Such a negative inductor current cancels down the positive current flows and input current becomes zero, called “zero-cross distortion” in PFC. www.fairchildsemi.com 15 VOUT VIN Though VIN is eliminated, operation of controller is normal due to the large bypass capacitor. VAUX MOSFET Gate DMAX fMIN fMIN DMIN NewVCOMP Input Voltage Absent Detected IDS Smooth SoftStart FAN7930 Rev.00 t Figure 42. Operation with Input Voltage Absent Circuit FAN7930B — Critical Conduction Mode PFC Controller 10. Input Voltage Absent Detection: To save power loss caused by input voltage sensing resistors and to optimize THD easily, the FAN7930B omits AC input voltage detection. Therefore, no information about AC input is available from the internal controller. In many cases, the VCC of PFC controller is supplied by an independent power source like standby power. In this scheme, some mismatch may exist. For example, when the electric power is suddenly interrupted during two or three AC line periods; VCC is still alive during that time, but output voltage drops because there is no input power source. Consequently, the control loop tries to compensate for the output voltage drop and VCOMP reaches its maximum. This lasts until AC input voltage is live again. When AC input voltage is live again, high VCOMP allows high switching current and more stress is put on the MOSFET and diode. To protect against this, FAN7930B internally checks if the input AC voltage exists. If input does not exist, soft-start is reset and waits until AC input is live again. Soft-start manages the turn-on time for smooth operation when it detects AC input is applied again and applies less voltage and current stress on startup. 11. Current Sense: The MOSFET current is sensed using an external sensing resistor for the over-current protection. If the CS pin voltage is higher than 0.8V, the over-current protection comparator generates a protection signal. An internal RC filter of 40kΩ and 8pF is included to filter switching noise. 12. Gate Driver Output: FAN7930B contains a single totem-pole output stage designed for a direct drive of the power MOSFET. The drive output is capable of up to +500/-800mA peak current with a typical rise and fall time of 50ns with 1nF load. The output voltage is clamped to 13V to protect the MOSFET gate even if the VCC voltage is higher than 13V. Figure 41. Operation without Input Voltage Absent Circuit © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 www.fairchildsemi.com 16 PFC block normally handles high switching current and the voltage low energy signal path can be affected by the high energy path. Cautious PCB layout is mandatory for stable operation. 1. 2. 3. 4. 5. The gate drive path should be as short as possible. The closed-loop that starts from the gate driver, MOSFET gate, and MOSFET source to ground of PFC controller is recommended as close as possible. This is also crossing point between power ground and signal ground. Power ground path from the bridge diode to the output bulk capacitor should be short and wide. The sharing position between power ground and signal ground should be only at one position to avoid ground loop noise. Signal path of PFC controller should be short and wide for external components to contact. PFC output voltage sensing resistor is normally high to reduce current consumption. This path can be affected by external noise. To reduce noise possibility at the INV pin, a shorter path for output sensing is recommended. If a shorter path is not possible, place some dividing resistors between PFC output and the INV pin — closer to the INV pin is better. Relative high voltage close to the INV pin can be helpful. ZCD path is recommended close to auxiliary winding from boost inductor and to the ZCD pin. If that is difficult, place a small capacitor (below 50pF) to reduce noise. Switching current sense path should not share with another path to avoid interference. Some additional components may be needed to reduce the noise level applied to the CS pin. © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 A stabilizing capacitor for VCC is recommended as close as possible to the VCC and ground pins. If it is difficult, place the SMD capacitor as close to the corresponding pins as possible. Figure 43. FAN7930B — Critical Conduction Mode PFC Controller PCB Layout Guide Recommended PCB Layout www.fairchildsemi.com 17 Application Device Input Voltage Range Rated Output Power Output Voltage (Maximum Current) LCD TV Power Supply FAN7930B 90-265VAC 195W 390V (0.5A) Features Average efficiency of 25%, 50%, 75%, and 100% load conditions is higher than 95% at universal input. Power factor at rated load is higher than 0.98 at universal input. Total Harmonic Distortion (THD) at rated load is lower than 15% at universal input. Key Design Notes When auxiliary VCC supply is not available, VCC power can be supplied through Zero Current Detect (ZCD) winding. The power consumption of R103 is quite high, so its power rating needs checking. Because the input bias current of INV pin is almost zero, output voltage sensing resistors (R112~R115) as high as possible. However, too-high resistance makes the node easily affected by noise. Thus values need to strike a balance between power consumption and noise immunity. Quick charge diode (D106) can be eliminated if output diode inrush current capability is enough. Thought D106, system operation is normal due to the controller’s highly reliable protection features. 1. Schematic FAN7930 — Critical Conduction Mode PFC Controller Typical Application Circuit R116 3.9M R112 3.9M R102, 330k R117 3.9M R113 3.9M C111 220 F, 450V R118 3.9M TH101, 5D15 R114 3.9M R104, 30k D101,1N4746 C1030,68 F ,630Vdc R119 75k R115 75k R111 0.08, 5W C116,1nF C110,1nF C112,470pF D104,1N4148 R110,10k C109, 47nF R107, C108, 10k 220nF C105, 100nF C107, 33 F LF101, 23mH FS101, 250V,5A Figure 44. © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 Demonstration Circuit www.fairchildsemi.com 18 Figure 45. Transformer Schematic Diagram of FAN7930B 3. Winding Specification Position Bottom Top No Pin (S → F) Wire Turns Winding Method Np 9, 10 → 7, 8 0.1φ×50 49 Solenoid Winding Barrier Tape TOP BOT Ts 1 FAN7930 — Critical Conduction Mode PFC Controller 2. Transformer Insulation: Polyester Tape t = 0.025mm, 3 Layers 2→4 NAUX 0.3φ 6 Solenoid Winding Insulation: Polyester Tape t = 0.025mm, 4 Layers 4. Electrical Characteristics Inductance Pin Specification Remark 9, 10 → 7, 8 230μH ± 7% 100kHz, 1V 5. Core & Bobbin 2 Core: EER3124, Samhwa (PL-7) (Ae=97.9mm ) Bobbin: EER3124 © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 www.fairchildsemi.com 19 Part # Value Note Part # Resister 1MΩ 1W R102 330 kΩ 1/2W R103 10 kΩ 1W 30kΩ Note Switch R101 R104 Value Q101 FCPF20N60 20A, 600V, SuperFET Diode D101 1/4W D102 1N4746 1W, 18V, Zener Diode UF4004 1A, 400V Glass Passivated High-Efficiency Rectifier R107 10kΩ 1/4W D103 1N4148 1A, 100V Small-Signal Diode R108 4.7kΩ 1/4W D104 1N4148 1A, 100V Small-Signal Diode R109 R110 R111 47kΩ 10kΩ 0.80kΩ R112, 113, 114,116,117,118 3.9kΩ R115,119 75kΩ 1/4W 1/4W D105 8A, 600V, General-Purpose Rectifier D106 3A, 600V, General-Purpose Rectifier 5W 1/4W IC101 FAN7930B 1/4W Capacitor Fuse C101 220nF/275VAC Box Capacitor C102 680nF/275VAC Box Capacitor C103 0.68µF/630V Box Capacitor C104 12nF/50V Ceramic Capacitor C105 100nF/50V SMD (1206) C107 33µF/50V Electrolytic Capacitor C108 220nF/50V Ceramic Capacitor FS101 5A/250V NTC TH101 5D-15 Bridge Diode BD101 C109 47nF/50V Ceramic Capacitor C110,116 1nF/50V Ceramic Capacitor C112 47nF/50V Ceramic Capacitor C111 220µF/450V Electrolytic Capacitor C114 2.2nF/450V Box Capacitor C115 2.2nF/450V Box Capacitor © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 CRM PFC Controller FAN7930 — Critical Conduction Mode PFC Controller 6. Bill of Materials 15A, 600V Line Filter LF101 23mH T1 EER3124 Transformer Ae=97.9mm 2 ZNR ZNR101 10D471 www.fairchildsemi.com 20 5.00 4.80 A 0.65 3.81 5 8 B 1.75 6.20 5.80 PIN ONE INDICATOR 4.00 3.80 1 5.60 4 1.27 (0.33) 1.27 0.25 C B A LAND PATTERN RECOMMENDATION SEE DETAIL A 0.25 0.10 1.75 MAX 0.25 0.19 C 0.51 0.33 0.10 C FAN7930 — Critical Conduction Mode PFC Controller Physical Dimensions OPTION A - BEVEL EDGE 0.50 x 45° 0.25 R0.10 GAGE PLANE R0.10 OPTION B - NO BEVEL EDGE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED 8° 0° 0.90 0.40 A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 46. 8-Lead Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 www.fairchildsemi.com 21 FAN7930 — Critical Conduction Mode PFC Controller © 2010 Fairchild Semiconductor Corporation FAN7930B • Rev. 1.0.2 www.fairchildsemi.com 22