FREESCALE MC33887PFK

Freescale Semiconductor
Technical Data
Document Number: MC33887
Rev. 14.0, 3/2011
5.0 A H-Bridge with Load
Current Feedback
33887
The 33887 is a monolithic H-Bridge Power IC with a load current
feedback feature making it ideal for closed-loop DC motor control.
The IC incorporates internal control logic, charge pump, gate drive,
and low RDS(ON) MOSFET output circuitry. The 33887 is able to
control inductive loads with continuous DC load currents up to 5.0 A,
and with peak current active limiting between 5.2 A and 7.8 A. Output
loads can be pulse width modulated (PWM-ed) at frequencies up to
10 kHz. The load current feedback feature provides a proportional (1/
375th of the load current) constant-current output suitable for
monitoring by a microcontroller’s A/D input. This feature facilitates
the design of closed-loop torque/speed control as well as open load
detection.
A Fault Status output pin reports undervoltage, short circuit, and
overtemperature conditions. Two independent inputs provide polarity
control of two half-bridge totem-pole outputs. Two disable inputs
force the H-Bridge outputs to tri-state (exhibit high-impedance).
The 33887 is parametrically specified over a temperature range of
-40°C ≤ TA ≤ 125°C and a voltage range of 5.0 V ≤ V+ ≤ 28 V.
Operation with voltages up to 40 V with derating of the specifications.
H-BRIDGE
VW SUFFIX (Pb-FREE)
98ASH70702A
20-PIN HSOP
FK SUFFIX
98ASA10583D
36-PIN PQFN
Bottom View
EK SUFFIX (Pb-FREE)
98ASA10506D
54-PIN SOICW-EP
ORDERING INFORMATION
Features
•
•
•
•
•
•
•
•
Fully specified operation 5.0 V to 28 V
Limited operation with reduced performance up to 40 V
120 mΩ RDS(ON) Typical H-Bridge MOSFETs
TTL/CMOS Compatible Inputs
PWM Frequencies up to 10 kHz
Active Current Limiting (Regulation)
Fault Status Reporting
Sleep Mode with Current Draw ≤50 μA (Inputs Floating or Set
to Match Default Logic States)
Temperature
Range (TA)
Device
MC33887APVW/R2
20 HSOP
MC33887PFK/R2
-40°C to 125°C
MC33887PEK/R2
V+
33887
MCU
IN
FS
OUT
EN
OUT
IN1
OUT
IN2
OUT
D1
OUT
D2
A/D
FB
V+
OUT1
MOTOR
OUT2
PGND
AGND
Figure 1. 33887 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2007 - 2011. All rights reserved.
36 PQFN
54 SOICW-EP
6.0 V
CCP
Package
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
CCP
CHARGE PUMP
EN
8 μA
(EACH)
CURRENT
LIMIT,
OVERCURRENT
SENSE &
FEEDBACK
CIRCUIT
5.0 V
REGULATOR
OUT1
IN1
IN2
D1
D2
VPWR
GATE
DRIVE
25 μA
CONTROL
LOGIC
OUT2
OVER
TEMPERATURE
FS
UNDERVOLTAGE
FB
AGND
PGND
Figure 2. 33887 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
Tab
AGND
FS
IN1
V+
V+
OUT1
OUT1
FB
PGND
PGND
1
20
2
19
3
4
18
17
5
16
6
7
15
14
8
13
9
12
10
11
EN
IN2
D1
CCP
V+
OUT2
OUT2
D2
PGND
PGND
Tab
Figure 3. 33887 Pin Connections
Table 1. 33887 HSOP PIN DEFINITIONS
A functional description of each pin can be found in the Functional Pin DescriptionS section, page 21.
Pin
Pin Name
Formal Name
Definition
1
AGND
Analog Ground
2
FS
Fault Status for H-Bridge
3
IN1
Logic Input Control 1
4 , 5, 16
V+
Positive Power Supply
6, 7
OUT1
H-Bridge Output 1
8
FB
Feedback for H-Bridge
9 – 12
PGND
Power Ground
13
D2
Disable 2
14 , 15
OUT2
H-Bridge Output 2
17
CCP
Charge Pump Capacitor
18
D1
Disable 1
19
IN2
Logic Input Control 2
20
EN
Enable
Logic input Enable control of device (i.e., EN logic HIGH = full operation, EN
logic LOW = Sleep Mode).
Tab/Pad
Thermal
Interface
Exposed Pad Thermal
Interface
Exposed pad thermal interface for sinking heat from the device.
Note Must be DC-coupled to analog ground and power ground via very low
impedance path to prevent injection of spurious signals into IC substrate.
Low-current analog signal ground.
Open drain active LOW Fault Status output requiring a pull-up resistor to
5.0 V.
Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).
Positive supply connections
Output 1 of H-Bridge.
Current sensing feedback output providing ground referenced 1/375th
(0.00266) of H-Bridge high-side current.
High-current power ground.
Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When D2 is Logic LOW, both outputs are tri-stated.
Output 2 of H-Bridge.
External reservoir capacitor connection for internal charge pump capacitor.
Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated.
Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
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Analog Integrated Circuit Device Data
Freescale Semiconductor
3
29
30
31
32
33
1
28
2
27
3
26
4
25
5
24
6
23
7
22
18
17
NC
D2
PGND
PGND
PGND
PGND
PGND
PGND
FB
NC
IN1
V+
V+
OUT1
OUT1
NC
OUT1
OUT1
16
19
15
10
14
20
13
21
9
11
8
12
NC
D1
IN2
EN
V+
V+
NC
AGND
FS
NC
34
36
Transparent Top View of Package
35
CCP
V+
V+
OUT2
OUT2
NC
OUT2
OUT2
PIN CONNECTIONS
Figure 4. 33887 Pin Connections
Table 2. PQFN PIN DEFINITIONS
A functional description of each pin can be found in the Functional Pin DescriptionS section, page 21.
Pin
Pin Name
Formal Name
1, 7, 10, 16,
19, 28, 31
NC
No Connect
2
D1
Disable 1
3
IN2
Logic Input Control 2
4
EN
Enable
5, 6, 12, 13, 34, 35
V+
Positive Power Supply
8
AGND
Analog Ground
9
FS
Fault Status for H-Bridge
11
IN1
Logic Input Control 1
14, 15, 17, 18
OUT1
H-Bridge Output 1
20
FB
Feedback for H-Bridge
21– 26
PGND
Power Ground
27
D2
Disable 2
29, 30, 32, 33
OUT2
H-Bridge Output 2
36
CCP
Charge Pump Capacitor
Pad
Thermal
Interface
Exposed Pad Thermal
Interface
Definition
No internal connection to this pin.
Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated.
Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
Logic input Enable control of device (i.e., EN logic HIGH = full operation,
EN logic LOW = Sleep Mode).
Positive supply connections.
Low-current analog signal ground.
Open drain active LOW Fault Status output requiring a pull-up resistor to
5.0 V.
Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).
Output 1 of H-Bridge.
Current feedback output providing ground referenced 1/375th ratio of
H-Bridge high-side current.
High-current power ground.
Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When D2 is Logic LOW, both outputs are tri-stated.
Output 2 of H-Bridge.
External reservoir capacitor connection for internal charge pump
capacitor.
Exposed pad thermal interface for sinking heat from the device.
Note: Must be DC-coupled to analog ground and power ground via very
low impedance path to prevent injection of spurious signals into IC
substrate.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
Transparent Top View of Package
PGND
PGND
PGND
PGND
NC
NC
NC
D2
NC
OUT2
OUT2
OUT2
OUT2
NC
V+
V+
V+
V+
NC
NC
NC
NC
CCP
D1
IN2
EN
NC
1
54
2
53
3
52
4
51
5
50
6
49
7
48
8
47
9
46
10
45
11
44
12
43
13
42
14
41
15
40
16
39
17
38
18
37
19
36
20
.35
21
34
22
33
23
32
24
31
25
30
26
29
27
28
PGND
PGND
PGND
PGND
NC
NC
NC
FB
NC
OUT1
OUT1
OUT1
OUT1
NC
V+
V+
V+
V+
NC
NC
NC
NC
IN1
FS
AGND
NC
NC
Figure 5. 33887 Pin Connections
Table 3. SOICW-EP PIN DEFINITIONS
A functional description of each pin can be found in the Functional Pin DescriptionS section, page 21.
Pin
Pin Name
Formal Name
1– 4, 51– 54
PGND
Power Ground
5 – 7, 9, 14, 19 – 22,
27 – 29, 33 – 36, 41,
46, 48 – 50
NC
No Connect
8
D2
Disable 2
10 – 13
OUT2
H-Bridge Output 2
15 – 18, 37 – 40
V+
Positive Power Supply
23
CCP
Charge Pump Capacitor
24
D1
Disable 1
25
IN2
Logic Input Control 2
26
EN
Enable
30
AGND
Analog Ground
31
FS
Fault Status for H-Bridge
32
IN1
Logic Input Control 1
Definition
High-current power ground.
No internal connection to this pin.
Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When D2 is Logic LOW, both outputs are tri-stated.
Output 2 of H-Bridge.
Positive supply connections.
External reservoir capacitor connection for internal charge pump
capacitor.
Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated.
Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
Logic input Enable control of device (i.e., EN logic HIGH = full operation,
EN logic LOW = Sleep Mode).
Low-current analog signal ground.
Open drain active LOW Fault Status output requiring a pull-up resistor to
5.0 V.
Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).
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Analog Integrated Circuit Device Data
Freescale Semiconductor
5
PIN CONNECTIONS
Table 3. SOICW-EP PIN DEFINITIONS
A functional description of each pin can be found in the Functional Pin DescriptionS section, page 21.
Pin
Pin Name
Formal Name
Definition
42 – 45
OUT1
H-Bridge Output 1
47
FB
Feedback for H-Bridge
Current feedback output providing ground referenced 1/375th ratio of
H-Bridge high-side current.
Pad
Thermal
Interface
Exposed Pad Thermal
Interface
Exposed pad thermal interface for sinking heat from the device.
Note Must be DC-coupled to analog ground and power ground via very
low impedance path to prevent injection of spurious signals into IC
substrate.
Output 1 of H-Bridge.
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6
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
V+
-0.3 to 40
V
ELECTRICAL RATINGS
Supply Voltage (1)
Input Voltage
(2)
VIN
- 0.3 to 7.0
V
FS Status Output (3)
V FS
-0.3 to 7.0
V
Continuous Current (4)
IOUT
5.0
A
DH Suffix HSOP ESD Voltage (5)
V
Human Body Model
Each Pin to AGND
Each Pin to PGND
Each Pin to V+
Each I/O to All Other I/Os
Machine Model
VW Suffix HSOP, SOICW-EP, and PQFN ESD Voltage
VESD1
±1000
VESD1
±1500
VESD1
±2000
VESD1
±2000
VESD2
±200
VESD1
± 2000
(5)
Human Body Model
Machine Model
V
VESD2
± 200
TSTG
- 65 to 150
TA
- 40 to 125
TJ
- 40 to 150
TPPRT
Note 8.
THERMAL RATINGS
Storage Temperature
Operating Temperature (6)
Ambient
Junction
Peak Package Reflow Temperature During Reflow (7), (8)
°C
°C
°C
Notes
1
Performance at voltages greater than 28V is degraded.See Electrical Performance Curves on page 18 and 19 for typical performance.
Extended operation at higher voltages has not been fully characterized and may reduce the operational lifetime.
2
Exceeding the input voltage on IN1, IN2, EN, D1, or D2 may cause a malfunction or permanent damage to the device.
3
Exceeding the pull-up resistor voltage on the open Drain FS pin may cause permanent damage to the device.
4
Continuous current capability so long as junction temperature is ≤ 150°C.
5
ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in
accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
6
7
8.
The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief
nonrepetitive excursions of junction temperature above 150°C can be tolerated as long as duration does not exceed 30 seconds
maximum. (nonrepetitive events are defined as not occurring more than once in 24 hours.)
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
MAXIMUM RATINGS (continued)
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
THERMAL RESISTANCE (AND PACKAGE DISSIPATION) RATINGS (9), (10), (11), (12)
Junction-to-Board (Bottom Exposed Pad Soldered to Board)
HSOP (6.0 W)
PQFN (4.0 W)
SOICW-EP (2.0 W)
Junction-to-Ambient, Natural Convection, Single-Layer Board (1s) (13)
°C/W
RθJB
~7.0
~8.0
~9.0
°C/W
RθJA
HSOP (6.0 W)
PQFN (4.0 W)
SOICW-EP (2.0 W)
~ 41
~ 50
~ 62
Junction-to-Ambient, Natural Convection, Four-Layer Board (2s2p)
(14)
HSOP (6.0 W)
PQFN (4.0 W)
SOICW-EP (2.0 W)
Junction-to-Case (Exposed Pad) (15)
HSOP (6.0 W)
PQFN (4.0 W)
SOICW-EP (2.0 W)
°C/W
RθJMA
~ 18
~ 21
~ 23
°C/W
RθJC
~ 0.8
~1.2
~2.0
Notes
9
The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking.
10
Exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. The actual RθJB (junction-to-PC board)
values will vary depending on solder thickness and composition and copper trace thickness. Maximum current at maximum die
temperature represents ~ 16 W of conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the RθJC-total must be
less than 5.0 °C/W for maximum load at 70°C ambient. Module thermal design must be planned accordingly.
11
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.
12
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
13
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
14
Per JEDEC JESD51-6 with the board horizontal.
15
Indicates the maximum thermal resistance between the die and the exposed pad surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
V+
5.0
–
28
V
–
25
50
POWER SUPPLY
Operating Voltage Range (16)
Sleep State Supply Current
(17)
Standby Supply Current
μA
IQ (SLEEP)
IOUT = 0 A, VEN = 0 V
IQ (STANDBY)
IOUT = 0 A, VEN = 5.0 V
mA
–
–
20
Threshold Supply Voltage
Switch-OFF
Switch-ON
Hysteresis
V+(THRES-OFF)
4.15
4.4
4.65
V+(THRES-ON)
4.5
4.75
5.0
V
V
V+(HYS)
150
–
–
mV
3.35
–
–
–
–
20
3.5
–
–
CHARGE PUMP
Charge Pump Voltage
VCP - V+
V+ = 5.0 V
8.0 V ≤ V+ ≤ 28 V
V
CONTROL INPUTS
Input Voltage (IN1, IN2, D1, D2)
Threshold HIGH
Threshold LOW
Hysteresis
Input Current (IN1, IN2, D1)
V
VIH
VIL
–
–
1.4
VHYS
0.7
1.0
–
- 200
- 80
–
Input Current (D2, EN)
V D2 = 5.0 V
–
25
100
μA
IINP
VIN - 0.0 V
μA
IINP
Notes
16
Specifications are characterized over the range of 5.0 V ≤ V+ ≤ 28 V. See See Electrical Performance Curves on page 18 and 19 and
the See Functional Description on page 21 for information about operation outside of this range.
17
IQ (sleep) is with sleep mode function enabled.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
5.0 V ≤ V+ ≤ 28 V, TJ = 25°C
–
120
–
8.0 V ≤ V+ ≤ 28 V, TJ = 150°C
–
–
225
5.0 V ≤ V+ ≤ 8.0 V, TJ = 150°C
–
–
300
Unit
POWER SUPPLY
POWER OUTPUTS (OUT1, OUT2)
Output ON-Resistance (18)
RDS(ON)
mΩ
Active Current Limiting Threshold (via Internal Constant OFF-Time
PWM) on Low-Side MOSFETs (19)
ILIM
5.2
6.5
7.8
A
High-Side Short Circuit Detection Threshold
ISCH
11
–
–
A
Low-Side Short Circuit Detection Threshold
ISCL
8.0
–
–
A
VOUT = V+
–
100
200
VOUT = Ground
–
30
60
Leakage Current (20)
Output MOSFET Body Diode Forward Voltage Drop
μA
IOUT(LEAK)
VF
V
IOUT = 3.0 A
–
–
2.0
Overtemperature Shutdown
Thermal Limit
Hysteresis
°C
TLIM
175
–
225
THYS
10
–
30
HIGH-SIDE CURRENT SENSE FEEDBACK
Feedback Current
I FB
I OUT = 0 mA
–
–
600
μA
I OUT = 500 mA
1.07
1.33
1.68
mA
I OUT = 1.5 A
3.6
4.0
4.62
mA
I OUT = 3.0 A
7.2
8.0
9.24
mA
I OUT = 6.0 A
14.4
16
18.48
mA
FAULT STATUS (21)
Fault Status Leakage Current (22)
Fault Status SET Voltage (23)
–
–
10
–
–
1.0
V FS(LOW)
I FS = 300 μA
Notes
18
19
20
21
22
23
μA
I FS(LEAK)
V FS = 5.0 V
V
Output-ON resistance as measured from output to V+ and ground.
Active current limitation applies only for the low-side MOSFETs.
Outputs switched OFF with D1 or D2.
Fault Status output is an open Drain output requiring a pull-up resistor to 5.0 V.
Fault Status Leakage Current is measured with Fault Status HIGH and not SET.
Fault Status Set Voltage is measured with Fault Status LOW and SET with I FS = 300 μA.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
f PWM
–
10
–
kHz
f MAX
–
–
20
kHz
–
–
18
TIMING CHARACTERISTICS
PWM Frequency (24)
Maximum Switching Frequency During Active Current Limiting
(25)
Output ON Delay (26)
Output OFF Delay (26)
μs
t D (OFF)
V+ = 14 V
ILIM Output Constant-OFF Time for Low-Side MOSFETs
(27) (28)
ILIM Blanking Time for Low-Side MOSFETs (29), (28)
Output Rise and Fall Time (30)
,
–
–
18
tA
15
20.5
26
μs
tB
12
16.5
21
μs
2.0
5.0
8.0
t D (DISABLE)
–
–
8.0
μs
t POD
–
1.0
5.0
ms
t WUD
–
1.0
5.0
ms
Disable Delay Time (31)
(32)
Wake-Up Delay Time (32)
Output MOSFET Body Diode Reverse Recovery Time
tRR
100
–
–
ns
μs
t F, t R
V+ = 14 V, IOUT = 3.0 A
Power-ON Delay Time
μs
t D (ON)
V+ = 14 V
(33)
Notes
24
The outputs can be PWM-controlled from an external source. This is typically done by holding one input high while applying a PWM
pulse train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching
frequency. See Typical Switching Waveforms, Figures 12 through 19, pp. 14–17.
25
The Maximum Switching Frequency during active current limiting is internally implemented. The internal current limit circuitry produces
a constant-OFF-time pulse-width modulation of the output current. The output load’s inductance, capacitance, and resistance
characteristics affect the total switching period (OFF-time + ON-time) and thus the PWM frequency during current limit.
26
Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition
direction) of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from the midpoint of the input signal to
the 90% point of the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from the midpoint of the input signal
to the 10% point of the output response signal. See Figure 6, page 12.
27
ILIM Output Constant-OFF Time is the time during which the internal constant-OFF time PWM current regulation circuit has tri-stated
the output bridge.
28
Load currents ramping up to the current regulation threshold become limited at the ILIM value. The short circuit currents possess a di/dt
that ramps up to the ISCH or ISCL threshold during the ILIM blanking time, registering as a short circuit event detection and causing the
shutdown circuitry to force the output into an immediate tri-state latch-OFF. See Figures 10 and 11, page 13. Operation in Current Limit
mode may cause junction temperatures to rise. Junction temperatures above ~160°C will cause the output current limit threshold to
progressively “fold back”, or decrease with temperature, until ~175°C is reached, after which the TLIM thermal latch-OFF will occur.
Permissible operation within this fold-back region is limited to nonrepetitive transient events of duration not to exceed 30 seconds. See
Figure 9, page 12.
29
ILIM Blanking Time is the time during which the current regulation threshold is ignored so that the short-circuit detection threshold
comparators my have time to act.
30
Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 8, page 12.
31
Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See
Figure 7, page 12.
32
Parameter has been characterized but not production tested.
33
Parameter is guaranteed by design but not production tested.
33887
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
5. 0
50%
0
50%
t D(OFF)
t D(ON)
VPWR
90%
10%
0
TIME
Figure 6. Output Delay Time
5.0 V
0V
℘?ℜ
0Ω
Figure 7. Disable Delay Time
VPWR
tF
tR
90%
90%
10%
10%
0
CURRENT
IIMAX
OUTPUT
, CURRENT
(A) (A)
LIM,ILIM
Figure 8. Output Switching Time
6.5
6.6
Operation within this region must be
limited to nonrepetitive events
not to exceed 30 seconds
4.0
2.5
Thermal Shutdown
150
160
175
T J, JUNCTION TEMPERATURE (o C)
Figure 9. Active Current Limiting Versus Temperature (Typical)
33887
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
SF, LOGIC OUT
D2, LOGIC IN
D1, LOGIC IN
INn, LOGIC IN
ILOAD, OUTPUT CURRENT (A)
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
>8A
Short Circuit Detection Threshold
Typical Current Limit Threshold
6.5
High Current Load Being Regulated via Constant-OFF-Time PWM
Active
Current
Limiting
on Low-Side
MOSFET
Hard Short Detection and Latch-OFF
Moderate Current Load
0
[1]
[0]
IN1 IN2
IN1 or IN2
IN1 or IN2
IN2 or IN1
IN2 or IN1
[1]
[0]
[1]
[0]
[1]
Outputs
[0]
Tri-Stated
Outputs Operation
(per Input Control Condition)
Outputs
Tri-Stated
Time
CURRENT
ILOADI,OUT
OUTPUT
, CURRENT
(A) (A)
Figure 10. Operating States
IShort
Circuit
Detection
Threshold
Circuit
Detect
Threshold
Overcurrent
Minimum
Threshold
SCL Short
8.0
t on
taa
t bb
6.5
taa==Tristate
Output Output
Constant-OFF
Time
OFF Time
ILIM Blanking
Time
Output
Blanking
Time
ttbb==Current
Limit
Blank
Time
Typical Current
Typical
Load
LimitingPWM
Waveform
Current Limiting
Waveform
short is
detected during t b
Hard Short
Output
Hard
Detection
Short
Latch-OFF
and output
is latched-off.
Hard short occurs.
0.0
5.0
TIME
Figure 11. Example Short Circuit Detection Detail on Low-Side MOSFET
33887
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
TYPICAL SWITCHING WAVEFORMS
TYPICAL SWITCHING WAVEFORMS
• LLOAD = 533 μH @ 1.0 kHz
• LLOAD = 530 μH @ 10.0 kHz
• RLOAD = 4.0 Ω
Important For all plots, the following applies:
• Ch2 = 2.0 A per division
Output Voltage
(OUT1)
IOUT
Input Voltage
(IN1)
V+=24 V
fPWM =1.0 kHz Duty Cycle=10%
Figure 12. Output Voltage and Current vs. Input Voltage at V+ = 24 V,
PMW Frequency of 1.0 kHz, and Duty Cycle of 10%
Output Voltage
(OUT1)
IOUT
Input Voltage
(IN1)
V+=24 V
fPWM = 1.0 kHz Duty Cycle = 50%
Figure 13. Output Voltage and Current vs. Input Voltage at V+ = 24 V,
PMW Frequency of 1.0 kHz, and Duty Cycle of 50%
33887
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TYPICAL SWITCHING WAVEFORMS
Output Voltage
(OUT1)
IOUT
Input Voltage
(IN1)
V+=34 V
fPWM =1.0 kHz Duty Cycle=90%
Figure 14. Output Voltage and Current vs. Input Voltage at V+ = 34 V, PMW Frequency of 1.0 kHz,
and Duty Cycle of 90%, Showing Device in Current Limiting Mode
Output Voltage
(OUT1)
IOUT
Input Voltage
(IN1)
V+=22 V
fPWM =1.0 kHz Duty Cycle=90%
Figure 15. Output Voltage and Current vs. Input Voltage at V+ = 22 V,
PMW Frequency of 1.0 kHz, and Duty Cycle of 90%
33887
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
ELECTRICAL CHARACTERISTICS
TYPICAL SWITCHING WAVEFORMS
Output Voltage
(OUT1)
IOUT
Input Voltage
(IN1)
V+=24 V
fPWM =10 kHz
Duty Cycle=50%
Figure 16. Output Voltage and Current vs. Input Voltage at V+ = 24 V,
PMW Frequency of 10 kHz, and Duty Cycle of 50%
Output Voltage
(OUT1)
IOUT
Input Voltage
(IN1)
V+=24 V
fPWM =10 kHz
Duty Cycle=90%
Figure 17. Output Voltage and Current vs. Input Voltage at V+ = 24 V,
PMW Frequency of 10 kHz, and Duty Cycle of 90%
33887
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TYPICAL SWITCHING WAVEFORMS
Output Voltage
(OUT1)
IOUT
Input Voltage
(IN1)
V+=12 V
fPWM =20 kHz
Duty Cycle=50%
Figure 18. Output Voltage and Current vs. Input Voltage at V+ = 12 V,
PMW Frequency of 20 kHz, and Duty Cycle of 50% for a Purely Resistive Load
Output Voltage
(OUT1)
IOUT
Input Voltage
(IN1)
V+=12 V
fPWM =20 kHz
Duty Cycle=90%
Figure 19. Output Voltage and Current vs. Input Voltage at V+ = 12 V,
PMW Frequency of 20 kHz, and Duty Cycle of 90% for a Purely Resistive Load
33887
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES
2KPV
9ROWV
Figure 20. Typical High-Side RDS(ON) Versus V+
2KPV
2+06
9ROWV
93:5
Figure 21. Typical Low-Side RDS(ON) Versus V+
33887
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
2+06
0LOOLDPSHUHV
9ROWV
93:5
Figure 22. Typical Quiescent Supply Current Versus V+
33887
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
Table 6. Truth Table
The tri-state conditions and the fault status are reset using D1 or D2. The truth table uses the following notations: L = LOW,
H = HIGH, X = HIGH or LOW, and Z = High impedance (all output power transistors are switched off).
Device State
Fault
Status
Flag
Input Conditions
Output States
EN
D1
D2
IN1
IN2
FS
OUT1
OUT2
Forward
H
L
H
H
L
H
H
L
Reverse
H
L
H
L
H
H
L
H
Freewheeling Low
H
L
H
L
L
H
L
L
Freewheeling High
H
L
H
H
H
H
H
H
Disable 1 (D1)
H
H
X
X
X
L
Z
Z
Disable 2 (D2)
H
X
L
X
X
L
Z
Z
IN1 Disconnected
H
L
H
Z
X
H
H
X
IN2 Disconnected
H
L
H
X
Z
H
X
H
D1 Disconnected
H
Z
X
X
X
L
Z
Z
D2 Disconnected
H
X
Z
X
X
L
Z
Z
H
X
X
X
X
L
Z
Z
H
X
X
X
X
L
Z
Z
Short Circuit (35)
H
X
X
X
X
L
Z
Z
Sleep Mode EN
L
X
X
X
X
H
Z
Z
EN Disconnected
Z
X
X
X
X
H
Z
Z
Undervoltage (34)
Overtemperature
(35)
Notes
34
In the case of an undervoltage condition, the outputs tri-state and the fault status is SET logic LOW. Upon undervoltage recovery, fault
status is reset automatically or automatically cleared and the outputs are restored to their original operating condition.
35
When a short circuit or overtemperature condition is detected, the power outputs are tri-state latched-OFF independent of the input
signals and the fault status flag is SET logic LOW.
33887
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
Numerous protection and operational features (speed,
torque, direction, dynamic braking, PWM control, and closedloop control), in addition to the 5.0 A current capability, make
the 33887 a very attractive, cost-effective solution for
controlling a broad range of small DC motors. In addition, a
pair of 33887 devices can be used to control bipolar stepper
motors. The 33887 can also be used to excite transformer
primary windings with a switched square wave to produce
secondary winding AC currents.
FUNCTIONAL PIN DESCRIPTIONS
POWER GROUND AND ANALOG GROUND
(PGND AND AGND)
few milliamperes. Refer to Table 6, Truth Table, and STATIC
ELECTRICAL CHARACTERISTICS table, page 9.
Power and analog ground pins should be connected
together with a very low impedance connection.
H-BRIDGE OUTPUT (OUT1 AND OUT2)
POSITIVE POWER SUPPLY (V+)
V+ pins are the power supply inputs to the device. All V+
pins must be connected together on the printed circuit board
with as short as possible traces offering as low impedance as
possible between pins.
V+ pins have an undervoltage threshold. If the supply
voltage drops below a V+ undervoltage threshold, the output
power stage switches to a tri-state condition and the fault
status flag is SET and the Fault Status pin voltage switched
to a logic LOW. When the supply voltage returns to a level
that is above the threshold, the power stage automatically
resumes normal operation according to the established
condition of the input pins and the fault status flag is
automatically reset logic HIGH.
As V+ increases in value above 28 V, the charge pump
performance begins to degrade. At +40 V, the charge pump
is effectively non-functional. Operation at this high voltage
level will result in the output FETs not being enhanced when
turned on. This means that the voltage on the output will be
VOUT = (V+) – VGS. This increased voltage drop under load
will produce a higher power dissipation.
FAULT STATUS (FS)
The FS pin is the device fault status output. This output is
an active LOW open drain structure requiring a pull-up
resistor to 5.0 V. Refer to Table 6, Truth Table, page 20.
LOGIC INPUT CONTROL AND DISABLE
(IN1, IN2, D1, AND D2)
These pins are input control pins used to control the
outputs. These pins are 5.0 V CMOS-compatible inputs with
hysteresis. The IN1 and IN2 independently control OUT1 and
OUT2, respectively. D1 and D2 are complementary inputs
used to tri-state disable the H-Bridge outputs.
When either D1 or D2 is SET (D1 = logic HIGH or D2 =
logic LOW) in the disable state, outputs OUT1 and OUT2 are
both tri-state disabled; however, the rest of the circuitry is fully
operational and the supply IQ (standby) current is reduced to a
These pins are the outputs of the H-Bridge with integrated
output MOSFET body diodes. The bridge output is controlled
using the IN1, IN2, D1, and D2 inputs. The low-side
MOSFETs have active current limiting above the ILIM
threshold. The outputs also have thermal shutdown (tri-state
latch-OFF) with hysteresis as well as short circuit latch-OFF
protection.
A disable timer (time t b) USED to detect currents that are
higher than current limit is activated at each output activation
to facilitate hard short detection (see Figure 11, page 13).
Charge Pump Capacitor (CCP)
A filter capacitor (up to 33 nF) can be connected from the
charge pump output pin and PGND. The device can operate
without the external capacitor, although the CCP capacitor
helps to reduce noise and allows the device to perform at
maximum speed, timing, and PWM frequency.
ENABLE (EN)
The EN pin is used to place the device in a sleep mode so
as to consume very low currents. When the EN pin voltage is
a logic LOW state, the device is in the sleep mode. The
device is enabled and fully operational when the EN pin
voltage is logic HIGH. An internal pull-down resistor
maintains the device in sleep mode in the event EN is driven
through a high impedance I/O or an unpowered
microcontroller, or the EN input becomes disconnected.
FEEDBACK FOR H-BRIDGE (FB)
The 33887 has a feedback output (FB) for “real time”
monitoring of H-Bridge high-side current to facilitate closedloop operation for motor speed and torque control.
The FB pin provides current sensing feedback of the
H-Bridge high-side drivers. When running in forward or
reverse direction, a ground referenced 1/375th (0.00266) of
load current is output to this pin. Through an external resistor
to ground, the proportional feedback current can be
converted to a proportional voltage equivalent and the
controlling microcontroller can “read” the current proportional
33887
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTIONS
voltage with its analog-to-digital converter (ADC). This is
intended to provide the user with motor current feedback for
motor torque control. The resistance range for the linear
operation of the FB pin is 100 < RFB < 200 Ω.
If PWM-ing is implemented using the disable pin inputs
(either D1 or D2), a small filter capacitor (1.0 μF or less) may
be required in parallel with the external resistor to ground for
fast spike suppression.
33887
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The 33887 Simplified Internal Block Diagram shown in
Figure 2, page 2, is a fully protected monolithic H-Bridge with
Enable, Fault Status reporting, and High-Side current sense
feedback to accommodate closed-loop PWM control. For a
DC motor to run, the input conditions need be as follows:
Enable input logic HIGH, D1 input logic LOW, D2 input logic
HIGH, FS flag cleared (logic HIGH), one IN logic LOW and
the other IN logic HIGH (to define output polarity). The 33887
can execute dynamic braking by simultaneously turning on
either both high-side MOSFETs or both low-side MOSFETs
in the output H-Bridge; e.g., IN1 and IN2 logic HIGH or IN1
and IN2 logic LOW.
The 33887 outputs are capable of providing a continuous
DC load current of 5.0 A from a 28 V V+ source. An internal
charge pump supports PWM frequencies to 10 kHz. An
external pull-up resistor is required at the FS pin for fault
status reporting. The 33887 has an analog feedback (current
mirror) output pin (the FB pin) that provides a constantcurrent source ratioed to the active high-side MOSFET. This
can be used to provide “real time” monitoring of load current
to facilitate closed-loop operation for motor speed/torque
control.
Two independent inputs (IN1 and IN2) provide control of
the two totem-pole half-bridge outputs. Two disable inputs
(D1 and D2) provide the means to force the H-Bridge outputs
to a high-impedance state (all H-Bridge switches OFF). An
EN pin controls an enable function that allows the 33887 to
be placed in a power-conserving sleep mode.
The 33887 has undervoltage shutdown with automatic
recovery, active current limiting, output short-circuit latchOFF, and overtemperature latch-OFF. An undervoltage
shutdown, output short-circuit latch-OFF, or overtemperature
latch-OFF fault condition will cause the outputs to turn OFF
(i.e., become high impedance or tri-stated) and the fault
output flag to be set LOW. Either of the Disable inputs or V+
must be “toggled” to clear the fault flag.
Active current limiting is accomplished by a constant OFFtime PWM method employing active current limiting threshold
triggering. The active current limiting scheme is unique in that
it incorporates a junction temperature-dependent current limit
threshold. This means the active current limiting threshold is
“ramped down” as the junction temperature increases above
160°C, until at 175°C the current will have been decreased to
about 4.0 A. Above 175°C, the overtemperature shutdown
(latch-OFF) occurs. This combination of features allows the
device to remain in operation for 30 seconds at junction
temperatures above 150°C for nonrepetitive unexpected
loads.
33887
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
PROTECTION AND DIAGNOSTIC FEATURES
SHORT CIRCUIT PROTECTION
If an output short circuit condition is detected, the power
outputs tri-state (latch-OFF) independent of the input (IN1
and IN2) states, and the fault status output flag is SET logic
LOW. If the D1 input changes from logic HIGH to logic LOW,
or if the D2 input changes from logic LOW to logic HIGH, the
output bridge will become operational again and the fault
status flag will be reset (cleared) to a logic HIGH state.
The output stage will always switch into the mode defined
by the input pins (IN1, IN2, D1, and D2), provided the device
junction temperature is within the specified operating
temperature range.
ACTIVE CURRENT LIMITING
The maximum current flow under normal operating
conditions is internally limited to ILIM (5.2 A to 7.8 A). When
the maximum current value is reached, the output stages are
tri-stated for a fixed time (t a) of 20 μs typical. Depending on
the time constant associated with the load characteristics, the
current decreases during the tri-state duration until the next
output ON cycle occurs (see Figures 11 and 14, page 13 and
page 15, respectively).
The current limiting threshold value is dependent upon the
device junction temperature. When -40°C ≤ TJ ≤ 160°C, ILIM
is between 5.2 A to 7.8 A. When TJ exceeds 160°C, the ILIM
current decreases linearly down to 4.0 A typical at 175°C.
Above 175°C the device overtemperature circuit detects TLIM
and overtemperature shutdown occurs (see Figure 9,
page 12). This feature allows the device to remain
operational for a longer time but at a regressing output
performance level at junction temperatures above 160°C.
Output Avalanche Protection
An inductive fly-back event, namely when the outputs are
suddenly disabled and V+ is lost, could result in electrical
overstress of the drivers. To prevent this the V+ input to the
33887 should not exceed the maximum rating during a flyback condition. This may be done with either a zener clamp
and/or an appropriately valued input capacitor with
sufficiently low ESR.
OVERTEMPERATURE SHUTDOWN AND
HYSTERESIS
If an overtemperature condition occurs, the power outputs
are tri-stated (latched-OFF) and the fault status flag is SET to
logic LOW.
To reset from this condition, D1 must change from logic
HIGH to logic LOW, or D2 must change from logic LOW to
logic HIGH. When reset, the output stage switches ON again,
provided that the junction temperature is now below the
overtemperature threshold limit minus the hysteresis.
Note Resetting from the fault condition will clear the fault
status flag.
33887
24
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
Figure 23 shows a typical application schematic. For precision high-current applications in harsh, noisy environments, the V+
by-pass capacitor may need to be substantially larger.
DC
MOTOR
V+
33887
AGND
V+
CCP
OUT1
FB
+
1.0 μF
33 nF
+
47 μF
OUT2
EN
D2
D1
100 Ω
FS
PGND
IN1
IN2
FB
IN2
IN1
FS
D1
D2
EN
Figure 23. 33887 Typical Application Schematic
33887
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
PACKAGING
SOLDERING INFORMATION
PACKAGING
SOLDERING INFORMATION
The 33887 packages are designed for thermal
performance. The significant feature of these packages is the
exposed pad on which the power die is soldered. When
soldered to a PCB, this pad provides a path for heat flow to
the ambient environment. The more copper area and
thickness on the PCB, the better the power dissipation and
transient behavior will be.
Example Characterization on a double-sided PCB:
bottom side area of copper is 7.8 cm2; top surface is 2.7 cm2
(see Figure ); grid array of 24 vias 0.3 mm in diameter
.
Top Side
Bottom Side
Figure 24. PCB Test Layout
33887
26
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
PACKAGING DIMENSIONS
Important For the most current revision of the package, visit www.freescale.com and perform a keyword search on the 98A
drawing number below
VW SUFFIX
20-PIN HSOP
98ASH70702A
ISSUE B
33887
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
PACKAGING
PACKAGING DIMENSIONS
VW SUFFIX
20-PIN HSOP
98ASH70702A
ISSUE B
33887
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
FK (Pb-FREE) SUFFIX
36-PIN PQFN
98ASA10583D
ISSUE C
33887
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
PACKAGING
PACKAGING DIMENSIONS
FK (Pb-FREE) SUFFIX
36-PIN PQFN
98ASA10583D
ISSUE C
33887
30
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
EK SUFFIX (PB-FREE)
54-PIN SOICW EXPOSED PAD
98ASA10506D
ISSUE C
33887
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
PACKAGING
PACKAGING DIMENSIONS
EK SUFFIX (PB-FREE)
54-PIN SOICW EXPOSED PAD
98ASA10506D
ISSUE C
33887
32
Analog Integrated Circuit Device Data
Freescale Semiconductor
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
33887HSOP
THERMAL ADDENDUM (REV 2.0)
Introduction
This thermal addendum is provided as a supplement to the MC33887 technical
data sheet. The addendum provides thermal performance information that may
be critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the data sheet.
20-PIN
HSOP-EP
Packaging and Thermal Considerations
The MC33887 is offered in a 20 pin HSOP exposed pad, single die package.
There is a single heat source (P), a single junction temperature (TJ), and thermal
resistance (RθJA).
TJ
=
RθJA
.
VW SUFFIX
98ASH70273A
20-PIN HSOP-EP
P
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not
meant to and will not predict the performance of a package in an applicationspecific environment. Stated values were obtained by measurement and
simulation according to the standards listed below.
Note For package dimensions, refer to
the 33887 device data sheet.
Standards
Table 7.
Thermal Performance Comparison
Thermal Resistance
1.0
[°C/W]
RθJA(1),(2)
20
RθJB (2),(3)
6.0
RθJA (1), (4)
52
RθJC (5)
1.0
1.0
0.2
0.2
* All measurements
are in millimeters
Soldermast
openings
NOTES:
1.Per JEDEC JESD51-2 at natural convection, still air condition.
2.2s2p thermal test board per JEDEC JESD51-5 and JESD51-7.
3.Per JEDEC JESD51-8, with the board temperature on the center
trace near the center lead.
4.Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5.Thermal resistance between the die junction and the exposed
pad surface; cold plate attached to the package bottom side,
remaining surfaces insulated
20 Terminal HSOP-EP
1.27 mm Pitch
16.0 mm x 11.0 mm Body
12.2 mm x 6.9 mm Exposed Pad
Thermal vias
connected to top
buried plane
Figure 25. Thermal Land Pattern for Direct Thermal
Attachment According to JESD51-5
33887
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
A
Tab
AGND
FS
IN1
V+
V+
OUT1
OUT1
FB
PGND
PGND
1
20
2
19
3
4
18
17
5
16
6
7
15
14
8
13
9
12
10
11
EN
IN2
D1
CCP
V+
OUT2
OUT2
D2
PGND
PGND
Tab
33887 Pin Connections
20-Pin HSOP-EP
1.27 mm Pitch
16.0 mm x 11.0 mm Body
12.2 mm x 6.9 mm Exposed Pad
Figure 26. Thermal Test Board
Device on Thermal Test Board
Material:
Outline:
Area A:
Ambient Conditions:
Single layer printed circuit board
FR4, 1.6 mm thickness
Cu traces, 0.07 mm thickness
Table 8.
Thermal Resistance Performance
Thermal Resistance
Area A (mm2)
°C/W
RθJA
0.0
52
300
36
600
32
0.0
10
300
7.0
600
6.0
80 mm x 100 mm board area,
including edge connector for thermal
testing
Cu heat spreading areas on board
surface
Natural convection, still air
RθJS
RθJA is the thermal resistance between die junction and
ambient air.
RθJS is the thermal resistance between die junction and the
reference location on the board surface near a center lead of the
package (see Figure 26).
33887
34
Analog Integrated Circuit Device Data
Freescale Semiconductor
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
Thermal Resistance [ºC/W]
60
50
40
30
20
x
RθJA
10
0
0
300
Heat spreading area A [mm²]
600
Figure 27. Device on Thermal Test Board RθJA
Thermal Resistance [ºC/W]
100
10
1
0.1
1.00E-03
1.00E-02
1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04
Time[s]
Figure 28. Transient Thermal Resistance RθJA
Device on Thermal Test Board Area A = 600 (mm2)
33887
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION
• Added Thermal Addendum & Converted to Freescale format, Revised PQFN drawing, made
several minor spelling correction. Added 33887A
• Updated Ordering information block with new epp information
• Changed the supply/ operating voltage from 40 V to 28 V
• Updated all package drawings to the current revision
• Adjusted to match device performance characteristics
• Updated the document to the prevailing Freescale form and style
• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from
Maximum Ratings on page 7.
• Added note (8)
• Added MCZ33887EK/R2 to the Ordering Information on Page 1
• Removed the 33887A from the data sheet and deleted Product Variation section now that is no
longer needed.
• Changed the third paragraph of the introduction on page 1
• Altered feature number 1 on page 1
• Added feature number 2 on page 1
• Changed Maximum Supply Voltage (1) to 0.3 to 40 V
• Added note (1)
• Changed note (16)
• Added a third paragraph to Positive Power Supply (V+) on page 21
• Replaced Figure 20, Figure 21, and Figure 22 with updated information.
10.0
7/2005
11.0
11/2006
12.0
1/2007
13.0
10/2008
• Added Part Number MC33887AVW/R2 to Ordering Information Table on page 1.
14.0
3/2011
• Removed part numbers MC33887APVW/R2, MC33887DH/R2, MC33887DWB/R2, MC33887AVW/
R2, MC33887PNB/R2 and MCZ33887EK/R2 and replaced with part numbers MC33887APVW/R2,
MC33887PFK/R2 and MC33887PEK/R2 in Ordering Information Table on Page 1.
33887
36
Analog Integrated Circuit Device Data
Freescale Semiconductor
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MC33887
Rev. 14.0
3/2011
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